diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2012-11-02 11:50:06 -0500 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2012-11-02 11:50:06 -0500 |
| commit | 1dbf9bb4ca6cc3bee68713a28778c1bdfe222f75 (patch) | |
| tree | 81108e7ff1951b652258f53bd5615a617b734ce2 /tests/long | |
| parent | ddd6af414cdd4939f4ff382f0e83e7dfa695781d (diff) | |
| download | gem5-1dbf9bb4ca6cc3bee68713a28778c1bdfe222f75.tar.xz | |
update stats for preceeding changes
Diffstat (limited to 'tests/long')
95 files changed, 22741 insertions, 21928 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini index 028711e47..158e17e5b 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini @@ -11,14 +11,15 @@ type=LinuxAlphaSystem children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 -console=/dist/m5/system/binaries/console +clock=1000 +console=/projects/pd/randd/dist/binaries/console init_param=0 -kernel=/dist/m5/system/binaries/vmlinux +kernel=/projects/pd/randd/dist/binaries/vmlinux load_addr_mask=1099511627775 mem_mode=timing memories=system.physmem num_work_ids=16 -pal=/dist/m5/system/binaries/ts_osfpal +pal=/projects/pd/randd/dist/binaries/ts_osfpal readfile=tests/halt.sh symbolfile= system_rev=1024 @@ -34,18 +35,17 @@ system_port=system.membus.slave[0] [system.bridge] type=Bridge +clock=1000 delay=50000 -nack_delay=4000 ranges=8796093022208:18446744073709551615 req_size=16 resp_size=16 -write_ack=false master=system.iobus.slave[0] slave=system.membus.master[0] [system.cpu0] type=DerivO3CPU -children=dcache dtb fuPool icache interrupts itb tracer +children=dcache dtb fuPool icache interrupts isa itb tracer BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -93,6 +93,7 @@ iewToFetchDelay=1 iewToRenameDelay=1 instShiftAmt=2 interrupts=system.cpu0.interrupts +isa=system.cpu0.isa issueToExecuteDelay=1 issueWidth=8 itb=system.cpu0.itb @@ -111,7 +112,6 @@ numPhysIntRegs=256 numROBEntries=192 numRobs=1 numThreads=1 -phase=0 predType=tournament profile=0 progress_interval=0 @@ -145,16 +145,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=4 block_size=64 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=2 is_top_level=true -latency=1000 max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=2 size=32768 subblock_size=0 system=system @@ -437,16 +439,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=1 block_size=64 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=2 is_top_level=true -latency=1000 max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=2 size=32768 subblock_size=0 system=system @@ -460,6 +464,9 @@ mem_side=system.toL2Bus.slave[0] [system.cpu0.interrupts] type=AlphaInterrupts +[system.cpu0.isa] +type=AlphaISA + [system.cpu0.itb] type=AlphaTLB size=48 @@ -469,7 +476,7 @@ type=ExeTracer [system.cpu1] type=DerivO3CPU -children=dcache dtb fuPool icache interrupts itb tracer +children=dcache dtb fuPool icache interrupts isa itb tracer BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -517,6 +524,7 @@ iewToFetchDelay=1 iewToRenameDelay=1 instShiftAmt=2 interrupts=system.cpu1.interrupts +isa=system.cpu1.isa issueToExecuteDelay=1 issueWidth=8 itb=system.cpu1.itb @@ -535,7 +543,6 @@ numPhysIntRegs=256 numROBEntries=192 numRobs=1 numThreads=1 -phase=0 predType=tournament profile=0 progress_interval=0 @@ -569,16 +576,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=4 block_size=64 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=2 is_top_level=true -latency=1000 max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=2 size=32768 subblock_size=0 system=system @@ -861,16 +870,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=1 block_size=64 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=2 is_top_level=true -latency=1000 max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=2 size=32768 subblock_size=0 system=system @@ -884,6 +895,9 @@ mem_side=system.toL2Bus.slave[2] [system.cpu1.interrupts] type=AlphaInterrupts +[system.cpu1.isa] +type=AlphaISA + [system.cpu1.itb] type=AlphaTLB size=48 @@ -908,7 +922,7 @@ table_size=65536 [system.disk0.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-latest.img +image_file=/projects/pd/randd/dist/disks/linux-latest.img read_only=true [system.disk2] @@ -928,7 +942,7 @@ table_size=65536 [system.disk2.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-bigswap2.img +image_file=/projects/pd/randd/dist/disks/linux-bigswap2.img read_only=true [system.intrctrl] @@ -951,16 +965,18 @@ type=BaseCache addr_ranges=0:8589934591 assoc=8 block_size=64 +clock=1000 forward_snoops=false hash_delay=1 +hit_latency=50 is_top_level=true -latency=50000 max_miss_count=0 mshrs=20 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=50 size=1024 subblock_size=0 system=system @@ -976,20 +992,22 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=8 block_size=64 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=20 is_top_level=false -latency=10000 max_miss_count=0 -mshrs=92 +mshrs=20 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=20 size=4194304 subblock_size=0 system=system -tgts_per_mshr=16 +tgts_per_mshr=12 trace_addr=0 two_queue=false write_buffers=8 @@ -1010,9 +1028,10 @@ slave=system.system_port system.iocache.mem_side system.l2c.mem_side [system.membus.badaddr_responder] type=IsaFake +clock=1000 fake_mem=false pio_addr=0 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=true ret_data16=65535 @@ -1025,14 +1044,28 @@ warn_access= pio=system.membus.default [system.physmem] -type=SimpleMemory +type=SimpleDRAM +addr_mapping=openmap +banks_per_rank=8 +clock=1000 conf_table_reported=false -file= in_addr_map=true -latency=30000 -latency_var=0 +lines_per_rowbuffer=64 +mem_sched_policy=fcfs null=false +page_policy=open range=0:134217727 +ranks_per_channel=2 +read_buffer_size=32 +tBURST=4000 +tCL=14000 +tRCD=14000 +tREFI=7800000 +tRFC=300000 +tRP=14000 +tWTR=1000 +write_buffer_size=32 +write_thresh_perc=70 zero=false port=system.membus.master[1] @@ -1044,7 +1077,7 @@ system=system [system.simple_disk.disk] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-latest.img +image_file=/projects/pd/randd/dist/disks/linux-latest.img read_only=true [system.terminal] @@ -1057,7 +1090,7 @@ port=3456 [system.toL2Bus] type=CoherentBus block_size=64 -clock=1000 +clock=500 header_cycles=1 use_default_range=false width=8 @@ -1072,10 +1105,11 @@ system=system [system.tsunami.backdoor] type=AlphaBackdoor +clock=1000 cpu=system.cpu0 disk=system.simple_disk pio_addr=8804682956800 -pio_latency=1000 +pio_latency=100000 platform=system.tsunami system=system terminal=system.terminal @@ -1083,8 +1117,9 @@ pio=system.iobus.master[24] [system.tsunami.cchip] type=TsunamiCChip +clock=1000 pio_addr=8803072344064 -pio_latency=1000 +pio_latency=100000 system=system tsunami=system.tsunami pio=system.iobus.master[0] @@ -1140,12 +1175,10 @@ dma_write_delay=0 dma_write_factor=0 hardware_address=00:90:00:00:00:01 intr_delay=10000000 -max_backoff_delay=10000000 -min_backoff_delay=4000 pci_bus=0 pci_dev=1 pci_func=0 -pio_latency=1000 +pio_latency=30000 platform=system.tsunami rss=false rx_delay=1000000 @@ -1162,9 +1195,10 @@ pio=system.iobus.master[27] [system.tsunami.fake_OROM] type=IsaFake +clock=1000 fake_mem=false pio_addr=8796093677568 -pio_latency=1000 +pio_latency=100000 pio_size=393216 ret_bad_addr=false ret_data16=65535 @@ -1178,9 +1212,10 @@ pio=system.iobus.master[8] [system.tsunami.fake_ata0] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848432 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -1194,9 +1229,10 @@ pio=system.iobus.master[19] [system.tsunami.fake_ata1] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848304 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -1210,9 +1246,10 @@ pio=system.iobus.master[20] [system.tsunami.fake_pnp_addr] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848569 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -1226,9 +1263,10 @@ pio=system.iobus.master[9] [system.tsunami.fake_pnp_read0] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848451 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -1242,9 +1280,10 @@ pio=system.iobus.master[11] [system.tsunami.fake_pnp_read1] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848515 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -1258,9 +1297,10 @@ pio=system.iobus.master[12] [system.tsunami.fake_pnp_read2] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848579 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -1274,9 +1314,10 @@ pio=system.iobus.master[13] [system.tsunami.fake_pnp_read3] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848643 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -1290,9 +1331,10 @@ pio=system.iobus.master[14] [system.tsunami.fake_pnp_read4] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848707 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -1306,9 +1348,10 @@ pio=system.iobus.master[15] [system.tsunami.fake_pnp_read5] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848771 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -1322,9 +1365,10 @@ pio=system.iobus.master[16] [system.tsunami.fake_pnp_read6] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848835 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -1338,9 +1382,10 @@ pio=system.iobus.master[17] [system.tsunami.fake_pnp_read7] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848899 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -1354,9 +1399,10 @@ pio=system.iobus.master[18] [system.tsunami.fake_pnp_write] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615850617 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -1370,9 +1416,10 @@ pio=system.iobus.master[10] [system.tsunami.fake_ppc] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848891 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -1386,9 +1433,10 @@ pio=system.iobus.master[7] [system.tsunami.fake_sm_chip] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848816 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -1402,9 +1450,10 @@ pio=system.iobus.master[2] [system.tsunami.fake_uart1] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848696 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -1418,9 +1467,10 @@ pio=system.iobus.master[3] [system.tsunami.fake_uart2] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848936 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -1434,9 +1484,10 @@ pio=system.iobus.master[4] [system.tsunami.fake_uart3] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848680 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -1450,9 +1501,10 @@ pio=system.iobus.master[5] [system.tsunami.fake_uart4] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848944 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -1466,9 +1518,10 @@ pio=system.iobus.master[6] [system.tsunami.fb] type=BadDevice +clock=1000 devicename=FrameBuffer pio_addr=8804615848912 -pio_latency=1000 +pio_latency=100000 system=system pio=system.iobus.master[21] @@ -1512,16 +1565,15 @@ SubClassCode=1 SubsystemID=0 SubsystemVendorID=0 VendorID=32902 +clock=1000 config_latency=20000 ctrl_offset=0 disks=system.disk0 system.disk2 io_shift=0 -max_backoff_delay=10000000 -min_backoff_delay=4000 pci_bus=0 pci_dev=0 pci_func=0 -pio_latency=1000 +pio_latency=30000 platform=system.tsunami system=system config=system.iobus.master[26] @@ -1530,9 +1582,10 @@ pio=system.iobus.master[25] [system.tsunami.io] type=TsunamiIO +clock=1000 frequency=976562500 pio_addr=8804615847936 -pio_latency=1000 +pio_latency=100000 system=system time=Thu Jan 1 00:00:00 2009 tsunami=system.tsunami @@ -1541,8 +1594,9 @@ pio=system.iobus.master[22] [system.tsunami.pchip] type=TsunamiPChip +clock=1000 pio_addr=8802535473152 -pio_latency=1000 +pio_latency=100000 system=system tsunami=system.tsunami pio=system.iobus.master[1] @@ -1550,7 +1604,8 @@ pio=system.iobus.master[1] [system.tsunami.pciconfig] type=PciConfigAll bus=0 -pio_latency=1 +clock=1000 +pio_latency=30000 platform=system.tsunami size=16777216 system=system @@ -1558,8 +1613,9 @@ pio=system.iobus.default [system.tsunami.uart] type=Uart8250 +clock=1000 pio_addr=8804615848952 -pio_latency=1000 +pio_latency=100000 platform=system.tsunami system=system terminal=system.terminal diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout index acdd4bc1c..200b08796 100755 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout @@ -1,13 +1,13 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 26 2012 21:20:05 -gem5 started Jul 26 2012 22:30:48 -gem5 executing on zizzer +gem5 compiled Oct 30 2012 11:02:14 +gem5 started Oct 30 2012 13:40:49 +gem5 executing on u200540-lin command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual -re tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual Global frequency set at 1000000000000 ticks per second -info: kernel located at: /dist/m5/system/binaries/vmlinux +info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 info: Entering event queue @ 0. Starting simulation... -info: Launching CPU 1 @ 112168000 -Exiting @ tick 1900530295500 because m5_exit instruction encountered +info: Launching CPU 1 @ 107840000 +Exiting @ tick 1897857556000 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt index 763ec5c7a..59d7770e6 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt @@ -1,104 +1,104 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.896908 # Number of seconds simulated -sim_ticks 1896907607500 # Number of ticks simulated -final_tick 1896907607500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.897858 # Number of seconds simulated +sim_ticks 1897857556000 # Number of ticks simulated +final_tick 1897857556000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 91997 # Simulator instruction rate (inst/s) -host_op_rate 91997 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3111116066 # Simulator tick rate (ticks/s) -host_mem_usage 330780 # Number of bytes of host memory used -host_seconds 609.72 # Real time elapsed on the host -sim_insts 56092592 # Number of instructions simulated -sim_ops 56092592 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu0.inst 788928 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 24066944 # Number of bytes read from this memory -system.physmem.bytes_read::tsunami.ide 2649408 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 193664 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 1095360 # Number of bytes read from this memory -system.physmem.bytes_read::total 28794304 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 788928 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 193664 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 982592 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7762048 # Number of bytes written to this memory -system.physmem.bytes_written::total 7762048 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 12327 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 376046 # Number of read requests responded to by this memory -system.physmem.num_reads::tsunami.ide 41397 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 3026 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 17115 # Number of read requests responded to by this memory -system.physmem.num_reads::total 449911 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 121282 # Number of write requests responded to by this memory -system.physmem.num_writes::total 121282 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 415902 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 12687462 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1396698 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 102095 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 577445 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 15179603 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 415902 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 102095 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 517997 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4091948 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4091948 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4091948 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 415902 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 12687462 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1396698 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 102095 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 577445 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 19271551 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 449911 # Total number of read requests seen -system.physmem.writeReqs 121282 # Total number of write requests seen -system.physmem.cpureqs 578344 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 28794304 # Total number of bytes read from memory -system.physmem.bytesWritten 7762048 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 28794304 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 7762048 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 53 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 3357 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 28022 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 27737 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 28393 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 27975 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 28585 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 28318 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 28204 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 28175 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 28470 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 28412 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 28316 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 28619 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 28149 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 27813 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 27389 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 27281 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 7511 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 7339 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 7747 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 7422 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 7940 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 7694 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 7599 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 7607 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 7865 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 7795 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 7764 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 8092 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 7767 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 7407 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 6913 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 6820 # Track writes on a per bank basis +host_inst_rate 131170 # Simulator instruction rate (inst/s) +host_op_rate 131170 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4437782045 # Simulator tick rate (ticks/s) +host_mem_usage 332328 # Number of bytes of host memory used +host_seconds 427.66 # Real time elapsed on the host +sim_insts 56096024 # Number of instructions simulated +sim_ops 56096024 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu0.inst 762816 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 24264832 # Number of bytes read from this memory +system.physmem.bytes_read::tsunami.ide 2650624 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 217920 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 955136 # Number of bytes read from this memory +system.physmem.bytes_read::total 28851328 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 762816 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 217920 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 980736 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7805952 # Number of bytes written to this memory +system.physmem.bytes_written::total 7805952 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 11919 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 379138 # Number of read requests responded to by this memory +system.physmem.num_reads::tsunami.ide 41416 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 3405 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 14924 # Number of read requests responded to by this memory +system.physmem.num_reads::total 450802 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 121968 # Number of write requests responded to by this memory +system.physmem.num_writes::total 121968 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 401935 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 12785381 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1396640 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 114824 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 503271 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 15202051 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 401935 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 114824 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 516760 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4113034 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4113034 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4113034 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 401935 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 12785381 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1396640 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 114824 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 503271 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 19315085 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 450802 # Total number of read requests seen +system.physmem.writeReqs 121968 # Total number of write requests seen +system.physmem.cpureqs 580318 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 28851328 # Total number of bytes read from memory +system.physmem.bytesWritten 7805952 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 28851328 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 7805952 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 52 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 3354 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 28275 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 28002 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 28406 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 28112 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 28525 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 28215 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 27879 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 27987 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 28286 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 28166 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 28504 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 28315 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 28066 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 28252 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 27946 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 27814 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 7745 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 7549 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 7802 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 7514 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 7914 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 7617 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 7286 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 7435 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 7648 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 7558 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 7984 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 7855 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 7634 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 7769 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 7378 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 7280 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 313 # Number of times wr buffer was full causing retry -system.physmem.totGap 1896888917000 # Total gap between requests +system.physmem.numWrRetry 525 # Number of times wr buffer was full causing retry +system.physmem.totGap 1897852967000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 449911 # Categorize read packet sizes +system.physmem.readPktSize::6 450802 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -107,7 +107,7 @@ system.physmem.writePktSize::2 0 # ca system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 121595 # categorize write packet sizes +system.physmem.writePktSize::6 122493 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -116,31 +116,31 @@ system.physmem.neitherpktsize::2 0 # ca system.physmem.neitherpktsize::3 0 # categorize neither packet sizes system.physmem.neitherpktsize::4 0 # categorize neither packet sizes system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 3357 # categorize neither packet sizes +system.physmem.neitherpktsize::6 3354 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 322755 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 66156 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 30830 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 6523 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2879 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2466 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1798 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1998 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1693 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1990 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1579 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1551 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1676 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1787 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 322811 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 66355 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 31450 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 6565 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2903 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2442 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1811 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 2029 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1666 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1950 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1569 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1554 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1659 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1788 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 1259 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 1472 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 908 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 254 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 147 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 124 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 7 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 1496 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 916 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 256 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 143 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 121 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see @@ -152,225 +152,225 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 4069 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 4980 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 5100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 5144 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 5219 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 5235 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 5267 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 5267 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 5268 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 5273 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 5273 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 5273 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 5273 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 5273 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 5273 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 5273 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 5273 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5273 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5273 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5273 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5273 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5273 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5273 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 1205 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 294 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 174 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 4091 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 5028 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 5125 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 5174 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 5249 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 5262 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 5292 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 5292 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 5295 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 5303 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 5303 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 5303 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 5303 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 5303 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 5303 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 5303 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 5303 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5303 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5303 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5303 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5303 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5303 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5302 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 1212 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 275 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 178 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 129 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 54 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 38 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 41 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 8 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 6417421318 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 13706967318 # Sum of mem lat for all requests -system.physmem.totBusLat 1799432000 # Total cycles spent in databus access -system.physmem.totBankLat 5490114000 # Total cycles spent in bank access -system.physmem.avgQLat 14265.44 # Average queueing delay per request -system.physmem.avgBankLat 12204.10 # Average bank access latency per request +system.physmem.totQLat 6654880960 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 13976960960 # Sum of mem lat for all requests +system.physmem.totBusLat 1803000000 # Total cycles spent in databus access +system.physmem.totBankLat 5519080000 # Total cycles spent in bank access +system.physmem.avgQLat 14764.02 # Average queueing delay per request +system.physmem.avgBankLat 12244.22 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 30469.54 # Average memory access latency -system.physmem.avgRdBW 15.18 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 4.09 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 15.18 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 4.09 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 31008.23 # Average memory access latency +system.physmem.avgRdBW 15.20 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 4.11 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 15.20 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 4.11 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.12 # Data bus utilization in percentage system.physmem.avgRdQLen 0.01 # Average read queue length over time -system.physmem.avgWrQLen 10.19 # Average write queue length over time -system.physmem.readRowHits 429697 # Number of row buffer hits during reads -system.physmem.writeRowHits 77704 # Number of row buffer hits during writes -system.physmem.readRowHitRate 95.52 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 64.07 # Row buffer hit rate for writes -system.physmem.avgGap 3320924.66 # Average gap between requests -system.l2c.replacements 342985 # number of replacements -system.l2c.tagsinuse 65321.507443 # Cycle average of tags in use -system.l2c.total_refs 2664537 # Total number of references to valid blocks. -system.l2c.sampled_refs 407990 # Sample count of references to valid blocks. -system.l2c.avg_refs 6.530888 # Average number of references to valid blocks. +system.physmem.avgWrQLen 7.39 # Average write queue length over time +system.physmem.readRowHits 429728 # Number of row buffer hits during reads +system.physmem.writeRowHits 77127 # Number of row buffer hits during writes +system.physmem.readRowHitRate 95.34 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 63.24 # Row buffer hit rate for writes +system.physmem.avgGap 3313464.33 # Average gap between requests +system.l2c.replacements 343886 # number of replacements +system.l2c.tagsinuse 65330.449226 # Cycle average of tags in use +system.l2c.total_refs 2612992 # Total number of references to valid blocks. +system.l2c.sampled_refs 408910 # Sample count of references to valid blocks. +system.l2c.avg_refs 6.390140 # Average number of references to valid blocks. system.l2c.warmup_cycle 5415654002 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 53803.345548 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 4275.017757 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 5362.992247 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 1295.991254 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 584.160637 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.820974 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.065232 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.081833 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.019775 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.008914 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.996727 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.inst 631150 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 433289 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 452366 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 409982 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1926787 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 859408 # number of Writeback hits -system.l2c.Writeback_hits::total 859408 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 132 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 86 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 218 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 33 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 35 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 68 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 121498 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 74869 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 196367 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.inst 631150 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 554787 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 452366 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 484851 # number of demand (read+write) hits -system.l2c.demand_hits::total 2123154 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 631150 # number of overall hits -system.l2c.overall_hits::cpu0.data 554787 # number of overall hits -system.l2c.overall_hits::cpu1.inst 452366 # number of overall hits -system.l2c.overall_hits::cpu1.data 484851 # number of overall hits -system.l2c.overall_hits::total 2123154 # number of overall hits -system.l2c.ReadReq_misses::cpu0.inst 12329 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 272557 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 3043 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 1706 # number of ReadReq misses -system.l2c.ReadReq_misses::total 289635 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 2549 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 508 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 3057 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 48 # number of SCUpgradeReq misses +system.l2c.occ_blocks::writebacks 53692.952391 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 4245.749457 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 5529.153379 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 1310.829137 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 551.764862 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.819289 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.inst 0.064785 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.data 0.084368 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.inst 0.020002 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.data 0.008419 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.996864 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.inst 779502 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 594261 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 294591 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 226328 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1894682 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 840085 # number of Writeback hits +system.l2c.Writeback_hits::total 840085 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 143 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 80 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 223 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 34 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 29 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 63 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 147131 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 42889 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 190020 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.inst 779502 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 741392 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 294591 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 269217 # number of demand (read+write) hits +system.l2c.demand_hits::total 2084702 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.inst 779502 # number of overall hits +system.l2c.overall_hits::cpu0.data 741392 # number of overall hits +system.l2c.overall_hits::cpu1.inst 294591 # number of overall hits +system.l2c.overall_hits::cpu1.data 269217 # number of overall hits +system.l2c.overall_hits::total 2084702 # number of overall hits +system.l2c.ReadReq_misses::cpu0.inst 11921 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 272257 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 3421 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 1751 # number of ReadReq misses +system.l2c.ReadReq_misses::total 289350 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 2525 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 517 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 3042 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 47 # number of SCUpgradeReq misses system.l2c.SCUpgradeReq_misses::cpu1.data 90 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 138 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 103909 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 15834 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 119743 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.inst 12329 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 376466 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 3043 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 17540 # number of demand (read+write) misses -system.l2c.demand_misses::total 409378 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.inst 12329 # number of overall misses -system.l2c.overall_misses::cpu0.data 376466 # number of overall misses -system.l2c.overall_misses::cpu1.inst 3043 # number of overall misses -system.l2c.overall_misses::cpu1.data 17540 # number of overall misses -system.l2c.overall_misses::total 409378 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.inst 738936500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 11707644000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 199188500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 90303499 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 12736072499 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 388500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 888500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 1277000 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 198500 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 114000 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 312500 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 7293917000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 1622405000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 8916322000 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.inst 738936500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 19001561000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 199188500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 1712708499 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 21652394499 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.inst 738936500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 19001561000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 199188500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 1712708499 # number of overall miss cycles -system.l2c.overall_miss_latency::total 21652394499 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.inst 643479 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 705846 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 455409 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 411688 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2216422 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 859408 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 859408 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 2681 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 594 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 3275 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_misses::total 137 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 107281 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 13452 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 120733 # number of ReadExReq misses +system.l2c.demand_misses::cpu0.inst 11921 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 379538 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 3421 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 15203 # number of demand (read+write) misses +system.l2c.demand_misses::total 410083 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.inst 11921 # number of overall misses +system.l2c.overall_misses::cpu0.data 379538 # number of overall misses +system.l2c.overall_misses::cpu1.inst 3421 # number of overall misses +system.l2c.overall_misses::cpu1.data 15203 # number of overall misses +system.l2c.overall_misses::total 410083 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0.inst 712478500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 11719521500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 222220000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 113744499 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 12767964499 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0.data 468000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 936000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 1404000 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.data 313000 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu1.data 113500 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 426500 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 7724029500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 1451007500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 9175037000 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0.inst 712478500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 19443551000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 222220000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 1564751999 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 21943001499 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.inst 712478500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 19443551000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 222220000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 1564751999 # number of overall miss cycles +system.l2c.overall_miss_latency::total 21943001499 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.inst 791423 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 866518 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 298012 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 228079 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2184032 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 840085 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 840085 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 2668 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 597 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 3265 # number of UpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::cpu0.data 81 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 125 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 206 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 225407 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 90703 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 316110 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.inst 643479 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 931253 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 455409 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 502391 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2532532 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 643479 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 931253 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 455409 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 502391 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2532532 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.019160 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.386142 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.006682 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.004144 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.130677 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.950765 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.855219 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.933435 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.592593 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.720000 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.669903 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.460984 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.174570 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.378802 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.inst 0.019160 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.404257 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.006682 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.034913 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.161648 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.inst 0.019160 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.404257 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.006682 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.034913 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.161648 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 59934.828453 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 42954.846142 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 65457.936247 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 52932.883353 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 43972.836498 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 152.412711 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 1749.015748 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 417.729800 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 4135.416667 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 1266.666667 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 2264.492754 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 70195.238141 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 102463.369963 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 74462.156452 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 59934.828453 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 50473.511552 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 65457.936247 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 97645.866534 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 52890.957743 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 59934.828453 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 50473.511552 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 65457.936247 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 97645.866534 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 52890.957743 # average overall miss latency +system.l2c.SCUpgradeReq_accesses::cpu1.data 119 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 200 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 254412 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 56341 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 310753 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.inst 791423 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 1120930 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 298012 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 284420 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2494785 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 791423 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 1120930 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 298012 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 284420 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2494785 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.015063 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.314197 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.011479 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.007677 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.132484 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.946402 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.865997 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.931700 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.580247 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.756303 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.685000 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.421682 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.238760 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.388518 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.inst 0.015063 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.338592 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.011479 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.053453 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.164376 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.inst 0.015063 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.338592 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.011479 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.053453 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.164376 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 59766.672259 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.data 43045.804148 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 64957.614733 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 64959.736722 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 44126.367717 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 185.346535 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 1810.444874 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 461.538462 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 6659.574468 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 1261.111111 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 3113.138686 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 71998.112434 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 107865.559025 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 75994.442282 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 59766.672259 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 51229.523789 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 64957.614733 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 102923.896534 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 53508.683606 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 59766.672259 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 51229.523789 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 64957.614733 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 102923.896534 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 53508.683606 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -379,122 +379,125 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 79759 # number of writebacks -system.l2c.writebacks::total 79759 # number of writebacks +system.l2c.writebacks::writebacks 80445 # number of writebacks +system.l2c.writebacks::total 80445 # number of writebacks system.l2c.ReadReq_mshr_hits::cpu0.inst 1 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu1.inst 17 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu1.inst 16 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu1.data 1 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::total 18 # number of ReadReq MSHR hits system.l2c.demand_mshr_hits::cpu0.inst 1 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1.inst 17 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1.inst 16 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1.data 1 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_hits::total 18 # number of demand (read+write) MSHR hits system.l2c.overall_mshr_hits::cpu0.inst 1 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1.inst 17 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1.inst 16 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1.data 1 # number of overall MSHR hits system.l2c.overall_mshr_hits::total 18 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu0.inst 12328 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.data 272557 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 3026 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 1706 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 289617 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 2549 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 508 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 3057 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 48 # number of SCUpgradeReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.inst 11920 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.data 272257 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.inst 3405 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 1750 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 289332 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 2525 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 517 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 3042 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 47 # number of SCUpgradeReq MSHR misses system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 90 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 138 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 103909 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 15834 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 119743 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 12328 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 376466 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 3026 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 17540 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 409360 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 12328 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 376466 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 3026 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 17540 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 409360 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 583232769 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.data 8178123323 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 160268481 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 113657266 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 9035281839 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 25542512 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 5088001 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 30630513 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 501546 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 901090 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 1402636 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 6022075568 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 1425456611 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 7447532179 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 583232769 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 14200198891 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 160268481 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 1539113877 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 16482814018 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 583232769 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 14200198891 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 160268481 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 1539113877 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 16482814018 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 936128000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 454553000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 1390681000 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1589336500 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 869577500 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 2458914000 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 2525464500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 1324130500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 3849595000 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.019158 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.386142 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.006645 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.004144 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.130669 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.950765 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.855219 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.933435 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.592593 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.720000 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.669903 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.460984 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.174570 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.378802 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.019158 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.404257 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.006645 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.034913 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.161641 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.019158 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.404257 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.006645 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.034913 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.161641 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 47309.601639 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 30005.185422 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 52963.807336 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 66622.078546 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 31197.346285 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10020.601020 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10015.750000 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10019.794897 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10448.875000 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10012.111111 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10164.028986 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 57955.283642 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 90025.048061 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 62195.971197 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 47309.601639 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 37719.738014 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 52963.807336 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 87748.795724 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 40264.837840 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 47309.601639 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 37719.738014 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 52963.807336 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 87748.795724 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40264.837840 # average overall mshr miss latency +system.l2c.SCUpgradeReq_mshr_misses::total 137 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 107281 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 13452 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 120733 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 11920 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 379538 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 3405 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 15202 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 410065 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 11920 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 379538 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 3405 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 15202 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 410065 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 561911095 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.data 8192955588 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 178565558 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 113324293 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 9046756534 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 25301493 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 5294512 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 30596005 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 516543 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 904088 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 1420631 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 6410159669 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 1283732505 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 7693892174 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 561911095 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 14603115257 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 178565558 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 1397056798 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 16740648708 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 561911095 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 14603115257 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 178565558 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 1397056798 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 16740648708 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 936053000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 455620500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 1391673500 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1587348000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 874199500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 2461547500 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 2523401000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 1329820000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 3853221000 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015061 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.314197 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.011426 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.007673 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.132476 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.946402 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.865997 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.931700 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.580247 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.756303 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.685000 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.421682 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.238760 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.388518 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015061 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.338592 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.011426 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.053449 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.164369 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015061 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.338592 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.011426 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.053449 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.164369 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 47140.192534 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 30092.727048 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 52442.160940 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 64756.738857 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 31267.735798 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10020.393267 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10240.835590 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10057.858317 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10990.276596 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10045.422222 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10369.569343 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 59751.117803 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 95430.605486 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 63726.505380 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 47140.192534 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 38476.029428 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 52442.160940 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 91899.539403 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40824.378350 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 47140.192534 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 38476.029428 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 52442.160940 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 91899.539403 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40824.378350 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -505,39 +508,39 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.replacements 41699 # number of replacements -system.iocache.tagsinuse 0.478350 # Cycle average of tags in use +system.iocache.replacements 41695 # number of replacements +system.iocache.tagsinuse 0.486173 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.sampled_refs 41715 # Sample count of references to valid blocks. +system.iocache.sampled_refs 41711 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 1705464300000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::tsunami.ide 0.478350 # Average occupied blocks per requestor -system.iocache.occ_percent::tsunami.ide 0.029897 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.029897 # Average percentage of cache occupancy -system.iocache.ReadReq_misses::tsunami.ide 176 # number of ReadReq misses -system.iocache.ReadReq_misses::total 176 # number of ReadReq misses +system.iocache.warmup_cycle 1705465376000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::tsunami.ide 0.486173 # Average occupied blocks per requestor +system.iocache.occ_percent::tsunami.ide 0.030386 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.030386 # Average percentage of cache occupancy +system.iocache.ReadReq_misses::tsunami.ide 172 # number of ReadReq misses +system.iocache.ReadReq_misses::total 172 # number of ReadReq misses system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses -system.iocache.demand_misses::tsunami.ide 41728 # number of demand (read+write) misses -system.iocache.demand_misses::total 41728 # number of demand (read+write) misses -system.iocache.overall_misses::tsunami.ide 41728 # number of overall misses -system.iocache.overall_misses::total 41728 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 21268998 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 21268998 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 9523967806 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 9523967806 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 9545236804 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 9545236804 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 9545236804 # number of overall miss cycles -system.iocache.overall_miss_latency::total 9545236804 # number of overall miss cycles -system.iocache.ReadReq_accesses::tsunami.ide 176 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 176 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::tsunami.ide 41724 # number of demand (read+write) misses +system.iocache.demand_misses::total 41724 # number of demand (read+write) misses +system.iocache.overall_misses::tsunami.ide 41724 # number of overall misses +system.iocache.overall_misses::total 41724 # number of overall misses +system.iocache.ReadReq_miss_latency::tsunami.ide 20816998 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 20816998 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 9540304806 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 9540304806 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 9561121804 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 9561121804 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 9561121804 # number of overall miss cycles +system.iocache.overall_miss_latency::total 9561121804 # number of overall miss cycles +system.iocache.ReadReq_accesses::tsunami.ide 172 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 172 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) -system.iocache.demand_accesses::tsunami.ide 41728 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 41728 # number of demand (read+write) accesses -system.iocache.overall_accesses::tsunami.ide 41728 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 41728 # number of overall (read+write) accesses +system.iocache.demand_accesses::tsunami.ide 41724 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 41724 # number of demand (read+write) accesses +system.iocache.overall_accesses::tsunami.ide 41724 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 41724 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses @@ -546,40 +549,40 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 120846.579545 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 120846.579545 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 229206.002262 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 229206.002262 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 228748.964820 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 228748.964820 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 228748.964820 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 228748.964820 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 193065 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 121029.058140 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 121029.058140 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 229599.172266 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 229599.172266 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 229151.610680 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 229151.610680 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 229151.610680 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 229151.610680 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 192730 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 23193 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 23021 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8.324279 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 8.371921 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 41523 # number of writebacks system.iocache.writebacks::total 41523 # number of writebacks -system.iocache.ReadReq_mshr_misses::tsunami.ide 176 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 176 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::tsunami.ide 172 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 172 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses::tsunami.ide 41728 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 41728 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::tsunami.ide 41728 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 41728 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12116000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 12116000 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 7361197521 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 7361197521 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 7373313521 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 7373313521 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 7373313521 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 7373313521 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::tsunami.ide 41724 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 41724 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::tsunami.ide 41724 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 41724 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11872000 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 11872000 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 7377518046 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 7377518046 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 7389390046 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 7389390046 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 7389390046 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 7389390046 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -588,14 +591,14 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68840.909091 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 68840.909091 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 177156.274572 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 177156.274572 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 176699.422953 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 176699.422953 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 176699.422953 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 176699.422953 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 69023.255814 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 69023.255814 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 177549.048084 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 177549.048084 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 177101.669207 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 177101.669207 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 177101.669207 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 177101.669207 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -613,22 +616,22 @@ system.cpu0.dtb.fetch_hits 0 # IT system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 7007258 # DTB read hits -system.cpu0.dtb.read_misses 29214 # DTB read misses -system.cpu0.dtb.read_acv 555 # DTB read access violations -system.cpu0.dtb.read_accesses 627494 # DTB read accesses -system.cpu0.dtb.write_hits 4619142 # DTB write hits -system.cpu0.dtb.write_misses 6985 # DTB write misses -system.cpu0.dtb.write_acv 345 # DTB write access violations -system.cpu0.dtb.write_accesses 208744 # DTB write accesses -system.cpu0.dtb.data_hits 11626400 # DTB hits -system.cpu0.dtb.data_misses 36199 # DTB misses -system.cpu0.dtb.data_acv 900 # DTB access violations -system.cpu0.dtb.data_accesses 836238 # DTB accesses -system.cpu0.itb.fetch_hits 888386 # ITB hits -system.cpu0.itb.fetch_misses 27286 # ITB misses -system.cpu0.itb.fetch_acv 998 # ITB acv -system.cpu0.itb.fetch_accesses 915672 # ITB accesses +system.cpu0.dtb.read_hits 7996955 # DTB read hits +system.cpu0.dtb.read_misses 29938 # DTB read misses +system.cpu0.dtb.read_acv 553 # DTB read access violations +system.cpu0.dtb.read_accesses 624438 # DTB read accesses +system.cpu0.dtb.write_hits 5309744 # DTB write hits +system.cpu0.dtb.write_misses 7955 # DTB write misses +system.cpu0.dtb.write_acv 319 # DTB write access violations +system.cpu0.dtb.write_accesses 207916 # DTB write accesses +system.cpu0.dtb.data_hits 13306699 # DTB hits +system.cpu0.dtb.data_misses 37893 # DTB misses +system.cpu0.dtb.data_acv 872 # DTB access violations +system.cpu0.dtb.data_accesses 832354 # DTB accesses +system.cpu0.itb.fetch_hits 944692 # ITB hits +system.cpu0.itb.fetch_misses 28693 # ITB misses +system.cpu0.itb.fetch_acv 988 # ITB acv +system.cpu0.itb.fetch_accesses 973385 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -641,277 +644,277 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 83155415 # number of cpu cycles simulated +system.cpu0.numCycles 92901317 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.BPredUnit.lookups 9804849 # Number of BP lookups -system.cpu0.BPredUnit.condPredicted 8272695 # Number of conditional branches predicted -system.cpu0.BPredUnit.condIncorrect 286303 # Number of conditional branches incorrect -system.cpu0.BPredUnit.BTBLookups 6905955 # Number of BTB lookups -system.cpu0.BPredUnit.BTBHits 4307856 # Number of BTB hits +system.cpu0.BPredUnit.lookups 11220993 # Number of BP lookups +system.cpu0.BPredUnit.condPredicted 9498823 # Number of conditional branches predicted +system.cpu0.BPredUnit.condIncorrect 301088 # Number of conditional branches incorrect +system.cpu0.BPredUnit.BTBLookups 7731310 # Number of BTB lookups +system.cpu0.BPredUnit.BTBHits 4807164 # Number of BTB hits system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.BPredUnit.usedRAS 619842 # Number of times the RAS was used to get a target. -system.cpu0.BPredUnit.RASInCorrect 27789 # Number of incorrect RAS predictions. -system.cpu0.fetch.icacheStallCycles 19011041 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 50915714 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 9804849 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 4927698 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 9659436 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 1473505 # Number of cycles fetch has spent squashing -system.cpu0.fetch.BlockedCycles 28455218 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 29555 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 194299 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 211367 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 143 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 6349535 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 190370 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.rateDist::samples 58504859 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.870282 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.201063 # Number of instructions fetched each cycle (Total) +system.cpu0.BPredUnit.usedRAS 696053 # Number of times the RAS was used to get a target. +system.cpu0.BPredUnit.RASInCorrect 31347 # Number of incorrect RAS predictions. +system.cpu0.fetch.icacheStallCycles 22682478 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 57580156 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 11220993 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 5503217 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 10836671 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 1573403 # Number of cycles fetch has spent squashing +system.cpu0.fetch.BlockedCycles 32658351 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 28974 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 198560 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 186652 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 190 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 6976582 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 207142 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.rateDist::samples 67595352 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.851836 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.189286 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 48845423 83.49% 83.49% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 638375 1.09% 84.58% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 1232766 2.11% 86.69% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 545499 0.93% 87.62% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 2228588 3.81% 91.43% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 432839 0.74% 92.17% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 448017 0.77% 92.94% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 658155 1.12% 94.06% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 3475197 5.94% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 56758681 83.97% 83.97% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 707820 1.05% 85.02% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 1385949 2.05% 87.07% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 615643 0.91% 87.98% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 2401218 3.55% 91.53% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 457628 0.68% 92.21% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 501258 0.74% 92.95% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 784291 1.16% 94.11% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 3982864 5.89% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 58504859 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.117910 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.612296 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 20221803 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 27858596 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 8736076 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 771700 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 916683 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 397847 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 27467 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 49800366 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 84499 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 916683 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 21025049 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 10730618 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 14396247 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 8233599 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 3202661 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 46975607 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 6729 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 282251 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 1314603 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.RenamedOperands 31610949 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 57450568 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 57189305 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 261263 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 27436892 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 4174049 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 1166690 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 177857 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 8656888 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 7389019 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 4877617 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 925746 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 640404 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 41641305 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1430691 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 40525941 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 100515 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 4996937 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 2778091 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 970759 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 58504859 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.692694 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.328093 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 67595352 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.120784 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.619799 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 23783356 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 32156359 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 9819480 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 864593 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 971563 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 447466 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 32236 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 56434658 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 99123 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 971563 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 24717335 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 12372612 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 16597679 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 9220139 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 3716022 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 53261468 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 6752 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 462341 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 1402867 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.RenamedOperands 35633564 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 64862965 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 64519168 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 343797 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 31292257 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 4341299 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 1345733 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 201778 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 10181749 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 8375667 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 5571987 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1008121 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 649590 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 47223004 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1661663 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 46145441 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 96356 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 5312296 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 2839377 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 1124463 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 67595352 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.682672 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.326673 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 40198625 68.71% 68.71% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 8496961 14.52% 83.23% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 3824833 6.54% 89.77% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 2421122 4.14% 93.91% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 1801555 3.08% 96.99% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 974491 1.67% 98.65% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 509636 0.87% 99.53% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 241631 0.41% 99.94% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 36005 0.06% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 46917740 69.41% 69.41% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 9524699 14.09% 83.50% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 4257234 6.30% 89.80% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 2757377 4.08% 93.88% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2128651 3.15% 97.03% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1105682 1.64% 98.66% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 579516 0.86% 99.52% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 281591 0.42% 99.94% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 42862 0.06% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 58504859 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 67595352 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 54985 10.35% 10.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 0 0.00% 10.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 10.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 10.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 10.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 10.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 10.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 10.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 10.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 10.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 10.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 10.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 10.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 10.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 10.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 10.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 10.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 10.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 10.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 10.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 10.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 10.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 10.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 10.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 10.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 10.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 10.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 10.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 255079 48.00% 58.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 221355 41.65% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 67879 11.08% 11.08% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 0 0.00% 11.08% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 11.08% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 11.08% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 11.08% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 11.08% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 11.08% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 11.08% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 11.08% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 11.08% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 11.08% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 11.08% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 11.08% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 11.08% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 11.08% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 11.08% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 11.08% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 11.08% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 11.08% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 11.08% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 11.08% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 11.08% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 11.08% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 11.08% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 11.08% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 11.08% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 11.08% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.08% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 11.08% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 286167 46.73% 57.81% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 258352 42.19% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 3785 0.01% 0.01% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 27833265 68.68% 68.69% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 41848 0.10% 68.79% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.79% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 13219 0.03% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 1879 0.00% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 7301690 18.02% 86.85% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 4678009 11.54% 98.39% # Type of FU issued -system.cpu0.iq.FU_type_0::IprAccess 652246 1.61% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 3762 0.01% 0.01% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 31627354 68.54% 68.55% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 48263 0.10% 68.65% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.65% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 14877 0.03% 68.68% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.68% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.68% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.68% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 1879 0.00% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 8323640 18.04% 86.73% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 5371898 11.64% 98.37% # Type of FU issued +system.cpu0.iq.FU_type_0::IprAccess 753768 1.63% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 40525941 # Type of FU issued -system.cpu0.iq.rate 0.487352 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 531419 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.013113 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 139814106 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 47896052 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 39650626 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 374568 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 182665 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 177037 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 40857986 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 195589 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 455505 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 46145441 # Type of FU issued +system.cpu0.iq.rate 0.496715 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 612398 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.013271 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 160102230 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 53968976 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 45199549 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 492757 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 238910 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 232575 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 46496253 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 257824 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 502915 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1004949 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 2086 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 10010 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 405892 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1032397 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 2215 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 11166 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 416538 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 11959 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 139790 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 13927 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 141497 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 916683 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 7413565 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 614240 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 45518060 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 556785 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 7389019 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 4877617 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 1263664 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 539342 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 5760 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 10010 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 149941 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 281478 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 431419 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 40181745 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 7054742 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 344195 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 971563 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 8614462 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 715502 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 51740003 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 598208 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 8375667 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 5571987 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 1467274 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 578076 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 5429 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 11166 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 147373 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 320873 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 468246 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 45797277 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 8048095 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 348163 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 2446064 # number of nop insts executed -system.cpu0.iew.exec_refs 11690884 # number of memory reference insts executed -system.cpu0.iew.exec_branches 6330042 # Number of branches executed -system.cpu0.iew.exec_stores 4636142 # Number of stores executed -system.cpu0.iew.exec_rate 0.483213 # Inst execution rate -system.cpu0.iew.wb_sent 39909560 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 39827663 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 19855593 # num instructions producing a value -system.cpu0.iew.wb_consumers 26361633 # num instructions consuming a value +system.cpu0.iew.exec_nop 2855336 # number of nop insts executed +system.cpu0.iew.exec_refs 13377753 # number of memory reference insts executed +system.cpu0.iew.exec_branches 7249094 # Number of branches executed +system.cpu0.iew.exec_stores 5329658 # Number of stores executed +system.cpu0.iew.exec_rate 0.492967 # Inst execution rate +system.cpu0.iew.wb_sent 45516467 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 45432124 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 22555336 # num instructions producing a value +system.cpu0.iew.wb_consumers 30242853 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.478955 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.753200 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.489036 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.745807 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 5375485 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 459932 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 404147 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 57588176 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.695477 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.605159 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 5732411 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 537200 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 438547 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 66623789 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.689159 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.608194 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 42371011 73.58% 73.58% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 6488229 11.27% 84.84% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 3374360 5.86% 90.70% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 1907115 3.31% 94.01% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 1044719 1.81% 95.83% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 416558 0.72% 96.55% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 355194 0.62% 97.17% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 347785 0.60% 97.77% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1283205 2.23% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 49353923 74.08% 74.08% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 7278183 10.92% 85.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 3860099 5.79% 90.80% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 2143933 3.22% 94.01% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 1188584 1.78% 95.80% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 481737 0.72% 96.52% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 414393 0.62% 97.14% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 388678 0.58% 97.73% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1514259 2.27% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 57588176 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 40051259 # Number of instructions committed -system.cpu0.commit.committedOps 40051259 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 66623789 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 45914377 # Number of instructions committed +system.cpu0.commit.committedOps 45914377 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 10855795 # Number of memory references committed -system.cpu0.commit.loads 6384070 # Number of loads committed -system.cpu0.commit.membars 151085 # Number of memory barriers committed -system.cpu0.commit.branches 6007416 # Number of branches committed -system.cpu0.commit.fp_insts 174841 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 37190024 # Number of committed integer instructions. -system.cpu0.commit.function_calls 489523 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 1283205 # number cycles where commit BW limit reached +system.cpu0.commit.refs 12498719 # Number of memory references committed +system.cpu0.commit.loads 7343270 # Number of loads committed +system.cpu0.commit.membars 179286 # Number of memory barriers committed +system.cpu0.commit.branches 6902899 # Number of branches committed +system.cpu0.commit.fp_insts 230540 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 42546523 # Number of committed integer instructions. +system.cpu0.commit.function_calls 573621 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 1514259 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 101537476 # The number of ROB reads -system.cpu0.rob.rob_writes 91770556 # The number of ROB writes -system.cpu0.timesIdled 793139 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 24650556 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 3710654942 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 37835874 # Number of Instructions Simulated -system.cpu0.committedOps 37835874 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 37835874 # Number of Instructions Simulated -system.cpu0.cpi 2.197793 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.197793 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.455002 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.455002 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 52969279 # number of integer regfile reads -system.cpu0.int_regfile_writes 28937240 # number of integer regfile writes -system.cpu0.fp_regfile_reads 87038 # number of floating regfile reads -system.cpu0.fp_regfile_writes 87248 # number of floating regfile writes -system.cpu0.misc_regfile_reads 1306578 # number of misc regfile reads -system.cpu0.misc_regfile_writes 663412 # number of misc regfile writes +system.cpu0.rob.rob_reads 116563585 # The number of ROB reads +system.cpu0.rob.rob_writes 104266102 # The number of ROB writes +system.cpu0.timesIdled 937015 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 25305965 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 3702808960 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 43304295 # Number of Instructions Simulated +system.cpu0.committedOps 43304295 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 43304295 # Number of Instructions Simulated +system.cpu0.cpi 2.145314 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.145314 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.466132 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.466132 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 60234005 # number of integer regfile reads +system.cpu0.int_regfile_writes 32862786 # number of integer regfile writes +system.cpu0.fp_regfile_reads 114240 # number of floating regfile reads +system.cpu0.fp_regfile_writes 115409 # number of floating regfile writes +system.cpu0.misc_regfile_reads 1561000 # number of misc regfile reads +system.cpu0.misc_regfile_writes 765601 # number of misc regfile writes system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -943,245 +946,245 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.cpu0.icache.replacements 642913 # number of replacements -system.cpu0.icache.tagsinuse 510.325206 # Cycle average of tags in use -system.cpu0.icache.total_refs 5670885 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 643421 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 8.813646 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 20341529000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 510.325206 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.996729 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.996729 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 5670885 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 5670885 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 5670885 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 5670885 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 5670885 # number of overall hits -system.cpu0.icache.overall_hits::total 5670885 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 678650 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 678650 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 678650 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 678650 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 678650 # number of overall misses -system.cpu0.icache.overall_misses::total 678650 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 9582412994 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 9582412994 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 9582412994 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 9582412994 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 9582412994 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 9582412994 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 6349535 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 6349535 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 6349535 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 6349535 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 6349535 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 6349535 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.106882 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.106882 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.106882 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.106882 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.106882 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.106882 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14119.815802 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 14119.815802 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14119.815802 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 14119.815802 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14119.815802 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 14119.815802 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 2234 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 145 # number of cycles access was blocked -system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 15.406897 # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu0.icache.replacements 790851 # number of replacements +system.cpu0.icache.tagsinuse 510.328171 # Cycle average of tags in use +system.cpu0.icache.total_refs 6144778 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 791359 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 7.764843 # Average number of references to valid blocks. +system.cpu0.icache.warmup_cycle 20315369000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.occ_blocks::cpu0.inst 510.328171 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.996735 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.996735 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 6144778 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 6144778 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 6144778 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 6144778 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 6144778 # number of overall hits +system.cpu0.icache.overall_hits::total 6144778 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 831804 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 831804 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 831804 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 831804 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 831804 # number of overall misses +system.cpu0.icache.overall_misses::total 831804 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 11563264492 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 11563264492 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 11563264492 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 11563264492 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 11563264492 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 11563264492 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 6976582 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 6976582 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 6976582 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 6976582 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 6976582 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 6976582 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.119228 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.119228 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.119228 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.119228 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.119228 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.119228 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13901.429293 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13901.429293 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13901.429293 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13901.429293 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13901.429293 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13901.429293 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 2068 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 1976 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 129 # number of cycles access was blocked +system.cpu0.icache.blocked::no_targets 2 # number of cycles access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 16.031008 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets 988 # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 35068 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 35068 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 35068 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 35068 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 35068 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 35068 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 643582 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 643582 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 643582 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 643582 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 643582 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 643582 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 7877266496 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 7877266496 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 7877266496 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 7877266496 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 7877266496 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 7877266496 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.101359 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.101359 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.101359 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.101359 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.101359 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.101359 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12239.724691 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12239.724691 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12239.724691 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12239.724691 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12239.724691 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12239.724691 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 40285 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 40285 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 40285 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 40285 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 40285 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 40285 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 791519 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 791519 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 791519 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 791519 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 791519 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 791519 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 9521125993 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 9521125993 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 9521125993 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 9521125993 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 9521125993 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 9521125993 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.113454 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.113454 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.113454 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.113454 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.113454 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.113454 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12028.929177 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12028.929177 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12028.929177 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12028.929177 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12028.929177 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12028.929177 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 932591 # number of replacements -system.cpu0.dcache.tagsinuse 478.331784 # Cycle average of tags in use -system.cpu0.dcache.total_refs 8251917 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 933103 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 8.843522 # Average number of references to valid blocks. -system.cpu0.dcache.warmup_cycle 21811000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 478.331784 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.934242 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.934242 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 5164945 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 5164945 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 2787881 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 2787881 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 136688 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 136688 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 157014 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 157014 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 7952826 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 7952826 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 7952826 # number of overall hits -system.cpu0.dcache.overall_hits::total 7952826 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 1127907 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1127907 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1514074 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1514074 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 12708 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 12708 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 640 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 640 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 2641981 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 2641981 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 2641981 # number of overall misses -system.cpu0.dcache.overall_misses::total 2641981 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 26996447000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 26996447000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 62901501244 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 62901501244 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 187201000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 187201000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 3956000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 3956000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 89897948244 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 89897948244 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 89897948244 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 89897948244 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 6292852 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 6292852 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 4301955 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 4301955 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 149396 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 149396 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 157654 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 157654 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 10594807 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 10594807 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 10594807 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 10594807 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.179236 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.179236 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.351950 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.351950 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.085063 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.085063 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.004060 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.004060 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.249366 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.249366 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.249366 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.249366 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 23934.993754 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 23934.993754 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 41544.535633 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 41544.535633 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14730.956878 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14730.956878 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6181.250000 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6181.250000 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 34026.720194 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 34026.720194 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 34026.720194 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 34026.720194 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 2213633 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 2219 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 43644 # number of cycles access was blocked +system.cpu0.dcache.replacements 1122816 # number of replacements +system.cpu0.dcache.tagsinuse 467.302243 # Cycle average of tags in use +system.cpu0.dcache.total_refs 9451134 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 1123328 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 8.413512 # Average number of references to valid blocks. +system.cpu0.dcache.warmup_cycle 21802000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.occ_blocks::cpu0.data 467.302243 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.912700 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.912700 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 5816576 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 5816576 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3291002 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 3291002 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 156681 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 156681 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 180603 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 180603 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 9107578 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 9107578 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 9107578 # number of overall hits +system.cpu0.dcache.overall_hits::total 9107578 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 1395487 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1395487 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1670757 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1670757 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 17192 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 17192 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 672 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 672 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 3066244 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 3066244 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 3066244 # number of overall misses +system.cpu0.dcache.overall_misses::total 3066244 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 31388896500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 31388896500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 67591366614 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 67591366614 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 251807000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 251807000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4105000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 4105000 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 98980263114 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 98980263114 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 98980263114 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 98980263114 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 7212063 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 7212063 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 4961759 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 4961759 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 173873 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 173873 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 181275 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 181275 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 12173822 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 12173822 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 12173822 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 12173822 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.193493 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.193493 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.336727 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.336727 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.098877 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.098877 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.003707 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.003707 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.251872 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.251872 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.251872 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.251872 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 22493.148628 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 22493.148628 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 40455.533997 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 40455.533997 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14646.754304 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14646.754304 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6108.630952 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6108.630952 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 32280.621866 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 32280.621866 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 32280.621866 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 32280.621866 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 2359081 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 919 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 46623 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 7 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 50.720214 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 317 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 50.599082 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 131.285714 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 453711 # number of writebacks -system.cpu0.dcache.writebacks::total 453711 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 427154 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 427154 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1285155 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1285155 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 3146 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 3146 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1712309 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 1712309 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1712309 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 1712309 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 700753 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 700753 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 228919 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 228919 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9562 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9562 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 640 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 640 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 929672 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 929672 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 929672 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 929672 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 17299108000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 17299108000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 9077949457 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 9077949457 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 117930500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 117930500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 2676000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 2676000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 26377057457 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 26377057457 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 26377057457 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 26377057457 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 998607000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 998607000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1686748998 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1686748998 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 2685355998 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 2685355998 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.111357 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.111357 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.053213 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.053213 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.064004 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.064004 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.004060 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.004060 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.087748 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.087748 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.087748 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.087748 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 24686.455855 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 24686.455855 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 39655.727384 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 39655.727384 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12333.246183 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12333.246183 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4181.250000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4181.250000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 28372.433995 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 28372.433995 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 28372.433995 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 28372.433995 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 614637 # number of writebacks +system.cpu0.dcache.writebacks::total 614637 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 536909 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 536909 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1412908 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1412908 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 3986 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 3986 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1949817 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1949817 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1949817 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1949817 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 858578 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 858578 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 257849 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 257849 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 13206 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 13206 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 672 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 672 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 1116427 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 1116427 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 1116427 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 1116427 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 19432503500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 19432503500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 9843225287 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 9843225287 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 161840000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 161840000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 2761000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 2761000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 29275728787 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 29275728787 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 29275728787 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 29275728787 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 998479000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 998479000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1684532498 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1684532498 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 2683011498 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 2683011498 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.119047 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.119047 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.051967 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.051967 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.075952 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.075952 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.003707 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.003707 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.091707 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.091707 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.091707 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.091707 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 22633.358297 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 22633.358297 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 38174.378365 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 38174.378365 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12255.035590 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12255.035590 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4108.630952 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4108.630952 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 26222.698651 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 26222.698651 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 26222.698651 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 26222.698651 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1193,22 +1196,22 @@ system.cpu1.dtb.fetch_hits 0 # IT system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 3713266 # DTB read hits -system.cpu1.dtb.read_misses 14359 # DTB read misses -system.cpu1.dtb.read_acv 33 # DTB read access violations -system.cpu1.dtb.read_accesses 328215 # DTB read accesses -system.cpu1.dtb.write_hits 2351870 # DTB write hits -system.cpu1.dtb.write_misses 2326 # DTB write misses -system.cpu1.dtb.write_acv 62 # DTB write access violations -system.cpu1.dtb.write_accesses 130566 # DTB write accesses -system.cpu1.dtb.data_hits 6065136 # DTB hits -system.cpu1.dtb.data_misses 16685 # DTB misses -system.cpu1.dtb.data_acv 95 # DTB access violations -system.cpu1.dtb.data_accesses 458781 # DTB accesses -system.cpu1.itb.fetch_hits 552396 # ITB hits -system.cpu1.itb.fetch_misses 7861 # ITB misses -system.cpu1.itb.fetch_acv 226 # ITB acv -system.cpu1.itb.fetch_accesses 560257 # ITB accesses +system.cpu1.dtb.read_hits 2657978 # DTB read hits +system.cpu1.dtb.read_misses 12789 # DTB read misses +system.cpu1.dtb.read_acv 27 # DTB read access violations +system.cpu1.dtb.read_accesses 325192 # DTB read accesses +system.cpu1.dtb.write_hits 1642917 # DTB write hits +system.cpu1.dtb.write_misses 2443 # DTB write misses +system.cpu1.dtb.write_acv 63 # DTB write access violations +system.cpu1.dtb.write_accesses 132832 # DTB write accesses +system.cpu1.dtb.data_hits 4300895 # DTB hits +system.cpu1.dtb.data_misses 15232 # DTB misses +system.cpu1.dtb.data_acv 90 # DTB access violations +system.cpu1.dtb.data_accesses 458024 # DTB accesses +system.cpu1.itb.fetch_hits 468004 # ITB hits +system.cpu1.itb.fetch_misses 6860 # ITB misses +system.cpu1.itb.fetch_acv 223 # ITB acv +system.cpu1.itb.fetch_accesses 474864 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -1221,516 +1224,516 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 34615367 # number of cpu cycles simulated +system.cpu1.numCycles 24425153 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.BPredUnit.lookups 5312293 # Number of BP lookups -system.cpu1.BPredUnit.condPredicted 4360790 # Number of conditional branches predicted -system.cpu1.BPredUnit.condIncorrect 184753 # Number of conditional branches incorrect -system.cpu1.BPredUnit.BTBLookups 3627578 # Number of BTB lookups -system.cpu1.BPredUnit.BTBHits 1933378 # Number of BTB hits +system.cpu1.BPredUnit.lookups 3729082 # Number of BP lookups +system.cpu1.BPredUnit.condPredicted 3054181 # Number of conditional branches predicted +system.cpu1.BPredUnit.condIncorrect 119454 # Number of conditional branches incorrect +system.cpu1.BPredUnit.BTBLookups 2320080 # Number of BTB lookups +system.cpu1.BPredUnit.BTBHits 1316503 # Number of BTB hits system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.BPredUnit.usedRAS 383381 # Number of times the RAS was used to get a target. -system.cpu1.BPredUnit.RASInCorrect 19114 # Number of incorrect RAS predictions. -system.cpu1.fetch.icacheStallCycles 12153279 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 25592027 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 5312293 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 2316759 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 4666723 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 848042 # Number of cycles fetch has spent squashing -system.cpu1.fetch.BlockedCycles 13957627 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 25440 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 65073 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 147747 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 14 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 2992364 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 115997 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.rateDist::samples 31571084 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.810616 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.170872 # Number of instructions fetched each cycle (Total) +system.cpu1.BPredUnit.usedRAS 271618 # Number of times the RAS was used to get a target. +system.cpu1.BPredUnit.RASInCorrect 12328 # Number of incorrect RAS predictions. +system.cpu1.fetch.icacheStallCycles 8114039 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 17895154 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 3729082 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 1588121 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 3257696 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 589472 # Number of cycles fetch has spent squashing +system.cpu1.fetch.BlockedCycles 9888413 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 24413 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 65338 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 153630 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 457 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 2125846 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 78174 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.rateDist::samples 21892478 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.817411 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.179159 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 26904361 85.22% 85.22% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 276998 0.88% 86.10% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 593564 1.88% 87.98% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 353090 1.12% 89.09% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 710175 2.25% 91.34% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 234476 0.74% 92.09% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 277213 0.88% 92.96% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 377383 1.20% 94.16% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 1843824 5.84% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 18634782 85.12% 85.12% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 188286 0.86% 85.98% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 405463 1.85% 87.83% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 257415 1.18% 89.01% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 494265 2.26% 91.27% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 174627 0.80% 92.06% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 196879 0.90% 92.96% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 233860 1.07% 94.03% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 1306901 5.97% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 31571084 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.153466 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.739326 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 12173556 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 14265063 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 4322746 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 271541 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 538177 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 245868 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 17179 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 25069869 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 51217 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 538177 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 12622413 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 4307697 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 8552551 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 4022106 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 1528138 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 23469307 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 521 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 403073 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 318746 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.RenamedOperands 15460907 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 27951432 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 27722595 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 228837 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 13017644 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 2443263 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 711049 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 79879 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 4546986 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 3946391 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 2480141 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 398992 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 247125 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 20556503 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 873226 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 19920635 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 45889 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 3011838 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 1481780 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 622079 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 31571084 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.630977 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.308978 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 21892478 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.152674 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.732653 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 8206589 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 10101487 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 3024410 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 183126 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 376865 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 172901 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 11788 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 17533822 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 34638 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 376865 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 8509917 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 2827279 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 6300793 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 2835389 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 1042233 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 16406077 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 208 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 240400 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 230284 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.RenamedOperands 10874639 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 19629758 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 19484069 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 145689 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 9164172 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 1710467 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 526024 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 52355 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 3079996 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 2820928 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 1739172 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 303279 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 178063 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 14428831 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 617828 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 13962547 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 36109 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 2150385 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 1081456 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 443630 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 21892478 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.637778 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.318020 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 22947759 72.69% 72.69% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 3816292 12.09% 84.77% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 1671768 5.30% 90.07% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 1218822 3.86% 93.93% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 1072376 3.40% 97.33% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 425454 1.35% 98.67% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 262904 0.83% 99.51% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 135529 0.43% 99.94% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 20180 0.06% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 15854245 72.42% 72.42% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 2672796 12.21% 84.63% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 1184242 5.41% 90.04% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 847687 3.87% 93.91% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 726248 3.32% 97.23% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 300582 1.37% 98.60% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 191038 0.87% 99.47% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 101044 0.46% 99.93% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 14596 0.07% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 31571084 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 21892478 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 28274 8.56% 8.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 0 0.00% 8.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 8.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 8.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 8.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 8.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 8.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 8.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 8.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 8.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 8.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 8.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 8.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 8.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 8.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 8.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 8.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 8.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 8.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 8.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 8.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 8.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 8.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 8.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 8.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 8.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 8.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 8.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 166109 50.30% 58.86% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 135868 41.14% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 17685 7.13% 7.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 7.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 7.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 7.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 7.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 7.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 7.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 7.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 7.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 7.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 7.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 7.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 7.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 7.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 7.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 7.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 7.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 7.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 7.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 7.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 7.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 7.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 7.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 7.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 7.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 7.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 7.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 7.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 130361 52.59% 59.73% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 99827 40.27% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 3526 0.02% 0.02% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 13189448 66.21% 66.23% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 28632 0.14% 66.37% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 66.37% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 12556 0.06% 66.43% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 66.43% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 66.43% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 66.43% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 1763 0.01% 66.44% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 66.44% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 66.44% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 66.44% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 66.44% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 66.44% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 66.44% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 66.44% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 66.44% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 66.44% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 66.44% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.44% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 66.44% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.44% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.44% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.44% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.44% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.44% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.44% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 66.44% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.44% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.44% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 3884810 19.50% 85.94% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 2385812 11.98% 97.92% # Type of FU issued -system.cpu1.iq.FU_type_0::IprAccess 414088 2.08% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 3526 0.03% 0.03% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 9165178 65.64% 65.67% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 22201 0.16% 65.83% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 65.83% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 10896 0.08% 65.90% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 65.90% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 65.90% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 65.90% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 1763 0.01% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 2775695 19.88% 85.80% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 1670228 11.96% 97.76% # Type of FU issued +system.cpu1.iq.FU_type_0::IprAccess 313060 2.24% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 19920635 # Type of FU issued -system.cpu1.iq.rate 0.575485 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 330251 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.016578 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 71458593 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 24286363 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 19388343 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 329901 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 159417 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 155652 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 20074577 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 172783 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 184439 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 13962547 # Type of FU issued +system.cpu1.iq.rate 0.571646 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 247873 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.017753 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 49890568 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 17097827 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 13608739 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 210986 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 102380 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 99816 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 14096605 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 110289 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 133191 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 581301 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 1183 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 4340 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 230089 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 414475 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 850 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 3253 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 172072 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 6918 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 18073 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 4939 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 13663 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 538177 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 3253999 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 229517 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 22699099 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 268114 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 3946391 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 2480141 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 779721 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 89744 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 2529 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 4340 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 96593 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 181110 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 277703 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 19708494 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 3738657 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 212141 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 376865 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 2193720 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 124101 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 15871795 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 185768 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 2820928 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 1739172 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 554609 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 45814 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 2212 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 3253 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 57900 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 130435 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 188335 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 13825969 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 2678414 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 136578 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 1269370 # number of nop insts executed -system.cpu1.iew.exec_refs 6100523 # number of memory reference insts executed -system.cpu1.iew.exec_branches 3128191 # Number of branches executed -system.cpu1.iew.exec_stores 2361866 # Number of stores executed -system.cpu1.iew.exec_rate 0.569357 # Inst execution rate -system.cpu1.iew.wb_sent 19587937 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 19543995 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 9462232 # num instructions producing a value -system.cpu1.iew.wb_consumers 13383566 # num instructions consuming a value +system.cpu1.iew.exec_nop 825136 # number of nop insts executed +system.cpu1.iew.exec_refs 4329493 # number of memory reference insts executed +system.cpu1.iew.exec_branches 2168898 # Number of branches executed +system.cpu1.iew.exec_stores 1651079 # Number of stores executed +system.cpu1.iew.exec_rate 0.566055 # Inst execution rate +system.cpu1.iew.wb_sent 13745874 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 13708555 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 6651311 # num instructions producing a value +system.cpu1.iew.wb_consumers 9340604 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.564605 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.707004 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.561247 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.712086 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 3264810 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 251147 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 260251 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 31032907 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.624350 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.557822 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 2293261 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 174198 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 176022 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 21515613 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.628195 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.562431 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 23883562 76.96% 76.96% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 2995086 9.65% 86.61% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 1581522 5.10% 91.71% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 799862 2.58% 94.29% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 502768 1.62% 95.91% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 236983 0.76% 96.67% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 224339 0.72% 97.39% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 194617 0.63% 98.02% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 614168 1.98% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 16491806 76.65% 76.65% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 2174989 10.11% 86.76% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 1058158 4.92% 91.68% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 548223 2.55% 94.23% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 352308 1.64% 95.86% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 166690 0.77% 96.64% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 160522 0.75% 97.38% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 129128 0.60% 97.98% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 433789 2.02% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 31032907 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 19375400 # Number of instructions committed -system.cpu1.commit.committedOps 19375400 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 21515613 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 13515996 # Number of instructions committed +system.cpu1.commit.committedOps 13515996 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 5615142 # Number of memory references committed -system.cpu1.commit.loads 3365090 # Number of loads committed -system.cpu1.commit.membars 85627 # Number of memory barriers committed -system.cpu1.commit.branches 2912516 # Number of branches committed -system.cpu1.commit.fp_insts 154287 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 17850043 # Number of committed integer instructions. -system.cpu1.commit.function_calls 300496 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 614168 # number cycles where commit BW limit reached +system.cpu1.commit.refs 3973553 # Number of memory references committed +system.cpu1.commit.loads 2406453 # Number of loads committed +system.cpu1.commit.membars 57533 # Number of memory barriers committed +system.cpu1.commit.branches 2017672 # Number of branches committed +system.cpu1.commit.fp_insts 98521 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 12496541 # Number of committed integer instructions. +system.cpu1.commit.function_calls 216490 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 433789 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 52972716 # The number of ROB reads -system.cpu1.rob.rob_writes 45818344 # The number of ROB writes -system.cpu1.timesIdled 377037 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 3044283 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 3758611040 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 18256718 # Number of Instructions Simulated -system.cpu1.committedOps 18256718 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 18256718 # Number of Instructions Simulated -system.cpu1.cpi 1.896034 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.896034 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.527417 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.527417 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 25482349 # number of integer regfile reads -system.cpu1.int_regfile_writes 13944369 # number of integer regfile writes -system.cpu1.fp_regfile_reads 81651 # number of floating regfile reads -system.cpu1.fp_regfile_writes 82372 # number of floating regfile writes -system.cpu1.misc_regfile_reads 840995 # number of misc regfile reads -system.cpu1.misc_regfile_writes 357443 # number of misc regfile writes -system.cpu1.icache.replacements 454861 # number of replacements -system.cpu1.icache.tagsinuse 506.121737 # Cycle average of tags in use -system.cpu1.icache.total_refs 2515591 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 455373 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 5.524243 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 42848278000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 506.121737 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.988519 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.988519 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 2515591 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 2515591 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 2515591 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 2515591 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 2515591 # number of overall hits -system.cpu1.icache.overall_hits::total 2515591 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 476773 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 476773 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 476773 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 476773 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 476773 # number of overall misses -system.cpu1.icache.overall_misses::total 476773 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 6462749000 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 6462749000 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 6462749000 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 6462749000 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 6462749000 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 6462749000 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 2992364 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 2992364 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 2992364 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 2992364 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 2992364 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 2992364 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.159330 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.159330 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.159330 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.159330 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.159330 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.159330 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13555.190835 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13555.190835 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13555.190835 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13555.190835 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13555.190835 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13555.190835 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 884 # number of cycles access was blocked -system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 47 # number of cycles access was blocked -system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 18.808511 # average number of cycles each access was blocked -system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu1.rob.rob_reads 36803153 # The number of ROB reads +system.cpu1.rob.rob_writes 31994561 # The number of ROB writes +system.cpu1.timesIdled 237566 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 2532675 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 3770663279 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 12791729 # Number of Instructions Simulated +system.cpu1.committedOps 12791729 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 12791729 # Number of Instructions Simulated +system.cpu1.cpi 1.909449 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.909449 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.523711 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.523711 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 17892474 # number of integer regfile reads +system.cpu1.int_regfile_writes 9829261 # number of integer regfile writes +system.cpu1.fp_regfile_reads 54188 # number of floating regfile reads +system.cpu1.fp_regfile_writes 54153 # number of floating regfile writes +system.cpu1.misc_regfile_reads 586782 # number of misc regfile reads +system.cpu1.misc_regfile_writes 255768 # number of misc regfile writes +system.cpu1.icache.replacements 297472 # number of replacements +system.cpu1.icache.tagsinuse 505.689996 # Cycle average of tags in use +system.cpu1.icache.total_refs 1814154 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 297984 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 6.088092 # Average number of references to valid blocks. +system.cpu1.icache.warmup_cycle 42534295000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.occ_blocks::cpu1.inst 505.689996 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.987676 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.987676 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 1814154 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 1814154 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 1814154 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 1814154 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 1814154 # number of overall hits +system.cpu1.icache.overall_hits::total 1814154 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 311692 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 311692 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 311692 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 311692 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 311692 # number of overall misses +system.cpu1.icache.overall_misses::total 311692 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4307826496 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 4307826496 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 4307826496 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 4307826496 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 4307826496 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 4307826496 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 2125846 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 2125846 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 2125846 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 2125846 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 2125846 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 2125846 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.146620 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.146620 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.146620 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.146620 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.146620 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.146620 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13820.779795 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13820.779795 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13820.779795 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13820.779795 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13820.779795 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13820.779795 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 806 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles::no_targets 423 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 43 # number of cycles access was blocked +system.cpu1.icache.blocked::no_targets 1 # number of cycles access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 18.744186 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_targets 423 # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 21323 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 21323 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 21323 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 21323 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 21323 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 21323 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 455450 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 455450 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 455450 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 455450 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 455450 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 455450 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5356907000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 5356907000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5356907000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 5356907000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5356907000 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 5356907000 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.152204 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.152204 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.152204 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.152204 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.152204 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.152204 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11761.789439 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11761.789439 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11761.789439 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 11761.789439 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11761.789439 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11761.789439 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 13650 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 13650 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 13650 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 13650 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 13650 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 13650 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 298042 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 298042 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 298042 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 298042 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 298042 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 298042 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3567181997 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 3567181997 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3567181997 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 3567181997 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3567181997 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 3567181997 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.140199 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.140199 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.140199 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.140199 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.140199 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.140199 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11968.722519 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11968.722519 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11968.722519 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11968.722519 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11968.722519 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11968.722519 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 520860 # number of replacements -system.cpu1.dcache.tagsinuse 498.284346 # Cycle average of tags in use -system.cpu1.dcache.total_refs 4488456 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 521257 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 8.610831 # Average number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 31290571500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 498.284346 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.973212 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.973212 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 2711578 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 2711578 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 1652227 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 1652227 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 59380 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 59380 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 66046 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 66046 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 4363805 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 4363805 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 4363805 # number of overall hits -system.cpu1.dcache.overall_hits::total 4363805 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 735473 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 735473 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 523667 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 523667 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 12800 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 12800 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 689 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 689 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 1259140 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 1259140 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 1259140 # number of overall misses -system.cpu1.dcache.overall_misses::total 1259140 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 11275775500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 11275775500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 16995132775 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 16995132775 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 186282500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 186282500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 5003500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 5003500 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 28270908275 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 28270908275 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 28270908275 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 28270908275 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 3447051 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 3447051 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 2175894 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 2175894 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 72180 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 72180 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 66735 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 66735 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 5622945 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 5622945 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 5622945 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 5622945 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.213363 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.213363 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.240668 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.240668 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.177334 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.177334 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.010324 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.010324 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.223929 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.223929 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.223929 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.223929 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15331.324875 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 15331.324875 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 32454.083941 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 32454.083941 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14553.320312 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14553.320312 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7261.973875 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7261.973875 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 22452.553548 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 22452.553548 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 22452.553548 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 22452.553548 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 551348 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 10411 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 52.958217 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu1.dcache.replacements 296647 # number of replacements +system.cpu1.dcache.tagsinuse 497.527759 # Cycle average of tags in use +system.cpu1.dcache.total_refs 3293413 # Total number of references to valid blocks. +system.cpu1.dcache.sampled_refs 297044 # Sample count of references to valid blocks. +system.cpu1.dcache.avg_refs 11.087290 # Average number of references to valid blocks. +system.cpu1.dcache.warmup_cycle 36352469000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.occ_blocks::cpu1.data 497.527759 # Average occupied blocks per requestor +system.cpu1.dcache.occ_percent::cpu1.data 0.971734 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::total 0.971734 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 2035773 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 2035773 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 1175370 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 1175370 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 40064 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 40064 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 42523 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 42523 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 3211143 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 3211143 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 3211143 # number of overall hits +system.cpu1.dcache.overall_hits::total 3211143 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 433262 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 433262 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 341345 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 341345 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 7035 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 7035 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 719 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 719 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 774607 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 774607 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 774607 # number of overall misses +system.cpu1.dcache.overall_misses::total 774607 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 6736451500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 6736451500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 13519924674 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 13519924674 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 102051000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 102051000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 5076000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 5076000 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 20256376174 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 20256376174 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 20256376174 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 20256376174 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 2469035 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 2469035 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 1516715 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 1516715 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 47099 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 47099 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 43242 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 43242 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 3985750 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 3985750 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 3985750 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 3985750 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.175478 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.175478 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.225055 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.225055 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.149366 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.149366 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.016627 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.016627 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.194344 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.194344 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.194344 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.194344 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15548.216783 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 15548.216783 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 39607.800536 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 39607.800536 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14506.183369 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14506.183369 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7059.805285 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7059.805285 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 26150.520424 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 26150.520424 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 26150.520424 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 26150.520424 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 473544 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 3 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 7013 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 1 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 67.523742 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 3 # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 405697 # number of writebacks -system.cpu1.dcache.writebacks::total 405697 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 310580 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 310580 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 431476 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 431476 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 2432 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 2432 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 742056 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 742056 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 742056 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 742056 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 424893 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 424893 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 92191 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 92191 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 10368 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 10368 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 689 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 689 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 517084 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 517084 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 517084 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 517084 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 5584148500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 5584148500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2607634127 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2607634127 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 126008000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 126008000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 3625500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 3625500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 8191782627 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 8191782627 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 8191782627 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 8191782627 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 485715000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 485715000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 920480500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 920480500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1406195500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1406195500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.123263 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.123263 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.042369 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.042369 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.143641 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.143641 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.010324 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.010324 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.091960 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.091960 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.091960 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.091960 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13142.481754 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13142.481754 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 28285.126824 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 28285.126824 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12153.549383 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12153.549383 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5261.973875 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5261.973875 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15842.266686 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15842.266686 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15842.266686 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15842.266686 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 225448 # number of writebacks +system.cpu1.dcache.writebacks::total 225448 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 193837 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 193837 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 283225 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 283225 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1368 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1368 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 477062 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 477062 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 477062 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 477062 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 239425 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 239425 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 58120 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 58120 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5667 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5667 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 718 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 718 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 297545 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 297545 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 297545 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 297545 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 3123298500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 3123298500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2029112304 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2029112304 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 67015000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 67015000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 3640000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 3640000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 5152410804 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 5152410804 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5152410804 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 5152410804 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 486888000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 486888000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 925465000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 925465000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1412353000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1412353000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.096971 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.096971 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.038320 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.038320 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.120321 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.120321 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.016604 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.016604 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.074652 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.074652 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.074652 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.074652 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13044.997390 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13044.997390 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 34912.462216 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 34912.462216 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11825.480854 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11825.480854 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5069.637883 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5069.637883 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17316.408624 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17316.408624 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17316.408624 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17316.408624 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1739,170 +1742,170 @@ system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 4859 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 144961 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 48033 39.13% 39.13% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 133 0.11% 39.24% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1924 1.57% 40.81% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 16 0.01% 40.82% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 72639 59.18% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 122745 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 47372 48.94% 48.94% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::21 133 0.14% 49.07% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1924 1.99% 51.06% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::30 16 0.02% 51.08% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 47357 48.92% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 96802 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1866486525500 98.40% 98.40% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 63938000 0.00% 98.40% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 572947000 0.03% 98.43% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 8827500 0.00% 98.43% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 29774513500 1.57% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1896906751500 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.986239 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.inst.quiesce 4836 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 169372 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 58506 39.88% 39.88% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 135 0.09% 39.97% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::22 1925 1.31% 41.28% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::30 16 0.01% 41.29% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 86127 58.71% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 146709 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 57513 49.12% 49.12% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::21 135 0.12% 49.23% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::22 1925 1.64% 50.88% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::30 16 0.01% 50.89% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 57499 49.11% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 117088 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1866028984500 98.32% 98.32% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 63917500 0.00% 98.33% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 571228500 0.03% 98.36% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 8802500 0.00% 98.36% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 31183758000 1.64% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1897856691000 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.983027 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.651950 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.788643 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.syscall::2 7 3.32% 3.32% # number of syscalls executed -system.cpu0.kern.syscall::3 17 8.06% 11.37% # number of syscalls executed -system.cpu0.kern.syscall::4 4 1.90% 13.27% # number of syscalls executed -system.cpu0.kern.syscall::6 29 13.74% 27.01% # number of syscalls executed -system.cpu0.kern.syscall::12 1 0.47% 27.49% # number of syscalls executed -system.cpu0.kern.syscall::17 10 4.74% 32.23% # number of syscalls executed -system.cpu0.kern.syscall::19 7 3.32% 35.55% # number of syscalls executed -system.cpu0.kern.syscall::20 4 1.90% 37.44% # number of syscalls executed -system.cpu0.kern.syscall::23 1 0.47% 37.91% # number of syscalls executed -system.cpu0.kern.syscall::24 3 1.42% 39.34% # number of syscalls executed -system.cpu0.kern.syscall::33 8 3.79% 43.13% # number of syscalls executed -system.cpu0.kern.syscall::41 2 0.95% 44.08% # number of syscalls executed -system.cpu0.kern.syscall::45 37 17.54% 61.61% # number of syscalls executed -system.cpu0.kern.syscall::47 3 1.42% 63.03% # number of syscalls executed -system.cpu0.kern.syscall::48 8 3.79% 66.82% # number of syscalls executed -system.cpu0.kern.syscall::54 9 4.27% 71.09% # number of syscalls executed -system.cpu0.kern.syscall::58 1 0.47% 71.56% # number of syscalls executed -system.cpu0.kern.syscall::59 5 2.37% 73.93% # number of syscalls executed -system.cpu0.kern.syscall::71 27 12.80% 86.73% # number of syscalls executed -system.cpu0.kern.syscall::73 3 1.42% 88.15% # number of syscalls executed -system.cpu0.kern.syscall::74 7 3.32% 91.47% # number of syscalls executed -system.cpu0.kern.syscall::87 1 0.47% 91.94% # number of syscalls executed -system.cpu0.kern.syscall::90 2 0.95% 92.89% # number of syscalls executed -system.cpu0.kern.syscall::92 7 3.32% 96.21% # number of syscalls executed -system.cpu0.kern.syscall::97 2 0.95% 97.16% # number of syscalls executed -system.cpu0.kern.syscall::98 2 0.95% 98.10% # number of syscalls executed -system.cpu0.kern.syscall::132 1 0.47% 98.58% # number of syscalls executed -system.cpu0.kern.syscall::144 1 0.47% 99.05% # number of syscalls executed -system.cpu0.kern.syscall::147 2 0.95% 100.00% # number of syscalls executed -system.cpu0.kern.syscall::total 211 # number of syscalls executed +system.cpu0.kern.ipl_used::31 0.667607 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.798097 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.syscall::2 7 3.35% 3.35% # number of syscalls executed +system.cpu0.kern.syscall::3 17 8.13% 11.48% # number of syscalls executed +system.cpu0.kern.syscall::4 4 1.91% 13.40% # number of syscalls executed +system.cpu0.kern.syscall::6 29 13.88% 27.27% # number of syscalls executed +system.cpu0.kern.syscall::12 1 0.48% 27.75% # number of syscalls executed +system.cpu0.kern.syscall::17 9 4.31% 32.06% # number of syscalls executed +system.cpu0.kern.syscall::19 7 3.35% 35.41% # number of syscalls executed +system.cpu0.kern.syscall::20 4 1.91% 37.32% # number of syscalls executed +system.cpu0.kern.syscall::23 1 0.48% 37.80% # number of syscalls executed +system.cpu0.kern.syscall::24 3 1.44% 39.23% # number of syscalls executed +system.cpu0.kern.syscall::33 7 3.35% 42.58% # number of syscalls executed +system.cpu0.kern.syscall::41 2 0.96% 43.54% # number of syscalls executed +system.cpu0.kern.syscall::45 37 17.70% 61.24% # number of syscalls executed +system.cpu0.kern.syscall::47 3 1.44% 62.68% # number of syscalls executed +system.cpu0.kern.syscall::48 8 3.83% 66.51% # number of syscalls executed +system.cpu0.kern.syscall::54 9 4.31% 70.81% # number of syscalls executed +system.cpu0.kern.syscall::58 1 0.48% 71.29% # number of syscalls executed +system.cpu0.kern.syscall::59 5 2.39% 73.68% # number of syscalls executed +system.cpu0.kern.syscall::71 27 12.92% 86.60% # number of syscalls executed +system.cpu0.kern.syscall::73 3 1.44% 88.04% # number of syscalls executed +system.cpu0.kern.syscall::74 7 3.35% 91.39% # number of syscalls executed +system.cpu0.kern.syscall::87 1 0.48% 91.87% # number of syscalls executed +system.cpu0.kern.syscall::90 2 0.96% 92.82% # number of syscalls executed +system.cpu0.kern.syscall::92 7 3.35% 96.17% # number of syscalls executed +system.cpu0.kern.syscall::97 2 0.96% 97.13% # number of syscalls executed +system.cpu0.kern.syscall::98 2 0.96% 98.09% # number of syscalls executed +system.cpu0.kern.syscall::132 1 0.48% 98.56% # number of syscalls executed +system.cpu0.kern.syscall::144 1 0.48% 99.04% # number of syscalls executed +system.cpu0.kern.syscall::147 2 0.96% 100.00% # number of syscalls executed +system.cpu0.kern.syscall::total 209 # number of syscalls executed system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wripir 97 0.07% 0.08% # number of callpals executed -system.cpu0.kern.callpal::wrmces 1 0.00% 0.08% # number of callpals executed -system.cpu0.kern.callpal::wrfen 1 0.00% 0.08% # number of callpals executed -system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.08% # number of callpals executed -system.cpu0.kern.callpal::swpctx 2435 1.87% 1.95% # number of callpals executed -system.cpu0.kern.callpal::tbi 48 0.04% 1.98% # number of callpals executed -system.cpu0.kern.callpal::wrent 7 0.01% 1.99% # number of callpals executed -system.cpu0.kern.callpal::swpipl 116655 89.61% 91.60% # number of callpals executed -system.cpu0.kern.callpal::rdps 6417 4.93% 96.53% # number of callpals executed -system.cpu0.kern.callpal::wrkgp 1 0.00% 96.53% # number of callpals executed -system.cpu0.kern.callpal::wrusp 4 0.00% 96.54% # number of callpals executed -system.cpu0.kern.callpal::rdusp 8 0.01% 96.54% # number of callpals executed -system.cpu0.kern.callpal::whami 2 0.00% 96.54% # number of callpals executed -system.cpu0.kern.callpal::rti 4017 3.09% 99.63% # number of callpals executed -system.cpu0.kern.callpal::callsys 345 0.27% 99.89% # number of callpals executed -system.cpu0.kern.callpal::imb 137 0.11% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 130177 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 5807 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1287 # number of protection mode switches +system.cpu0.kern.callpal::wripir 100 0.06% 0.07% # number of callpals executed +system.cpu0.kern.callpal::wrmces 1 0.00% 0.07% # number of callpals executed +system.cpu0.kern.callpal::wrfen 1 0.00% 0.07% # number of callpals executed +system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.07% # number of callpals executed +system.cpu0.kern.callpal::swpctx 3082 1.99% 2.06% # number of callpals executed +system.cpu0.kern.callpal::tbi 48 0.03% 2.09% # number of callpals executed +system.cpu0.kern.callpal::wrent 7 0.00% 2.09% # number of callpals executed +system.cpu0.kern.callpal::swpipl 140299 90.69% 92.78% # number of callpals executed +system.cpu0.kern.callpal::rdps 6336 4.10% 96.88% # number of callpals executed +system.cpu0.kern.callpal::wrkgp 1 0.00% 96.88% # number of callpals executed +system.cpu0.kern.callpal::wrusp 3 0.00% 96.88% # number of callpals executed +system.cpu0.kern.callpal::rdusp 8 0.01% 96.89% # number of callpals executed +system.cpu0.kern.callpal::whami 2 0.00% 96.89% # number of callpals executed +system.cpu0.kern.callpal::rti 4335 2.80% 99.69% # number of callpals executed +system.cpu0.kern.callpal::callsys 342 0.22% 99.91% # number of callpals executed +system.cpu0.kern.callpal::imb 137 0.09% 100.00% # number of callpals executed +system.cpu0.kern.callpal::total 154704 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 6439 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1272 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1286 -system.cpu0.kern.mode_good::user 1287 +system.cpu0.kern.mode_good::kernel 1271 +system.cpu0.kern.mode_good::user 1272 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.221457 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.197391 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.362701 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1894993254500 99.90% 99.90% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 1913489000 0.10% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.329789 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1895973773500 99.90% 99.90% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 1882909500 0.10% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 2436 # number of times the context was actually changed +system.cpu0.kern.swap_context 3083 # number of times the context was actually changed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 3786 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 92502 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 33560 40.13% 40.13% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1921 2.30% 42.42% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 97 0.12% 42.54% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 48058 57.46% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 83636 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 32844 48.58% 48.58% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1921 2.84% 51.42% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 97 0.14% 51.56% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 32747 48.44% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 67609 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1867334401000 98.46% 98.46% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 533283000 0.03% 98.48% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 45472500 0.00% 98.49% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 28701925000 1.51% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1896615081500 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.978665 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.quiesce 3800 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 68195 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 23112 38.67% 38.67% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1924 3.22% 41.89% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::30 100 0.17% 42.06% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 34629 57.94% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 59765 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 22728 47.97% 47.97% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1924 4.06% 52.03% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 100 0.21% 52.24% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 22629 47.76% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 47381 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1870052426500 98.55% 98.55% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 533448500 0.03% 98.58% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 47034500 0.00% 98.58% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 26913191500 1.42% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1897546101000 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.983385 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.681406 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.808372 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.syscall::2 1 0.87% 0.87% # number of syscalls executed -system.cpu1.kern.syscall::3 13 11.30% 12.17% # number of syscalls executed -system.cpu1.kern.syscall::6 13 11.30% 23.48% # number of syscalls executed -system.cpu1.kern.syscall::15 1 0.87% 24.35% # number of syscalls executed -system.cpu1.kern.syscall::17 5 4.35% 28.70% # number of syscalls executed -system.cpu1.kern.syscall::19 3 2.61% 31.30% # number of syscalls executed -system.cpu1.kern.syscall::20 2 1.74% 33.04% # number of syscalls executed -system.cpu1.kern.syscall::23 3 2.61% 35.65% # number of syscalls executed -system.cpu1.kern.syscall::24 3 2.61% 38.26% # number of syscalls executed -system.cpu1.kern.syscall::33 3 2.61% 40.87% # number of syscalls executed -system.cpu1.kern.syscall::45 17 14.78% 55.65% # number of syscalls executed -system.cpu1.kern.syscall::47 3 2.61% 58.26% # number of syscalls executed -system.cpu1.kern.syscall::48 2 1.74% 60.00% # number of syscalls executed -system.cpu1.kern.syscall::54 1 0.87% 60.87% # number of syscalls executed -system.cpu1.kern.syscall::59 2 1.74% 62.61% # number of syscalls executed -system.cpu1.kern.syscall::71 27 23.48% 86.09% # number of syscalls executed -system.cpu1.kern.syscall::74 9 7.83% 93.91% # number of syscalls executed -system.cpu1.kern.syscall::90 1 0.87% 94.78% # number of syscalls executed -system.cpu1.kern.syscall::92 2 1.74% 96.52% # number of syscalls executed -system.cpu1.kern.syscall::132 3 2.61% 99.13% # number of syscalls executed -system.cpu1.kern.syscall::144 1 0.87% 100.00% # number of syscalls executed -system.cpu1.kern.syscall::total 115 # number of syscalls executed +system.cpu1.kern.ipl_used::31 0.653470 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.792788 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.syscall::2 1 0.85% 0.85% # number of syscalls executed +system.cpu1.kern.syscall::3 13 11.11% 11.97% # number of syscalls executed +system.cpu1.kern.syscall::6 13 11.11% 23.08% # number of syscalls executed +system.cpu1.kern.syscall::15 1 0.85% 23.93% # number of syscalls executed +system.cpu1.kern.syscall::17 6 5.13% 29.06% # number of syscalls executed +system.cpu1.kern.syscall::19 3 2.56% 31.62% # number of syscalls executed +system.cpu1.kern.syscall::20 2 1.71% 33.33% # number of syscalls executed +system.cpu1.kern.syscall::23 3 2.56% 35.90% # number of syscalls executed +system.cpu1.kern.syscall::24 3 2.56% 38.46% # number of syscalls executed +system.cpu1.kern.syscall::33 4 3.42% 41.88% # number of syscalls executed +system.cpu1.kern.syscall::45 17 14.53% 56.41% # number of syscalls executed +system.cpu1.kern.syscall::47 3 2.56% 58.97% # number of syscalls executed +system.cpu1.kern.syscall::48 2 1.71% 60.68% # number of syscalls executed +system.cpu1.kern.syscall::54 1 0.85% 61.54% # number of syscalls executed +system.cpu1.kern.syscall::59 2 1.71% 63.25% # number of syscalls executed +system.cpu1.kern.syscall::71 27 23.08% 86.32% # number of syscalls executed +system.cpu1.kern.syscall::74 9 7.69% 94.02% # number of syscalls executed +system.cpu1.kern.syscall::90 1 0.85% 94.87% # number of syscalls executed +system.cpu1.kern.syscall::92 2 1.71% 96.58% # number of syscalls executed +system.cpu1.kern.syscall::132 3 2.56% 99.15% # number of syscalls executed +system.cpu1.kern.syscall::144 1 0.85% 100.00% # number of syscalls executed +system.cpu1.kern.syscall::total 117 # number of syscalls executed system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal::wripir 16 0.02% 0.02% # number of callpals executed -system.cpu1.kern.callpal::wrmces 1 0.00% 0.02% # number of callpals executed -system.cpu1.kern.callpal::wrfen 1 0.00% 0.02% # number of callpals executed -system.cpu1.kern.callpal::swpctx 1813 2.11% 2.13% # number of callpals executed -system.cpu1.kern.callpal::tbi 6 0.01% 2.14% # number of callpals executed -system.cpu1.kern.callpal::wrent 7 0.01% 2.14% # number of callpals executed -system.cpu1.kern.callpal::swpipl 78432 91.18% 93.32% # number of callpals executed -system.cpu1.kern.callpal::rdps 2336 2.72% 96.04% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 96.04% # number of callpals executed -system.cpu1.kern.callpal::wrusp 3 0.00% 96.04% # number of callpals executed -system.cpu1.kern.callpal::rdusp 1 0.00% 96.04% # number of callpals executed -system.cpu1.kern.callpal::whami 3 0.00% 96.05% # number of callpals executed -system.cpu1.kern.callpal::rti 3185 3.70% 99.75% # number of callpals executed -system.cpu1.kern.callpal::callsys 172 0.20% 99.95% # number of callpals executed -system.cpu1.kern.callpal::imb 43 0.05% 100.00% # number of callpals executed +system.cpu1.kern.callpal::wripir 16 0.03% 0.03% # number of callpals executed +system.cpu1.kern.callpal::wrmces 1 0.00% 0.03% # number of callpals executed +system.cpu1.kern.callpal::wrfen 1 0.00% 0.03% # number of callpals executed +system.cpu1.kern.callpal::swpctx 1165 1.89% 1.92% # number of callpals executed +system.cpu1.kern.callpal::tbi 6 0.01% 1.93% # number of callpals executed +system.cpu1.kern.callpal::wrent 7 0.01% 1.94% # number of callpals executed +system.cpu1.kern.callpal::swpipl 54867 89.09% 91.04% # number of callpals executed +system.cpu1.kern.callpal::rdps 2419 3.93% 94.96% # number of callpals executed +system.cpu1.kern.callpal::wrkgp 1 0.00% 94.96% # number of callpals executed +system.cpu1.kern.callpal::wrusp 4 0.01% 94.97% # number of callpals executed +system.cpu1.kern.callpal::rdusp 1 0.00% 94.97% # number of callpals executed +system.cpu1.kern.callpal::whami 3 0.00% 94.98% # number of callpals executed +system.cpu1.kern.callpal::rti 2874 4.67% 99.64% # number of callpals executed +system.cpu1.kern.callpal::callsys 175 0.28% 99.93% # number of callpals executed +system.cpu1.kern.callpal::imb 43 0.07% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 86022 # number of callpals executed -system.cpu1.kern.mode_switch::kernel 2264 # number of protection mode switches -system.cpu1.kern.mode_switch::user 459 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2037 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 518 -system.cpu1.kern.mode_good::user 459 -system.cpu1.kern.mode_good::idle 59 -system.cpu1.kern.mode_switch_good::kernel 0.228799 # fraction of useful protection mode switches +system.cpu1.kern.callpal::total 61585 # number of callpals executed +system.cpu1.kern.mode_switch::kernel 1629 # number of protection mode switches +system.cpu1.kern.mode_switch::user 476 # number of protection mode switches +system.cpu1.kern.mode_switch::idle 2046 # number of protection mode switches +system.cpu1.kern.mode_good::kernel 537 +system.cpu1.kern.mode_good::user 476 +system.cpu1.kern.mode_good::idle 61 +system.cpu1.kern.mode_switch_good::kernel 0.329650 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.028964 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.217647 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 42822911000 2.26% 2.26% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 817792500 0.04% 2.30% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1852963538500 97.70% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 1814 # number of times the context was actually changed +system.cpu1.kern.mode_switch_good::idle 0.029814 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 0.258733 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 37752222500 1.99% 1.99% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 817466500 0.04% 2.03% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1858966004500 97.97% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 1166 # number of times the context was actually changed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini index 353ee4820..4e3852a72 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini @@ -8,17 +8,18 @@ time_sync_spin_threshold=100000000 [system] type=LinuxAlphaSystem -children=bridge cpu disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami +children=bridge cpu disk0 disk2 intrctrl iobus iocache membus physmem simple_disk terminal tsunami boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 -console=/dist/m5/system/binaries/console +clock=1000 +console=/projects/pd/randd/dist/binaries/console init_param=0 -kernel=/dist/m5/system/binaries/vmlinux +kernel=/projects/pd/randd/dist/binaries/vmlinux load_addr_mask=1099511627775 mem_mode=timing memories=system.physmem num_work_ids=16 -pal=/dist/m5/system/binaries/ts_osfpal +pal=/projects/pd/randd/dist/binaries/ts_osfpal readfile=tests/halt.sh symbolfile= system_rev=1024 @@ -34,18 +35,17 @@ system_port=system.membus.slave[0] [system.bridge] type=Bridge +clock=1000 delay=50000 -nack_delay=4000 ranges=8796093022208:18446744073709551615 req_size=16 resp_size=16 -write_ack=false master=system.iobus.slave[0] slave=system.membus.master[0] [system.cpu] type=DerivO3CPU -children=dcache dtb fuPool icache interrupts itb tracer +children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -93,6 +93,7 @@ iewToFetchDelay=1 iewToRenameDelay=1 instShiftAmt=2 interrupts=system.cpu.interrupts +isa=system.cpu.isa issueToExecuteDelay=1 issueWidth=8 itb=system.cpu.itb @@ -111,7 +112,6 @@ numPhysIntRegs=256 numROBEntries=192 numRobs=1 numThreads=1 -phase=0 predType=tournament profile=0 progress_interval=0 @@ -145,16 +145,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=4 block_size=64 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=2 is_top_level=true -latency=1000 max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=2 size=32768 subblock_size=0 system=system @@ -163,7 +165,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port -mem_side=system.toL2Bus.slave[1] +mem_side=system.cpu.toL2Bus.slave[1] [system.cpu.dtb] type=AlphaTLB @@ -437,16 +439,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=1 block_size=64 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=2 is_top_level=true -latency=1000 max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=2 size=32768 subblock_size=0 system=system @@ -455,15 +459,55 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port -mem_side=system.toL2Bus.slave[0] +mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=AlphaInterrupts +[system.cpu.isa] +type=AlphaISA + [system.cpu.itb] type=AlphaTLB size=48 +[system.cpu.l2cache] +type=BaseCache +addr_ranges=0:18446744073709551615 +assoc=8 +block_size=64 +clock=500 +forward_snoops=true +hash_delay=1 +hit_latency=20 +is_top_level=false +max_miss_count=0 +mshrs=20 +prefetch_on_access=false +prefetcher=Null +prioritizeRequests=false +repl=Null +response_latency=20 +size=4194304 +subblock_size=0 +system=system +tgts_per_mshr=12 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.toL2Bus.master[0] +mem_side=system.membus.slave[2] + +[system.cpu.toL2Bus] +type=CoherentBus +block_size=64 +clock=500 +header_cycles=1 +use_default_range=false +width=32 +master=system.cpu.l2cache.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side + [system.cpu.tracer] type=ExeTracer @@ -484,7 +528,7 @@ table_size=65536 [system.disk0.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-latest.img +image_file=/projects/pd/randd/dist/disks/linux-latest.img read_only=true [system.disk2] @@ -504,7 +548,7 @@ table_size=65536 [system.disk2.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-bigswap2.img +image_file=/projects/pd/randd/dist/disks/linux-bigswap2.img read_only=true [system.intrctrl] @@ -527,16 +571,18 @@ type=BaseCache addr_ranges=0:8589934591 assoc=8 block_size=64 +clock=1000 forward_snoops=false hash_delay=1 +hit_latency=50 is_top_level=true -latency=50000 max_miss_count=0 mshrs=20 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=50 size=1024 subblock_size=0 system=system @@ -547,31 +593,6 @@ write_buffers=8 cpu_side=system.iobus.master[29] mem_side=system.membus.slave[1] -[system.l2c] -type=BaseCache -addr_ranges=0:18446744073709551615 -assoc=8 -block_size=64 -forward_snoops=true -hash_delay=1 -is_top_level=false -latency=10000 -max_miss_count=0 -mshrs=92 -prefetch_on_access=false -prefetcher=Null -prioritizeRequests=false -repl=Null -size=4194304 -subblock_size=0 -system=system -tgts_per_mshr=16 -trace_addr=0 -two_queue=false -write_buffers=8 -cpu_side=system.toL2Bus.master[0] -mem_side=system.membus.slave[2] - [system.membus] type=CoherentBus children=badaddr_responder @@ -582,13 +603,14 @@ use_default_range=false width=8 default=system.membus.badaddr_responder.pio master=system.bridge.slave system.physmem.port -slave=system.system_port system.iocache.mem_side system.l2c.mem_side +slave=system.system_port system.iocache.mem_side system.cpu.l2cache.mem_side [system.membus.badaddr_responder] type=IsaFake +clock=1000 fake_mem=false pio_addr=0 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=true ret_data16=65535 @@ -601,14 +623,28 @@ warn_access= pio=system.membus.default [system.physmem] -type=SimpleMemory +type=SimpleDRAM +addr_mapping=openmap +banks_per_rank=8 +clock=1000 conf_table_reported=false -file= in_addr_map=true -latency=30000 -latency_var=0 +lines_per_rowbuffer=64 +mem_sched_policy=fcfs null=false +page_policy=open range=0:134217727 +ranks_per_channel=2 +read_buffer_size=32 +tBURST=4000 +tCL=14000 +tRCD=14000 +tREFI=7800000 +tRFC=300000 +tRP=14000 +tWTR=1000 +write_buffer_size=32 +write_thresh_perc=70 zero=false port=system.membus.master[1] @@ -620,7 +656,7 @@ system=system [system.simple_disk.disk] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-latest.img +image_file=/projects/pd/randd/dist/disks/linux-latest.img read_only=true [system.terminal] @@ -630,16 +666,6 @@ number=0 output=true port=3456 -[system.toL2Bus] -type=CoherentBus -block_size=64 -clock=1000 -header_cycles=1 -use_default_range=false -width=8 -master=system.l2c.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side - [system.tsunami] type=Tsunami children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart @@ -648,10 +674,11 @@ system=system [system.tsunami.backdoor] type=AlphaBackdoor +clock=1000 cpu=system.cpu disk=system.simple_disk pio_addr=8804682956800 -pio_latency=1000 +pio_latency=100000 platform=system.tsunami system=system terminal=system.terminal @@ -659,8 +686,9 @@ pio=system.iobus.master[24] [system.tsunami.cchip] type=TsunamiCChip +clock=1000 pio_addr=8803072344064 -pio_latency=1000 +pio_latency=100000 system=system tsunami=system.tsunami pio=system.iobus.master[0] @@ -716,12 +744,10 @@ dma_write_delay=0 dma_write_factor=0 hardware_address=00:90:00:00:00:01 intr_delay=10000000 -max_backoff_delay=10000000 -min_backoff_delay=4000 pci_bus=0 pci_dev=1 pci_func=0 -pio_latency=1000 +pio_latency=30000 platform=system.tsunami rss=false rx_delay=1000000 @@ -738,9 +764,10 @@ pio=system.iobus.master[27] [system.tsunami.fake_OROM] type=IsaFake +clock=1000 fake_mem=false pio_addr=8796093677568 -pio_latency=1000 +pio_latency=100000 pio_size=393216 ret_bad_addr=false ret_data16=65535 @@ -754,9 +781,10 @@ pio=system.iobus.master[8] [system.tsunami.fake_ata0] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848432 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -770,9 +798,10 @@ pio=system.iobus.master[19] [system.tsunami.fake_ata1] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848304 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -786,9 +815,10 @@ pio=system.iobus.master[20] [system.tsunami.fake_pnp_addr] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848569 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -802,9 +832,10 @@ pio=system.iobus.master[9] [system.tsunami.fake_pnp_read0] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848451 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -818,9 +849,10 @@ pio=system.iobus.master[11] [system.tsunami.fake_pnp_read1] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848515 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -834,9 +866,10 @@ pio=system.iobus.master[12] [system.tsunami.fake_pnp_read2] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848579 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -850,9 +883,10 @@ pio=system.iobus.master[13] [system.tsunami.fake_pnp_read3] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848643 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -866,9 +900,10 @@ pio=system.iobus.master[14] [system.tsunami.fake_pnp_read4] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848707 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -882,9 +917,10 @@ pio=system.iobus.master[15] [system.tsunami.fake_pnp_read5] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848771 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -898,9 +934,10 @@ pio=system.iobus.master[16] [system.tsunami.fake_pnp_read6] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848835 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -914,9 +951,10 @@ pio=system.iobus.master[17] [system.tsunami.fake_pnp_read7] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848899 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -930,9 +968,10 @@ pio=system.iobus.master[18] [system.tsunami.fake_pnp_write] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615850617 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -946,9 +985,10 @@ pio=system.iobus.master[10] [system.tsunami.fake_ppc] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848891 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -962,9 +1002,10 @@ pio=system.iobus.master[7] [system.tsunami.fake_sm_chip] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848816 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -978,9 +1019,10 @@ pio=system.iobus.master[2] [system.tsunami.fake_uart1] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848696 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -994,9 +1036,10 @@ pio=system.iobus.master[3] [system.tsunami.fake_uart2] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848936 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -1010,9 +1053,10 @@ pio=system.iobus.master[4] [system.tsunami.fake_uart3] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848680 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -1026,9 +1070,10 @@ pio=system.iobus.master[5] [system.tsunami.fake_uart4] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848944 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -1042,9 +1087,10 @@ pio=system.iobus.master[6] [system.tsunami.fb] type=BadDevice +clock=1000 devicename=FrameBuffer pio_addr=8804615848912 -pio_latency=1000 +pio_latency=100000 system=system pio=system.iobus.master[21] @@ -1088,16 +1134,15 @@ SubClassCode=1 SubsystemID=0 SubsystemVendorID=0 VendorID=32902 +clock=1000 config_latency=20000 ctrl_offset=0 disks=system.disk0 system.disk2 io_shift=0 -max_backoff_delay=10000000 -min_backoff_delay=4000 pci_bus=0 pci_dev=0 pci_func=0 -pio_latency=1000 +pio_latency=30000 platform=system.tsunami system=system config=system.iobus.master[26] @@ -1106,9 +1151,10 @@ pio=system.iobus.master[25] [system.tsunami.io] type=TsunamiIO +clock=1000 frequency=976562500 pio_addr=8804615847936 -pio_latency=1000 +pio_latency=100000 system=system time=Thu Jan 1 00:00:00 2009 tsunami=system.tsunami @@ -1117,8 +1163,9 @@ pio=system.iobus.master[22] [system.tsunami.pchip] type=TsunamiPChip +clock=1000 pio_addr=8802535473152 -pio_latency=1000 +pio_latency=100000 system=system tsunami=system.tsunami pio=system.iobus.master[1] @@ -1126,7 +1173,8 @@ pio=system.iobus.master[1] [system.tsunami.pciconfig] type=PciConfigAll bus=0 -pio_latency=1 +clock=1000 +pio_latency=30000 platform=system.tsunami size=16777216 system=system @@ -1134,8 +1182,9 @@ pio=system.iobus.default [system.tsunami.uart] type=Uart8250 +clock=1000 pio_addr=8804615848952 -pio_latency=1000 +pio_latency=100000 platform=system.tsunami system=system terminal=system.terminal diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout index f67dea3de..6a7037f2d 100755 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 26 2012 21:20:05 -gem5 started Jul 26 2012 22:30:38 -gem5 executing on zizzer +gem5 compiled Oct 30 2012 11:02:14 +gem5 started Oct 30 2012 13:34:06 +gem5 executing on u200540-lin command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3 -re tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3 Global frequency set at 1000000000000 ticks per second -info: kernel located at: /dist/m5/system/binaries/vmlinux +info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 1864423957500 because m5_exit instruction encountered +Exiting @ tick 1854349611000 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt index e834f19f3..cbfa90061 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt @@ -1,94 +1,94 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.854370 # Number of seconds simulated -sim_ticks 1854370484500 # Number of ticks simulated -final_tick 1854370484500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.854350 # Number of seconds simulated +sim_ticks 1854349611000 # Number of ticks simulated +final_tick 1854349611000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 120780 # Simulator instruction rate (inst/s) -host_op_rate 120780 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4226353954 # Simulator tick rate (ticks/s) -host_mem_usage 326684 # Number of bytes of host memory used -host_seconds 438.76 # Real time elapsed on the host -sim_insts 52993965 # Number of instructions simulated -sim_ops 52993965 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 969088 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24876288 # Number of bytes read from this memory -system.physmem.bytes_read::tsunami.ide 2652352 # Number of bytes read from this memory -system.physmem.bytes_read::total 28497728 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 969088 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 969088 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7507712 # Number of bytes written to this memory -system.physmem.bytes_written::total 7507712 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 15142 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 388692 # Number of read requests responded to by this memory -system.physmem.num_reads::tsunami.ide 41443 # Number of read requests responded to by this memory -system.physmem.num_reads::total 445277 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 117308 # Number of write requests responded to by this memory -system.physmem.num_writes::total 117308 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 522597 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 13414950 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1430325 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 15367872 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 522597 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 522597 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4048658 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4048658 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4048658 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 522597 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 13414950 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1430325 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 19416530 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 445277 # Total number of read requests seen -system.physmem.writeReqs 117308 # Total number of write requests seen -system.physmem.cpureqs 564090 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 28497728 # Total number of bytes read from memory -system.physmem.bytesWritten 7507712 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 28497728 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 7507712 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 56 # Number of read reqs serviced by write Q +host_inst_rate 135035 # Simulator instruction rate (inst/s) +host_op_rate 135035 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4724741522 # Simulator tick rate (ticks/s) +host_mem_usage 327760 # Number of bytes of host memory used +host_seconds 392.48 # Real time elapsed on the host +sim_insts 52998188 # Number of instructions simulated +sim_ops 52998188 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 967168 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24880448 # Number of bytes read from this memory +system.physmem.bytes_read::tsunami.ide 2652288 # Number of bytes read from this memory +system.physmem.bytes_read::total 28499904 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 967168 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 967168 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7518592 # Number of bytes written to this memory +system.physmem.bytes_written::total 7518592 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 15112 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 388757 # Number of read requests responded to by this memory +system.physmem.num_reads::tsunami.ide 41442 # Number of read requests responded to by this memory +system.physmem.num_reads::total 445311 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 117478 # Number of write requests responded to by this memory +system.physmem.num_writes::total 117478 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 521567 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 13417345 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1430306 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 15369218 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 521567 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 521567 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4054571 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4054571 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4054571 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 521567 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 13417345 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1430306 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 19423789 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 445311 # Total number of read requests seen +system.physmem.writeReqs 117478 # Total number of write requests seen +system.physmem.cpureqs 564077 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 28499904 # Total number of bytes read from memory +system.physmem.bytesWritten 7518592 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 28499904 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 7518592 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 58 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 175 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 28080 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 27611 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 27911 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 27629 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 28123 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 28001 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 27963 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 27770 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 27692 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 27278 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 27918 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 28145 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 27785 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 27747 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 27834 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 27734 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 7584 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 7270 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 7291 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 7101 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 7583 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 7405 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 7380 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 7215 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 7260 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 6854 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 7428 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 7671 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 7427 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 7350 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 7315 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 7174 # Track writes on a per bank basis +system.physmem.perBankRdReqs::0 28171 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 27744 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 27861 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 27384 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 28325 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 28126 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 27859 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 27693 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 27840 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 27508 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 27634 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 27843 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 27857 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 27753 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 27753 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 27902 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 7651 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 7405 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 7296 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 6891 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 7793 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 7560 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 7306 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 7181 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 7405 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 7055 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 7167 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 7397 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 7475 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 7357 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 7210 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 7329 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 772 # Number of times wr buffer was full causing retry -system.physmem.totGap 1854365055000 # Total gap between requests +system.physmem.numWrRetry 554 # Number of times wr buffer was full causing retry +system.physmem.totGap 1854344226000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 445277 # Categorize read packet sizes +system.physmem.readPktSize::6 445311 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -97,7 +97,7 @@ system.physmem.writePktSize::2 0 # ca system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 118080 # categorize write packet sizes +system.physmem.writePktSize::6 118032 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -109,29 +109,29 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 175 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 331917 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 65103 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 18248 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 6337 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2872 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2456 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1809 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 2035 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1684 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1980 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1575 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 331896 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 65179 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 18458 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 6410 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2875 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2427 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1797 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 2003 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1654 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1944 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1608 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 1548 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1648 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1788 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 1261 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 1518 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 936 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 252 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 140 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 108 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1627 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1778 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 1217 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 1424 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 888 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 254 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 142 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 117 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see @@ -142,47 +142,47 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 3912 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 4841 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4917 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 4965 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 5049 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 5061 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 5094 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 5094 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 5093 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 5100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 5100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 5100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 5100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 5100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 5100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 5100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 5100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 1189 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 260 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 184 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 136 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 52 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 3926 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 4833 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4929 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 4979 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 5052 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 5068 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 5097 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 5100 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 5101 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 5108 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 5108 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 5108 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 5108 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 5108 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 5108 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 5108 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 5108 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5107 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5107 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5107 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5107 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5107 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5107 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 1182 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 275 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 179 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 129 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 56 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 40 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 8 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 7 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 6175504423 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 13385770423 # Sum of mem lat for all requests -system.physmem.totBusLat 1780884000 # Total cycles spent in databus access -system.physmem.totBankLat 5429382000 # Total cycles spent in bank access -system.physmem.avgQLat 13870.65 # Average queueing delay per request -system.physmem.avgBankLat 12194.80 # Average bank access latency per request +system.physmem.totQLat 6253510302 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 13461286302 # Sum of mem lat for all requests +system.physmem.totBusLat 1781012000 # Total cycles spent in databus access +system.physmem.totBankLat 5426764000 # Total cycles spent in bank access +system.physmem.avgQLat 14044.85 # Average queueing delay per request +system.physmem.avgBankLat 12188.05 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 30065.45 # Average memory access latency +system.physmem.avgMemAccLat 30232.89 # Average memory access latency system.physmem.avgRdBW 15.37 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 4.05 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 15.37 # Average consumed read bandwidth in MB/s @@ -190,21 +190,21 @@ system.physmem.avgConsumedWrBW 4.05 # Av system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.12 # Data bus utilization in percentage system.physmem.avgRdQLen 0.01 # Average read queue length over time -system.physmem.avgWrQLen 10.01 # Average write queue length over time -system.physmem.readRowHits 425232 # Number of row buffer hits during reads -system.physmem.writeRowHits 76485 # Number of row buffer hits during writes -system.physmem.readRowHitRate 95.51 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 65.20 # Row buffer hit rate for writes -system.physmem.avgGap 3296150.90 # Average gap between requests +system.physmem.avgWrQLen 11.07 # Average write queue length over time +system.physmem.readRowHits 425296 # Number of row buffer hits during reads +system.physmem.writeRowHits 76454 # Number of row buffer hits during writes +system.physmem.readRowHitRate 95.52 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 65.08 # Row buffer hit rate for writes +system.physmem.avgGap 3294919.10 # Average gap between requests system.iocache.replacements 41685 # number of replacements -system.iocache.tagsinuse 1.265505 # Cycle average of tags in use +system.iocache.tagsinuse 1.265413 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. system.iocache.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 1704471567000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::tsunami.ide 1.265505 # Average occupied blocks per requestor -system.iocache.occ_percent::tsunami.ide 0.079094 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.079094 # Average percentage of cache occupancy +system.iocache.warmup_cycle 1704469740000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::tsunami.ide 1.265413 # Average occupied blocks per requestor +system.iocache.occ_percent::tsunami.ide 0.079088 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.079088 # Average percentage of cache occupancy system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses system.iocache.ReadReq_misses::total 173 # number of ReadReq misses system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses @@ -213,14 +213,14 @@ system.iocache.demand_misses::tsunami.ide 41725 # n system.iocache.demand_misses::total 41725 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses system.iocache.overall_misses::total 41725 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 20930998 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 20930998 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 9501230806 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 9501230806 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 9522161804 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 9522161804 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 9522161804 # number of overall miss cycles -system.iocache.overall_miss_latency::total 9522161804 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::tsunami.ide 20927998 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 20927998 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 9494924806 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 9494924806 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 9515852804 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 9515852804 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 9515852804 # number of overall miss cycles +system.iocache.overall_miss_latency::total 9515852804 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) @@ -237,19 +237,19 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 120988.427746 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 120988.427746 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 228658.808385 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 228658.808385 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 228212.385956 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 228212.385956 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 228212.385956 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 228212.385956 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 190847 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 120971.086705 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 120971.086705 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 228507.046737 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 228507.046737 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 228061.181642 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 228061.181642 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 228061.181642 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 228061.181642 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 189089 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 22837 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 22862 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8.356921 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 8.270886 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -263,14 +263,14 @@ system.iocache.demand_mshr_misses::tsunami.ide 41725 system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11934000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 11934000 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 7338470481 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 7338470481 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 7350404481 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 7350404481 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 7350404481 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 7350404481 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11931000 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 11931000 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 7332138561 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 7332138561 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 7344069561 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 7344069561 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 7344069561 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 7344069561 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -279,14 +279,14 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68982.658960 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 68982.658960 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 176609.320394 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 176609.320394 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 176163.079233 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 176163.079233 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 176163.079233 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 176163.079233 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68965.317919 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 68965.317919 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 176456.934949 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 176456.934949 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 176011.253709 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 176011.253709 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 176011.253709 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 176011.253709 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -304,22 +304,22 @@ system.cpu.dtb.fetch_hits 0 # IT system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 10013236 # DTB read hits -system.cpu.dtb.read_misses 44959 # DTB read misses -system.cpu.dtb.read_acv 558 # DTB read access violations -system.cpu.dtb.read_accesses 947796 # DTB read accesses -system.cpu.dtb.write_hits 6616814 # DTB write hits -system.cpu.dtb.write_misses 10390 # DTB write misses -system.cpu.dtb.write_acv 394 # DTB write access violations -system.cpu.dtb.write_accesses 338465 # DTB write accesses -system.cpu.dtb.data_hits 16630050 # DTB hits -system.cpu.dtb.data_misses 55349 # DTB misses -system.cpu.dtb.data_acv 952 # DTB access violations -system.cpu.dtb.data_accesses 1286261 # DTB accesses -system.cpu.itb.fetch_hits 1329992 # ITB hits -system.cpu.itb.fetch_misses 37108 # ITB misses -system.cpu.itb.fetch_acv 1110 # ITB acv -system.cpu.itb.fetch_accesses 1367100 # ITB accesses +system.cpu.dtb.read_hits 9959916 # DTB read hits +system.cpu.dtb.read_misses 41524 # DTB read misses +system.cpu.dtb.read_acv 557 # DTB read access violations +system.cpu.dtb.read_accesses 942700 # DTB read accesses +system.cpu.dtb.write_hits 6603148 # DTB write hits +system.cpu.dtb.write_misses 10669 # DTB write misses +system.cpu.dtb.write_acv 409 # DTB write access violations +system.cpu.dtb.write_accesses 338186 # DTB write accesses +system.cpu.dtb.data_hits 16563064 # DTB hits +system.cpu.dtb.data_misses 52193 # DTB misses +system.cpu.dtb.data_acv 966 # DTB access violations +system.cpu.dtb.data_accesses 1280886 # DTB accesses +system.cpu.itb.fetch_hits 1308562 # ITB hits +system.cpu.itb.fetch_misses 36917 # ITB misses +system.cpu.itb.fetch_acv 1051 # ITB acv +system.cpu.itb.fetch_accesses 1345479 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -332,147 +332,147 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 109331520 # number of cpu cycles simulated +system.cpu.numCycles 108866981 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 14034298 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 11727409 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 442398 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 10070774 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 5936443 # Number of BTB hits +system.cpu.BPredUnit.lookups 13878911 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 11630816 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 403232 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 9482716 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 5833581 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 932889 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 42550 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 28466944 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 71882691 # Number of instructions fetch has processed -system.cpu.fetch.Branches 14034298 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 6869332 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 13501507 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2157830 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 37395098 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 33730 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 253371 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 308992 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 216 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 8797269 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 284448 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 81356873 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.883548 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.225368 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 911561 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 38998 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 28184398 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 70994195 # Number of instructions fetch has processed +system.cpu.fetch.Branches 13878911 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 6745142 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 13311939 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2031019 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 37417570 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 32583 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 255429 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 315513 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 191 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 8617973 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 269432 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 80827249 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.878345 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.221663 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 67855366 83.40% 83.40% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 872636 1.07% 84.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1735283 2.13% 86.61% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 845860 1.04% 87.65% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2811672 3.46% 91.11% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 591009 0.73% 91.83% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 671901 0.83% 92.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1016398 1.25% 93.91% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 4956748 6.09% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 67515310 83.53% 83.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 859289 1.06% 84.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1709305 2.11% 86.71% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 824937 1.02% 87.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2774546 3.43% 91.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 565272 0.70% 91.86% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 652347 0.81% 92.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1007085 1.25% 93.91% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 4919158 6.09% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 81356873 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.128365 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.657475 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 29579770 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 37116941 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 12329905 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 976081 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1354175 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 610220 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 43308 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 70446207 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 129922 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1354175 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 30731567 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 13642128 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 19830185 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 11551170 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 4247646 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 66474061 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 6758 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 499961 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 1485755 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 44416415 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 80669752 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 80190207 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 479545 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 38187514 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 6228893 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1695379 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 248206 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12171415 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 10595299 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 6961029 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1313529 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 845283 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 58768050 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2080813 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 57151750 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 119190 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 7476261 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 3968695 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1415822 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 81356873 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.702482 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.362452 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 80827249 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.127485 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.652119 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 29306094 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 37119542 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 12159527 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 975132 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1266953 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 590499 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 43097 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 69660736 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 130298 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1266953 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 30443941 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 13656496 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 19805604 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 11392846 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 4261407 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 65802441 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 6765 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 504009 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 1491914 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 43932847 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 79894315 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 79415060 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 479255 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 38191269 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 5741570 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1687796 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 244874 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12188114 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 10482106 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 6925475 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1313213 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 855117 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 58302952 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2055207 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 56888280 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 110464 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 6988476 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 3659625 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1390229 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 80827249 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.703826 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.364551 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 56509823 69.46% 69.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 10919806 13.42% 82.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 5202066 6.39% 89.28% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 3421332 4.21% 93.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 2660699 3.27% 96.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 1462898 1.80% 98.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 750627 0.92% 99.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 334208 0.41% 99.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 95414 0.12% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 56119293 69.43% 69.43% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 10851228 13.43% 82.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 5175866 6.40% 89.26% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 3389461 4.19% 93.45% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 2645582 3.27% 96.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 1466047 1.81% 98.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 750476 0.93% 99.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 332850 0.41% 99.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 96446 0.12% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 81356873 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 80827249 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 88942 11.25% 11.25% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 11.25% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 11.25% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.25% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.25% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.25% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 11.25% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.25% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 11.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 11.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.25% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 375615 47.50% 58.75% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 326165 41.25% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 91026 11.51% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 373270 47.20% 58.71% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 326472 41.29% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 7287 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 38947584 68.15% 68.16% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 61688 0.11% 68.27% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 7286 0.01% 0.01% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 38768679 68.15% 68.16% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 61732 0.11% 68.27% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.27% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 25607 0.04% 68.31% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.31% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.31% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.31% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 25607 0.05% 68.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.32% # Type of FU issued system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.32% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.32% # Type of FU issued @@ -495,114 +495,114 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.32% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.32% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 10460697 18.30% 86.62% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 6696198 11.72% 98.34% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 949053 1.66% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 10391331 18.27% 86.59% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 6681118 11.74% 98.33% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 948891 1.67% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 57151750 # Type of FU issued -system.cpu.iq.rate 0.522738 # Inst issue rate -system.cpu.iq.fu_busy_cnt 790722 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.013835 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 195876834 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 68001610 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 55798747 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 693450 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 336801 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 327935 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 57573031 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 362154 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 597795 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 56888280 # Type of FU issued +system.cpu.iq.rate 0.522549 # Inst issue rate +system.cpu.iq.fu_busy_cnt 790768 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.013900 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 194812399 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 67023826 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 55617934 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 692641 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 336620 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 327880 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 57310327 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 361435 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 598219 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1500833 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 3663 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 13623 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 580148 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1386761 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 3497 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 14147 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 544022 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 17973 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 208284 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 17955 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 206298 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1354175 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 9957840 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 684465 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 64406962 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 718774 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 10595299 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 6961029 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1833098 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 512595 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 19043 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 13623 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 239398 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 420347 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 659745 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 56634449 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 10087078 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 517300 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1266953 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 9965004 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 682330 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 63888752 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 694377 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 10482106 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 6925475 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1810071 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 511236 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 18909 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 14147 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 204344 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 411597 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 615941 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 56420713 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 10029634 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 467566 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 3558099 # number of nop insts executed -system.cpu.iew.exec_refs 16729501 # number of memory reference insts executed -system.cpu.iew.exec_branches 8966109 # Number of branches executed -system.cpu.iew.exec_stores 6642423 # Number of stores executed -system.cpu.iew.exec_rate 0.518007 # Inst execution rate -system.cpu.iew.wb_sent 56249945 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 56126682 # cumulative count of insts written-back -system.cpu.iew.wb_producers 27860065 # num instructions producing a value -system.cpu.iew.wb_consumers 37718288 # num instructions consuming a value +system.cpu.iew.exec_nop 3530593 # number of nop insts executed +system.cpu.iew.exec_refs 16658677 # number of memory reference insts executed +system.cpu.iew.exec_branches 8937468 # Number of branches executed +system.cpu.iew.exec_stores 6629043 # Number of stores executed +system.cpu.iew.exec_rate 0.518254 # Inst execution rate +system.cpu.iew.wb_sent 56060470 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 55945814 # cumulative count of insts written-back +system.cpu.iew.wb_producers 27785553 # num instructions producing a value +system.cpu.iew.wb_consumers 37633865 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.513362 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.738635 # average fanout of values written-back +system.cpu.iew.wb_rate 0.513891 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.738313 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 8108089 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 664991 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 610571 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 80002698 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.702279 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.626723 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 7580888 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 664978 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 571532 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 79560296 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.706241 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.634825 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 59120920 73.90% 73.90% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 8670305 10.84% 84.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4656948 5.82% 90.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2544039 3.18% 93.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1525301 1.91% 95.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 612184 0.77% 96.41% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 529748 0.66% 97.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 518714 0.65% 97.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 1824539 2.28% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 58754657 73.85% 73.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 8628270 10.84% 84.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4624578 5.81% 90.51% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2529268 3.18% 93.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1515738 1.91% 95.59% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 609533 0.77% 96.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 524421 0.66% 97.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 524312 0.66% 97.68% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 1849519 2.32% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 80002698 # Number of insts commited each cycle -system.cpu.commit.committedInsts 56184240 # Number of instructions committed -system.cpu.commit.committedOps 56184240 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 79560296 # Number of insts commited each cycle +system.cpu.commit.committedInsts 56188709 # Number of instructions committed +system.cpu.commit.committedOps 56188709 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 15475347 # Number of memory references committed -system.cpu.commit.loads 9094466 # Number of loads committed -system.cpu.commit.membars 226347 # Number of memory barriers committed -system.cpu.commit.branches 8447798 # Number of branches committed +system.cpu.commit.refs 15476798 # Number of memory references committed +system.cpu.commit.loads 9095345 # Number of loads committed +system.cpu.commit.membars 226320 # Number of memory barriers committed +system.cpu.commit.branches 8447896 # Number of branches committed system.cpu.commit.fp_insts 324384 # Number of committed floating point instructions. -system.cpu.commit.int_insts 52030338 # Number of committed integer instructions. -system.cpu.commit.function_calls 740415 # Number of function calls committed. -system.cpu.commit.bw_lim_events 1824539 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 52034633 # Number of committed integer instructions. +system.cpu.commit.function_calls 740447 # Number of function calls committed. +system.cpu.commit.bw_lim_events 1849519 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 142220969 # The number of ROB reads -system.cpu.rob.rob_writes 129940455 # The number of ROB writes -system.cpu.timesIdled 1178635 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 27974647 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 3599403014 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 52993965 # Number of Instructions Simulated -system.cpu.committedOps 52993965 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 52993965 # Number of Instructions Simulated -system.cpu.cpi 2.063094 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.063094 # CPI: Total CPI of All Threads -system.cpu.ipc 0.484709 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.484709 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 74218754 # number of integer regfile reads -system.cpu.int_regfile_writes 40498790 # number of integer regfile writes -system.cpu.fp_regfile_reads 166070 # number of floating regfile reads -system.cpu.fp_regfile_writes 167447 # number of floating regfile writes -system.cpu.misc_regfile_reads 1994018 # number of misc regfile reads -system.cpu.misc_regfile_writes 947042 # number of misc regfile writes +system.cpu.rob.rob_reads 141230883 # The number of ROB reads +system.cpu.rob.rob_writes 128808067 # The number of ROB writes +system.cpu.timesIdled 1177683 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 28039732 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 3599825806 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 52998188 # Number of Instructions Simulated +system.cpu.committedOps 52998188 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 52998188 # Number of Instructions Simulated +system.cpu.cpi 2.054164 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.054164 # CPI: Total CPI of All Threads +system.cpu.ipc 0.486816 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.486816 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 73962724 # number of integer regfile reads +system.cpu.int_regfile_writes 40347354 # number of integer regfile writes +system.cpu.fp_regfile_reads 166024 # number of floating regfile reads +system.cpu.fp_regfile_writes 167429 # number of floating regfile writes +system.cpu.misc_regfile_reads 1993125 # number of misc regfile reads +system.cpu.misc_regfile_writes 947074 # number of misc regfile writes system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -634,355 +634,189 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.cpu.icache.replacements 1020188 # number of replacements -system.cpu.icache.tagsinuse 510.304097 # Cycle average of tags in use -system.cpu.icache.total_refs 7717774 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1020696 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 7.561286 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 20124452000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 510.304097 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.996688 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.996688 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 7717775 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 7717775 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 7717775 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 7717775 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 7717775 # number of overall hits -system.cpu.icache.overall_hits::total 7717775 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1079494 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1079494 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1079494 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1079494 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1079494 # number of overall misses -system.cpu.icache.overall_misses::total 1079494 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 14680685994 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 14680685994 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 14680685994 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 14680685994 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 14680685994 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 14680685994 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 8797269 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 8797269 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 8797269 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 8797269 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 8797269 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 8797269 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.122708 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.122708 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.122708 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.122708 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.122708 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.122708 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13599.599436 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13599.599436 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13599.599436 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13599.599436 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13599.599436 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13599.599436 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 3410 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 686 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 137 # number of cycles access was blocked +system.cpu.icache.replacements 1012720 # number of replacements +system.cpu.icache.tagsinuse 510.299473 # Cycle average of tags in use +system.cpu.icache.total_refs 7548318 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 1013228 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 7.449772 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 20110483000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 510.299473 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.996679 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.996679 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 7548319 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 7548319 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 7548319 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 7548319 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 7548319 # number of overall hits +system.cpu.icache.overall_hits::total 7548319 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1069652 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1069652 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1069652 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1069652 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1069652 # number of overall misses +system.cpu.icache.overall_misses::total 1069652 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 14542561994 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 14542561994 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 14542561994 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 14542561994 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 14542561994 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 14542561994 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 8617971 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 8617971 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 8617971 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 8617971 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 8617971 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 8617971 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.124119 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.124119 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.124119 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.124119 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.124119 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.124119 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13595.601181 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13595.601181 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13595.601181 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13595.601181 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13595.601181 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13595.601181 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 4808 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 32 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 175 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 24.890511 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 686 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 27.474286 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 32 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 58579 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 58579 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 58579 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 58579 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 58579 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 58579 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1020915 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1020915 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1020915 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1020915 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1020915 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1020915 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12036646497 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 12036646497 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12036646497 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 12036646497 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12036646497 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 12036646497 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.116049 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.116049 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.116049 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.116049 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.116049 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.116049 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11790.057446 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11790.057446 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11790.057446 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11790.057446 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11790.057446 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11790.057446 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 56203 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 56203 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 56203 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 56203 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 56203 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 56203 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1013449 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1013449 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1013449 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1013449 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1013449 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1013449 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11948814497 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 11948814497 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11948814497 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 11948814497 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11948814497 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 11948814497 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.117597 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.117597 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.117597 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.117597 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.117597 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.117597 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11790.247459 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11790.247459 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11790.247459 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11790.247459 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11790.247459 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11790.247459 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1402245 # number of replacements -system.cpu.dcache.tagsinuse 511.995160 # Cycle average of tags in use -system.cpu.dcache.total_refs 11879672 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1402757 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 8.468803 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 21544000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 511.995160 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999991 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999991 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 7264730 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7264730 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 4204895 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4204895 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 190246 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 190246 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 219552 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 219552 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 11469625 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 11469625 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 11469625 # number of overall hits -system.cpu.dcache.overall_hits::total 11469625 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1801434 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1801434 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1941730 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1941730 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 22995 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 22995 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 3743164 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3743164 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3743164 # number of overall misses -system.cpu.dcache.overall_misses::total 3743164 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 33852672500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 33852672500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 70445061639 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 70445061639 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 307962000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 307962000 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 38000 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 38000 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 104297734139 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 104297734139 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 104297734139 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 104297734139 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 9066164 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 9066164 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 6146625 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6146625 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 213241 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 213241 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 219554 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 219554 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 15212789 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 15212789 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 15212789 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15212789 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.198699 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.198699 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.315902 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.315902 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.107836 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.107836 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000009 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::total 0.000009 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.246054 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.246054 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.246054 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.246054 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 18792.069263 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 18792.069263 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 36279.535074 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 36279.535074 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13392.563601 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13392.563601 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 19000 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 19000 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 27863.522448 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 27863.522448 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 27863.522448 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 27863.522448 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 2571680 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 508 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 95435 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 7 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 26.946927 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 72.571429 # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 841139 # number of writebacks -system.cpu.dcache.writebacks::total 841139 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 716695 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 716695 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1641513 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1641513 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5045 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 5045 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2358208 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2358208 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2358208 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2358208 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1084739 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1084739 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 300217 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 300217 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17950 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 17950 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1384956 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1384956 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1384956 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1384956 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21195472500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 21195472500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10712386769 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 10712386769 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 204757500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 204757500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 34000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 34000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 31907859269 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 31907859269 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 31907859269 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 31907859269 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1423908000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1423908000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1997720998 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1997720998 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3421628998 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 3421628998 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.119647 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.119647 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.048843 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.048843 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.084177 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.084177 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000009 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000009 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091039 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.091039 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091039 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.091039 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19539.698029 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19539.698029 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35682.145811 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35682.145811 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11407.103064 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11407.103064 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 17000 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 17000 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23038.897459 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 23038.897459 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23038.897459 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 23038.897459 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 338360 # number of replacements -system.cpu.l2cache.tagsinuse 65364.997376 # Cycle average of tags in use -system.cpu.l2cache.total_refs 2558215 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 403528 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 6.339622 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 4044746002 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 53963.120652 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 5350.230870 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 6051.645853 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.823412 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.081638 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.092341 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.997391 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 1005648 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 828171 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1833819 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 841139 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 841139 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 31 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 31 # number of UpgradeReq hits -system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 1 # number of SCUpgradeReq hits -system.cpu.l2cache.SCUpgradeReq_hits::total 1 # number of SCUpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 185483 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 185483 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 1005648 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1013654 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2019302 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 1005648 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1013654 # number of overall hits -system.cpu.l2cache.overall_hits::total 2019302 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 15144 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 273859 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 289003 # number of ReadReq misses +system.cpu.l2cache.replacements 338368 # number of replacements +system.cpu.l2cache.tagsinuse 65364.962205 # Cycle average of tags in use +system.cpu.l2cache.total_refs 2548619 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 403534 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 6.315748 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 4043215002 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::writebacks 54020.981996 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 5337.307261 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 6006.672948 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.824295 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.081441 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.091655 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.997390 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 998214 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 826620 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1824834 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 840489 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 840489 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 26 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 26 # number of UpgradeReq hits +system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 2 # number of SCUpgradeReq hits +system.cpu.l2cache.SCUpgradeReq_hits::total 2 # number of SCUpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 185505 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 185505 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 998214 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 1012125 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2010339 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 998214 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 1012125 # number of overall hits +system.cpu.l2cache.overall_hits::total 2010339 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 15114 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 273846 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 288960 # number of ReadReq misses system.cpu.l2cache.UpgradeReq_misses::cpu.data 36 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_misses::total 36 # number of UpgradeReq misses -system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 1 # number of SCUpgradeReq misses -system.cpu.l2cache.SCUpgradeReq_misses::total 1 # number of SCUpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 115327 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 115327 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 15144 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 389186 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 404330 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 15144 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 389186 # number of overall misses -system.cpu.l2cache.overall_misses::total 404330 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 916217000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 11804091500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 12720308500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_misses::cpu.data 115406 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 115406 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 15114 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 389252 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 404366 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 15114 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 389252 # number of overall misses +system.cpu.l2cache.overall_misses::total 404366 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 909377000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 11791174000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 12700551000 # number of ReadReq miss cycles system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 261500 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_latency::total 261500 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8496188000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 8496188000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 916217000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 20300279500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 21216496500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 916217000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 20300279500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 21216496500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 1020792 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1102030 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 2122822 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 841139 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 841139 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 67 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 67 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8601240000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 8601240000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 909377000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 20392414000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 21301791000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 909377000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 20392414000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 21301791000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 1013328 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 1100466 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 2113794 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 840489 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 840489 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 62 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 62 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 300810 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 300810 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 1020792 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1402840 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2423632 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 1020792 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1402840 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2423632 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014836 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.248504 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.136141 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.537313 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.537313 # miss rate for UpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.500000 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.500000 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383388 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.383388 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014836 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.277427 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.166828 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014836 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.277427 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.166828 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 60500.330164 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 43102.806554 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 44014.451407 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_accesses::cpu.data 300911 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 300911 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 1013328 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1401377 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2414705 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 1013328 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1401377 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2414705 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014915 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.248845 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.136702 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.580645 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.580645 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383522 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.383522 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014915 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.277764 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.167460 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014915 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.277764 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.167460 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 60167.857615 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 43057.682055 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 43952.626661 # average ReadReq miss latency system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 7263.888889 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 7263.888889 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73670.415427 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73670.415427 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60500.330164 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52160.867811 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52473.218658 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60500.330164 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52160.867811 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52473.218658 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74530.267057 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74530.267057 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60167.857615 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52388.719904 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52679.480965 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60167.857615 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52388.719904 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52679.480965 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -991,80 +825,72 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 75796 # number of writebacks -system.cpu.l2cache.writebacks::total 75796 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 75966 # number of writebacks +system.cpu.l2cache.writebacks::total 75966 # number of writebacks system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits system.cpu.l2cache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 1 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 15143 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 273859 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 289002 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 15113 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 273846 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 288959 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 36 # number of UpgradeReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::total 36 # number of UpgradeReq MSHR misses -system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 1 # number of SCUpgradeReq MSHR misses -system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 1 # number of SCUpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 115327 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 115327 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 15143 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 389186 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 404329 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 15143 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 389186 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 404329 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 725022440 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 8259922361 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 8984944801 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 115406 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 115406 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 15113 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 389252 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 404365 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 15113 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 389252 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 404365 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 718571789 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 8247220261 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 8965792050 # number of ReadReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 511032 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 511032 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 10001 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 10001 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7067947103 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7067947103 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 725022440 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 15327869464 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 16052891904 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 725022440 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 15327869464 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 16052891904 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1333831000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1333831000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1882540500 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1882540500 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3216371500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3216371500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014835 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.248504 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.136140 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.537313 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.537313 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383388 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383388 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014835 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.277427 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.166828 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014835 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.277427 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.166828 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 47878.388694 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 30161.222969 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31089.559245 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7172240815 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7172240815 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 718571789 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 15419461076 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 16138032865 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 718571789 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 15419461076 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 16138032865 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1333809500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1333809500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1882195500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1882195500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3216005000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3216005000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014914 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.248845 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.136702 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.580645 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.580645 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383522 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383522 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014914 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.277764 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.167459 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014914 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.277764 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.167459 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 47546.601535 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 30116.270681 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31027.903786 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14195.333333 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14195.333333 # average UpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61286.143774 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61286.143774 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 47878.388694 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 39384.431773 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39702.548924 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 47878.388694 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 39384.431773 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39702.548924 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62147.902319 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62147.902319 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 47546.601535 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 39613.055491 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39909.568991 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 47546.601535 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 39613.055491 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39909.568991 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1072,29 +898,191 @@ system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.replacements 1400783 # number of replacements +system.cpu.dcache.tagsinuse 511.995190 # Cycle average of tags in use +system.cpu.dcache.total_refs 11827578 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1401295 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 8.440463 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 21532000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 511.995190 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999991 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999991 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 7213661 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7213661 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 4203894 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4203894 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 190181 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 190181 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 219613 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 219613 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 11417555 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 11417555 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 11417555 # number of overall hits +system.cpu.dcache.overall_hits::total 11417555 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1801125 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1801125 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1943246 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1943246 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 22685 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 22685 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::cpu.data 3744371 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3744371 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3744371 # number of overall misses +system.cpu.dcache.overall_misses::total 3744371 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 33805478000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 33805478000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 71113991647 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 71113991647 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 303653500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 303653500 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 26000 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 26000 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 104919469647 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 104919469647 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 104919469647 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 104919469647 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 9014786 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 9014786 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6147140 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6147140 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 212866 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 212866 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 219615 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 219615 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 15161926 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 15161926 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 15161926 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 15161926 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.199797 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.199797 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.316122 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.316122 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.106569 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.106569 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000009 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000009 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.246959 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.246959 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.246959 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.246959 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 18769.090430 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 18769.090430 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 36595.465344 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 36595.465344 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13385.651311 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13385.651311 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 13000 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 13000 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 28020.586007 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 28020.586007 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 28020.586007 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 28020.586007 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 2640119 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 587 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 95652 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 8 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 27.601294 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 73.375000 # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 840489 # number of writebacks +system.cpu.dcache.writebacks::total 840489 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 717559 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 717559 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1642936 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1642936 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5123 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 5123 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2360495 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2360495 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2360495 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2360495 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1083566 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1083566 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 300310 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 300310 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17562 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 17562 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1383876 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1383876 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1383876 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1383876 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21170477000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 21170477000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10817290277 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 10817290277 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 199800500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 199800500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 22000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 22000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 31987767277 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 31987767277 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 31987767277 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 31987767277 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1423886500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1423886500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1997350998 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1997350998 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3421237498 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 3421237498 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120199 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120199 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.048854 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.048854 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.082503 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.082503 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000009 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000009 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091273 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.091273 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091273 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.091273 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19537.782655 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19537.782655 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36020.413163 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 36020.413163 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11376.864822 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11376.864822 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 11000 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23114.619574 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 23114.619574 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23114.619574 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 23114.619574 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 6436 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 211013 # number of hwrei instructions executed -system.cpu.kern.ipl_count::0 74663 40.97% 40.97% # number of times we switched to this ipl +system.cpu.kern.inst.hwrei 210973 # number of hwrei instructions executed +system.cpu.kern.ipl_count::0 74651 40.97% 40.97% # number of times we switched to this ipl system.cpu.kern.ipl_count::21 131 0.07% 41.04% # number of times we switched to this ipl -system.cpu.kern.ipl_count::22 1880 1.03% 42.07% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 105569 57.93% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 182243 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73296 49.32% 49.32% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_count::22 1878 1.03% 42.07% # number of times we switched to this ipl +system.cpu.kern.ipl_count::31 105545 57.93% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 182205 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73284 49.32% 49.32% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::21 131 0.09% 49.41% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::22 1880 1.27% 50.68% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73296 49.32% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 148603 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1818451122500 98.06% 98.06% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 64044500 0.00% 98.07% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 561305000 0.03% 98.10% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 35293166500 1.90% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1854369638500 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981691 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_good::22 1878 1.26% 50.68% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::31 73284 49.32% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 148577 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1818516202000 98.07% 98.07% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 64252000 0.00% 98.07% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 558035000 0.03% 98.10% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 35210286000 1.90% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1854348775000 # number of cycles we spent at this ipl +system.cpu.kern.ipl_used::0 0.981688 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.694295 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.815411 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.694339 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.815439 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -1133,29 +1121,29 @@ system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # nu system.cpu.kern.callpal::swpctx 4176 2.18% 2.18% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.21% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed -system.cpu.kern.callpal::swpipl 175126 91.22% 93.43% # number of callpals executed -system.cpu.kern.callpal::rdps 6785 3.53% 96.97% # number of callpals executed +system.cpu.kern.callpal::swpipl 175092 91.23% 93.43% # number of callpals executed +system.cpu.kern.callpal::rdps 6783 3.53% 96.97% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.97% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed system.cpu.kern.callpal::rdusp 9 0.00% 96.98% # number of callpals executed system.cpu.kern.callpal::whami 2 0.00% 96.98% # number of callpals executed -system.cpu.kern.callpal::rti 5105 2.66% 99.64% # number of callpals executed +system.cpu.kern.callpal::rti 5103 2.66% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 191972 # number of callpals executed -system.cpu.kern.mode_switch::kernel 5851 # number of protection mode switches -system.cpu.kern.mode_switch::user 1739 # number of protection mode switches -system.cpu.kern.mode_switch::idle 2096 # number of protection mode switches -system.cpu.kern.mode_good::kernel 1909 -system.cpu.kern.mode_good::user 1739 +system.cpu.kern.callpal::total 191934 # number of callpals executed +system.cpu.kern.mode_switch::kernel 5848 # number of protection mode switches +system.cpu.kern.mode_switch::user 1741 # number of protection mode switches +system.cpu.kern.mode_switch::idle 2097 # number of protection mode switches +system.cpu.kern.mode_good::kernel 1911 +system.cpu.kern.mode_good::user 1741 system.cpu.kern.mode_good::idle 170 -system.cpu.kern.mode_switch_good::kernel 0.326269 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::kernel 0.326778 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::idle 0.081107 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 0.394177 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 29748704000 1.60% 1.60% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 2690261500 0.15% 1.75% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1821930665000 98.25% 100.00% # number of ticks spent at the given mode +system.cpu.kern.mode_switch_good::idle 0.081068 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::total 0.394590 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 29709775500 1.60% 1.60% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 2660669000 0.14% 1.75% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1821978322500 98.25% 100.00% # number of ticks spent at the given mode system.cpu.kern.swap_context 4177 # number of times the context was actually changed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini index f66d752af..219ef17ea 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini @@ -8,13 +8,14 @@ time_sync_spin_threshold=100000000 [system] type=LinuxArmSystem -children=bridge cf0 cpu intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver +children=bridge cf0 cpu intrctrl iobus iocache membus physmem realview terminal vncserver atags_addr=256 boot_loader=/projects/pd/randd/dist/binaries/boot.arm boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 -clock=1 +clock=1000 dtb_filename= early_kernel_symbols=false +enable_context_switch_stats_dump=false flags_addr=268435504 gic_cpu_addr=520093952 init_param=0 @@ -39,7 +40,7 @@ system_port=system.membus.slave[0] [system.bridge] type=Bridge -clock=1 +clock=1000 delay=50000 ranges=268435456:520093695 1073741824:1610612735 req_size=16 @@ -69,7 +70,7 @@ read_only=true [system.cpu] type=DerivO3CPU -children=checker dcache dtb fuPool icache interrupts itb tracer +children=checker dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -167,7 +168,7 @@ icache_port=system.cpu.icache.cpu_side type=O3Checker children=dtb itb tracer checker=Null -clock=1 +clock=500 cpu_id=0 defer_registration=false do_checkpoint_insts=true @@ -200,10 +201,10 @@ walker=system.cpu.checker.dtb.walker [system.cpu.checker.dtb.walker] type=ArmTableWalker -clock=1 +clock=500 num_squash_per_cycle=2 sys=system -port=system.toL2Bus.slave[5] +port=system.cpu.toL2Bus.slave[5] [system.cpu.checker.itb] type=ArmTLB @@ -213,10 +214,10 @@ walker=system.cpu.checker.itb.walker [system.cpu.checker.itb.walker] type=ArmTableWalker -clock=1 +clock=500 num_squash_per_cycle=2 sys=system -port=system.toL2Bus.slave[4] +port=system.cpu.toL2Bus.slave[4] [system.cpu.checker.tracer] type=ExeTracer @@ -226,10 +227,10 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=4 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 @@ -237,7 +238,7 @@ prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=32768 subblock_size=0 system=system @@ -246,7 +247,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port -mem_side=system.toL2Bus.slave[1] +mem_side=system.cpu.toL2Bus.slave[1] [system.cpu.dtb] type=ArmTLB @@ -256,10 +257,10 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=ArmTableWalker -clock=1 +clock=500 num_squash_per_cycle=2 sys=system -port=system.toL2Bus.slave[3] +port=system.cpu.toL2Bus.slave[3] [system.cpu.fuPool] type=FUPool @@ -529,10 +530,10 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=1 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 @@ -540,7 +541,7 @@ prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=32768 subblock_size=0 system=system @@ -549,7 +550,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port -mem_side=system.toL2Bus.slave[0] +mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=ArmInterrupts @@ -562,10 +563,47 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=ArmTableWalker -clock=1 +clock=500 num_squash_per_cycle=2 sys=system -port=system.toL2Bus.slave[2] +port=system.cpu.toL2Bus.slave[2] + +[system.cpu.l2cache] +type=BaseCache +addr_ranges=0:18446744073709551615 +assoc=8 +block_size=64 +clock=500 +forward_snoops=true +hash_delay=1 +hit_latency=20 +is_top_level=false +max_miss_count=0 +mshrs=20 +prefetch_on_access=false +prefetcher=Null +prioritizeRequests=false +repl=Null +response_latency=20 +size=4194304 +subblock_size=0 +system=system +tgts_per_mshr=12 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.toL2Bus.master[0] +mem_side=system.membus.slave[2] + +[system.cpu.toL2Bus] +type=CoherentBus +block_size=64 +clock=500 +header_cycles=1 +use_default_range=false +width=32 +master=system.cpu.l2cache.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.checker.itb.walker.port system.cpu.checker.dtb.walker.port [system.cpu.tracer] type=ExeTracer @@ -589,18 +627,18 @@ type=BaseCache addr_ranges=0:268435455 assoc=8 block_size=64 -clock=1 +clock=1000 forward_snoops=false hash_delay=1 -hit_latency=50000 -is_top_level=false +hit_latency=50 +is_top_level=true max_miss_count=0 mshrs=20 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=50000 +response_latency=50 size=1024 subblock_size=0 system=system @@ -611,33 +649,6 @@ write_buffers=8 cpu_side=system.iobus.master[25] mem_side=system.membus.slave[1] -[system.l2c] -type=BaseCache -addr_ranges=0:18446744073709551615 -assoc=8 -block_size=64 -clock=1 -forward_snoops=true -hash_delay=1 -hit_latency=10000 -is_top_level=false -max_miss_count=0 -mshrs=92 -prefetch_on_access=false -prefetcher=Null -prioritizeRequests=false -repl=Null -response_latency=10000 -size=4194304 -subblock_size=0 -system=system -tgts_per_mshr=16 -trace_addr=0 -two_queue=false -write_buffers=8 -cpu_side=system.toL2Bus.master[0] -mem_side=system.membus.slave[2] - [system.membus] type=CoherentBus children=badaddr_responder @@ -648,11 +659,11 @@ use_default_range=false width=8 default=system.membus.badaddr_responder.pio master=system.bridge.slave system.realview.nvmem.port system.physmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio -slave=system.system_port system.iocache.mem_side system.l2c.mem_side +slave=system.system_port system.iocache.mem_side system.cpu.l2cache.mem_side [system.membus.badaddr_responder] type=IsaFake -clock=1 +clock=1000 fake_mem=false pio_addr=0 pio_latency=100000 @@ -668,15 +679,28 @@ warn_access=warn pio=system.membus.default [system.physmem] -type=SimpleMemory -bandwidth=73.000000 -clock=1 +type=SimpleDRAM +addr_mapping=openmap +banks_per_rank=8 +clock=1000 conf_table_reported=true in_addr_map=true -latency=30000 -latency_var=0 +lines_per_rowbuffer=64 +mem_sched_policy=fcfs null=false +page_policy=open range=0:134217727 +ranks_per_channel=2 +read_buffer_size=32 +tBURST=4000 +tCL=14000 +tRCD=14000 +tREFI=7800000 +tRFC=300000 +tRP=14000 +tWTR=1000 +write_buffer_size=32 +write_thresh_perc=70 zero=false port=system.membus.master[2] @@ -691,7 +715,7 @@ system=system [system.realview.a9scu] type=A9SCU -clock=1 +clock=1000 pio_addr=520093696 pio_latency=100000 system=system @@ -700,7 +724,7 @@ pio=system.membus.master[5] [system.realview.aaci_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268451840 pio_latency=100000 @@ -747,7 +771,7 @@ SubClassCode=1 SubsystemID=0 SubsystemVendorID=0 VendorID=32902 -clock=1 +clock=1000 config_latency=20000 ctrl_offset=2 disks=system.cf0 @@ -778,7 +802,7 @@ pio=system.iobus.master[4] [system.realview.dmac_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268632064 pio_latency=100000 @@ -787,7 +811,7 @@ pio=system.iobus.master[9] [system.realview.flash_fake] type=IsaFake -clock=1 +clock=1000 fake_mem=true pio_addr=1073741824 pio_latency=100000 @@ -804,7 +828,7 @@ pio=system.iobus.master[24] [system.realview.gic] type=Gic -clock=1 +clock=1000 cpu_addr=520093952 cpu_pio_delay=10000 dist_addr=520097792 @@ -818,7 +842,7 @@ pio=system.membus.master[3] [system.realview.gpio0_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268513280 pio_latency=100000 @@ -828,7 +852,7 @@ pio=system.iobus.master[16] [system.realview.gpio1_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268517376 pio_latency=100000 @@ -838,7 +862,7 @@ pio=system.iobus.master[17] [system.realview.gpio2_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268521472 pio_latency=100000 @@ -848,7 +872,7 @@ pio=system.iobus.master[18] [system.realview.kmi0] type=Pl050 amba_id=1314896 -clock=1 +clock=1000 gic=system.realview.gic int_delay=1000000 int_num=52 @@ -862,7 +886,7 @@ pio=system.iobus.master[5] [system.realview.kmi1] type=Pl050 amba_id=1314896 -clock=1 +clock=1000 gic=system.realview.gic int_delay=1000000 int_num=53 @@ -875,7 +899,7 @@ pio=system.iobus.master[6] [system.realview.l2x0_fake] type=IsaFake -clock=1 +clock=1000 fake_mem=false pio_addr=520101888 pio_latency=100000 @@ -904,7 +928,7 @@ pio=system.membus.master[6] [system.realview.mmc_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268455936 pio_latency=100000 @@ -914,7 +938,7 @@ pio=system.iobus.master[22] [system.realview.nvmem] type=SimpleMemory bandwidth=73.000000 -clock=1 +clock=1000 conf_table_reported=false in_addr_map=true latency=30000 @@ -926,7 +950,7 @@ port=system.membus.master[1] [system.realview.realview_io] type=RealViewCtrl -clock=1 +clock=1000 idreg=0 pio_addr=268435456 pio_latency=100000 @@ -938,7 +962,7 @@ pio=system.iobus.master[1] [system.realview.rtc] type=PL031 amba_id=3412017 -clock=1 +clock=1000 gic=system.realview.gic int_delay=100000 int_num=42 @@ -951,7 +975,7 @@ pio=system.iobus.master[23] [system.realview.sci_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268492800 pio_latency=100000 @@ -961,7 +985,7 @@ pio=system.iobus.master[20] [system.realview.smc_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=269357056 pio_latency=100000 @@ -971,7 +995,7 @@ pio=system.iobus.master[13] [system.realview.sp810_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=true pio_addr=268439552 pio_latency=100000 @@ -981,7 +1005,7 @@ pio=system.iobus.master[14] [system.realview.ssp_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268488704 pio_latency=100000 @@ -991,7 +1015,7 @@ pio=system.iobus.master[19] [system.realview.timer0] type=Sp804 amba_id=1316868 -clock=1 +clock=1000 clock0=1000000 clock1=1000000 gic=system.realview.gic @@ -1005,7 +1029,7 @@ pio=system.iobus.master[2] [system.realview.timer1] type=Sp804 amba_id=1316868 -clock=1 +clock=1000 clock0=1000000 clock1=1000000 gic=system.realview.gic @@ -1018,7 +1042,7 @@ pio=system.iobus.master[3] [system.realview.uart] type=Pl011 -clock=1 +clock=1000 end_on_eot=false gic=system.realview.gic int_delay=100000 @@ -1033,7 +1057,7 @@ pio=system.iobus.master[0] [system.realview.uart1_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268476416 pio_latency=100000 @@ -1043,7 +1067,7 @@ pio=system.iobus.master[10] [system.realview.uart2_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268480512 pio_latency=100000 @@ -1053,7 +1077,7 @@ pio=system.iobus.master[11] [system.realview.uart3_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268484608 pio_latency=100000 @@ -1063,7 +1087,7 @@ pio=system.iobus.master[12] [system.realview.watchdog_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268500992 pio_latency=100000 @@ -1077,16 +1101,6 @@ number=0 output=true port=3456 -[system.toL2Bus] -type=CoherentBus -block_size=64 -clock=1000 -header_cycles=1 -use_default_range=false -width=8 -master=system.l2c.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.checker.itb.walker.port system.cpu.checker.dtb.walker.port - [system.vncserver] type=VncServer frame_capture=false diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simerr index 3e85e4166..2082cdfd9 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simerr +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simerr @@ -10,34 +10,27 @@ warn: instruction 'mcr icialluis' unimplemented warn: instruction 'mcr dccimvac' unimplemented warn: instruction 'mcr dccmvau' unimplemented warn: instruction 'mcr icimvau' unimplemented -warn: 6471379000: Instruction results do not match! (Values may not actually be integers) Inst: 0x3744, checker: 0x3748 -warn: 6479236500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3704, checker: 0x3708 -warn: 6488789500: Instruction results do not match! (Values may not actually be integers) Inst: 0x36c4, checker: 0x36c8 -warn: 6527432500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3604, checker: 0x3608 -warn: 6543641500: Instruction results do not match! (Values may not actually be integers) Inst: 0x35c4, checker: 0x35c8 -warn: 7089434000: Instruction results do not match! (Values may not actually be integers) Inst: 0x34f0, checker: 0x34f8 -warn: 12809896500: Instruction results do not match! (Values may not actually be integers) Inst: 0xc02dd14c, checker: 0xc781befc -warn: 12854316500: Instruction results do not match! (Values may not actually be integers) Inst: 0xc02dd14c, checker: 0xc781befc -warn: 13169361500: Instruction results do not match! (Values may not actually be integers) Inst: 0xc02dd14c, checker: 0xc781befc -warn: 14424922500: Instruction results do not match! (Values may not actually be integers) Inst: 0xc02dd14c, checker: 0xc781befc -warn: 14474529500: Instruction results do not match! (Values may not actually be integers) Inst: 0xc02dd14c, checker: 0xc781befc -warn: 15519752500: Instruction results do not match! (Values may not actually be integers) Inst: 0xc02dd14c, checker: 0xc781befc -warn: 15669382500: Instruction results do not match! (Values may not actually be integers) Inst: 0xc02dd14c, checker: 0xc781befc +warn: 5946987000: Instruction results do not match! (Values may not actually be integers) Inst: 0x3744, checker: 0x3748 +warn: 5954355500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3704, checker: 0x3708 +warn: 5963229500: Instruction results do not match! (Values may not actually be integers) Inst: 0x36c4, checker: 0x36c8 +warn: 5999905500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3604, checker: 0x3608 +warn: 6015449500: Instruction results do not match! (Values may not actually be integers) Inst: 0x35c4, checker: 0x35c8 warn: LCD dual screen mode not supported -warn: 54391557500: Instruction results do not match! (Values may not actually be integers) Inst: 0x19dc, checker: 0x1a04 +warn: 51801575500: Instruction results do not match! (Values may not actually be integers) Inst: 0x19dc, checker: 0x1a04 warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors -warn: 816692532000: Instruction results do not match! (Values may not actually be integers) Inst: 0, checker: 0x1 warn: instruction 'mcr icialluis' unimplemented warn: instruction 'mcr bpiallis' unimplemented -warn: 2486377425500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9debc, checker: 0 -warn: 2500398254500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0 -warn: 2501706856500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2a4, checker: 0 -warn: 2523057678500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0 -warn: 2523647855500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0 -warn: 2529994034500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d974, checker: 0 -warn: 2530576345500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d954, checker: 0 -warn: 2531219324500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d9fc, checker: 0 -warn: 2531220454500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9da34, checker: 0 +warn: 2473940227500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9debc, checker: 0 +warn: 2487729164500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0 +warn: 2488940395000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2a4, checker: 0 +warn: 2503139484500: Instruction results do not match! (Values may not actually be integers) Inst: 0x2, checker: 0 +warn: 2510001697500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0 +warn: 2510516362000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0 +warn: 2516240346500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d974, checker: 0 +warn: 2516753495000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d954, checker: 0 +warn: 2517315503000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d9fc, checker: 0 +warn: 2517316610000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9da34, checker: 0 +warn: 2517867351500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2fc, checker: 0 hack: be nice to actually delete the event here diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout index 5011d2336..a3de8bb34 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 21 2012 11:19:00 -gem5 started Sep 21 2012 12:35:22 +gem5 compiled Nov 1 2012 15:18:10 +gem5 started Nov 2 2012 01:09:00 gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker Global frequency set at 1000000000000 ticks per second info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: Using bootloader at address 0x80000000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 2537929870500 because m5_exit instruction encountered +Exiting @ tick 2523500318000 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt index 3725b6e15..a24f5a985 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt @@ -1,114 +1,114 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.523629 # Number of seconds simulated -sim_ticks 2523629285500 # Number of ticks simulated -final_tick 2523629285500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.523500 # Number of seconds simulated +sim_ticks 2523500318000 # Number of ticks simulated +final_tick 2523500318000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 68763 # Simulator instruction rate (inst/s) -host_op_rate 88448 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2863680529 # Simulator tick rate (ticks/s) -host_mem_usage 399792 # Number of bytes of host memory used -host_seconds 881.25 # Real time elapsed on the host -sim_insts 60597236 # Number of instructions simulated -sim_ops 77945371 # Number of ops (including micro ops) simulated +host_inst_rate 54734 # Simulator instruction rate (inst/s) +host_op_rate 70403 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2279341302 # Simulator tick rate (ticks/s) +host_mem_usage 401036 # Number of bytes of host memory used +host_seconds 1107.12 # Real time elapsed on the host +sim_insts 60596849 # Number of instructions simulated +sim_ops 77944928 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 3520 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 799232 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9095696 # Number of bytes read from this memory -system.physmem.bytes_read::total 129436176 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 799232 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 799232 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3784448 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.dtb.walker 2752 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 798592 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9094096 # Number of bytes read from this memory +system.physmem.bytes_read::total 129433232 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 798592 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 798592 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3784064 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 6800520 # Number of bytes written to this memory +system.physmem.bytes_written::total 6800136 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 55 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 12488 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 142154 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15096906 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59132 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 43 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 12478 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 142129 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15096860 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 59126 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 813150 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47367363 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 1395 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 25 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 316699 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3604212 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51289695 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 316699 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 316699 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1499605 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1195133 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2694738 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1499605 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47367363 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 1395 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 25 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 316699 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4799345 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53984433 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15096906 # Total number of read requests seen -system.physmem.writeReqs 813150 # Total number of write requests seen -system.physmem.cpureqs 218484 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 966201984 # Total number of bytes read from memory -system.physmem.bytesWritten 52041600 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 129436176 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 6800520 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 390 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 4690 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 943619 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 943957 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 943433 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 943463 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 943389 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 943250 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 943110 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 943289 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 943778 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 943634 # Track reads on a per bank basis +system.physmem.num_writes::total 813144 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47369784 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 1091 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 51 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 316462 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3603763 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51291149 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 316462 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 316462 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1499530 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1195194 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2694724 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1499530 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47369784 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 1091 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 51 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 316462 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4798956 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53985873 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15096860 # Total number of read requests seen +system.physmem.writeReqs 813144 # Total number of write requests seen +system.physmem.cpureqs 218421 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 966199040 # Total number of bytes read from memory +system.physmem.bytesWritten 52041216 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 129433232 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 6800136 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 334 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 4679 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 943626 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 943958 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 943414 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 943465 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 943376 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 943238 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 943099 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 943292 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 943771 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 943641 # Track reads on a per bank basis system.physmem.perBankRdReqs::10 943712 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 943686 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 943739 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 943592 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 943646 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 943219 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 50102 # Track writes on a per bank basis +system.physmem.perBankRdReqs::11 943689 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 943743 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 943611 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 943653 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 943238 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 50107 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 50378 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 49977 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 50030 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 50914 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 50821 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 50673 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 50817 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 51140 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 51219 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 51127 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 49961 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 50027 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 50912 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 50814 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 50662 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 50821 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 51143 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 51225 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 51129 # Track writes on a per bank basis system.physmem.perBankWrReqs::11 51111 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 51352 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 51158 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 51299 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 51032 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 51353 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 51175 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 51296 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 51030 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 1156336 # Number of times wr buffer was full causing retry -system.physmem.totGap 2523628152000 # Total gap between requests +system.physmem.numWrRetry 1153879 # Number of times wr buffer was full causing retry +system.physmem.totGap 2523499110500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 36 # Categorize read packet sizes system.physmem.readPktSize::3 14942208 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 154662 # Categorize read packet sizes +system.physmem.readPktSize::6 154616 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 1910354 # categorize write packet sizes +system.physmem.writePktSize::2 1907897 # categorize write packet sizes system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 59132 # categorize write packet sizes +system.physmem.writePktSize::6 59126 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -117,28 +117,28 @@ system.physmem.neitherpktsize::2 0 # ca system.physmem.neitherpktsize::3 0 # categorize neither packet sizes system.physmem.neitherpktsize::4 0 # categorize neither packet sizes system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 4690 # categorize neither packet sizes +system.physmem.neitherpktsize::6 4679 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 14955823 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 89957 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 6537 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 2881 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2334 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2059 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1873 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1682 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 14954842 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 89676 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 6568 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 2998 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2443 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2395 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2334 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1858 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 1270 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1277 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1234 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 6283 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 9566 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 13077 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 563 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 50 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 33 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1251 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1236 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 6388 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 9595 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 13055 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 523 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 48 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 31 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 15 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see @@ -153,15 +153,15 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 2800 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 2950 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 3067 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 3195 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 3352 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 3546 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 3760 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 3932 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 4090 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 2802 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 2959 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 3079 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 3181 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 3335 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 3514 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 3726 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 3889 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 4040 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 35354 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 35354 # What write queue length does an incoming req see system.physmem.wrQLenPdf::11 35354 # What write queue length does an incoming req see @@ -176,37 +176,37 @@ system.physmem.wrQLenPdf::19 35354 # Wh system.physmem.wrQLenPdf::20 35354 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 35354 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 35354 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 32555 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 32405 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 32288 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 32160 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 32003 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 31809 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 31595 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 31423 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 31264 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 32553 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 32396 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 32275 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 32173 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 32019 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 31840 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 31628 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 31465 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 31314 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 46839255594 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 317495505594 # Sum of mem lat for all requests -system.physmem.totBusLat 60386064000 # Total cycles spent in databus access -system.physmem.totBankLat 210270186000 # Total cycles spent in bank access -system.physmem.avgQLat 3102.65 # Average queueing delay per request -system.physmem.avgBankLat 13928.39 # Average bank access latency per request +system.physmem.totQLat 47052553851 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 317720785851 # Sum of mem lat for all requests +system.physmem.totBusLat 60386104000 # Total cycles spent in databus access +system.physmem.totBankLat 210282128000 # Total cycles spent in bank access +system.physmem.avgQLat 3116.78 # Average queueing delay per request +system.physmem.avgBankLat 13929.17 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 21031.04 # Average memory access latency -system.physmem.avgRdBW 382.86 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 21045.95 # Average memory access latency +system.physmem.avgRdBW 382.88 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 20.62 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 51.29 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 2.69 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 2.52 # Data bus utilization in percentage system.physmem.avgRdQLen 0.13 # Average read queue length over time -system.physmem.avgWrQLen 13.20 # Average write queue length over time -system.physmem.readRowHits 15050623 # Number of row buffer hits during reads -system.physmem.writeRowHits 784578 # Number of row buffer hits during writes -system.physmem.readRowHitRate 99.70 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 96.49 # Row buffer hit rate for writes -system.physmem.avgGap 158618.43 # Average gap between requests +system.physmem.avgWrQLen 11.37 # Average write queue length over time +system.physmem.readRowHits 15049962 # Number of row buffer hits during reads +system.physmem.writeRowHits 784769 # Number of row buffer hits during writes +system.physmem.readRowHitRate 99.69 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 96.51 # Row buffer hit rate for writes +system.physmem.avgGap 158610.84 # Average gap between requests system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory @@ -227,9 +227,9 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu.checker.dtb.inst_hits 0 # ITB inst hits system.cpu.checker.dtb.inst_misses 0 # ITB inst misses -system.cpu.checker.dtb.read_hits 15048943 # DTB read hits -system.cpu.checker.dtb.read_misses 7309 # DTB read misses -system.cpu.checker.dtb.write_hits 11294215 # DTB write hits +system.cpu.checker.dtb.read_hits 15048842 # DTB read hits +system.cpu.checker.dtb.read_misses 7308 # DTB read misses +system.cpu.checker.dtb.write_hits 11294147 # DTB write hits system.cpu.checker.dtb.write_misses 2189 # DTB write misses system.cpu.checker.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA @@ -240,13 +240,13 @@ system.cpu.checker.dtb.align_faults 0 # Nu system.cpu.checker.dtb.prefetch_faults 178 # Number of TLB faults due to prefetch system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.checker.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions -system.cpu.checker.dtb.read_accesses 15056252 # DTB read accesses -system.cpu.checker.dtb.write_accesses 11296404 # DTB write accesses +system.cpu.checker.dtb.read_accesses 15056150 # DTB read accesses +system.cpu.checker.dtb.write_accesses 11296336 # DTB write accesses system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.checker.dtb.hits 26343158 # DTB hits -system.cpu.checker.dtb.misses 9498 # DTB misses -system.cpu.checker.dtb.accesses 26352656 # DTB accesses -system.cpu.checker.itb.inst_hits 61775988 # ITB inst hits +system.cpu.checker.dtb.hits 26342989 # DTB hits +system.cpu.checker.dtb.misses 9497 # DTB misses +system.cpu.checker.dtb.accesses 26352486 # DTB accesses +system.cpu.checker.itb.inst_hits 61775601 # ITB inst hits system.cpu.checker.itb.inst_misses 4471 # ITB inst misses system.cpu.checker.itb.read_hits 0 # DTB read hits system.cpu.checker.itb.read_misses 0 # DTB read misses @@ -263,36 +263,36 @@ system.cpu.checker.itb.domain_faults 0 # Nu system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.checker.itb.read_accesses 0 # DTB read accesses system.cpu.checker.itb.write_accesses 0 # DTB write accesses -system.cpu.checker.itb.inst_accesses 61780459 # ITB inst accesses -system.cpu.checker.itb.hits 61775988 # DTB hits +system.cpu.checker.itb.inst_accesses 61780072 # ITB inst accesses +system.cpu.checker.itb.hits 61775601 # DTB hits system.cpu.checker.itb.misses 4471 # DTB misses -system.cpu.checker.itb.accesses 61780459 # DTB accesses -system.cpu.checker.numCycles 78235930 # number of cpu cycles simulated +system.cpu.checker.itb.accesses 61780072 # DTB accesses +system.cpu.checker.numCycles 78235487 # number of cpu cycles simulated system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 51393832 # DTB read hits -system.cpu.dtb.read_misses 77273 # DTB read misses -system.cpu.dtb.write_hits 11807513 # DTB write hits -system.cpu.dtb.write_misses 17284 # DTB write misses +system.cpu.dtb.read_hits 51279526 # DTB read hits +system.cpu.dtb.read_misses 73667 # DTB read misses +system.cpu.dtb.write_hits 11753863 # DTB write hits +system.cpu.dtb.write_misses 17234 # DTB write misses system.cpu.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 7715 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 2923 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 497 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 7683 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 2376 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 510 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 1303 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 51471105 # DTB read accesses -system.cpu.dtb.write_accesses 11824797 # DTB write accesses +system.cpu.dtb.perms_faults 1366 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 51353193 # DTB read accesses +system.cpu.dtb.write_accesses 11771097 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 63201345 # DTB hits -system.cpu.dtb.misses 94557 # DTB misses -system.cpu.dtb.accesses 63295902 # DTB accesses -system.cpu.itb.inst_hits 11866090 # ITB inst hits -system.cpu.itb.inst_misses 12256 # ITB inst misses +system.cpu.dtb.hits 63033389 # DTB hits +system.cpu.dtb.misses 90901 # DTB misses +system.cpu.dtb.accesses 63124290 # DTB accesses +system.cpu.itb.inst_hits 11603865 # ITB inst hits +system.cpu.itb.inst_misses 11359 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -301,538 +301,538 @@ system.cpu.itb.flush_tlb 4 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 5202 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 5142 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 3056 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 2961 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 11878346 # ITB inst accesses -system.cpu.itb.hits 11866090 # DTB hits -system.cpu.itb.misses 12256 # DTB misses -system.cpu.itb.accesses 11878346 # DTB accesses -system.cpu.numCycles 471617242 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 11615224 # ITB inst accesses +system.cpu.itb.hits 11603865 # DTB hits +system.cpu.itb.misses 11359 # DTB misses +system.cpu.itb.accesses 11615224 # DTB accesses +system.cpu.numCycles 470951029 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 14707934 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 11701482 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 783806 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 9735591 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 7867248 # Number of BTB hits +system.cpu.BPredUnit.lookups 14482147 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 11548936 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 711590 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 9469344 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 7720983 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1454059 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 82839 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 30177247 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 91949952 # Number of instructions fetch has processed -system.cpu.fetch.Branches 14707934 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9321307 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 20604105 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 4981007 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 133002 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 96623906 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 2605 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 100214 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 208761 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 353 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 11862293 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 731589 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 6461 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 151283915 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.758817 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.115765 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1413907 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 72813 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 29880342 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 90834905 # Number of instructions fetch has processed +system.cpu.fetch.Branches 14482147 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9134890 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 20280806 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 4750716 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 122594 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 96709258 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 2560 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 94111 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 205295 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 281 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 11600179 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 700998 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 5704 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 150571175 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.752471 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.109183 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 130696614 86.39% 86.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1382439 0.91% 87.31% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1755242 1.16% 88.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2339470 1.55% 90.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2142585 1.42% 91.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1134296 0.75% 92.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 2618835 1.73% 93.91% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 784869 0.52% 94.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 8429565 5.57% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 130305873 86.54% 86.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1344979 0.89% 87.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1685836 1.12% 88.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2306234 1.53% 90.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2113026 1.40% 91.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1118544 0.74% 92.23% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2593877 1.72% 93.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 765442 0.51% 94.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 8337364 5.54% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 151283915 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.031186 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.194967 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 32009474 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 96255861 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 18724959 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1031397 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3262224 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 2019817 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 174593 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 109260478 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 576218 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3262224 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 33806773 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 36827261 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 53335707 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 17902220 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 6149730 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 104066052 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 21507 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1015259 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4119258 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 31916 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 107817309 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 475022232 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 474932056 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 90176 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 78731209 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 29086099 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 892462 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 797997 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12333143 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 20063520 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 13521808 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1973034 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2429271 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 96511584 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2058662 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 123961862 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 189585 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 20013916 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 50091772 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 514148 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 151283915 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.819399 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.531663 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 150571175 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.030751 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.192875 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 31657449 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 96342520 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 18430846 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1034189 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3106171 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 1969595 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 172369 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 107934392 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 571655 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3106171 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 33426960 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 36897380 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 53334301 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 17638840 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 6167523 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 102924268 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 21343 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1016075 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4132060 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 29183 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 106686272 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 469883831 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 469792749 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 91082 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 78730768 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 27955503 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 879837 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 786100 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12323975 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 19838005 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 13393703 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1972033 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2410684 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 95618817 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2046180 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 123387582 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 174864 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 19151232 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 48036492 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 501695 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 150571175 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.819463 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.532492 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 106904579 70.66% 70.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 13863783 9.16% 79.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7099546 4.69% 84.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 5863279 3.88% 88.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12474907 8.25% 96.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2771705 1.83% 98.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1719952 1.14% 99.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 458027 0.30% 99.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 128137 0.08% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 106455995 70.70% 70.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 13758975 9.14% 79.84% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7009673 4.66% 84.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 5842702 3.88% 88.38% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12442883 8.26% 96.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2768710 1.84% 98.48% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1710517 1.14% 99.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 450789 0.30% 99.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 130931 0.09% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 151283915 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 150571175 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 57031 0.64% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 3 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 8373952 94.62% 95.27% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 418898 4.73% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 59954 0.68% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 4 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 8366032 94.65% 95.32% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 413370 4.68% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 363666 0.29% 0.29% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 58283800 47.02% 47.31% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 95201 0.08% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 19 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 5 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 13 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 2113 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 13 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 52766411 42.57% 89.96% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 12450621 10.04% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 57926411 46.95% 47.24% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 93267 0.08% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 22 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 1 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 17 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 2114 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 17 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 52616961 42.64% 89.96% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 12385106 10.04% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 123961862 # Type of FU issued -system.cpu.iq.rate 0.262844 # Inst issue rate -system.cpu.iq.fu_busy_cnt 8849884 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.071392 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 408318037 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 118600535 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 86285351 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 23227 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 12408 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 10278 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 132435732 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 12348 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 629942 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 123387582 # Type of FU issued +system.cpu.iq.rate 0.261997 # Inst issue rate +system.cpu.iq.fu_busy_cnt 8839360 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.071639 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 406427994 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 116832614 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 85860436 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 23103 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 12565 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 10308 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 131851026 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 12250 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 624646 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 4347483 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 7997 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 29897 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1723272 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 4122070 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 6381 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 30063 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1595239 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 34108218 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 695964 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 34107814 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 695818 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3262224 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 27920683 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 435052 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 98794824 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 232558 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 20063520 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 13521808 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1467094 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 114012 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3652 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 29897 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 410015 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 293518 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 703533 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 121755337 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 52081116 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2206525 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3106171 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 27981842 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 438339 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 97885744 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 205866 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 19838005 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 13393703 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1459318 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 116468 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3836 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 30063 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 352690 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 272400 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 625090 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 121269392 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 51965419 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2118190 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 224578 # number of nop insts executed -system.cpu.iew.exec_refs 64400589 # number of memory reference insts executed -system.cpu.iew.exec_branches 11599904 # Number of branches executed -system.cpu.iew.exec_stores 12319473 # Number of stores executed -system.cpu.iew.exec_rate 0.258166 # Inst execution rate -system.cpu.iew.wb_sent 120729614 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 86295629 # cumulative count of insts written-back -system.cpu.iew.wb_producers 47354389 # num instructions producing a value -system.cpu.iew.wb_consumers 88420573 # num instructions consuming a value +system.cpu.iew.exec_nop 220747 # number of nop insts executed +system.cpu.iew.exec_refs 64230871 # number of memory reference insts executed +system.cpu.iew.exec_branches 11527542 # Number of branches executed +system.cpu.iew.exec_stores 12265452 # Number of stores executed +system.cpu.iew.exec_rate 0.257499 # Inst execution rate +system.cpu.iew.wb_sent 120289637 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 85870744 # cumulative count of insts written-back +system.cpu.iew.wb_producers 47162688 # num instructions producing a value +system.cpu.iew.wb_consumers 88075667 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.182978 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.535558 # average fanout of values written-back +system.cpu.iew.wb_rate 0.182335 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.535479 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 19868776 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1544514 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 612308 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 148104118 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.527303 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.512767 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 18952599 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1544485 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 541833 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 147547429 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.529290 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.517447 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 120332893 81.25% 81.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 13565443 9.16% 90.41% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3964002 2.68% 93.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2135941 1.44% 94.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1954116 1.32% 95.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 973664 0.66% 96.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1592335 1.08% 97.58% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 730104 0.49% 98.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2855620 1.93% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 119858518 81.23% 81.23% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 13515143 9.16% 90.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3916529 2.65% 93.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2132463 1.45% 94.49% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1950760 1.32% 95.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 976387 0.66% 96.48% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1592516 1.08% 97.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 731256 0.50% 98.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2873857 1.95% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 148104118 # Number of insts commited each cycle -system.cpu.commit.committedInsts 60747617 # Number of instructions committed -system.cpu.commit.committedOps 78095752 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 147547429 # Number of insts commited each cycle +system.cpu.commit.committedInsts 60747230 # Number of instructions committed +system.cpu.commit.committedOps 78095309 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 27514573 # Number of memory references committed -system.cpu.commit.loads 15716037 # Number of loads committed -system.cpu.commit.membars 413105 # Number of memory barriers committed -system.cpu.commit.branches 10023091 # Number of branches committed +system.cpu.commit.refs 27514399 # Number of memory references committed +system.cpu.commit.loads 15715935 # Number of loads committed +system.cpu.commit.membars 413101 # Number of memory barriers committed +system.cpu.commit.branches 10023041 # Number of branches committed system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions. -system.cpu.commit.int_insts 69134185 # Number of committed integer instructions. -system.cpu.commit.function_calls 995980 # Number of function calls committed. -system.cpu.commit.bw_lim_events 2855620 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 69133795 # Number of committed integer instructions. +system.cpu.commit.function_calls 995976 # Number of function calls committed. +system.cpu.commit.bw_lim_events 2873857 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 241297904 # The number of ROB reads -system.cpu.rob.rob_writes 199283253 # The number of ROB writes -system.cpu.timesIdled 1774711 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 320333327 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 4575553300 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 60597236 # Number of Instructions Simulated -system.cpu.committedOps 77945371 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 60597236 # Number of Instructions Simulated -system.cpu.cpi 7.782818 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.782818 # CPI: Total CPI of All Threads -system.cpu.ipc 0.128488 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.128488 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 551506178 # number of integer regfile reads -system.cpu.int_regfile_writes 88407138 # number of integer regfile writes -system.cpu.fp_regfile_reads 8339 # number of floating regfile reads -system.cpu.fp_regfile_writes 2916 # number of floating regfile writes -system.cpu.misc_regfile_reads 124072221 # number of misc regfile reads -system.cpu.misc_regfile_writes 912903 # number of misc regfile writes -system.cpu.icache.replacements 990875 # number of replacements -system.cpu.icache.tagsinuse 510.405236 # Cycle average of tags in use -system.cpu.icache.total_refs 10787830 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 991387 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 10.881553 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 6691567000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 510.405236 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.996885 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.996885 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 10787830 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 10787830 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 10787830 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 10787830 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 10787830 # number of overall hits -system.cpu.icache.overall_hits::total 10787830 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1074333 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1074333 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1074333 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1074333 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1074333 # number of overall misses -system.cpu.icache.overall_misses::total 1074333 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 14125562486 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 14125562486 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 14125562486 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 14125562486 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 14125562486 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 14125562486 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 11862163 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 11862163 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 11862163 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 11862163 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 11862163 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 11862163 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.090568 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.090568 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.090568 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.090568 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.090568 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.090568 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13148.216136 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13148.216136 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13148.216136 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13148.216136 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13148.216136 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13148.216136 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 4400 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 296 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 14.864865 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.rob.rob_reads 239806361 # The number of ROB reads +system.cpu.rob.rob_writes 197293644 # The number of ROB writes +system.cpu.timesIdled 1776983 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 320379854 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 4575961583 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 60596849 # Number of Instructions Simulated +system.cpu.committedOps 77944928 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 60596849 # Number of Instructions Simulated +system.cpu.cpi 7.771873 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.771873 # CPI: Total CPI of All Threads +system.cpu.ipc 0.128669 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.128669 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 549353820 # number of integer regfile reads +system.cpu.int_regfile_writes 87979072 # number of integer regfile writes +system.cpu.fp_regfile_reads 8318 # number of floating regfile reads +system.cpu.fp_regfile_writes 2932 # number of floating regfile writes +system.cpu.misc_regfile_reads 122823412 # number of misc regfile reads +system.cpu.misc_regfile_writes 912865 # number of misc regfile writes +system.cpu.icache.replacements 980837 # number of replacements +system.cpu.icache.tagsinuse 511.007226 # Cycle average of tags in use +system.cpu.icache.total_refs 10539450 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 981349 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 10.739757 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 6666804000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 511.007226 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.998061 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.998061 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 10539450 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 10539450 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 10539450 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 10539450 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 10539450 # number of overall hits +system.cpu.icache.overall_hits::total 10539450 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1060605 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1060605 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1060605 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1060605 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1060605 # number of overall misses +system.cpu.icache.overall_misses::total 1060605 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 13961403491 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 13961403491 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 13961403491 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 13961403491 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 13961403491 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 13961403491 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 11600055 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 11600055 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 11600055 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 11600055 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 11600055 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 11600055 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.091431 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.091431 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.091431 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.091431 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.091431 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.091431 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13163.622169 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13163.622169 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13163.622169 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13163.622169 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13163.622169 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13163.622169 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 5262 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 8 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 297 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 17.717172 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 8 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 82890 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 82890 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 82890 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 82890 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 82890 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 82890 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 991443 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 991443 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 991443 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 991443 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 991443 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 991443 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11470045988 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 11470045988 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11470045988 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 11470045988 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11470045988 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 11470045988 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 7052500 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 7052500 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 7052500 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::total 7052500 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.083580 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.083580 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.083580 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.083580 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.083580 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.083580 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11569.042283 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11569.042283 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11569.042283 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11569.042283 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11569.042283 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11569.042283 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 79214 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 79214 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 79214 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 79214 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 79214 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 79214 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 981391 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 981391 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 981391 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 981391 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 981391 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 981391 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11354795991 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 11354795991 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11354795991 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 11354795991 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11354795991 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 11354795991 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 6803000 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 6803000 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 6803000 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::total 6803000 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.084602 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.084602 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.084602 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.084602 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.084602 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.084602 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11570.104057 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11570.104057 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11570.104057 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11570.104057 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11570.104057 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11570.104057 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 645101 # number of replacements -system.cpu.dcache.tagsinuse 511.994184 # Cycle average of tags in use -system.cpu.dcache.total_refs 21772820 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 645613 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 33.724259 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 35202000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 511.994184 # Average occupied blocks per requestor +system.cpu.dcache.replacements 643459 # number of replacements +system.cpu.dcache.tagsinuse 511.994224 # Cycle average of tags in use +system.cpu.dcache.total_refs 21664123 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 643971 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 33.641457 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 35006000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 511.994224 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999989 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999989 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 13909719 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 13909719 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 7289021 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 7289021 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 285196 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 285196 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 285739 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 285739 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 21198740 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 21198740 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 21198740 # number of overall hits -system.cpu.dcache.overall_hits::total 21198740 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 730115 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 730115 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2961662 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2961662 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 13591 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 13591 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 19 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 19 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 3691777 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3691777 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3691777 # number of overall misses -system.cpu.dcache.overall_misses::total 3691777 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 9540231500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 9540231500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 104360444235 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 104360444235 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 180814000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 180814000 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 283000 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 283000 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 113900675735 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 113900675735 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 113900675735 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 113900675735 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 14639834 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 14639834 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 10250683 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 10250683 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 298787 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 298787 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 285758 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 285758 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 24890517 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 24890517 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 24890517 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 24890517 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.049872 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.049872 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.288923 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.288923 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045487 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.045487 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000066 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::total 0.000066 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.148321 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.148321 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.148321 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.148321 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13066.751813 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13066.751813 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35237.121669 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 35237.121669 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13303.951144 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13303.951144 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 14894.736842 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 14894.736842 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 30852.534087 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 30852.534087 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 30852.534087 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 30852.534087 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 29089 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 14501 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 2531 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 252 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 11.493086 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 57.543651 # average number of cycles each access was blocked +system.cpu.dcache.ReadReq_hits::cpu.data 13804735 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 13804735 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 7290056 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 7290056 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 280491 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 280491 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 285728 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 285728 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 21094791 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 21094791 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 21094791 # number of overall hits +system.cpu.dcache.overall_hits::total 21094791 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 731455 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 731455 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2960577 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2960577 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 13626 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 13626 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 12 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 12 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::cpu.data 3692032 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3692032 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3692032 # number of overall misses +system.cpu.dcache.overall_misses::total 3692032 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 9566755000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 9566755000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 105515855226 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 105515855226 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 181290500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 181290500 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 192000 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 192000 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 115082610226 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 115082610226 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 115082610226 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 115082610226 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 14536190 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 14536190 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 10250633 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 10250633 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 294117 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 294117 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 285740 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 285740 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 24786823 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 24786823 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 24786823 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 24786823 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050320 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.050320 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.288819 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.288819 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.046329 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.046329 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000042 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000042 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.148951 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.148951 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.148951 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.148951 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13079.075268 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13079.075268 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35640.300937 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 35640.300937 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13304.748275 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13304.748275 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 16000 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 16000 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 31170.534336 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 31170.534336 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 31170.534336 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 31170.534336 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 30622 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 13737 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2589 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 255 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 11.827733 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 53.870588 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 609133 # number of writebacks -system.cpu.dcache.writebacks::total 609133 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 342878 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 342878 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2712526 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2712526 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1365 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 1365 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3055404 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3055404 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3055404 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3055404 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 387237 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 387237 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249136 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 249136 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12226 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 12226 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 19 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 19 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 636373 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 636373 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 636373 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 636373 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4781839500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4781839500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8147970920 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8147970920 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 141479000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 141479000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 245000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 245000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12929810420 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 12929810420 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12929810420 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 12929810420 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182356641500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182356641500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 28006523855 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 28006523855 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 210363165355 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 210363165355 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026451 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026451 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024304 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024304 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.040919 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.040919 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000066 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000066 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025567 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.025567 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025567 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.025567 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12348.612090 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12348.612090 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32704.911855 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32704.911855 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11571.977752 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11571.977752 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 12894.736842 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 12894.736842 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20317.974553 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 20317.974553 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20317.974553 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 20317.974553 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 607749 # number of writebacks +system.cpu.dcache.writebacks::total 607749 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 345667 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 345667 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2711644 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2711644 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1415 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 1415 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3057311 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3057311 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3057311 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3057311 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385788 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 385788 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 248933 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 248933 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12211 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 12211 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 12 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 12 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 634721 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 634721 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 634721 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 634721 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4768255000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4768255000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8227495919 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8227495919 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 141520500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 141520500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 168000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 168000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12995750919 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 12995750919 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12995750919 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 12995750919 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182357111500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182357111500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 27981839814 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 27981839814 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 210338951314 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 210338951314 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026540 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026540 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024285 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024285 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.041517 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.041517 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000042 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000042 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025607 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.025607 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025607 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.025607 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12359.780501 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12359.780501 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33051.045538 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33051.045538 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11589.591352 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11589.591352 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 14000 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 14000 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20474.745469 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20474.745469 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20474.745469 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20474.745469 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -840,149 +840,149 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 64428 # number of replacements -system.cpu.l2cache.tagsinuse 51367.264734 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1930539 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 129823 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 14.870547 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 2488482557500 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 36879.772922 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.dtb.walker 44.022997 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.000230 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 8192.461940 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 6251.006645 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.562741 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000672 # Average percentage of cache occupancy +system.cpu.l2cache.replacements 64388 # number of replacements +system.cpu.l2cache.tagsinuse 51373.602635 # Cycle average of tags in use +system.cpu.l2cache.total_refs 1911501 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 129780 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 14.728779 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 2488431429000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::writebacks 36915.014302 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.dtb.walker 29.696477 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.000348 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 8183.272105 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 6245.619403 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.563278 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000453 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.125007 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.095383 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.783802 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 83028 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 12007 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 977743 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 388649 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1461427 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 609133 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 609133 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 53 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 53 # number of UpgradeReq hits -system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 16 # number of SCUpgradeReq hits -system.cpu.l2cache.SCUpgradeReq_hits::total 16 # number of SCUpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 113031 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 113031 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 83028 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 12007 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 977743 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 501680 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1574458 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 83028 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 12007 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 977743 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 501680 # number of overall hits -system.cpu.l2cache.overall_hits::total 1574458 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 55 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 1 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.inst 12377 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 10733 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 23166 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 2933 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 2933 # number of UpgradeReq misses +system.cpu.l2cache.occ_percent::cpu.inst 0.124867 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.095301 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.783899 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 79304 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 10595 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 967765 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 387173 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1444837 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 607749 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 607749 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 43 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 43 # number of UpgradeReq hits +system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 9 # number of SCUpgradeReq hits +system.cpu.l2cache.SCUpgradeReq_hits::total 9 # number of SCUpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 112887 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 112887 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.dtb.walker 79304 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.itb.walker 10595 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 967765 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 500060 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 1557724 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.dtb.walker 79304 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.itb.walker 10595 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 967765 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 500060 # number of overall hits +system.cpu.l2cache.overall_hits::total 1557724 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 43 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 12372 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 10735 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 23152 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 2918 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 2918 # number of UpgradeReq misses system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 3 # number of SCUpgradeReq misses system.cpu.l2cache.SCUpgradeReq_misses::total 3 # number of SCUpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 133200 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 133200 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.dtb.walker 55 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.itb.walker 1 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 12377 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 143933 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 156366 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.dtb.walker 55 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.itb.walker 1 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 12377 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 143933 # number of overall misses -system.cpu.l2cache.overall_misses::total 156366 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 3825000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 49000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 666073500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 589040998 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 1258988498 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 478000 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 478000 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6695831998 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 6695831998 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 3825000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 49000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 666073500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 7284872996 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 7954820496 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 3825000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 49000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 666073500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 7284872996 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 7954820496 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 83083 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 12008 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.inst 990120 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 399382 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 1484593 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 609133 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 609133 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2986 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 2986 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 19 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.SCUpgradeReq_accesses::total 19 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 246231 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 246231 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 83083 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.itb.walker 12008 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 990120 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 645613 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 1730824 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 83083 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.itb.walker 12008 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 990120 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 645613 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 1730824 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000662 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000083 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012501 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026874 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.015604 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.982251 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.982251 # miss rate for UpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.157895 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.157895 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.540955 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.540955 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000662 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000083 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012501 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.222940 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.090342 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000662 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000083 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012501 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.222940 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.090342 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 69545.454545 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 49000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53815.423770 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 54881.300475 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 54346.391177 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 162.973065 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 162.973065 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 50269.008994 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 50269.008994 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 69545.454545 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 49000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53815.423770 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 50612.944884 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 50873.082998 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 69545.454545 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 49000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53815.423770 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 50612.944884 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 50873.082998 # average overall miss latency +system.cpu.l2cache.ReadExReq_misses::cpu.data 133176 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 133176 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.dtb.walker 43 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 12372 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 143911 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 156328 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.dtb.walker 43 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.inst 12372 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 143911 # number of overall misses +system.cpu.l2cache.overall_misses::total 156328 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 2913500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 118000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 660133000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 590903498 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 1254067998 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 477000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 477000 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6777740498 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 6777740498 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 2913500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 118000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 660133000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 7368643996 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 8031808496 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 2913500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 118000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 660133000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 7368643996 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 8031808496 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 79347 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 10597 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.inst 980137 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 397908 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 1467989 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 607749 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 607749 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2961 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 2961 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 12 # number of SCUpgradeReq accesses(hits+misses) +system.cpu.l2cache.SCUpgradeReq_accesses::total 12 # number of SCUpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 246063 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 246063 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.dtb.walker 79347 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.itb.walker 10597 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 980137 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 643971 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 1714052 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.dtb.walker 79347 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.itb.walker 10597 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 980137 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 643971 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 1714052 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000542 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000189 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012623 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026979 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.015771 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.985478 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.985478 # miss rate for UpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.250000 # miss rate for SCUpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.250000 # miss rate for SCUpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.541227 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.541227 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000542 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000189 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012623 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.223474 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.091204 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000542 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000189 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012623 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.223474 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.091204 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 67755.813953 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 59000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53357.015842 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 55044.573638 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 54166.724171 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 163.468129 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 163.468129 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 50893.107602 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 50893.107602 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 67755.813953 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 59000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53357.015842 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 51202.785027 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 51377.926513 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 67755.813953 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 59000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53357.015842 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 51202.785027 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 51377.926513 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -991,109 +991,109 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 59132 # number of writebacks -system.cpu.l2cache.writebacks::total 59132 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 13 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 61 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 74 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 13 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 61 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 74 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 13 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 61 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 74 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 55 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 1 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 12364 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 10672 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 23092 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2933 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 2933 # number of UpgradeReq MSHR misses +system.cpu.l2cache.writebacks::writebacks 59126 # number of writebacks +system.cpu.l2cache.writebacks::total 59126 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 12 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 60 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 72 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 12 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 60 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 72 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 12 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 60 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 72 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 43 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 2 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 12360 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 10675 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 23080 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2918 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 2918 # number of UpgradeReq MSHR misses system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 3 # number of SCUpgradeReq MSHR misses system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 3 # number of SCUpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133200 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 133200 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 55 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 1 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 12364 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 143872 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 156292 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 55 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 1 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 12364 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 143872 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 156292 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 3125110 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 37000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 508931159 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 450583388 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 962676657 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 29345422 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 29345422 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133176 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 133176 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 43 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 2 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 12360 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 143851 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 156256 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 43 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 2 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 12360 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 143851 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 156256 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 2368082 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 93002 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 503399135 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 452451368 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 958311587 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 29209900 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 29209900 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 30003 # number of SCUpgradeReq MSHR miss cycles system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 30003 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5043706030 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5043706030 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 3125110 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 37000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 508931159 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5494289418 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 6006382687 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 3125110 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 37000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 508931159 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5494289418 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 6006382687 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 4470659 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166963401029 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 166967871688 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 18112636815 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 18112636815 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 4470659 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 185076037844 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 185080508503 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000662 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000083 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012487 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026721 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015554 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.982251 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.982251 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.157895 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.157895 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.540955 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.540955 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000662 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000083 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012487 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.222846 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.090299 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000662 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000083 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012487 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.222846 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.090299 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 56820.181818 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 37000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41162.338968 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42221.082084 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 41688.751819 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10005.258098 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10005.258098 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5125972608 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5125972608 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 2368082 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 93002 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 503399135 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5578423976 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 6084284195 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 2368082 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 93002 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 503399135 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5578423976 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 6084284195 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 4345155 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166963877530 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 166968222685 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 18087556027 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 18087556027 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 4345155 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 185051433557 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 185055778712 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000542 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000189 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012610 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026828 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015722 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.985478 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.985478 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.250000 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.250000 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541227 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541227 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000542 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000189 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012610 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.223381 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.091162 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000542 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000189 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012610 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.223381 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.091162 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 55071.674419 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 46501 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40728.085356 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42384.203091 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 41521.299263 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10010.246744 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10010.246744 # average UpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average SCUpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 37865.660886 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 37865.660886 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 56820.181818 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 37000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41162.338968 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38188.733166 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38430.519073 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 56820.181818 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 37000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41162.338968 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38188.733166 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38430.519073 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 38490.213011 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 38490.213011 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 55071.674419 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 46501 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40728.085356 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38779.181069 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38937.923632 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 55071.674419 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 46501 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40728.085356 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38779.181069 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38937.923632 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1117,16 +1117,16 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1068163777856 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1068163777856 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1068163777856 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1068163777856 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1068305538529 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1068305538529 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1068305538529 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1068305538529 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 88030 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 88025 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini index f00ea7875..966a7a822 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini @@ -12,9 +12,10 @@ children=bridge cf0 cpu0 cpu1 intrctrl iobus iocache l2c membus physmem realview atags_addr=256 boot_loader=/projects/pd/randd/dist/binaries/boot.arm boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 -clock=1 +clock=1000 dtb_filename= early_kernel_symbols=false +enable_context_switch_stats_dump=false flags_addr=268435504 gic_cpu_addr=520093952 init_param=0 @@ -23,7 +24,6 @@ load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=timing memories=system.physmem system.realview.nvmem -midr_regval=890224640 multi_proc=true num_work_ids=16 readfile=tests/halt.sh @@ -39,7 +39,7 @@ system_port=system.membus.slave[0] [system.bridge] type=Bridge -clock=1 +clock=1000 delay=50000 ranges=268435456:520093695 1073741824:1610612735 req_size=16 @@ -69,7 +69,7 @@ read_only=true [system.cpu0] type=DerivO3CPU -children=dcache dtb fuPool icache interrupts itb tracer +children=dcache dtb fuPool icache interrupts isa itb tracer BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -117,6 +117,7 @@ iewToFetchDelay=1 iewToRenameDelay=1 instShiftAmt=2 interrupts=system.cpu0.interrupts +isa=system.cpu0.isa issueToExecuteDelay=1 issueWidth=8 itb=system.cpu0.itb @@ -168,10 +169,10 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=4 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 @@ -179,7 +180,7 @@ prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=32768 subblock_size=0 system=system @@ -198,7 +199,7 @@ walker=system.cpu0.dtb.walker [system.cpu0.dtb.walker] type=ArmTableWalker -clock=1 +clock=500 num_squash_per_cycle=2 sys=system port=system.toL2Bus.slave[3] @@ -471,10 +472,10 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=1 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 @@ -482,7 +483,7 @@ prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=32768 subblock_size=0 system=system @@ -496,6 +497,23 @@ mem_side=system.toL2Bus.slave[0] [system.cpu0.interrupts] type=ArmInterrupts +[system.cpu0.isa] +type=ArmISA +fpsid=1090793632 +id_isar0=34607377 +id_isar1=34677009 +id_isar2=555950401 +id_isar3=17899825 +id_isar4=268501314 +id_isar5=0 +id_mmfr0=3 +id_mmfr1=0 +id_mmfr2=19070976 +id_mmfr3=4027589137 +id_pfr0=49 +id_pfr1=1 +midr=890224640 + [system.cpu0.itb] type=ArmTLB children=walker @@ -504,7 +522,7 @@ walker=system.cpu0.itb.walker [system.cpu0.itb.walker] type=ArmTableWalker -clock=1 +clock=500 num_squash_per_cycle=2 sys=system port=system.toL2Bus.slave[2] @@ -514,7 +532,7 @@ type=ExeTracer [system.cpu1] type=DerivO3CPU -children=dcache dtb fuPool icache interrupts itb tracer +children=dcache dtb fuPool icache interrupts isa itb tracer BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -562,6 +580,7 @@ iewToFetchDelay=1 iewToRenameDelay=1 instShiftAmt=2 interrupts=system.cpu1.interrupts +isa=system.cpu1.isa issueToExecuteDelay=1 issueWidth=8 itb=system.cpu1.itb @@ -613,10 +632,10 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=4 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 @@ -624,7 +643,7 @@ prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=32768 subblock_size=0 system=system @@ -643,7 +662,7 @@ walker=system.cpu1.dtb.walker [system.cpu1.dtb.walker] type=ArmTableWalker -clock=1 +clock=500 num_squash_per_cycle=2 sys=system port=system.toL2Bus.slave[7] @@ -916,10 +935,10 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=1 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 @@ -927,7 +946,7 @@ prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=32768 subblock_size=0 system=system @@ -941,6 +960,23 @@ mem_side=system.toL2Bus.slave[4] [system.cpu1.interrupts] type=ArmInterrupts +[system.cpu1.isa] +type=ArmISA +fpsid=1090793632 +id_isar0=34607377 +id_isar1=34677009 +id_isar2=555950401 +id_isar3=17899825 +id_isar4=268501314 +id_isar5=0 +id_mmfr0=3 +id_mmfr1=0 +id_mmfr2=19070976 +id_mmfr3=4027589137 +id_pfr0=49 +id_pfr1=1 +midr=890224640 + [system.cpu1.itb] type=ArmTLB children=walker @@ -949,7 +985,7 @@ walker=system.cpu1.itb.walker [system.cpu1.itb.walker] type=ArmTableWalker -clock=1 +clock=500 num_squash_per_cycle=2 sys=system port=system.toL2Bus.slave[6] @@ -976,18 +1012,18 @@ type=BaseCache addr_ranges=0:268435455 assoc=8 block_size=64 -clock=1 +clock=1000 forward_snoops=false hash_delay=1 -hit_latency=50000 -is_top_level=false +hit_latency=50 +is_top_level=true max_miss_count=0 mshrs=20 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=50000 +response_latency=50 size=1024 subblock_size=0 system=system @@ -1003,22 +1039,22 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=8 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=10000 +hit_latency=20 is_top_level=false max_miss_count=0 -mshrs=92 +mshrs=20 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=10000 +response_latency=20 size=4194304 subblock_size=0 system=system -tgts_per_mshr=16 +tgts_per_mshr=12 trace_addr=0 two_queue=false write_buffers=8 @@ -1039,7 +1075,7 @@ slave=system.system_port system.iocache.mem_side system.l2c.mem_side [system.membus.badaddr_responder] type=IsaFake -clock=1 +clock=1000 fake_mem=false pio_addr=0 pio_latency=100000 @@ -1055,15 +1091,28 @@ warn_access=warn pio=system.membus.default [system.physmem] -type=SimpleMemory -bandwidth=73.000000 -clock=1 +type=SimpleDRAM +addr_mapping=openmap +banks_per_rank=8 +clock=1000 conf_table_reported=true in_addr_map=true -latency=30000 -latency_var=0 +lines_per_rowbuffer=64 +mem_sched_policy=fcfs null=false +page_policy=open range=0:134217727 +ranks_per_channel=2 +read_buffer_size=32 +tBURST=4000 +tCL=14000 +tRCD=14000 +tREFI=7800000 +tRFC=300000 +tRP=14000 +tWTR=1000 +write_buffer_size=32 +write_thresh_perc=70 zero=false port=system.membus.master[2] @@ -1078,7 +1127,7 @@ system=system [system.realview.a9scu] type=A9SCU -clock=1 +clock=1000 pio_addr=520093696 pio_latency=100000 system=system @@ -1087,7 +1136,7 @@ pio=system.membus.master[5] [system.realview.aaci_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268451840 pio_latency=100000 @@ -1134,7 +1183,7 @@ SubClassCode=1 SubsystemID=0 SubsystemVendorID=0 VendorID=32902 -clock=1 +clock=1000 config_latency=20000 ctrl_offset=2 disks=system.cf0 @@ -1165,7 +1214,7 @@ pio=system.iobus.master[4] [system.realview.dmac_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268632064 pio_latency=100000 @@ -1174,7 +1223,7 @@ pio=system.iobus.master[9] [system.realview.flash_fake] type=IsaFake -clock=1 +clock=1000 fake_mem=true pio_addr=1073741824 pio_latency=100000 @@ -1191,7 +1240,7 @@ pio=system.iobus.master[24] [system.realview.gic] type=Gic -clock=1 +clock=1000 cpu_addr=520093952 cpu_pio_delay=10000 dist_addr=520097792 @@ -1205,7 +1254,7 @@ pio=system.membus.master[3] [system.realview.gpio0_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268513280 pio_latency=100000 @@ -1215,7 +1264,7 @@ pio=system.iobus.master[16] [system.realview.gpio1_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268517376 pio_latency=100000 @@ -1225,7 +1274,7 @@ pio=system.iobus.master[17] [system.realview.gpio2_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268521472 pio_latency=100000 @@ -1235,7 +1284,7 @@ pio=system.iobus.master[18] [system.realview.kmi0] type=Pl050 amba_id=1314896 -clock=1 +clock=1000 gic=system.realview.gic int_delay=1000000 int_num=52 @@ -1249,7 +1298,7 @@ pio=system.iobus.master[5] [system.realview.kmi1] type=Pl050 amba_id=1314896 -clock=1 +clock=1000 gic=system.realview.gic int_delay=1000000 int_num=53 @@ -1262,7 +1311,7 @@ pio=system.iobus.master[6] [system.realview.l2x0_fake] type=IsaFake -clock=1 +clock=1000 fake_mem=false pio_addr=520101888 pio_latency=100000 @@ -1291,7 +1340,7 @@ pio=system.membus.master[6] [system.realview.mmc_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268455936 pio_latency=100000 @@ -1301,7 +1350,7 @@ pio=system.iobus.master[22] [system.realview.nvmem] type=SimpleMemory bandwidth=73.000000 -clock=1 +clock=1000 conf_table_reported=false in_addr_map=true latency=30000 @@ -1313,7 +1362,7 @@ port=system.membus.master[1] [system.realview.realview_io] type=RealViewCtrl -clock=1 +clock=1000 idreg=0 pio_addr=268435456 pio_latency=100000 @@ -1325,7 +1374,7 @@ pio=system.iobus.master[1] [system.realview.rtc] type=PL031 amba_id=3412017 -clock=1 +clock=1000 gic=system.realview.gic int_delay=100000 int_num=42 @@ -1338,7 +1387,7 @@ pio=system.iobus.master[23] [system.realview.sci_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268492800 pio_latency=100000 @@ -1348,7 +1397,7 @@ pio=system.iobus.master[20] [system.realview.smc_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=269357056 pio_latency=100000 @@ -1358,7 +1407,7 @@ pio=system.iobus.master[13] [system.realview.sp810_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=true pio_addr=268439552 pio_latency=100000 @@ -1368,7 +1417,7 @@ pio=system.iobus.master[14] [system.realview.ssp_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268488704 pio_latency=100000 @@ -1378,7 +1427,7 @@ pio=system.iobus.master[19] [system.realview.timer0] type=Sp804 amba_id=1316868 -clock=1 +clock=1000 clock0=1000000 clock1=1000000 gic=system.realview.gic @@ -1392,7 +1441,7 @@ pio=system.iobus.master[2] [system.realview.timer1] type=Sp804 amba_id=1316868 -clock=1 +clock=1000 clock0=1000000 clock1=1000000 gic=system.realview.gic @@ -1405,7 +1454,7 @@ pio=system.iobus.master[3] [system.realview.uart] type=Pl011 -clock=1 +clock=1000 end_on_eot=false gic=system.realview.gic int_delay=100000 @@ -1420,7 +1469,7 @@ pio=system.iobus.master[0] [system.realview.uart1_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268476416 pio_latency=100000 @@ -1430,7 +1479,7 @@ pio=system.iobus.master[10] [system.realview.uart2_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268480512 pio_latency=100000 @@ -1440,7 +1489,7 @@ pio=system.iobus.master[11] [system.realview.uart3_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268484608 pio_latency=100000 @@ -1450,7 +1499,7 @@ pio=system.iobus.master[12] [system.realview.watchdog_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268500992 pio_latency=100000 @@ -1467,7 +1516,7 @@ port=3456 [system.toL2Bus] type=CoherentBus block_size=64 -clock=1000 +clock=500 header_cycles=1 use_default_range=false width=8 diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr index 04178bb32..e8e271d58 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr @@ -12,7 +12,6 @@ warn: instruction 'mcr dccmvau' unimplemented warn: instruction 'mcr icimvau' unimplemented warn: instruction 'mcr bpiallis' unimplemented warn: LCD dual screen mode not supported -warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors warn: instruction 'mcr icialluis' unimplemented warn: instruction 'mcr icialluis' unimplemented hack: be nice to actually delete the event here diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout index 4c598b20c..ac731cab9 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 21 2012 11:19:00 -gem5 started Sep 21 2012 12:18:35 +gem5 compiled Oct 30 2012 11:20:14 +gem5 started Oct 30 2012 21:14:52 gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual Global frequency set at 1000000000000 ticks per second info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: Using bootloader at address 0x80000000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 2616878893500 because m5_exit instruction encountered +Exiting @ tick 2593146078000 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt index 30d23f9d7..2681ab283 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt @@ -1,131 +1,135 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.603317 # Number of seconds simulated -sim_ticks 2603316759000 # Number of ticks simulated -final_tick 2603316759000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.593146 # Number of seconds simulated +sim_ticks 2593146078000 # Number of ticks simulated +final_tick 2593146078000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 64170 # Simulator instruction rate (inst/s) -host_op_rate 82590 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2648964509 # Simulator tick rate (ticks/s) -host_mem_usage 407980 # Number of bytes of host memory used -host_seconds 982.77 # Real time elapsed on the host -sim_insts 63063787 # Number of instructions simulated -sim_ops 81167171 # Number of ops (including micro ops) simulated +host_inst_rate 66425 # Simulator instruction rate (inst/s) +host_op_rate 85503 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2731005239 # Simulator tick rate (ticks/s) +host_mem_usage 409388 # Number of bytes of host memory used +host_seconds 949.52 # Real time elapsed on the host +sim_insts 63072130 # Number of instructions simulated +sim_ops 81187111 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 832 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 896 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 396352 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4375860 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 1024 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 425408 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 5260720 # Number of bytes read from this memory -system.physmem.bytes_read::total 131570852 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 396352 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 425408 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 821760 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4284288 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.inst 395328 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4376500 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 960 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 426752 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 5261232 # Number of bytes read from this memory +system.physmem.bytes_read::total 131572388 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 395328 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 426752 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 822080 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4282048 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 3012136 # Number of bytes written to this memory -system.physmem.bytes_written::total 7313424 # Number of bytes written to this memory +system.physmem.bytes_written::total 7311184 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 13 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 14 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 6193 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 68445 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 16 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 6647 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 82225 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15302357 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 66942 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu0.inst 6177 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 68455 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 15 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 6668 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 82233 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15302381 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 66907 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 753034 # Number of write requests responded to by this memory -system.physmem.num_writes::total 824226 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 46521626 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 320 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 824191 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 46704090 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 346 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 49 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 152249 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1680879 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 393 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 163410 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 2020776 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 50539702 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 152249 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 163410 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 315659 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1645704 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 6530 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 1157038 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2809272 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1645704 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 46521626 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 320 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 152451 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1687718 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 370 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 25 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 164569 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 2028899 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 50738518 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 152451 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 164569 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 317020 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1651295 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 6556 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 1161576 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2819426 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1651295 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 46704090 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 346 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 49 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 152249 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 1687409 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 393 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 163410 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 3177814 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53348973 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15302357 # Total number of read requests seen -system.physmem.writeReqs 824226 # Total number of write requests seen -system.physmem.cpureqs 284853 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 979350848 # Total number of bytes read from memory -system.physmem.bytesWritten 52750464 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 131570852 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 7313424 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 375 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 14171 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 956419 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 956744 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 956349 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 956561 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 956521 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 956118 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 955968 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 956063 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 957003 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 956395 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 956361 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 956664 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 956312 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 956494 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 956128 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 955882 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 50798 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 51080 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 50753 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 50993 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 51913 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 51591 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 51454 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 51530 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 52149 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 51821 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 51633 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 51817 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 51736 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 51833 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 51645 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 51480 # Track writes on a per bank basis +system.physmem.bw_total::cpu0.inst 152451 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1694274 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 370 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 25 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 164569 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 3190475 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53557944 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15302381 # Total number of read requests seen +system.physmem.writeReqs 824191 # Total number of write requests seen +system.physmem.cpureqs 284713 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 979352384 # Total number of bytes read from memory +system.physmem.bytesWritten 52748224 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 131572388 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 7311184 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 335 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 14131 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 956528 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 956655 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 956404 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 956499 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 956473 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 956086 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 955879 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 956080 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 957009 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 956354 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 956393 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 956606 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 956350 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 956542 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 956247 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 955941 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 50875 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 51001 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 50801 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 50933 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 51869 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 51569 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 51383 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 51546 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 52151 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 51788 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 51664 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 51769 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 51735 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 51864 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 51697 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 51546 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 1152088 # Number of times wr buffer was full causing retry -system.physmem.totGap 2603315545500 # Total gap between requests +system.physmem.numWrRetry 1150487 # Number of times wr buffer was full causing retry +system.physmem.totGap 2593144762500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 105 # Categorize read packet sizes system.physmem.readPktSize::3 15138816 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 163436 # Categorize read packet sizes +system.physmem.readPktSize::6 163460 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 1909372 # categorize write packet sizes +system.physmem.writePktSize::2 1907771 # categorize write packet sizes system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 66942 # categorize write packet sizes +system.physmem.writePktSize::6 66907 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -134,29 +138,29 @@ system.physmem.neitherpktsize::2 0 # ca system.physmem.neitherpktsize::3 0 # categorize neither packet sizes system.physmem.neitherpktsize::4 0 # categorize neither packet sizes system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 14171 # categorize neither packet sizes +system.physmem.neitherpktsize::6 14131 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 15151636 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 94017 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 8640 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3524 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2842 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2641 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2454 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 2030 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1454 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1352 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1387 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 6499 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 9632 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 13082 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 603 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 103 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 62 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 15151641 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 94331 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 8809 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3486 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2848 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2557 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2313 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1993 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1407 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1368 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1369 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 6472 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 9621 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 13063 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 592 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 97 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 54 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 23 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see @@ -170,60 +174,60 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 3194 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 3392 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 3540 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 3651 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 3816 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 4008 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 4231 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 4426 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 4620 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 35836 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 35836 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 35836 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 35836 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 35836 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 35836 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 35836 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 35836 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 35836 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 35836 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 35836 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 35836 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 35835 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 35835 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 32642 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 32444 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 32296 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 32185 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 32020 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 31828 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 31605 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 31410 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 31216 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 3183 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 3385 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 3534 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 3673 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 3833 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 4027 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 4248 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 4407 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 4586 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 35834 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 35834 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 35834 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 35834 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 35834 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 35834 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 35834 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 35834 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 35834 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 35834 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 35834 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 35834 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 35834 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 35834 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 32652 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 32450 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 32301 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 32162 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 32002 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 31808 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 31587 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 31428 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 31249 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 48061683883 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 322412499883 # Sum of mem lat for all requests -system.physmem.totBusLat 61207928000 # Total cycles spent in databus access -system.physmem.totBankLat 213142888000 # Total cycles spent in bank access -system.physmem.avgQLat 3140.88 # Average queueing delay per request -system.physmem.avgBankLat 13929.10 # Average bank access latency per request +system.physmem.totQLat 47868619345 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 322210199345 # Sum of mem lat for all requests +system.physmem.totBusLat 61208184000 # Total cycles spent in databus access +system.physmem.totBankLat 213133396000 # Total cycles spent in bank access +system.physmem.avgQLat 3128.25 # Average queueing delay per request +system.physmem.avgBankLat 13928.42 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 21069.98 # Average memory access latency -system.physmem.avgRdBW 376.19 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 20.26 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 50.54 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 2.81 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 21056.67 # Average memory access latency +system.physmem.avgRdBW 377.67 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 20.34 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 50.74 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 2.82 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 2.48 # Data bus utilization in percentage +system.physmem.busUtil 2.49 # Data bus utilization in percentage system.physmem.avgRdQLen 0.12 # Average read queue length over time -system.physmem.avgWrQLen 11.94 # Average write queue length over time -system.physmem.readRowHits 15253098 # Number of row buffer hits during reads -system.physmem.writeRowHits 789391 # Number of row buffer hits during writes +system.physmem.avgWrQLen 10.88 # Average write queue length over time +system.physmem.readRowHits 15253448 # Number of row buffer hits during reads +system.physmem.writeRowHits 789566 # Number of row buffer hits during writes system.physmem.readRowHitRate 99.68 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 95.77 # Row buffer hit rate for writes -system.physmem.avgGap 161430.08 # Average gap between requests +system.physmem.writeRowHitRate 95.80 # Row buffer hit rate for writes +system.physmem.avgGap 160799.50 # Average gap between requests system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 384 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 448 # Number of bytes read from this memory @@ -235,244 +239,258 @@ system.realview.nvmem.num_reads::cpu1.inst 6 # system.realview.nvmem.num_reads::total 7 # Number of read requests responded to by this memory system.realview.nvmem.bw_read::cpu0.inst 25 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_read::cpu1.inst 148 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 172 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 173 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_inst_read::cpu0.inst 25 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_inst_read::cpu1.inst 148 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 172 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 173 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu0.inst 25 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.inst 148 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 172 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 73153 # number of replacements -system.l2c.tagsinuse 53083.361452 # Cycle average of tags in use -system.l2c.total_refs 1922203 # Total number of references to valid blocks. -system.l2c.sampled_refs 138333 # Sample count of references to valid blocks. -system.l2c.avg_refs 13.895477 # Average number of references to valid blocks. +system.realview.nvmem.bw_total::total 173 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 73184 # number of replacements +system.l2c.tagsinuse 53096.266008 # Cycle average of tags in use +system.l2c.total_refs 1906265 # Total number of references to valid blocks. +system.l2c.sampled_refs 138351 # Sample count of references to valid blocks. +system.l2c.avg_refs 13.778469 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 37742.975736 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.dtb.walker 6.244346 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.itb.walker 0.876765 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 4208.985983 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 2954.129199 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.dtb.walker 11.276001 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 4048.165548 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 4110.707874 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.575912 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.dtb.walker 0.000095 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.itb.walker 0.000013 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.064224 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.045076 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.dtb.walker 0.000172 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.061770 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.062724 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.809988 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.dtb.walker 35828 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 5516 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 398518 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 165446 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 53941 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 6316 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 614017 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 202060 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1481642 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 584379 # number of Writeback hits -system.l2c.Writeback_hits::total 584379 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 1214 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 738 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 1952 # number of UpgradeReq hits +system.l2c.occ_blocks::writebacks 37733.790025 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.dtb.walker 7.219153 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.itb.walker 0.000341 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 4206.047810 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 2960.317078 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.dtb.walker 11.178862 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.itb.walker 0.966447 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 4058.933416 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 4117.812877 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.575772 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.dtb.walker 0.000110 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.inst 0.064179 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.data 0.045171 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.dtb.walker 0.000171 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.itb.walker 0.000015 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.inst 0.061934 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.data 0.062833 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.810185 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.dtb.walker 33579 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 4963 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 393016 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 165084 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 53008 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 6038 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 608232 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 201468 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1465388 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 583960 # number of Writeback hits +system.l2c.Writeback_hits::total 583960 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 1107 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 848 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 1955 # number of UpgradeReq hits system.l2c.SCUpgradeReq_hits::cpu0.data 209 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 156 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 365 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 47923 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 58901 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 106824 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 35828 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 5516 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 398518 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 213369 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 53941 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 6316 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 614017 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 260961 # number of demand (read+write) hits -system.l2c.demand_hits::total 1588466 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 35828 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 5516 # number of overall hits -system.l2c.overall_hits::cpu0.inst 398518 # number of overall hits -system.l2c.overall_hits::cpu0.data 213369 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 53941 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 6316 # number of overall hits -system.l2c.overall_hits::cpu1.inst 614017 # number of overall hits -system.l2c.overall_hits::cpu1.data 260961 # number of overall hits -system.l2c.overall_hits::total 1588466 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 13 # number of ReadReq misses +system.l2c.SCUpgradeReq_hits::cpu1.data 159 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 368 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 47823 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 59123 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 106946 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 33579 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 4963 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 393016 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 212907 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 53008 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 6038 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 608232 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 260591 # number of demand (read+write) hits +system.l2c.demand_hits::total 1572334 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 33579 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 4963 # number of overall hits +system.l2c.overall_hits::cpu0.inst 393016 # number of overall hits +system.l2c.overall_hits::cpu0.data 212907 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 53008 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 6038 # number of overall hits +system.l2c.overall_hits::cpu1.inst 608232 # number of overall hits +system.l2c.overall_hits::cpu1.data 260591 # number of overall hits +system.l2c.overall_hits::total 1572334 # number of overall hits +system.l2c.ReadReq_misses::cpu0.dtb.walker 14 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 6067 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 6359 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 16 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 6609 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 6244 # number of ReadReq misses -system.l2c.ReadReq_misses::total 25310 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 5733 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 4361 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 10094 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 775 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 597 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1372 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 63477 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 77252 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 140729 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.dtb.walker 13 # number of demand (read+write) misses +system.l2c.ReadReq_misses::cpu0.inst 6056 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 6345 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.dtb.walker 15 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.itb.walker 1 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 6633 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 6362 # number of ReadReq misses +system.l2c.ReadReq_misses::total 25428 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 5684 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 4404 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 10088 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 773 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 585 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 1358 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 63519 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 77106 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 140625 # number of ReadExReq misses +system.l2c.demand_misses::cpu0.dtb.walker 14 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 6067 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 69836 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 16 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 6609 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 83496 # number of demand (read+write) misses -system.l2c.demand_misses::total 166039 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 13 # number of overall misses +system.l2c.demand_misses::cpu0.inst 6056 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 69864 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.dtb.walker 15 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.itb.walker 1 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 6633 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 83468 # number of demand (read+write) misses +system.l2c.demand_misses::total 166053 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.dtb.walker 14 # number of overall misses system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses -system.l2c.overall_misses::cpu0.inst 6067 # number of overall misses -system.l2c.overall_misses::cpu0.data 69836 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 16 # number of overall misses -system.l2c.overall_misses::cpu1.inst 6609 # number of overall misses -system.l2c.overall_misses::cpu1.data 83496 # number of overall misses -system.l2c.overall_misses::total 166039 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 935000 # number of ReadReq miss cycles +system.l2c.overall_misses::cpu0.inst 6056 # number of overall misses +system.l2c.overall_misses::cpu0.data 69864 # number of overall misses +system.l2c.overall_misses::cpu1.dtb.walker 15 # number of overall misses +system.l2c.overall_misses::cpu1.itb.walker 1 # number of overall misses +system.l2c.overall_misses::cpu1.inst 6633 # number of overall misses +system.l2c.overall_misses::cpu1.data 83468 # number of overall misses +system.l2c.overall_misses::total 166053 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 1175500 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu0.itb.walker 118000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.inst 317714000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 346268999 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 1088500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 363822000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 365563000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 1395509499 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 9087986 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 11973500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 21061486 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 478000 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 3102500 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 3580500 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 3187413984 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 4286901491 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 7474315475 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.dtb.walker 935000 # number of demand (read+write) miss cycles +system.l2c.ReadReq_miss_latency::cpu0.inst 320358500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 344253498 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 1038500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.itb.walker 122500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 371653000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 369594500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 1408313998 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0.data 9084989 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 12192500 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 21277489 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.data 591000 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu1.data 2932000 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 3523000 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 3155374488 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 4272368491 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 7427742979 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0.dtb.walker 1175500 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu0.itb.walker 118000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 317714000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 3533682983 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.dtb.walker 1088500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 363822000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 4652464491 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 8869824974 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.dtb.walker 935000 # number of overall miss cycles +system.l2c.demand_miss_latency::cpu0.inst 320358500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 3499627986 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.dtb.walker 1038500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.itb.walker 122500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 371653000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 4641962991 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 8836056977 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.dtb.walker 1175500 # number of overall miss cycles system.l2c.overall_miss_latency::cpu0.itb.walker 118000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.inst 317714000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 3533682983 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.dtb.walker 1088500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 363822000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 4652464491 # number of overall miss cycles -system.l2c.overall_miss_latency::total 8869824974 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.dtb.walker 35841 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 5518 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 404585 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 171805 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 53957 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 6316 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 620626 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 208304 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 1506952 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 584379 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 584379 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 6947 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 5099 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 12046 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 984 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 753 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 1737 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 111400 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 136153 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 247553 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 35841 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 5518 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 404585 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 283205 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 53957 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 6316 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 620626 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 344457 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 1754505 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 35841 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 5518 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 404585 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 283205 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 53957 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 6316 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 620626 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 344457 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 1754505 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000363 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000362 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.014996 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.037013 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000297 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.010649 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.029975 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.016795 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.825248 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.855266 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.837955 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.787602 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.792829 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.789868 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.569811 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.567391 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.568480 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000363 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.000362 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.014996 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.246592 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000297 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.010649 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.242399 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.094636 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000363 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.000362 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.014996 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.246592 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000297 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.010649 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.242399 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.094636 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 71923.076923 # average ReadReq miss latency +system.l2c.overall_miss_latency::cpu0.inst 320358500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 3499627986 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.dtb.walker 1038500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.itb.walker 122500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 371653000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 4641962991 # number of overall miss cycles +system.l2c.overall_miss_latency::total 8836056977 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.dtb.walker 33593 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 4965 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 399072 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 171429 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 53023 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 6039 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 614865 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 207830 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 1490816 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 583960 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 583960 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 6791 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 5252 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 12043 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 982 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 744 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 1726 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 111342 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 136229 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 247571 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 33593 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 4965 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 399072 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 282771 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 53023 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 6039 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 614865 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 344059 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 1738387 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 33593 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 4965 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 399072 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 282771 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 53023 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 6039 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 614865 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 344059 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 1738387 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000417 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000403 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.015175 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.037012 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000283 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.000166 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.010788 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.030612 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.017056 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.836990 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.838538 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.837665 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.787169 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.786290 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.786790 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.570486 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.566003 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.568019 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000417 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.000403 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.015175 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.247069 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000283 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.itb.walker 0.000166 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.010788 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.242598 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.095521 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000417 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.000403 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.015175 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.247069 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000283 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.itb.walker 0.000166 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.010788 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.242598 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.095521 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 83964.285714 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 59000 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52367.562222 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 54453.373015 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 68031.250000 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 55049.477985 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 58546.284433 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 55136.685065 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 1585.206000 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 2745.585875 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 2086.535169 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 616.774194 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 5196.817420 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 2609.693878 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 50213.683444 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 55492.433736 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 53111.408985 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 71923.076923 # average overall miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52899.356011 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.data 54255.870449 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 69233.333333 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 122500 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 56030.906076 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 58094.074191 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 55384.379346 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 1598.344300 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 2768.505904 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 2109.188045 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 764.553687 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 5011.965812 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 2594.256259 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 49676.073112 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 55409.027715 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 52819.505628 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 83964.285714 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu0.itb.walker 59000 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 52367.562222 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 50599.733418 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 68031.250000 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 55049.477985 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 55720.806877 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 53420.130054 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 71923.076923 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 52899.356011 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 50092.007128 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 69233.333333 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.itb.walker 122500 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 56030.906076 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 55613.684178 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 53212.269438 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 83964.285714 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.itb.walker 59000 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 52367.562222 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 50599.733418 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 68031.250000 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 55049.477985 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 55720.806877 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 53420.130054 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 52899.356011 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 50092.007128 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 69233.333333 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.itb.walker 122500 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 56030.906076 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 55613.684178 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 53212.269438 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -481,168 +499,180 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 66942 # number of writebacks -system.l2c.writebacks::total 66942 # number of writebacks -system.l2c.ReadReq_mshr_hits::cpu0.inst 4 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu0.data 38 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu1.inst 7 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu1.data 24 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::total 73 # number of ReadReq MSHR hits -system.l2c.demand_mshr_hits::cpu0.inst 4 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu0.data 38 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1.inst 7 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1.data 24 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 73 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu0.inst 4 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu0.data 38 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1.inst 7 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1.data 24 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 73 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 13 # number of ReadReq MSHR misses +system.l2c.writebacks::writebacks 66907 # number of writebacks +system.l2c.writebacks::total 66907 # number of writebacks +system.l2c.ReadReq_mshr_hits::cpu0.inst 3 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu0.data 39 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu1.inst 8 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu1.data 25 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::total 75 # number of ReadReq MSHR hits +system.l2c.demand_mshr_hits::cpu0.inst 3 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu0.data 39 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1.inst 8 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1.data 25 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 75 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits::cpu0.inst 3 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu0.data 39 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1.inst 8 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1.data 25 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 75 # number of overall MSHR hits +system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 14 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 2 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.inst 6063 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.data 6321 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 16 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 6602 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 6220 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 25237 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 5733 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 4361 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 10094 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 775 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 597 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 1372 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 63477 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 77252 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 140729 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu0.dtb.walker 13 # number of demand (read+write) MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.inst 6053 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.data 6306 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 15 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 1 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.inst 6625 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 6337 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 25353 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 5684 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 4404 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 10088 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 773 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 585 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 1358 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 63519 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 77106 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 140625 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu0.dtb.walker 14 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu0.itb.walker 2 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 6063 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 69798 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.dtb.walker 16 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 6602 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 83472 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 165966 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0.dtb.walker 13 # number of overall MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 6053 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 69825 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.dtb.walker 15 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.itb.walker 1 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 6625 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 83443 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 165978 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0.dtb.walker 14 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu0.itb.walker 2 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 6063 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 69798 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.dtb.walker 16 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 6602 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 83472 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 165966 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 769524 # number of ReadReq MSHR miss cycles +system.l2c.overall_mshr_misses::cpu0.inst 6053 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 69825 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.dtb.walker 15 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.itb.walker 1 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 6625 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 83443 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 165978 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 998025 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 93002 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 240985728 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.data 264114875 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 885028 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 280065375 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 285358123 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 1072271655 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 57814013 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 44321751 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 102135764 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 7773761 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 5990089 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 13763850 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 2401729527 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 3326209366 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 5727938893 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 769524 # number of demand (read+write) MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 243809691 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.data 262215347 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 849526 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 109502 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 287575375 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 287912849 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 1083563317 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 57255976 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 44756275 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 102012251 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 7762758 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 5877575 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 13640333 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 2369346199 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 3313598990 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 5682945189 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 998025 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 93002 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 240985728 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 2665844402 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 885028 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 280065375 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 3611567489 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 6800210548 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 769524 # number of overall MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 243809691 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 2631561546 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 849526 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 109502 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 287575375 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 3601511839 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 6766508506 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 998025 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 93002 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 240985728 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 2665844402 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 885028 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 280065375 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 3611567489 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 6800210548 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 4694165 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 12330499053 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 1876066 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 154911224998 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 167248294282 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1062750734 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 17129759420 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 18192510154 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 4694165 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 13393249787 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 1876066 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 172040984418 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 185440804436 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000363 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000362 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.014986 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.036792 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000297 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010638 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.029860 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.016747 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.825248 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.855266 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.837955 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.787602 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.792829 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.789868 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.569811 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.567391 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.568480 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000363 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000362 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.014986 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.246458 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000297 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010638 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.242329 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.094594 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000363 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000362 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.014986 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.246458 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000297 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010638 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.242329 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.094594 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 59194.153846 # average ReadReq mshr miss latency +system.l2c.overall_mshr_miss_latency::cpu0.inst 243809691 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 2631561546 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 849526 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 109502 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 287575375 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 3601511839 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 6766508506 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 4558163 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 12330302064 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 1815064 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 154912119500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 167248794791 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1062521236 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 17116054868 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 18178576104 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 4558163 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 13392823300 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 1815064 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 172028174368 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 185427370895 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000417 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000403 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015168 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.036785 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000283 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.000166 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010775 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.030491 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.017006 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.836990 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.838538 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.837665 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.787169 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.786290 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.786790 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.570486 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.566003 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.568019 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000417 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000403 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015168 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.246931 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000283 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.000166 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010775 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.242525 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.095478 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000417 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000403 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015168 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.246931 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000283 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.000166 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010775 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.242525 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.095478 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 71287.500000 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 46501 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 39746.945077 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 41783.716975 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 55314.250000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 42421.292790 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 45877.511736 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 42488.079209 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10084.425781 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10163.208209 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10118.462849 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10030.659355 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10033.649916 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10031.960641 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 37836.216693 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 43056.611686 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 40701.908583 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 59194.153846 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40279.149347 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 41581.881859 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 56635.066667 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 109502 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 43407.603774 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 45433.619852 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 42739.057192 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10073.183673 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10162.641916 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10112.237411 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10042.377749 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10047.136752 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10044.427835 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 37301.377525 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 42974.593287 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 40412.054677 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 71287.500000 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 46501 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 39746.945077 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 38193.707585 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 55314.250000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 42421.292790 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 43266.813890 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 40973.515949 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 59194.153846 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40279.149347 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 37687.956262 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 56635.066667 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 109502 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 43407.603774 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 43161.341742 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40767.502356 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 71287.500000 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 46501 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 39746.945077 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 38193.707585 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 55314.250000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 42421.292790 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 43266.813890 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40973.515949 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40279.149347 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 37687.956262 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 56635.066667 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 109502 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 43407.603774 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 43161.341742 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40767.502356 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -665,27 +695,27 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 9063545 # DTB read hits -system.cpu0.dtb.read_misses 36220 # DTB read misses -system.cpu0.dtb.write_hits 5280653 # DTB write hits -system.cpu0.dtb.write_misses 6480 # DTB write misses +system.cpu0.dtb.read_hits 9014303 # DTB read hits +system.cpu0.dtb.read_misses 34965 # DTB read misses +system.cpu0.dtb.write_hits 5253714 # DTB write hits +system.cpu0.dtb.write_misses 6399 # DTB write misses system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 2158 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 1224 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 336 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 2155 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 1094 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 321 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 569 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 9099765 # DTB read accesses -system.cpu0.dtb.write_accesses 5287133 # DTB write accesses +system.cpu0.dtb.perms_faults 573 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 9049268 # DTB read accesses +system.cpu0.dtb.write_accesses 5260113 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 14344198 # DTB hits -system.cpu0.dtb.misses 42700 # DTB misses -system.cpu0.dtb.accesses 14386898 # DTB accesses -system.cpu0.itb.inst_hits 4425189 # ITB inst hits -system.cpu0.itb.inst_misses 5562 # ITB inst misses +system.cpu0.dtb.hits 14268017 # DTB hits +system.cpu0.dtb.misses 41364 # DTB misses +system.cpu0.dtb.accesses 14309381 # DTB accesses +system.cpu0.itb.inst_hits 4294311 # ITB inst hits +system.cpu0.itb.inst_misses 5261 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -694,542 +724,538 @@ system.cpu0.itb.flush_tlb 4 # Nu system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 1395 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 1385 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 1518 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 1364 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 4430751 # ITB inst accesses -system.cpu0.itb.hits 4425189 # DTB hits -system.cpu0.itb.misses 5562 # DTB misses -system.cpu0.itb.accesses 4430751 # DTB accesses -system.cpu0.numCycles 69436793 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 4299572 # ITB inst accesses +system.cpu0.itb.hits 4294311 # DTB hits +system.cpu0.itb.misses 5261 # DTB misses +system.cpu0.itb.accesses 4299572 # DTB accesses +system.cpu0.numCycles 69013505 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.BPredUnit.lookups 6232893 # Number of BP lookups -system.cpu0.BPredUnit.condPredicted 4743306 # Number of conditional branches predicted -system.cpu0.BPredUnit.condIncorrect 327822 # Number of conditional branches incorrect -system.cpu0.BPredUnit.BTBLookups 3788300 # Number of BTB lookups -system.cpu0.BPredUnit.BTBHits 3047807 # Number of BTB hits +system.cpu0.BPredUnit.lookups 6123831 # Number of BP lookups +system.cpu0.BPredUnit.condPredicted 4675790 # Number of conditional branches predicted +system.cpu0.BPredUnit.condIncorrect 298271 # Number of conditional branches incorrect +system.cpu0.BPredUnit.BTBLookups 3798227 # Number of BTB lookups +system.cpu0.BPredUnit.BTBHits 2989296 # Number of BTB hits system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.BPredUnit.usedRAS 701189 # Number of times the RAS was used to get a target. -system.cpu0.BPredUnit.RASInCorrect 31986 # Number of incorrect RAS predictions. -system.cpu0.fetch.icacheStallCycles 12165372 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 33223009 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 6232893 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 3748996 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 7801748 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 1579515 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 70495 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.BlockedCycles 21773574 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 5807 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 55458 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 92257 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 165 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 4423471 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 173760 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 2652 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 43098147 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.994806 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.374305 # Number of instructions fetched each cycle (Total) +system.cpu0.BPredUnit.usedRAS 685728 # Number of times the RAS was used to get a target. +system.cpu0.BPredUnit.RASInCorrect 28375 # Number of incorrect RAS predictions. +system.cpu0.fetch.icacheStallCycles 11998527 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 32710943 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 6123831 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 3675024 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 7667644 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 1480146 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 66638 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.BlockedCycles 21758305 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 5862 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 53793 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 90248 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 221 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 4292744 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 155269 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 2401 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 42704543 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.988603 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.369673 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 35304381 81.92% 81.92% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 609582 1.41% 83.33% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 823952 1.91% 85.24% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 710643 1.65% 86.89% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 795409 1.85% 88.74% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 570879 1.32% 90.06% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 720960 1.67% 91.73% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 375620 0.87% 92.61% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 3186721 7.39% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 35044149 82.06% 82.06% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 606065 1.42% 83.48% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 793528 1.86% 85.34% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 689319 1.61% 86.95% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 781424 1.83% 88.78% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 567584 1.33% 90.11% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 711320 1.67% 91.78% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 364019 0.85% 92.63% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 3147135 7.37% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 43098147 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.089764 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.478464 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 12694368 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 21733151 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 7021973 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 580158 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1068497 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 974425 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 66014 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 41440720 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 216131 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 1068497 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 13283568 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 5811502 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 13763022 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 6961604 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 2209954 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 40230567 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 2204 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 441496 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 1232571 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.FullRegisterEvents 70 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 40628697 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 181762207 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 181727693 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 34514 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 31673882 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 8954814 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 460934 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 417253 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 5454618 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 7893877 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 5899231 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1129288 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 1250491 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 37987189 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 942287 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 38211306 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 88088 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 6766776 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 14417426 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 253739 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 43098147 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.886611 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.498890 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 42704543 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.088734 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.473979 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 12497333 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 21726841 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 6896095 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 584636 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 999638 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 951812 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 64726 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 40836330 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 213865 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 999638 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 13071648 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 5812993 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 13759259 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 6855374 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 2205631 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 39711904 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 2173 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 427558 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 1242268 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.FullRegisterEvents 68 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 40116309 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 179435830 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 179401258 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 34572 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 31681024 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 8435284 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 457771 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 414521 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 5443309 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 7819363 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 5820332 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1146243 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 1242216 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 37575405 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 946067 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 37951575 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 82274 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 6366228 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 13456450 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 257591 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 42704543 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.888701 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.500077 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 27429044 63.64% 63.64% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 6069688 14.08% 77.73% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 3249267 7.54% 85.27% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 2519397 5.85% 91.11% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2120550 4.92% 96.03% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 959758 2.23% 98.26% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 504062 1.17% 99.43% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 191517 0.44% 99.87% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 54864 0.13% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 27159670 63.60% 63.60% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 6000291 14.05% 77.65% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 3232720 7.57% 85.22% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 2489147 5.83% 91.05% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2132528 4.99% 96.04% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 950123 2.22% 98.27% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 497063 1.16% 99.43% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 188710 0.44% 99.87% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 54291 0.13% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 43098147 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 42704543 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 25519 2.38% 2.38% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 464 0.04% 2.42% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.42% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.42% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.42% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.42% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.42% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.42% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.42% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.42% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.42% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.42% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.42% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.42% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.42% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.42% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.42% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.42% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.42% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.42% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.42% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.42% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.42% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.42% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.42% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.42% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.42% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.42% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.42% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 839951 78.37% 80.80% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 205830 19.20% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 24659 2.31% 2.31% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 467 0.04% 2.35% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.35% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.35% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.35% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.35% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.35% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.35% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.35% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.35% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.35% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.35% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.35% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.35% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.35% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.35% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.35% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.35% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.35% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.35% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.35% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.35% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.35% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.35% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.35% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.35% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.35% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.35% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.35% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 838061 78.41% 80.76% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 205631 19.24% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 52084 0.14% 0.14% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 22953142 60.07% 60.21% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 49969 0.13% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 11 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 2 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 8 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 683 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 8 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 9542960 24.97% 85.31% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 5612439 14.69% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 52344 0.14% 0.14% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 22793341 60.06% 60.20% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 48224 0.13% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 10 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 1 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 7 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 680 0.00% 60.33% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 60.33% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 7 0.00% 60.33% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.33% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 9480747 24.98% 85.31% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 5576214 14.69% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 38211306 # Type of FU issued -system.cpu0.iq.rate 0.550303 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 1071764 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.028048 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 120714498 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 45704259 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 35275992 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 8506 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 4731 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 3909 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 39226540 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 4446 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 323503 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 37951575 # Type of FU issued +system.cpu0.iq.rate 0.549915 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 1068818 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.028163 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 119791525 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 44895833 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 35071497 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 8304 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 4710 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 3884 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 38963714 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 4335 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 318123 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1474665 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 3677 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 13402 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 626328 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1396327 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 2506 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 13403 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 544501 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 2149439 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 5367 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 2149359 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 5385 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1068497 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 4177933 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 101495 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 39049116 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 95858 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 7893877 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 5899231 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 616112 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 40709 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 3360 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 13402 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 173604 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 128122 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 301726 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 37794024 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 9381421 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 417282 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 999638 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 4184428 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 103741 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 38639126 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 85944 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 7819363 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 5820332 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 614711 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 41414 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 3290 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 13403 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 151339 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 119425 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 270764 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 37563861 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 9331167 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 387714 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 119640 # number of nop insts executed -system.cpu0.iew.exec_refs 14935051 # number of memory reference insts executed -system.cpu0.iew.exec_branches 4997979 # Number of branches executed -system.cpu0.iew.exec_stores 5553630 # Number of stores executed -system.cpu0.iew.exec_rate 0.544294 # Inst execution rate -system.cpu0.iew.wb_sent 37576425 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 35279901 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 18742857 # num instructions producing a value -system.cpu0.iew.wb_consumers 36023721 # num instructions consuming a value +system.cpu0.iew.exec_nop 117654 # number of nop insts executed +system.cpu0.iew.exec_refs 14857557 # number of memory reference insts executed +system.cpu0.iew.exec_branches 4958494 # Number of branches executed +system.cpu0.iew.exec_stores 5526390 # Number of stores executed +system.cpu0.iew.exec_rate 0.544297 # Inst execution rate +system.cpu0.iew.wb_sent 37365472 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 35075381 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 18655901 # num instructions producing a value +system.cpu0.iew.wb_consumers 35819655 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.508087 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.520292 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.508239 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.520829 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 6624150 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 688548 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 263048 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 42066039 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.760422 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.715065 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 6205381 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 688476 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 234604 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 41741265 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.766601 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.727877 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 29990291 71.29% 71.29% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 5984334 14.23% 85.52% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 1979513 4.71% 90.23% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 1007903 2.40% 92.62% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 802639 1.91% 94.53% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 528288 1.26% 95.79% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 397543 0.95% 96.73% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 220589 0.52% 97.25% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1154939 2.75% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 29720457 71.20% 71.20% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 5963123 14.29% 85.49% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 1948324 4.67% 90.16% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 1002440 2.40% 92.56% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 789371 1.89% 94.45% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 520489 1.25% 95.69% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 393953 0.94% 96.64% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 216687 0.52% 97.16% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1186421 2.84% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 42066039 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 24262669 # Number of instructions committed -system.cpu0.commit.committedOps 31987958 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 41741265 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 24264310 # Number of instructions committed +system.cpu0.commit.committedOps 31998915 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 11692115 # Number of memory references committed -system.cpu0.commit.loads 6419212 # Number of loads committed -system.cpu0.commit.membars 234468 # Number of memory barriers committed -system.cpu0.commit.branches 4346825 # Number of branches committed +system.cpu0.commit.refs 11698867 # Number of memory references committed +system.cpu0.commit.loads 6423036 # Number of loads committed +system.cpu0.commit.membars 234373 # Number of memory barriers committed +system.cpu0.commit.branches 4346960 # Number of branches committed system.cpu0.commit.fp_insts 3838 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 28256367 # Number of committed integer instructions. -system.cpu0.commit.function_calls 500017 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 1154939 # number cycles where commit BW limit reached +system.cpu0.commit.int_insts 28266871 # Number of committed integer instructions. +system.cpu0.commit.function_calls 499893 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 1186421 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 78638973 # The number of ROB reads -system.cpu0.rob.rob_writes 78294863 # The number of ROB writes -system.cpu0.timesIdled 365151 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 26338646 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 5137152930 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 24181927 # Number of Instructions Simulated -system.cpu0.committedOps 31907216 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 24181927 # Number of Instructions Simulated -system.cpu0.cpi 2.871433 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.871433 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.348258 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.348258 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 176324047 # number of integer regfile reads -system.cpu0.int_regfile_writes 35061690 # number of integer regfile writes -system.cpu0.fp_regfile_reads 3352 # number of floating regfile reads -system.cpu0.fp_regfile_writes 912 # number of floating regfile writes -system.cpu0.misc_regfile_reads 47470625 # number of misc regfile reads -system.cpu0.misc_regfile_writes 527597 # number of misc regfile writes -system.cpu0.icache.replacements 404775 # number of replacements -system.cpu0.icache.tagsinuse 511.602715 # Cycle average of tags in use -system.cpu0.icache.total_refs 3985323 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 405287 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 9.833335 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 6841145000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 511.602715 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.999224 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.999224 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 3985323 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 3985323 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 3985323 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 3985323 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 3985323 # number of overall hits -system.cpu0.icache.overall_hits::total 3985323 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 438012 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 438012 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 438012 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 438012 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 438012 # number of overall misses -system.cpu0.icache.overall_misses::total 438012 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5943655997 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 5943655997 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 5943655997 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 5943655997 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 5943655997 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 5943655997 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 4423335 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 4423335 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 4423335 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 4423335 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 4423335 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 4423335 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.099023 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.099023 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.099023 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.099023 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.099023 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.099023 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13569.619090 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13569.619090 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13569.619090 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13569.619090 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13569.619090 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13569.619090 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 2262 # number of cycles access was blocked +system.cpu0.rob.rob_reads 77875275 # The number of ROB reads +system.cpu0.rob.rob_writes 77410136 # The number of ROB writes +system.cpu0.timesIdled 364830 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 26308962 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 5117234895 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 24183568 # Number of Instructions Simulated +system.cpu0.committedOps 31918173 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 24183568 # Number of Instructions Simulated +system.cpu0.cpi 2.853735 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.853735 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.350418 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.350418 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 175323075 # number of integer regfile reads +system.cpu0.int_regfile_writes 34853003 # number of integer regfile writes +system.cpu0.fp_regfile_reads 3246 # number of floating regfile reads +system.cpu0.fp_regfile_writes 906 # number of floating regfile writes +system.cpu0.misc_regfile_reads 46878729 # number of misc regfile reads +system.cpu0.misc_regfile_writes 527371 # number of misc regfile writes +system.cpu0.icache.replacements 399233 # number of replacements +system.cpu0.icache.tagsinuse 511.592262 # Cycle average of tags in use +system.cpu0.icache.total_refs 3861943 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 399745 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 9.661016 # Average number of references to valid blocks. +system.cpu0.icache.warmup_cycle 6802423000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.occ_blocks::cpu0.inst 511.592262 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.999204 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.999204 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 3861943 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 3861943 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 3861943 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 3861943 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 3861943 # number of overall hits +system.cpu0.icache.overall_hits::total 3861943 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 430668 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 430668 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 430668 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 430668 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 430668 # number of overall misses +system.cpu0.icache.overall_misses::total 430668 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5857521993 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 5857521993 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 5857521993 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 5857521993 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 5857521993 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 5857521993 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 4292611 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 4292611 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 4292611 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 4292611 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 4292611 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 4292611 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.100328 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.100328 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.100328 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.100328 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.100328 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.100328 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13601.015151 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13601.015151 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13601.015151 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13601.015151 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13601.015151 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13601.015151 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 2687 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 131 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 157 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 17.267176 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 17.114650 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 32710 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 32710 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 32710 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 32710 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 32710 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 32710 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 405302 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 405302 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 405302 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 405302 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 405302 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 405302 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4852452498 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 4852452498 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4852452498 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 4852452498 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4852452498 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 4852452498 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 7399000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 7399000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 7399000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 7399000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.091628 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.091628 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.091628 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.091628 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.091628 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.091628 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11972.436598 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11972.436598 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11972.436598 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 11972.436598 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11972.436598 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11972.436598 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 30901 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 30901 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 30901 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 30901 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 30901 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 30901 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 399767 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 399767 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 399767 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 399767 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 399767 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 399767 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4790784994 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 4790784994 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4790784994 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 4790784994 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4790784994 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 4790784994 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 7139500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 7139500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 7139500 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 7139500 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.093129 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.093129 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.093129 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.093129 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.093129 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.093129 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11983.943132 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11983.943132 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11983.943132 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11983.943132 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11983.943132 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11983.943132 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 274922 # number of replacements -system.cpu0.dcache.tagsinuse 477.004191 # Cycle average of tags in use -system.cpu0.dcache.total_refs 9558639 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 275434 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 34.703918 # Average number of references to valid blocks. -system.cpu0.dcache.warmup_cycle 36505000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 477.004191 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.931649 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.931649 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 5930824 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 5930824 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3236437 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 3236437 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 174250 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 174250 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 171562 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 171562 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 9167261 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 9167261 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 9167261 # number of overall hits -system.cpu0.dcache.overall_hits::total 9167261 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 390293 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 390293 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1580955 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1580955 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 8903 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 8903 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7756 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 7756 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1971248 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1971248 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1971248 # number of overall misses -system.cpu0.dcache.overall_misses::total 1971248 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5368045500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 5368045500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 61391771868 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 61391771868 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 88103500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 88103500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 50615000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 50615000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 66759817368 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 66759817368 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 66759817368 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 66759817368 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 6321117 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 6321117 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 4817392 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 4817392 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 183153 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 183153 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 179318 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 179318 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 11138509 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 11138509 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 11138509 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 11138509 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.061744 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.061744 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.328177 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.328177 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.048610 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.048610 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.043253 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.043253 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.176976 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.176976 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.176976 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.176976 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13753.886183 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 13753.886183 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38832.080526 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 38832.080526 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 9895.933955 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 9895.933955 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6525.915420 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6525.915420 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33866.777477 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 33866.777477 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33866.777477 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 33866.777477 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 7897 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 2466 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 585 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 72 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 13.499145 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 34.250000 # average number of cycles each access was blocked +system.cpu0.dcache.replacements 274937 # number of replacements +system.cpu0.dcache.tagsinuse 481.181813 # Cycle average of tags in use +system.cpu0.dcache.total_refs 9516256 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 275449 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 34.548160 # Average number of references to valid blocks. +system.cpu0.dcache.warmup_cycle 36452000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.occ_blocks::cpu0.data 481.181813 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.939808 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.939808 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 5887183 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 5887183 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3238358 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 3238358 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 173666 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 173666 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 171542 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 171542 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 9125541 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 9125541 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 9125541 # number of overall hits +system.cpu0.dcache.overall_hits::total 9125541 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 390766 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 390766 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1582021 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1582021 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 8872 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 8872 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7743 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 7743 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1972787 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1972787 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1972787 # number of overall misses +system.cpu0.dcache.overall_misses::total 1972787 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5377265000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 5377265000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 60881411847 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 60881411847 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 88222500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 88222500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 50475500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 50475500 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 66258676847 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 66258676847 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 66258676847 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 66258676847 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 6277949 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 6277949 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 4820379 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 4820379 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 182538 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 182538 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 179285 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 179285 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 11098328 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 11098328 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 11098328 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 11098328 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.062244 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.062244 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.328194 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.328194 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.048604 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.048604 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.043188 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.043188 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.177755 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.177755 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.177755 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.177755 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13760.831290 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 13760.831290 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38483.314600 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 38483.314600 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 9943.924707 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 9943.924707 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6518.855741 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6518.855741 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33586.330834 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 33586.330834 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33586.330834 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 33586.330834 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 8283 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 3369 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 596 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 82 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 13.897651 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 41.085366 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 255626 # number of writebacks -system.cpu0.dcache.writebacks::total 255626 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 201523 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 201523 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1449784 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1449784 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 468 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 468 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1651307 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 1651307 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1651307 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 1651307 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 188770 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 188770 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 131171 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 131171 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8435 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8435 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7755 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 7755 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 319941 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 319941 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 319941 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 319941 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2338858500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2338858500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4087753491 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4087753491 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 66408500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 66408500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 35107000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 35107000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6426611991 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 6426611991 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6426611991 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 6426611991 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13431962000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13431962000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1199718891 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1199718891 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14631680891 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14631680891 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.029863 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.029863 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.027229 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027229 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.046054 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.046054 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.043247 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.043247 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028724 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.028724 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.028724 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.028724 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12389.990465 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12389.990465 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 31163.545990 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 31163.545990 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7872.969769 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7872.969769 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4527.014829 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4527.014829 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20086.865988 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 20086.865988 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20086.865988 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20086.865988 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 255577 # number of writebacks +system.cpu0.dcache.writebacks::total 255577 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 202032 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 202032 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1450989 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1450989 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 498 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 498 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1653021 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1653021 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1653021 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1653021 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 188734 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 188734 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 131032 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 131032 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8374 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8374 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7739 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 7739 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 319766 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 319766 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 319766 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 319766 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2333622500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2333622500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4054127491 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4054127491 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 66245000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 66245000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 34997500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 34997500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6387749991 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 6387749991 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6387749991 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 6387749991 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13431600500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13431600500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1199905877 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1199905877 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14631506377 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14631506377 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030063 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.030063 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.027183 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027183 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.045875 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.045875 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.043166 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.043166 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028812 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.028812 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.028812 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.028812 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12364.611040 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12364.611040 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 30939.980241 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 30939.980241 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7910.795319 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7910.795319 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4522.225094 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4522.225094 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19976.326411 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19976.326411 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19976.326411 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19976.326411 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1239,27 +1265,27 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 43093620 # DTB read hits -system.cpu1.dtb.read_misses 44212 # DTB read misses -system.cpu1.dtb.write_hits 7019560 # DTB write hits -system.cpu1.dtb.write_misses 11765 # DTB write misses +system.cpu1.dtb.read_hits 43030291 # DTB read hits +system.cpu1.dtb.read_misses 42638 # DTB read misses +system.cpu1.dtb.write_hits 6991861 # DTB write hits +system.cpu1.dtb.write_misses 11867 # DTB write misses system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 2367 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 3591 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 309 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 2362 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 2846 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 322 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 679 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 43137832 # DTB read accesses -system.cpu1.dtb.write_accesses 7031325 # DTB write accesses +system.cpu1.dtb.perms_faults 690 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 43072929 # DTB read accesses +system.cpu1.dtb.write_accesses 7003728 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 50113180 # DTB hits -system.cpu1.dtb.misses 55977 # DTB misses -system.cpu1.dtb.accesses 50169157 # DTB accesses -system.cpu1.itb.inst_hits 7945263 # ITB inst hits -system.cpu1.itb.inst_misses 6054 # ITB inst misses +system.cpu1.dtb.hits 50022152 # DTB hits +system.cpu1.dtb.misses 54505 # DTB misses +system.cpu1.dtb.accesses 50076657 # DTB accesses +system.cpu1.itb.inst_hits 7786412 # ITB inst hits +system.cpu1.itb.inst_misses 5635 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1268,538 +1294,538 @@ system.cpu1.itb.flush_tlb 4 # Nu system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1580 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1587 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 1618 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 1520 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 7951317 # ITB inst accesses -system.cpu1.itb.hits 7945263 # DTB hits -system.cpu1.itb.misses 6054 # DTB misses -system.cpu1.itb.accesses 7951317 # DTB accesses -system.cpu1.numCycles 409430571 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 7792047 # ITB inst accesses +system.cpu1.itb.hits 7786412 # DTB hits +system.cpu1.itb.misses 5635 # DTB misses +system.cpu1.itb.accesses 7792047 # DTB accesses +system.cpu1.numCycles 409024249 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.BPredUnit.lookups 9152257 # Number of BP lookups -system.cpu1.BPredUnit.condPredicted 7432560 # Number of conditional branches predicted -system.cpu1.BPredUnit.condIncorrect 466867 # Number of conditional branches incorrect -system.cpu1.BPredUnit.BTBLookups 6195424 # Number of BTB lookups -system.cpu1.BPredUnit.BTBHits 5148293 # Number of BTB hits +system.cpu1.BPredUnit.lookups 9020667 # Number of BP lookups +system.cpu1.BPredUnit.condPredicted 7346445 # Number of conditional branches predicted +system.cpu1.BPredUnit.condIncorrect 421687 # Number of conditional branches incorrect +system.cpu1.BPredUnit.BTBLookups 5902094 # Number of BTB lookups +system.cpu1.BPredUnit.BTBHits 5066087 # Number of BTB hits system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.BPredUnit.usedRAS 835215 # Number of times the RAS was used to get a target. -system.cpu1.BPredUnit.RASInCorrect 50625 # Number of incorrect RAS predictions. -system.cpu1.fetch.icacheStallCycles 19713770 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 62254744 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 9152257 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 5983508 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 13632356 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 3573599 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 74747 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.BlockedCycles 78115877 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 5836 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 48120 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 142516 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 165 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 7943235 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 563949 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 3459 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 114180028 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.668662 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 1.999663 # Number of instructions fetched each cycle (Total) +system.cpu1.BPredUnit.usedRAS 810235 # Number of times the RAS was used to get a target. +system.cpu1.BPredUnit.RASInCorrect 44717 # Number of incorrect RAS predictions. +system.cpu1.fetch.icacheStallCycles 19548819 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 61628162 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 9020667 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 5876322 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 13445282 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 3432135 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 71958 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.BlockedCycles 78159434 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 5756 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 48212 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 140837 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 164 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 7784486 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 545452 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 3066 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 113770833 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.663645 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 1.994153 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 100555609 88.07% 88.07% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 838988 0.73% 88.80% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 1011000 0.89% 89.69% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 1744900 1.53% 91.22% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 1443541 1.26% 92.48% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 605100 0.53% 93.01% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 1974563 1.73% 94.74% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 445551 0.39% 95.13% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 5560776 4.87% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 100333102 88.19% 88.19% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 820750 0.72% 88.91% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 967014 0.85% 89.76% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 1722421 1.51% 91.27% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 1420935 1.25% 92.52% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 598048 0.53% 93.05% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 1962596 1.73% 94.77% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 435893 0.38% 95.16% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 5510074 4.84% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 114180028 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.022354 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.152052 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 21120325 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 77740288 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 12430171 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 543608 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 2345636 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 1176073 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 102892 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 72257305 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 341492 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 2345636 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 22356190 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 32102348 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 41268894 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 11643477 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 4463483 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 68190005 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 19565 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 695237 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 3171764 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.FullRegisterEvents 33722 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 71496605 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 312933263 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 312874076 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 59187 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 50205657 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 21290948 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 480351 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 419670 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 8129610 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 13049293 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 8227563 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 1078580 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 1518105 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 62664777 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 1204533 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 89464326 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 109059 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 14241211 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 38124625 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 284346 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 114180028 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.783537 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.520062 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 113770833 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.022054 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.150671 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 20932611 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 77783544 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 12260401 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 543319 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 2250958 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 1146967 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 100968 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 71503765 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 336196 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 2250958 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 22152530 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 32126143 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 41276446 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 11489660 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 4475096 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 67542275 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 19496 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 697256 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 3178756 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.FullRegisterEvents 32684 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 70870880 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 310023883 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 309964693 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 59190 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 50213421 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 20657459 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 473589 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 413624 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 8131877 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 12919526 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 8160199 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 1076421 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 1515550 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 62172086 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 1201080 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 89161848 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 100982 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 13762748 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 36926540 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 280453 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 113770833 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.783697 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.520241 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 83489742 73.12% 73.12% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 8670086 7.59% 80.71% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 4385231 3.84% 84.56% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 3749968 3.28% 87.84% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 10493751 9.19% 97.03% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1975559 1.73% 98.76% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 1067200 0.93% 99.69% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 270053 0.24% 99.93% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 78438 0.07% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 83205809 73.13% 73.13% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 8622127 7.58% 80.71% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 4341809 3.82% 84.53% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 3750529 3.30% 87.83% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 10472490 9.20% 97.03% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1973623 1.73% 98.77% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 1061651 0.93% 99.70% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 265825 0.23% 99.93% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 76970 0.07% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 114180028 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 113770833 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 28685 0.36% 0.36% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 990 0.01% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 7576734 95.92% 96.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 292663 3.71% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 29803 0.38% 0.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 992 0.01% 0.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 7572506 95.90% 96.29% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 293239 3.71% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.FU_type_0::No_OpClass 314062 0.35% 0.35% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 37676817 42.11% 42.46% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 61442 0.07% 42.53% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 42.53% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 42.53% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 42.53% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 42.53% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 42.53% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 42.53% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 42.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 42.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 42.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 42.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 42.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 42.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 12 0.00% 42.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 42.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 42.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 2 0.00% 42.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 8 0.00% 42.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 42.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 1698 0.00% 42.54% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 42.54% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 8 0.00% 42.54% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.54% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 44006207 49.19% 91.72% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 7404070 8.28% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 37491969 42.05% 42.40% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 61148 0.07% 42.47% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 42.47% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 42.47% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 42.47% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 42.47% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 42.47% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 42.47% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 42.47% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 42.47% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 42.47% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 42.47% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 42.47% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 42.47% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 11 0.00% 42.47% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 42.47% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 42.47% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 42.47% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 9 0.00% 42.47% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 42.47% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.47% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.47% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.47% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.47% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.47% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 1700 0.00% 42.47% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 42.47% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 9 0.00% 42.47% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.47% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 43923048 49.26% 91.73% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 7369892 8.27% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 89464326 # Type of FU issued -system.cpu1.iq.rate 0.218509 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 7899072 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.088293 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 301157769 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 78119517 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 54662771 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 14827 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 8100 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 6807 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 97041573 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 7763 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 356788 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 89161848 # Type of FU issued +system.cpu1.iq.rate 0.217987 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 7896540 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.088564 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 300131429 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 77144913 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 54450273 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 14948 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 8092 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 6814 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 96736439 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 7887 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 357826 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 3051550 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 4387 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 17666 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 1202172 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 2919371 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 4089 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 17660 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 1133342 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 31965367 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 692896 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 31965401 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 692354 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 2345636 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 24201399 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 366318 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 63975423 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 133542 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 13049293 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 8227563 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 893848 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 67557 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 3836 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 17666 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 244185 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 171619 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 415804 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 87650825 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 43476570 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 1813501 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 2250958 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 24192691 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 367138 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 63477454 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 113697 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 12919526 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 8160199 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 893697 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 68960 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 3858 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 17660 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 208465 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 159370 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 367835 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 87401818 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 43412086 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 1760030 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 106113 # number of nop insts executed -system.cpu1.iew.exec_refs 50801692 # number of memory reference insts executed -system.cpu1.iew.exec_branches 7123929 # Number of branches executed -system.cpu1.iew.exec_stores 7325122 # Number of stores executed -system.cpu1.iew.exec_rate 0.214080 # Inst execution rate -system.cpu1.iew.wb_sent 86821194 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 54669578 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 30455976 # num instructions producing a value -system.cpu1.iew.wb_consumers 54432612 # num instructions consuming a value +system.cpu1.iew.exec_nop 104288 # number of nop insts executed +system.cpu1.iew.exec_refs 50709476 # number of memory reference insts executed +system.cpu1.iew.exec_branches 7088545 # Number of branches executed +system.cpu1.iew.exec_stores 7297390 # Number of stores executed +system.cpu1.iew.exec_rate 0.213684 # Inst execution rate +system.cpu1.iew.wb_sent 86601126 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 54457087 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 30364436 # num instructions producing a value +system.cpu1.iew.wb_consumers 54295656 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.133526 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.559517 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.133139 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.559242 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 14216299 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 920187 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 365862 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 111882823 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.440904 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.409715 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 13692554 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 920627 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 322274 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 111568344 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.442227 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.413238 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 94662436 84.61% 84.61% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 8450873 7.55% 92.16% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 2228797 1.99% 94.15% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 1285384 1.15% 95.30% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 1281795 1.15% 96.45% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 596967 0.53% 96.98% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 1010034 0.90% 97.88% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 539540 0.48% 98.37% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 1826997 1.63% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 94375668 84.59% 84.59% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 8446118 7.57% 92.16% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 2197127 1.97% 94.13% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 1290727 1.16% 95.29% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1277171 1.14% 96.43% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 591366 0.53% 96.96% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 1009730 0.91% 97.87% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 541366 0.49% 98.35% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 1839071 1.65% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 111882823 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 38951499 # Number of instructions committed -system.cpu1.commit.committedOps 49329594 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 111568344 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 38958201 # Number of instructions committed +system.cpu1.commit.committedOps 49338577 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 17023134 # Number of memory references committed -system.cpu1.commit.loads 9997743 # Number of loads committed -system.cpu1.commit.membars 202380 # Number of memory barriers committed -system.cpu1.commit.branches 6138522 # Number of branches committed +system.cpu1.commit.refs 17027012 # Number of memory references committed +system.cpu1.commit.loads 10000155 # Number of loads committed +system.cpu1.commit.membars 202531 # Number of memory barriers committed +system.cpu1.commit.branches 6139960 # Number of branches committed system.cpu1.commit.fp_insts 6758 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 43719778 # Number of committed integer instructions. -system.cpu1.commit.function_calls 556453 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 1826997 # number cycles where commit BW limit reached +system.cpu1.commit.int_insts 43727423 # Number of committed integer instructions. +system.cpu1.commit.function_calls 556605 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 1839071 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 172487010 # The number of ROB reads -system.cpu1.rob.rob_writes 129525616 # The number of ROB writes -system.cpu1.timesIdled 1423460 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 295250543 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 4796554837 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 38881860 # Number of Instructions Simulated -system.cpu1.committedOps 49259955 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 38881860 # Number of Instructions Simulated -system.cpu1.cpi 10.530118 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 10.530118 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.094966 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.094966 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 392568937 # number of integer regfile reads -system.cpu1.int_regfile_writes 56802865 # number of integer regfile writes -system.cpu1.fp_regfile_reads 4926 # number of floating regfile reads -system.cpu1.fp_regfile_writes 2332 # number of floating regfile writes -system.cpu1.misc_regfile_reads 81929191 # number of misc regfile reads -system.cpu1.misc_regfile_writes 429868 # number of misc regfile writes -system.cpu1.icache.replacements 620724 # number of replacements -system.cpu1.icache.tagsinuse 498.809985 # Cycle average of tags in use -system.cpu1.icache.total_refs 7273497 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 621236 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 11.708106 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 74643061500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 498.809985 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.974238 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.974238 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 7273497 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 7273497 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 7273497 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 7273497 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 7273497 # number of overall hits -system.cpu1.icache.overall_hits::total 7273497 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 669686 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 669686 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 669686 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 669686 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 669686 # number of overall misses -system.cpu1.icache.overall_misses::total 669686 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8966780496 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 8966780496 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 8966780496 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 8966780496 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 8966780496 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 8966780496 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 7943183 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 7943183 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 7943183 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 7943183 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 7943183 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 7943183 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.084310 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.084310 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.084310 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.084310 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.084310 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.084310 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13389.529565 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13389.529565 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13389.529565 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13389.529565 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13389.529565 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13389.529565 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 2782 # number of cycles access was blocked +system.cpu1.rob.rob_reads 171645222 # The number of ROB reads +system.cpu1.rob.rob_writes 128401309 # The number of ROB writes +system.cpu1.timesIdled 1423775 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 295253416 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 4776625618 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 38888562 # Number of Instructions Simulated +system.cpu1.committedOps 49268938 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 38888562 # Number of Instructions Simulated +system.cpu1.cpi 10.517855 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 10.517855 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.095076 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.095076 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 391481129 # number of integer regfile reads +system.cpu1.int_regfile_writes 56596470 # number of integer regfile writes +system.cpu1.fp_regfile_reads 4905 # number of floating regfile reads +system.cpu1.fp_regfile_writes 2328 # number of floating regfile writes +system.cpu1.misc_regfile_reads 81326805 # number of misc regfile reads +system.cpu1.misc_regfile_writes 430176 # number of misc regfile writes +system.cpu1.icache.replacements 614989 # number of replacements +system.cpu1.icache.tagsinuse 498.619037 # Cycle average of tags in use +system.cpu1.icache.total_refs 7122851 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 615501 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 11.572444 # Average number of references to valid blocks. +system.cpu1.icache.warmup_cycle 74507010000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.occ_blocks::cpu1.inst 498.619037 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.973865 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.973865 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 7122851 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 7122851 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 7122851 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 7122851 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 7122851 # number of overall hits +system.cpu1.icache.overall_hits::total 7122851 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 661583 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 661583 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 661583 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 661583 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 661583 # number of overall misses +system.cpu1.icache.overall_misses::total 661583 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8883357995 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 8883357995 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 8883357995 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 8883357995 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 8883357995 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 8883357995 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 7784434 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 7784434 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 7784434 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 7784434 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 7784434 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 7784434 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.084988 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.084988 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.084988 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.084988 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.084988 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.084988 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13427.427844 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13427.427844 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13427.427844 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13427.427844 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13427.427844 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13427.427844 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 3547 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 195 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 182 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 14.266667 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 19.489011 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 48404 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 48404 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 48404 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 48404 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 48404 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 48404 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 621282 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 621282 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 621282 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 621282 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 621282 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 621282 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 7328304997 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 7328304997 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 7328304997 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 7328304997 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 7328304997 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 7328304997 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 2925000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 2925000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 2925000 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 2925000 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.078216 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.078216 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.078216 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.078216 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.078216 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.078216 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11795.456809 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11795.456809 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11795.456809 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 11795.456809 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11795.456809 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11795.456809 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 46050 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 46050 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 46050 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 46050 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 46050 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 46050 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 615533 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 615533 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 615533 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 615533 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 615533 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 615533 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 7269169496 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 7269169496 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 7269169496 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 7269169496 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 7269169496 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 7269169496 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 2823500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 2823500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 2823500 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 2823500 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.079072 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.079072 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.079072 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.079072 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.079072 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.079072 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11809.552853 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11809.552853 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11809.552853 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11809.552853 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11809.552853 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11809.552853 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 363973 # number of replacements -system.cpu1.dcache.tagsinuse 487.193831 # Cycle average of tags in use -system.cpu1.dcache.total_refs 13149320 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 364327 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 36.092082 # Average number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 70722416000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 487.193831 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.951550 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.951550 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 8614465 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 8614465 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 4290599 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 4290599 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 105175 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 105175 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 100810 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 100810 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 12905064 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 12905064 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 12905064 # number of overall hits -system.cpu1.dcache.overall_hits::total 12905064 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 401162 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 401162 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 1564756 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 1564756 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 14285 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 14285 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10913 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 10913 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 1965918 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 1965918 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 1965918 # number of overall misses -system.cpu1.dcache.overall_misses::total 1965918 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 6004176000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 6004176000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 64721170014 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 64721170014 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 132767500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 132767500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 58656500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 58656500 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 70725346014 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 70725346014 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 70725346014 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 70725346014 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 9015627 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 9015627 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 5855355 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 5855355 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 119460 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 119460 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 111723 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 111723 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 14870982 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 14870982 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 14870982 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 14870982 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.044496 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.044496 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.267235 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.267235 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.119580 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.119580 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.097679 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.097679 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.132198 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.132198 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.132198 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.132198 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14966.960978 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 14966.960978 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 41361.828946 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 41361.828946 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9294.189709 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9294.189709 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5374.919820 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5374.919820 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 35975.735516 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 35975.735516 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 35975.735516 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 35975.735516 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 27876 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 16218 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 3195 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 164 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 8.724883 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets 98.890244 # average number of cycles each access was blocked +system.cpu1.dcache.replacements 363437 # number of replacements +system.cpu1.dcache.tagsinuse 485.666262 # Cycle average of tags in use +system.cpu1.dcache.total_refs 13086846 # Total number of references to valid blocks. +system.cpu1.dcache.sampled_refs 363802 # Sample count of references to valid blocks. +system.cpu1.dcache.avg_refs 35.972441 # Average number of references to valid blocks. +system.cpu1.dcache.warmup_cycle 70623957000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.occ_blocks::cpu1.data 485.666262 # Average occupied blocks per requestor +system.cpu1.dcache.occ_percent::cpu1.data 0.948567 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::total 0.948567 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 8551806 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 8551806 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 4291461 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 4291461 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 103521 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 103521 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 100890 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 100890 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 12843267 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 12843267 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 12843267 # number of overall hits +system.cpu1.dcache.overall_hits::total 12843267 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 401802 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 401802 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 1565358 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 1565358 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 14225 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 14225 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10942 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 10942 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 1967160 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 1967160 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 1967160 # number of overall misses +system.cpu1.dcache.overall_misses::total 1967160 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 6026246000 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 6026246000 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 64613580018 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 64613580018 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 131651000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 131651000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 58881000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 58881000 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 70639826018 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 70639826018 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 70639826018 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 70639826018 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 8953608 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 8953608 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 5856819 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 5856819 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 117746 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 117746 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 111832 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 111832 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 14810427 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 14810427 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 14810427 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 14810427 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.044876 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.044876 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.267271 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.267271 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.120811 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.120811 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.097843 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.097843 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.132823 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.132823 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.132823 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.132823 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14998.048790 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 14998.048790 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 41277.190277 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 41277.190277 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9254.903339 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9254.903339 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5381.191738 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5381.191738 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 35909.547784 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 35909.547784 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 35909.547784 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 35909.547784 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 28351 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 15005 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 3227 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 168 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 8.785559 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 89.315476 # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 328753 # number of writebacks -system.cpu1.dcache.writebacks::total 328753 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 169362 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 169362 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1401575 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 1401575 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1448 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1448 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 1570937 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 1570937 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 1570937 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 1570937 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 231800 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 231800 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 163181 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 163181 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12837 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12837 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10908 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 10908 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 394981 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 394981 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 394981 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 394981 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2870952500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2870952500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 5312418211 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 5312418211 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 91073000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 91073000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 36840500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 36840500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 8183370711 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 8183370711 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 8183370711 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 8183370711 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 169263287500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 169263287500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 26961622519 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 26961622519 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 196224910019 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 196224910019 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.025711 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.025711 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027869 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027869 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.107459 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.107459 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.097634 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.097634 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026561 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.026561 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026561 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.026561 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12385.472390 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12385.472390 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 32555.372323 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 32555.372323 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7094.570382 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7094.570382 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3377.383572 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3377.383572 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20718.390786 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20718.390786 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20718.390786 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20718.390786 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 328383 # number of writebacks +system.cpu1.dcache.writebacks::total 328383 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 170419 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 170419 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1402227 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 1402227 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1450 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1450 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 1572646 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 1572646 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 1572646 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 1572646 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 231383 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 231383 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 163131 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 163131 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12775 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12775 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10936 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 10936 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 394514 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 394514 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 394514 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 394514 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2870368000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2870368000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 5301094210 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 5301094210 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 90117500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 90117500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 37009000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 37009000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 8171462210 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 8171462210 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 8171462210 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 8171462210 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 169263515000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 169263515000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 26947906394 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 26947906394 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 196211421394 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 196211421394 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.025842 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.025842 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027853 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027853 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.108496 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.108496 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.097790 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.097790 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026638 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.026638 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026638 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.026638 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12405.267457 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12405.267457 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 32495.934004 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 32495.934004 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7054.207436 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7054.207436 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3384.144111 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3384.144111 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20712.730626 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20712.730626 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20712.730626 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20712.730626 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1821,18 +1847,18 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1082331782222 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1082331782222 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1082331782222 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1082331782222 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1082174693399 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1082174693399 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1082174693399 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1082174693399 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 43796 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 43757 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 53932 # number of quiesce instructions executed +system.cpu1.kern.inst.quiesce 53969 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini index e428e398a..fbd26bc50 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini @@ -8,13 +8,14 @@ time_sync_spin_threshold=100000000 [system] type=LinuxArmSystem -children=bridge cf0 cpu intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver +children=bridge cf0 cpu intrctrl iobus iocache membus physmem realview terminal vncserver atags_addr=256 boot_loader=/projects/pd/randd/dist/binaries/boot.arm boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 -clock=1 +clock=1000 dtb_filename= early_kernel_symbols=false +enable_context_switch_stats_dump=false flags_addr=268435504 gic_cpu_addr=520093952 init_param=0 @@ -23,7 +24,6 @@ load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=timing memories=system.physmem system.realview.nvmem -midr_regval=890224640 multi_proc=true num_work_ids=16 readfile=tests/halt.sh @@ -39,7 +39,7 @@ system_port=system.membus.slave[0] [system.bridge] type=Bridge -clock=1 +clock=1000 delay=50000 ranges=268435456:520093695 1073741824:1610612735 req_size=16 @@ -69,7 +69,7 @@ read_only=true [system.cpu] type=DerivO3CPU -children=dcache dtb fuPool icache interrupts itb tracer +children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -117,6 +117,7 @@ iewToFetchDelay=1 iewToRenameDelay=1 instShiftAmt=2 interrupts=system.cpu.interrupts +isa=system.cpu.isa issueToExecuteDelay=1 issueWidth=8 itb=system.cpu.itb @@ -168,10 +169,10 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=4 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 @@ -179,7 +180,7 @@ prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=32768 subblock_size=0 system=system @@ -188,7 +189,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port -mem_side=system.toL2Bus.slave[1] +mem_side=system.cpu.toL2Bus.slave[1] [system.cpu.dtb] type=ArmTLB @@ -198,10 +199,10 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=ArmTableWalker -clock=1 +clock=500 num_squash_per_cycle=2 sys=system -port=system.toL2Bus.slave[3] +port=system.cpu.toL2Bus.slave[3] [system.cpu.fuPool] type=FUPool @@ -471,10 +472,10 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=1 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 @@ -482,7 +483,7 @@ prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=32768 subblock_size=0 system=system @@ -491,11 +492,28 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port -mem_side=system.toL2Bus.slave[0] +mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=ArmInterrupts +[system.cpu.isa] +type=ArmISA +fpsid=1090793632 +id_isar0=34607377 +id_isar1=34677009 +id_isar2=555950401 +id_isar3=17899825 +id_isar4=268501314 +id_isar5=0 +id_mmfr0=3 +id_mmfr1=0 +id_mmfr2=19070976 +id_mmfr3=4027589137 +id_pfr0=49 +id_pfr1=1 +midr=890224640 + [system.cpu.itb] type=ArmTLB children=walker @@ -504,10 +522,47 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=ArmTableWalker -clock=1 +clock=500 num_squash_per_cycle=2 sys=system -port=system.toL2Bus.slave[2] +port=system.cpu.toL2Bus.slave[2] + +[system.cpu.l2cache] +type=BaseCache +addr_ranges=0:18446744073709551615 +assoc=8 +block_size=64 +clock=500 +forward_snoops=true +hash_delay=1 +hit_latency=20 +is_top_level=false +max_miss_count=0 +mshrs=20 +prefetch_on_access=false +prefetcher=Null +prioritizeRequests=false +repl=Null +response_latency=20 +size=4194304 +subblock_size=0 +system=system +tgts_per_mshr=12 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.toL2Bus.master[0] +mem_side=system.membus.slave[2] + +[system.cpu.toL2Bus] +type=CoherentBus +block_size=64 +clock=500 +header_cycles=1 +use_default_range=false +width=32 +master=system.cpu.l2cache.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port [system.cpu.tracer] type=ExeTracer @@ -531,18 +586,18 @@ type=BaseCache addr_ranges=0:268435455 assoc=8 block_size=64 -clock=1 +clock=1000 forward_snoops=false hash_delay=1 -hit_latency=50000 -is_top_level=false +hit_latency=50 +is_top_level=true max_miss_count=0 mshrs=20 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=50000 +response_latency=50 size=1024 subblock_size=0 system=system @@ -553,33 +608,6 @@ write_buffers=8 cpu_side=system.iobus.master[25] mem_side=system.membus.slave[1] -[system.l2c] -type=BaseCache -addr_ranges=0:18446744073709551615 -assoc=8 -block_size=64 -clock=1 -forward_snoops=true -hash_delay=1 -hit_latency=10000 -is_top_level=false -max_miss_count=0 -mshrs=92 -prefetch_on_access=false -prefetcher=Null -prioritizeRequests=false -repl=Null -response_latency=10000 -size=4194304 -subblock_size=0 -system=system -tgts_per_mshr=16 -trace_addr=0 -two_queue=false -write_buffers=8 -cpu_side=system.toL2Bus.master[0] -mem_side=system.membus.slave[2] - [system.membus] type=CoherentBus children=badaddr_responder @@ -590,11 +618,11 @@ use_default_range=false width=8 default=system.membus.badaddr_responder.pio master=system.bridge.slave system.realview.nvmem.port system.physmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio -slave=system.system_port system.iocache.mem_side system.l2c.mem_side +slave=system.system_port system.iocache.mem_side system.cpu.l2cache.mem_side [system.membus.badaddr_responder] type=IsaFake -clock=1 +clock=1000 fake_mem=false pio_addr=0 pio_latency=100000 @@ -610,15 +638,28 @@ warn_access=warn pio=system.membus.default [system.physmem] -type=SimpleMemory -bandwidth=73.000000 -clock=1 +type=SimpleDRAM +addr_mapping=openmap +banks_per_rank=8 +clock=1000 conf_table_reported=true in_addr_map=true -latency=30000 -latency_var=0 +lines_per_rowbuffer=64 +mem_sched_policy=fcfs null=false +page_policy=open range=0:134217727 +ranks_per_channel=2 +read_buffer_size=32 +tBURST=4000 +tCL=14000 +tRCD=14000 +tREFI=7800000 +tRFC=300000 +tRP=14000 +tWTR=1000 +write_buffer_size=32 +write_thresh_perc=70 zero=false port=system.membus.master[2] @@ -633,7 +674,7 @@ system=system [system.realview.a9scu] type=A9SCU -clock=1 +clock=1000 pio_addr=520093696 pio_latency=100000 system=system @@ -642,7 +683,7 @@ pio=system.membus.master[5] [system.realview.aaci_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268451840 pio_latency=100000 @@ -689,7 +730,7 @@ SubClassCode=1 SubsystemID=0 SubsystemVendorID=0 VendorID=32902 -clock=1 +clock=1000 config_latency=20000 ctrl_offset=2 disks=system.cf0 @@ -720,7 +761,7 @@ pio=system.iobus.master[4] [system.realview.dmac_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268632064 pio_latency=100000 @@ -729,7 +770,7 @@ pio=system.iobus.master[9] [system.realview.flash_fake] type=IsaFake -clock=1 +clock=1000 fake_mem=true pio_addr=1073741824 pio_latency=100000 @@ -746,7 +787,7 @@ pio=system.iobus.master[24] [system.realview.gic] type=Gic -clock=1 +clock=1000 cpu_addr=520093952 cpu_pio_delay=10000 dist_addr=520097792 @@ -760,7 +801,7 @@ pio=system.membus.master[3] [system.realview.gpio0_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268513280 pio_latency=100000 @@ -770,7 +811,7 @@ pio=system.iobus.master[16] [system.realview.gpio1_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268517376 pio_latency=100000 @@ -780,7 +821,7 @@ pio=system.iobus.master[17] [system.realview.gpio2_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268521472 pio_latency=100000 @@ -790,7 +831,7 @@ pio=system.iobus.master[18] [system.realview.kmi0] type=Pl050 amba_id=1314896 -clock=1 +clock=1000 gic=system.realview.gic int_delay=1000000 int_num=52 @@ -804,7 +845,7 @@ pio=system.iobus.master[5] [system.realview.kmi1] type=Pl050 amba_id=1314896 -clock=1 +clock=1000 gic=system.realview.gic int_delay=1000000 int_num=53 @@ -817,7 +858,7 @@ pio=system.iobus.master[6] [system.realview.l2x0_fake] type=IsaFake -clock=1 +clock=1000 fake_mem=false pio_addr=520101888 pio_latency=100000 @@ -846,7 +887,7 @@ pio=system.membus.master[6] [system.realview.mmc_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268455936 pio_latency=100000 @@ -856,7 +897,7 @@ pio=system.iobus.master[22] [system.realview.nvmem] type=SimpleMemory bandwidth=73.000000 -clock=1 +clock=1000 conf_table_reported=false in_addr_map=true latency=30000 @@ -868,7 +909,7 @@ port=system.membus.master[1] [system.realview.realview_io] type=RealViewCtrl -clock=1 +clock=1000 idreg=0 pio_addr=268435456 pio_latency=100000 @@ -880,7 +921,7 @@ pio=system.iobus.master[1] [system.realview.rtc] type=PL031 amba_id=3412017 -clock=1 +clock=1000 gic=system.realview.gic int_delay=100000 int_num=42 @@ -893,7 +934,7 @@ pio=system.iobus.master[23] [system.realview.sci_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268492800 pio_latency=100000 @@ -903,7 +944,7 @@ pio=system.iobus.master[20] [system.realview.smc_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=269357056 pio_latency=100000 @@ -913,7 +954,7 @@ pio=system.iobus.master[13] [system.realview.sp810_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=true pio_addr=268439552 pio_latency=100000 @@ -923,7 +964,7 @@ pio=system.iobus.master[14] [system.realview.ssp_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268488704 pio_latency=100000 @@ -933,7 +974,7 @@ pio=system.iobus.master[19] [system.realview.timer0] type=Sp804 amba_id=1316868 -clock=1 +clock=1000 clock0=1000000 clock1=1000000 gic=system.realview.gic @@ -947,7 +988,7 @@ pio=system.iobus.master[2] [system.realview.timer1] type=Sp804 amba_id=1316868 -clock=1 +clock=1000 clock0=1000000 clock1=1000000 gic=system.realview.gic @@ -960,7 +1001,7 @@ pio=system.iobus.master[3] [system.realview.uart] type=Pl011 -clock=1 +clock=1000 end_on_eot=false gic=system.realview.gic int_delay=100000 @@ -975,7 +1016,7 @@ pio=system.iobus.master[0] [system.realview.uart1_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268476416 pio_latency=100000 @@ -985,7 +1026,7 @@ pio=system.iobus.master[10] [system.realview.uart2_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268480512 pio_latency=100000 @@ -995,7 +1036,7 @@ pio=system.iobus.master[11] [system.realview.uart3_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268484608 pio_latency=100000 @@ -1005,7 +1046,7 @@ pio=system.iobus.master[12] [system.realview.watchdog_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268500992 pio_latency=100000 @@ -1019,16 +1060,6 @@ number=0 output=true port=3456 -[system.toL2Bus] -type=CoherentBus -block_size=64 -clock=1000 -header_cycles=1 -use_default_range=false -width=8 -master=system.l2c.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port - [system.vncserver] type=VncServer frame_capture=false diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simerr index affb69ad6..3ee89fc27 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simerr +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simerr @@ -11,8 +11,6 @@ warn: instruction 'mcr dccimvac' unimplemented warn: instruction 'mcr dccmvau' unimplemented warn: instruction 'mcr icimvau' unimplemented warn: LCD dual screen mode not supported -warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors -warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors warn: instruction 'mcr icialluis' unimplemented warn: instruction 'mcr bpiallis' unimplemented hack: be nice to actually delete the event here diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout index 304caa505..e4320499c 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 21 2012 11:19:00 -gem5 started Sep 21 2012 12:10:34 +gem5 compiled Oct 30 2012 11:20:14 +gem5 started Oct 30 2012 21:11:31 gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3 -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3 Global frequency set at 1000000000000 ticks per second info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: Using bootloader at address 0x80000000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 2537929870500 because m5_exit instruction encountered +Exiting @ tick 2523500318000 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt index 68a4a5e77..6a79df0e0 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt @@ -1,114 +1,114 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.523629 # Number of seconds simulated -sim_ticks 2523629285500 # Number of ticks simulated -final_tick 2523629285500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.523500 # Number of seconds simulated +sim_ticks 2523500318000 # Number of ticks simulated +final_tick 2523500318000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 77702 # Simulator instruction rate (inst/s) -host_op_rate 99947 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3235958193 # Simulator tick rate (ticks/s) -host_mem_usage 399788 # Number of bytes of host memory used -host_seconds 779.87 # Real time elapsed on the host -sim_insts 60597236 # Number of instructions simulated -sim_ops 77945371 # Number of ops (including micro ops) simulated +host_inst_rate 66325 # Simulator instruction rate (inst/s) +host_op_rate 85314 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2762063576 # Simulator tick rate (ticks/s) +host_mem_usage 400896 # Number of bytes of host memory used +host_seconds 913.63 # Real time elapsed on the host +sim_insts 60596849 # Number of instructions simulated +sim_ops 77944928 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 3520 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 799232 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9095696 # Number of bytes read from this memory -system.physmem.bytes_read::total 129436176 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 799232 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 799232 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3784448 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.dtb.walker 2752 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 798592 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9094096 # Number of bytes read from this memory +system.physmem.bytes_read::total 129433232 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 798592 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 798592 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3784064 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 6800520 # Number of bytes written to this memory +system.physmem.bytes_written::total 6800136 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 55 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 12488 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 142154 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15096906 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59132 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 43 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 12478 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 142129 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15096860 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 59126 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 813150 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47367363 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 1395 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 25 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 316699 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3604212 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51289695 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 316699 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 316699 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1499605 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1195133 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2694738 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1499605 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47367363 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 1395 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 25 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 316699 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4799345 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53984433 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15096906 # Total number of read requests seen -system.physmem.writeReqs 813150 # Total number of write requests seen -system.physmem.cpureqs 218484 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 966201984 # Total number of bytes read from memory -system.physmem.bytesWritten 52041600 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 129436176 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 6800520 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 390 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 4690 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 943619 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 943957 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 943433 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 943463 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 943389 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 943250 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 943110 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 943289 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 943778 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 943634 # Track reads on a per bank basis +system.physmem.num_writes::total 813144 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47369784 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 1091 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 51 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 316462 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3603763 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51291149 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 316462 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 316462 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1499530 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1195194 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2694724 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1499530 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47369784 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 1091 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 51 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 316462 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4798956 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53985873 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15096860 # Total number of read requests seen +system.physmem.writeReqs 813144 # Total number of write requests seen +system.physmem.cpureqs 218421 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 966199040 # Total number of bytes read from memory +system.physmem.bytesWritten 52041216 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 129433232 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 6800136 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 334 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 4679 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 943626 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 943958 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 943414 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 943465 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 943376 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 943238 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 943099 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 943292 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 943771 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 943641 # Track reads on a per bank basis system.physmem.perBankRdReqs::10 943712 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 943686 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 943739 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 943592 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 943646 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 943219 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 50102 # Track writes on a per bank basis +system.physmem.perBankRdReqs::11 943689 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 943743 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 943611 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 943653 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 943238 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 50107 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 50378 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 49977 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 50030 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 50914 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 50821 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 50673 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 50817 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 51140 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 51219 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 51127 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 49961 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 50027 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 50912 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 50814 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 50662 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 50821 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 51143 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 51225 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 51129 # Track writes on a per bank basis system.physmem.perBankWrReqs::11 51111 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 51352 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 51158 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 51299 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 51032 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 51353 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 51175 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 51296 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 51030 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 1156336 # Number of times wr buffer was full causing retry -system.physmem.totGap 2523628152000 # Total gap between requests +system.physmem.numWrRetry 1153879 # Number of times wr buffer was full causing retry +system.physmem.totGap 2523499110500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 36 # Categorize read packet sizes system.physmem.readPktSize::3 14942208 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 154662 # Categorize read packet sizes +system.physmem.readPktSize::6 154616 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 1910354 # categorize write packet sizes +system.physmem.writePktSize::2 1907897 # categorize write packet sizes system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 59132 # categorize write packet sizes +system.physmem.writePktSize::6 59126 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -117,28 +117,28 @@ system.physmem.neitherpktsize::2 0 # ca system.physmem.neitherpktsize::3 0 # categorize neither packet sizes system.physmem.neitherpktsize::4 0 # categorize neither packet sizes system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 4690 # categorize neither packet sizes +system.physmem.neitherpktsize::6 4679 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 14955823 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 89957 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 6537 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 2881 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2334 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2059 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1873 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1682 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 14954842 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 89676 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 6568 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 2998 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2443 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2395 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2334 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1858 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 1270 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1277 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1234 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 6283 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 9566 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 13077 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 563 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 50 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 33 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1251 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1236 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 6388 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 9595 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 13055 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 523 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 48 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 31 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 15 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see @@ -153,15 +153,15 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 2800 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 2950 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 3067 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 3195 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 3352 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 3546 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 3760 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 3932 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 4090 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 2802 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 2959 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 3079 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 3181 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 3335 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 3514 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 3726 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 3889 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 4040 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 35354 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 35354 # What write queue length does an incoming req see system.physmem.wrQLenPdf::11 35354 # What write queue length does an incoming req see @@ -176,37 +176,37 @@ system.physmem.wrQLenPdf::19 35354 # Wh system.physmem.wrQLenPdf::20 35354 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 35354 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 35354 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 32555 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 32405 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 32288 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 32160 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 32003 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 31809 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 31595 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 31423 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 31264 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 32553 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 32396 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 32275 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 32173 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 32019 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 31840 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 31628 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 31465 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 31314 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 46839255594 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 317495505594 # Sum of mem lat for all requests -system.physmem.totBusLat 60386064000 # Total cycles spent in databus access -system.physmem.totBankLat 210270186000 # Total cycles spent in bank access -system.physmem.avgQLat 3102.65 # Average queueing delay per request -system.physmem.avgBankLat 13928.39 # Average bank access latency per request +system.physmem.totQLat 47052553851 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 317720785851 # Sum of mem lat for all requests +system.physmem.totBusLat 60386104000 # Total cycles spent in databus access +system.physmem.totBankLat 210282128000 # Total cycles spent in bank access +system.physmem.avgQLat 3116.78 # Average queueing delay per request +system.physmem.avgBankLat 13929.17 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 21031.04 # Average memory access latency -system.physmem.avgRdBW 382.86 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 21045.95 # Average memory access latency +system.physmem.avgRdBW 382.88 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 20.62 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 51.29 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 2.69 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 2.52 # Data bus utilization in percentage system.physmem.avgRdQLen 0.13 # Average read queue length over time -system.physmem.avgWrQLen 13.20 # Average write queue length over time -system.physmem.readRowHits 15050623 # Number of row buffer hits during reads -system.physmem.writeRowHits 784578 # Number of row buffer hits during writes -system.physmem.readRowHitRate 99.70 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 96.49 # Row buffer hit rate for writes -system.physmem.avgGap 158618.43 # Average gap between requests +system.physmem.avgWrQLen 11.37 # Average write queue length over time +system.physmem.readRowHits 15049962 # Number of row buffer hits during reads +system.physmem.writeRowHits 784769 # Number of row buffer hits during writes +system.physmem.readRowHitRate 99.69 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 96.51 # Row buffer hit rate for writes +system.physmem.avgGap 158610.84 # Average gap between requests system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory @@ -227,27 +227,27 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 51393832 # DTB read hits -system.cpu.dtb.read_misses 77273 # DTB read misses -system.cpu.dtb.write_hits 11807513 # DTB write hits -system.cpu.dtb.write_misses 17284 # DTB write misses +system.cpu.dtb.read_hits 51279526 # DTB read hits +system.cpu.dtb.read_misses 73667 # DTB read misses +system.cpu.dtb.write_hits 11753863 # DTB write hits +system.cpu.dtb.write_misses 17234 # DTB write misses system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 4230 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 2923 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 497 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 4224 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 2376 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 510 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 1303 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 51471105 # DTB read accesses -system.cpu.dtb.write_accesses 11824797 # DTB write accesses +system.cpu.dtb.perms_faults 1366 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 51353193 # DTB read accesses +system.cpu.dtb.write_accesses 11771097 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 63201345 # DTB hits -system.cpu.dtb.misses 94557 # DTB misses -system.cpu.dtb.accesses 63295902 # DTB accesses -system.cpu.itb.inst_hits 11866090 # ITB inst hits -system.cpu.itb.inst_misses 12256 # ITB inst misses +system.cpu.dtb.hits 63033389 # DTB hits +system.cpu.dtb.misses 90901 # DTB misses +system.cpu.dtb.accesses 63124290 # DTB accesses +system.cpu.itb.inst_hits 11603865 # ITB inst hits +system.cpu.itb.inst_misses 11359 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -256,688 +256,526 @@ system.cpu.itb.flush_tlb 2 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 2603 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 2573 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 3056 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 2961 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 11878346 # ITB inst accesses -system.cpu.itb.hits 11866090 # DTB hits -system.cpu.itb.misses 12256 # DTB misses -system.cpu.itb.accesses 11878346 # DTB accesses -system.cpu.numCycles 471617242 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 11615224 # ITB inst accesses +system.cpu.itb.hits 11603865 # DTB hits +system.cpu.itb.misses 11359 # DTB misses +system.cpu.itb.accesses 11615224 # DTB accesses +system.cpu.numCycles 470951029 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 14707934 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 11701482 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 783806 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 9735591 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 7867248 # Number of BTB hits +system.cpu.BPredUnit.lookups 14482147 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 11548936 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 711590 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 9469344 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 7720983 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1454059 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 82839 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 30177247 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 91949952 # Number of instructions fetch has processed -system.cpu.fetch.Branches 14707934 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9321307 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 20604105 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 4981007 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 133002 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 96623906 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 2605 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 100214 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 208761 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 353 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 11862293 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 731589 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 6461 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 151283915 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.758817 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.115765 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1413907 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 72813 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 29880342 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 90834905 # Number of instructions fetch has processed +system.cpu.fetch.Branches 14482147 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9134890 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 20280806 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 4750716 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 122594 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 96709258 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 2560 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 94111 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 205295 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 281 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 11600179 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 700998 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 5704 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 150571175 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.752471 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.109183 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 130696614 86.39% 86.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1382439 0.91% 87.31% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1755242 1.16% 88.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2339470 1.55% 90.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2142585 1.42% 91.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1134296 0.75% 92.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 2618835 1.73% 93.91% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 784869 0.52% 94.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 8429565 5.57% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 130305873 86.54% 86.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1344979 0.89% 87.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1685836 1.12% 88.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2306234 1.53% 90.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2113026 1.40% 91.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1118544 0.74% 92.23% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2593877 1.72% 93.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 765442 0.51% 94.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 8337364 5.54% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 151283915 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.031186 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.194967 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 32009474 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 96255861 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 18724959 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1031397 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3262224 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 2019817 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 174593 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 109260478 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 576218 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3262224 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 33806773 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 36827261 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 53335707 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 17902220 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 6149730 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 104066052 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 21507 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1015259 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4119258 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 31916 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 107817309 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 475022232 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 474932056 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 90176 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 78731209 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 29086099 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 892462 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 797997 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12333143 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 20063520 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 13521808 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1973034 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2429271 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 96511584 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2058662 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 123961862 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 189585 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 20013916 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 50091772 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 514148 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 151283915 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.819399 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.531663 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 150571175 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.030751 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.192875 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 31657449 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 96342520 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 18430846 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1034189 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3106171 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 1969595 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 172369 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 107934392 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 571655 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3106171 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 33426960 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 36897380 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 53334301 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 17638840 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 6167523 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 102924268 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 21343 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1016075 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4132060 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 29183 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 106686272 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 469883831 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 469792749 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 91082 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 78730768 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 27955503 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 879837 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 786100 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12323975 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 19838005 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 13393703 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1972033 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2410684 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 95618817 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2046180 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 123387582 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 174864 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 19151232 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 48036492 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 501695 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 150571175 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.819463 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.532492 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 106904579 70.66% 70.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 13863783 9.16% 79.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7099546 4.69% 84.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 5863279 3.88% 88.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12474907 8.25% 96.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2771705 1.83% 98.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1719952 1.14% 99.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 458027 0.30% 99.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 128137 0.08% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 106455995 70.70% 70.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 13758975 9.14% 79.84% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7009673 4.66% 84.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 5842702 3.88% 88.38% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12442883 8.26% 96.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2768710 1.84% 98.48% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1710517 1.14% 99.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 450789 0.30% 99.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 130931 0.09% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 151283915 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 150571175 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 57031 0.64% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 3 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 8373952 94.62% 95.27% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 418898 4.73% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 59954 0.68% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 4 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 8366032 94.65% 95.32% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 413370 4.68% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 363666 0.29% 0.29% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 58283800 47.02% 47.31% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 95201 0.08% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 19 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 5 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 13 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 2113 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 13 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 52766411 42.57% 89.96% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 12450621 10.04% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 57926411 46.95% 47.24% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 93267 0.08% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 22 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 1 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 17 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 2114 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 17 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 52616961 42.64% 89.96% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 12385106 10.04% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 123961862 # Type of FU issued -system.cpu.iq.rate 0.262844 # Inst issue rate -system.cpu.iq.fu_busy_cnt 8849884 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.071392 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 408318037 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 118600535 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 86285351 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 23227 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 12408 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 10278 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 132435732 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 12348 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 629942 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 123387582 # Type of FU issued +system.cpu.iq.rate 0.261997 # Inst issue rate +system.cpu.iq.fu_busy_cnt 8839360 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.071639 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 406427994 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 116832614 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 85860436 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 23103 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 12565 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 10308 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 131851026 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 12250 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 624646 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 4347483 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 7997 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 29897 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1723272 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 4122070 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 6381 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 30063 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1595239 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 34108218 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 695964 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 34107814 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 695818 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3262224 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 27920683 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 435052 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 98794824 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 232558 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 20063520 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 13521808 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1467094 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 114012 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3652 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 29897 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 410015 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 293518 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 703533 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 121755337 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 52081116 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2206525 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3106171 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 27981842 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 438339 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 97885744 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 205866 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 19838005 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 13393703 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1459318 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 116468 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3836 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 30063 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 352690 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 272400 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 625090 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 121269392 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 51965419 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2118190 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 224578 # number of nop insts executed -system.cpu.iew.exec_refs 64400589 # number of memory reference insts executed -system.cpu.iew.exec_branches 11599904 # Number of branches executed -system.cpu.iew.exec_stores 12319473 # Number of stores executed -system.cpu.iew.exec_rate 0.258166 # Inst execution rate -system.cpu.iew.wb_sent 120729614 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 86295629 # cumulative count of insts written-back -system.cpu.iew.wb_producers 47354389 # num instructions producing a value -system.cpu.iew.wb_consumers 88420573 # num instructions consuming a value +system.cpu.iew.exec_nop 220747 # number of nop insts executed +system.cpu.iew.exec_refs 64230871 # number of memory reference insts executed +system.cpu.iew.exec_branches 11527542 # Number of branches executed +system.cpu.iew.exec_stores 12265452 # Number of stores executed +system.cpu.iew.exec_rate 0.257499 # Inst execution rate +system.cpu.iew.wb_sent 120289637 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 85870744 # cumulative count of insts written-back +system.cpu.iew.wb_producers 47162688 # num instructions producing a value +system.cpu.iew.wb_consumers 88075667 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.182978 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.535558 # average fanout of values written-back +system.cpu.iew.wb_rate 0.182335 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.535479 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 19868776 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1544514 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 612308 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 148104118 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.527303 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.512767 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 18952599 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1544485 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 541833 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 147547429 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.529290 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.517447 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 120332893 81.25% 81.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 13565443 9.16% 90.41% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3964002 2.68% 93.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2135941 1.44% 94.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1954116 1.32% 95.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 973664 0.66% 96.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1592335 1.08% 97.58% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 730104 0.49% 98.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2855620 1.93% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 119858518 81.23% 81.23% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 13515143 9.16% 90.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3916529 2.65% 93.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2132463 1.45% 94.49% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1950760 1.32% 95.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 976387 0.66% 96.48% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1592516 1.08% 97.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 731256 0.50% 98.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2873857 1.95% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 148104118 # Number of insts commited each cycle -system.cpu.commit.committedInsts 60747617 # Number of instructions committed -system.cpu.commit.committedOps 78095752 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 147547429 # Number of insts commited each cycle +system.cpu.commit.committedInsts 60747230 # Number of instructions committed +system.cpu.commit.committedOps 78095309 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 27514573 # Number of memory references committed -system.cpu.commit.loads 15716037 # Number of loads committed -system.cpu.commit.membars 413105 # Number of memory barriers committed -system.cpu.commit.branches 10023091 # Number of branches committed +system.cpu.commit.refs 27514399 # Number of memory references committed +system.cpu.commit.loads 15715935 # Number of loads committed +system.cpu.commit.membars 413101 # Number of memory barriers committed +system.cpu.commit.branches 10023041 # Number of branches committed system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions. -system.cpu.commit.int_insts 69134185 # Number of committed integer instructions. -system.cpu.commit.function_calls 995980 # Number of function calls committed. -system.cpu.commit.bw_lim_events 2855620 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 69133795 # Number of committed integer instructions. +system.cpu.commit.function_calls 995976 # Number of function calls committed. +system.cpu.commit.bw_lim_events 2873857 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 241297904 # The number of ROB reads -system.cpu.rob.rob_writes 199283253 # The number of ROB writes -system.cpu.timesIdled 1774711 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 320333327 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 4575553300 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 60597236 # Number of Instructions Simulated -system.cpu.committedOps 77945371 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 60597236 # Number of Instructions Simulated -system.cpu.cpi 7.782818 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.782818 # CPI: Total CPI of All Threads -system.cpu.ipc 0.128488 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.128488 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 551506175 # number of integer regfile reads -system.cpu.int_regfile_writes 88407137 # number of integer regfile writes -system.cpu.fp_regfile_reads 8339 # number of floating regfile reads -system.cpu.fp_regfile_writes 2916 # number of floating regfile writes -system.cpu.misc_regfile_reads 124072221 # number of misc regfile reads -system.cpu.misc_regfile_writes 912903 # number of misc regfile writes -system.cpu.icache.replacements 990875 # number of replacements -system.cpu.icache.tagsinuse 510.405236 # Cycle average of tags in use -system.cpu.icache.total_refs 10787830 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 991387 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 10.881553 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 6691567000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 510.405236 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.996885 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.996885 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 10787830 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 10787830 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 10787830 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 10787830 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 10787830 # number of overall hits -system.cpu.icache.overall_hits::total 10787830 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1074333 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1074333 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1074333 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1074333 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1074333 # number of overall misses -system.cpu.icache.overall_misses::total 1074333 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 14125562486 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 14125562486 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 14125562486 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 14125562486 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 14125562486 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 14125562486 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 11862163 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 11862163 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 11862163 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 11862163 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 11862163 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 11862163 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.090568 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.090568 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.090568 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.090568 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.090568 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.090568 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13148.216136 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13148.216136 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13148.216136 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13148.216136 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13148.216136 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13148.216136 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 4400 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 296 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 14.864865 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.rob.rob_reads 239806361 # The number of ROB reads +system.cpu.rob.rob_writes 197293644 # The number of ROB writes +system.cpu.timesIdled 1776983 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 320379854 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 4575961583 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 60596849 # Number of Instructions Simulated +system.cpu.committedOps 77944928 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 60596849 # Number of Instructions Simulated +system.cpu.cpi 7.771873 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.771873 # CPI: Total CPI of All Threads +system.cpu.ipc 0.128669 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.128669 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 549353817 # number of integer regfile reads +system.cpu.int_regfile_writes 87979071 # number of integer regfile writes +system.cpu.fp_regfile_reads 8318 # number of floating regfile reads +system.cpu.fp_regfile_writes 2932 # number of floating regfile writes +system.cpu.misc_regfile_reads 122823412 # number of misc regfile reads +system.cpu.misc_regfile_writes 912865 # number of misc regfile writes +system.cpu.icache.replacements 980837 # number of replacements +system.cpu.icache.tagsinuse 511.007226 # Cycle average of tags in use +system.cpu.icache.total_refs 10539450 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 981349 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 10.739757 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 6666804000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 511.007226 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.998061 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.998061 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 10539450 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 10539450 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 10539450 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 10539450 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 10539450 # number of overall hits +system.cpu.icache.overall_hits::total 10539450 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1060605 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1060605 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1060605 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1060605 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1060605 # number of overall misses +system.cpu.icache.overall_misses::total 1060605 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 13961403491 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 13961403491 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 13961403491 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 13961403491 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 13961403491 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 13961403491 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 11600055 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 11600055 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 11600055 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 11600055 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 11600055 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 11600055 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.091431 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.091431 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.091431 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.091431 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.091431 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.091431 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13163.622169 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13163.622169 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13163.622169 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13163.622169 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13163.622169 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13163.622169 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 5262 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 8 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 297 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 17.717172 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 8 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 82890 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 82890 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 82890 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 82890 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 82890 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 82890 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 991443 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 991443 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 991443 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 991443 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 991443 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 991443 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11470045988 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 11470045988 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11470045988 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 11470045988 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11470045988 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 11470045988 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 7052500 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 7052500 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 7052500 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::total 7052500 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.083580 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.083580 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.083580 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.083580 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.083580 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.083580 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11569.042283 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11569.042283 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11569.042283 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11569.042283 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11569.042283 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11569.042283 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 79214 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 79214 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 79214 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 79214 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 79214 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 79214 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 981391 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 981391 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 981391 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 981391 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 981391 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 981391 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11354795991 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 11354795991 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11354795991 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 11354795991 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11354795991 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 11354795991 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 6803000 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 6803000 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 6803000 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::total 6803000 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.084602 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.084602 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.084602 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.084602 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.084602 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.084602 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11570.104057 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11570.104057 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11570.104057 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11570.104057 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11570.104057 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11570.104057 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 645101 # number of replacements -system.cpu.dcache.tagsinuse 511.994184 # Cycle average of tags in use -system.cpu.dcache.total_refs 21772820 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 645613 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 33.724259 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 35202000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 511.994184 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999989 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999989 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 13909719 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 13909719 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 7289021 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 7289021 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 285196 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 285196 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 285739 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 285739 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 21198740 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 21198740 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 21198740 # number of overall hits -system.cpu.dcache.overall_hits::total 21198740 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 730115 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 730115 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2961662 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2961662 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 13591 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 13591 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 19 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 19 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 3691777 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3691777 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3691777 # number of overall misses -system.cpu.dcache.overall_misses::total 3691777 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 9540231500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 9540231500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 104360444235 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 104360444235 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 180814000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 180814000 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 283000 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 283000 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 113900675735 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 113900675735 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 113900675735 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 113900675735 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 14639834 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 14639834 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 10250683 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 10250683 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 298787 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 298787 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 285758 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 285758 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 24890517 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 24890517 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 24890517 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 24890517 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.049872 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.049872 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.288923 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.288923 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045487 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.045487 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000066 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::total 0.000066 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.148321 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.148321 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.148321 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.148321 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13066.751813 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13066.751813 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35237.121669 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 35237.121669 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13303.951144 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13303.951144 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 14894.736842 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 14894.736842 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 30852.534087 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 30852.534087 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 30852.534087 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 30852.534087 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 29089 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 14501 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 2531 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 252 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 11.493086 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 57.543651 # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 609133 # number of writebacks -system.cpu.dcache.writebacks::total 609133 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 342878 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 342878 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2712526 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2712526 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1365 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 1365 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3055404 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3055404 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3055404 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3055404 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 387237 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 387237 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249136 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 249136 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12226 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 12226 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 19 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 19 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 636373 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 636373 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 636373 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 636373 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4781839500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4781839500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8147970920 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8147970920 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 141479000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 141479000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 245000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 245000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12929810420 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 12929810420 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12929810420 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 12929810420 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182356641500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182356641500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 28006523855 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 28006523855 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 210363165355 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 210363165355 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026451 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026451 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024304 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024304 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.040919 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.040919 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000066 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000066 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025567 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.025567 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025567 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.025567 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12348.612090 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12348.612090 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32704.911855 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32704.911855 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11571.977752 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11571.977752 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 12894.736842 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 12894.736842 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20317.974553 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 20317.974553 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20317.974553 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 20317.974553 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 64428 # number of replacements -system.cpu.l2cache.tagsinuse 51367.264734 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1930539 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 129823 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 14.870547 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 2488482557500 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 36879.772922 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.dtb.walker 44.022997 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.000230 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 8192.461940 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 6251.006645 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.562741 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000672 # Average percentage of cache occupancy +system.cpu.l2cache.replacements 64388 # number of replacements +system.cpu.l2cache.tagsinuse 51373.602635 # Cycle average of tags in use +system.cpu.l2cache.total_refs 1911501 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 129780 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 14.728779 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 2488431429000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::writebacks 36915.014302 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.dtb.walker 29.696477 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.000348 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 8183.272105 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 6245.619403 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.563278 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000453 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.125007 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.095383 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.783802 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 83028 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 12007 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 977743 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 388649 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1461427 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 609133 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 609133 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 53 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 53 # number of UpgradeReq hits -system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 16 # number of SCUpgradeReq hits -system.cpu.l2cache.SCUpgradeReq_hits::total 16 # number of SCUpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 113031 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 113031 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 83028 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 12007 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 977743 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 501680 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1574458 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 83028 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 12007 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 977743 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 501680 # number of overall hits -system.cpu.l2cache.overall_hits::total 1574458 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 55 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 1 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.inst 12377 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 10733 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 23166 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 2933 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 2933 # number of UpgradeReq misses +system.cpu.l2cache.occ_percent::cpu.inst 0.124867 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.095301 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.783899 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 79304 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 10595 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 967765 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 387173 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1444837 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 607749 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 607749 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 43 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 43 # number of UpgradeReq hits +system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 9 # number of SCUpgradeReq hits +system.cpu.l2cache.SCUpgradeReq_hits::total 9 # number of SCUpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 112887 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 112887 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.dtb.walker 79304 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.itb.walker 10595 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 967765 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 500060 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 1557724 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.dtb.walker 79304 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.itb.walker 10595 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 967765 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 500060 # number of overall hits +system.cpu.l2cache.overall_hits::total 1557724 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 43 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 12372 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 10735 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 23152 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 2918 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 2918 # number of UpgradeReq misses system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 3 # number of SCUpgradeReq misses system.cpu.l2cache.SCUpgradeReq_misses::total 3 # number of SCUpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 133200 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 133200 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.dtb.walker 55 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.itb.walker 1 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 12377 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 143933 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 156366 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.dtb.walker 55 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.itb.walker 1 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 12377 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 143933 # number of overall misses -system.cpu.l2cache.overall_misses::total 156366 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 3825000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 49000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 666073500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 589040998 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 1258988498 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 478000 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 478000 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6695831998 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 6695831998 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 3825000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 49000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 666073500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 7284872996 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 7954820496 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 3825000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 49000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 666073500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 7284872996 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 7954820496 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 83083 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 12008 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.inst 990120 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 399382 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 1484593 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 609133 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 609133 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2986 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 2986 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 19 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.SCUpgradeReq_accesses::total 19 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 246231 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 246231 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 83083 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.itb.walker 12008 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 990120 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 645613 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 1730824 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 83083 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.itb.walker 12008 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 990120 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 645613 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 1730824 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000662 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000083 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012501 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026874 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.015604 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.982251 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.982251 # miss rate for UpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.157895 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.157895 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.540955 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.540955 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000662 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000083 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012501 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.222940 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.090342 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000662 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000083 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012501 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.222940 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.090342 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 69545.454545 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 49000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53815.423770 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 54881.300475 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 54346.391177 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 162.973065 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 162.973065 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 50269.008994 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 50269.008994 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 69545.454545 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 49000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53815.423770 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 50612.944884 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 50873.082998 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 69545.454545 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 49000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53815.423770 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 50612.944884 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 50873.082998 # average overall miss latency +system.cpu.l2cache.ReadExReq_misses::cpu.data 133176 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 133176 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.dtb.walker 43 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 12372 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 143911 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 156328 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.dtb.walker 43 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.inst 12372 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 143911 # number of overall misses +system.cpu.l2cache.overall_misses::total 156328 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 2913500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 118000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 660133000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 590903498 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 1254067998 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 477000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 477000 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6777740498 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 6777740498 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 2913500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 118000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 660133000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 7368643996 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 8031808496 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 2913500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 118000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 660133000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 7368643996 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 8031808496 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 79347 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 10597 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.inst 980137 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 397908 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 1467989 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 607749 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 607749 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2961 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 2961 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 12 # number of SCUpgradeReq accesses(hits+misses) +system.cpu.l2cache.SCUpgradeReq_accesses::total 12 # number of SCUpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 246063 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 246063 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.dtb.walker 79347 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.itb.walker 10597 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 980137 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 643971 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 1714052 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.dtb.walker 79347 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.itb.walker 10597 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 980137 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 643971 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 1714052 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000542 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000189 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012623 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026979 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.015771 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.985478 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.985478 # miss rate for UpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.250000 # miss rate for SCUpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.250000 # miss rate for SCUpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.541227 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.541227 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000542 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000189 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012623 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.223474 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.091204 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000542 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000189 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012623 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.223474 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.091204 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 67755.813953 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 59000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53357.015842 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 55044.573638 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 54166.724171 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 163.468129 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 163.468129 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 50893.107602 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 50893.107602 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 67755.813953 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 59000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53357.015842 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 51202.785027 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 51377.926513 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 67755.813953 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 59000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53357.015842 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 51202.785027 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 51377.926513 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -946,109 +784,109 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 59132 # number of writebacks -system.cpu.l2cache.writebacks::total 59132 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 13 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 61 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 74 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 13 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 61 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 74 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 13 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 61 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 74 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 55 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 1 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 12364 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 10672 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 23092 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2933 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 2933 # number of UpgradeReq MSHR misses +system.cpu.l2cache.writebacks::writebacks 59126 # number of writebacks +system.cpu.l2cache.writebacks::total 59126 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 12 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 60 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 72 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 12 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 60 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 72 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 12 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 60 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 72 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 43 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 2 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 12360 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 10675 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 23080 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2918 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 2918 # number of UpgradeReq MSHR misses system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 3 # number of SCUpgradeReq MSHR misses system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 3 # number of SCUpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133200 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 133200 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 55 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 1 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 12364 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 143872 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 156292 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 55 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 1 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 12364 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 143872 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 156292 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 3125110 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 37000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 508931159 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 450583388 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 962676657 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 29345422 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 29345422 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133176 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 133176 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 43 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 2 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 12360 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 143851 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 156256 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 43 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 2 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 12360 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 143851 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 156256 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 2368082 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 93002 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 503399135 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 452451368 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 958311587 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 29209900 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 29209900 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 30003 # number of SCUpgradeReq MSHR miss cycles system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 30003 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5043706030 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5043706030 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 3125110 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 37000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 508931159 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5494289418 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 6006382687 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 3125110 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 37000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 508931159 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5494289418 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 6006382687 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 4470659 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166963401029 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 166967871688 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 18112636815 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 18112636815 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 4470659 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 185076037844 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 185080508503 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000662 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000083 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012487 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026721 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015554 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.982251 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.982251 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.157895 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.157895 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.540955 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.540955 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000662 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000083 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012487 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.222846 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.090299 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000662 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000083 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012487 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.222846 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.090299 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 56820.181818 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 37000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41162.338968 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42221.082084 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 41688.751819 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10005.258098 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10005.258098 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5125972608 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5125972608 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 2368082 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 93002 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 503399135 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5578423976 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 6084284195 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 2368082 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 93002 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 503399135 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5578423976 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 6084284195 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 4345155 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166963877530 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 166968222685 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 18087556027 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 18087556027 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 4345155 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 185051433557 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 185055778712 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000542 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000189 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012610 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026828 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015722 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.985478 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.985478 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.250000 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.250000 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541227 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541227 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000542 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000189 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012610 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.223381 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.091162 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000542 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000189 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012610 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.223381 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.091162 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 55071.674419 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 46501 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40728.085356 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42384.203091 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 41521.299263 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10010.246744 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10010.246744 # average UpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average SCUpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 37865.660886 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 37865.660886 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 56820.181818 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 37000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41162.338968 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38188.733166 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38430.519073 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 56820.181818 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 37000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41162.338968 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38188.733166 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38430.519073 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 38490.213011 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 38490.213011 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 55071.674419 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 46501 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40728.085356 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38779.181069 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38937.923632 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 55071.674419 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 46501 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40728.085356 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38779.181069 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38937.923632 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1058,6 +896,168 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.replacements 643459 # number of replacements +system.cpu.dcache.tagsinuse 511.994224 # Cycle average of tags in use +system.cpu.dcache.total_refs 21664123 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 643971 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 33.641457 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 35006000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 511.994224 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999989 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999989 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 13804735 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 13804735 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 7290056 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 7290056 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 280491 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 280491 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 285728 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 285728 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 21094791 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 21094791 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 21094791 # number of overall hits +system.cpu.dcache.overall_hits::total 21094791 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 731455 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 731455 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2960577 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2960577 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 13626 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 13626 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 12 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 12 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::cpu.data 3692032 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3692032 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3692032 # number of overall misses +system.cpu.dcache.overall_misses::total 3692032 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 9566755000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 9566755000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 105515855226 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 105515855226 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 181290500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 181290500 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 192000 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 192000 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 115082610226 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 115082610226 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 115082610226 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 115082610226 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 14536190 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 14536190 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 10250633 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 10250633 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 294117 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 294117 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 285740 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 285740 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 24786823 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 24786823 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 24786823 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 24786823 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050320 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.050320 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.288819 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.288819 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.046329 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.046329 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000042 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000042 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.148951 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.148951 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.148951 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.148951 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13079.075268 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13079.075268 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35640.300937 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 35640.300937 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13304.748275 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13304.748275 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 16000 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 16000 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 31170.534336 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 31170.534336 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 31170.534336 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 31170.534336 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 30622 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 13737 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2589 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 255 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 11.827733 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 53.870588 # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 607749 # number of writebacks +system.cpu.dcache.writebacks::total 607749 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 345667 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 345667 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2711644 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2711644 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1415 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 1415 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3057311 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3057311 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3057311 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3057311 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385788 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 385788 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 248933 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 248933 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12211 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 12211 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 12 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 12 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 634721 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 634721 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 634721 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 634721 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4768255000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4768255000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8227495919 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8227495919 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 141520500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 141520500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 168000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 168000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12995750919 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 12995750919 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12995750919 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 12995750919 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182357111500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182357111500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 27981839814 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 27981839814 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 210338951314 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 210338951314 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026540 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026540 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024285 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024285 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.041517 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.041517 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000042 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000042 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025607 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.025607 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025607 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.025607 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12359.780501 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12359.780501 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33051.045538 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33051.045538 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11589.591352 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11589.591352 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 14000 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 14000 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20474.745469 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20474.745469 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20474.745469 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20474.745469 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 0 # number of replacements system.iocache.tagsinuse 0 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. @@ -1072,16 +1072,16 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1068163777856 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1068163777856 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1068163777856 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1068163777856 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1068305538529 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1068305538529 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1068305538529 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1068305538529 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 88030 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 88025 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini index 97b29a376..f7ba63a28 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini @@ -8,15 +8,15 @@ time_sync_spin_threshold=100000000 [system] type=LinuxX86System -children=acpi_description_table_pointer apicbridge bridge cpu e820_table intel_mp_pointer intel_mp_table intrctrl iobus iocache l2c membus pc physmem smbios_table toL2Bus +children=acpi_description_table_pointer apicbridge bridge cpu e820_table intel_mp_pointer intel_mp_table intrctrl iobus iocache membus pc physmem smbios_table acpi_description_table_pointer=system.acpi_description_table_pointer boot_osflags=earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1 -clock=1 +clock=1000 e820_table=system.e820_table init_param=0 intel_mp_pointer=system.intel_mp_pointer intel_mp_table=system.intel_mp_table -kernel=/scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9 +kernel=/projects/pd/randd/dist/binaries/x86_64-vmlinux-2.6.22.9 load_addr_mask=18446744073709551615 mem_mode=timing memories=system.physmem @@ -52,7 +52,7 @@ oem_table_id= [system.apicbridge] type=Bridge -clock=1 +clock=1000 delay=50000 ranges=11529215046068469760:11529215046068473855 req_size=16 @@ -62,7 +62,7 @@ slave=system.iobus.master[0] [system.bridge] type=Bridge -clock=1 +clock=1000 delay=50000 ranges=4273995776:4273999871 9223372036854775808:11529215046068469759 13835058055282163712:18446744073709551615 req_size=16 @@ -72,7 +72,7 @@ slave=system.membus.master[1] [system.cpu] type=DerivO3CPU -children=dcache dtb dtb_walker_cache fuPool icache interrupts itb itb_walker_cache tracer +children=dcache dtb dtb_walker_cache fuPool icache interrupts isa itb itb_walker_cache l2cache toL2Bus tracer BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -120,6 +120,7 @@ iewToFetchDelay=1 iewToRenameDelay=1 instShiftAmt=2 interrupts=system.cpu.interrupts +isa=system.cpu.isa issueToExecuteDelay=1 issueWidth=8 itb=system.cpu.itb @@ -171,17 +172,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=4 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=2 is_top_level=true -latency=1000 max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=2 size=32768 subblock_size=0 system=system @@ -190,7 +192,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port -mem_side=system.toL2Bus.slave[1] +mem_side=system.cpu.toL2Bus.slave[1] [system.cpu.dtb] type=X86TLB @@ -200,7 +202,7 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=X86PagetableWalker -clock=1 +clock=500 system=system port=system.cpu.dtb_walker_cache.cpu_side @@ -209,17 +211,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -is_top_level=false -latency=1000 +hit_latency=2 +is_top_level=true max_miss_count=0 mshrs=10 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=2 size=1024 subblock_size=0 system=system @@ -228,7 +231,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.dtb.walker.port -mem_side=system.toL2Bus.slave[3] +mem_side=system.cpu.toL2Bus.slave[3] [system.cpu.fuPool] type=FUPool @@ -498,17 +501,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=1 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=2 is_top_level=true -latency=1000 max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=2 size=32768 subblock_size=0 system=system @@ -517,11 +521,11 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port -mem_side=system.toL2Bus.slave[0] +mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=X86LocalApic -clock=1 +clock=500 int_latency=1000 pio_addr=2305843009213693952 pio_latency=100000 @@ -530,6 +534,9 @@ int_master=system.membus.slave[4] int_slave=system.membus.master[3] pio=system.membus.master[2] +[system.cpu.isa] +type=X86ISA + [system.cpu.itb] type=X86TLB children=walker @@ -538,7 +545,7 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=X86PagetableWalker -clock=1 +clock=500 system=system port=system.cpu.itb_walker_cache.cpu_side @@ -547,17 +554,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -is_top_level=false -latency=1000 +hit_latency=2 +is_top_level=true max_miss_count=0 mshrs=10 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=2 size=1024 subblock_size=0 system=system @@ -566,7 +574,44 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.itb.walker.port -mem_side=system.toL2Bus.slave[2] +mem_side=system.cpu.toL2Bus.slave[2] + +[system.cpu.l2cache] +type=BaseCache +addr_ranges=0:18446744073709551615 +assoc=8 +block_size=64 +clock=500 +forward_snoops=true +hash_delay=1 +hit_latency=20 +is_top_level=false +max_miss_count=0 +mshrs=20 +prefetch_on_access=false +prefetcher=Null +prioritizeRequests=false +repl=Null +response_latency=20 +size=4194304 +subblock_size=0 +system=system +tgts_per_mshr=12 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.toL2Bus.master[0] +mem_side=system.membus.slave[3] + +[system.cpu.toL2Bus] +type=CoherentBus +block_size=64 +clock=500 +header_cycles=1 +use_default_range=false +width=32 +master=system.cpu.l2cache.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb_walker_cache.mem_side system.cpu.dtb_walker_cache.mem_side [system.cpu.tracer] type=ExeTracer @@ -950,17 +995,18 @@ type=BaseCache addr_ranges=0:134217727 assoc=8 block_size=64 -clock=1 +clock=1000 forward_snoops=false hash_delay=1 -is_top_level=false -latency=50000 +hit_latency=50 +is_top_level=true max_miss_count=0 mshrs=20 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=50 size=1024 subblock_size=0 system=system @@ -971,32 +1017,6 @@ write_buffers=8 cpu_side=system.iobus.master[18] mem_side=system.membus.slave[2] -[system.l2c] -type=BaseCache -addr_ranges=0:18446744073709551615 -assoc=8 -block_size=64 -clock=1 -forward_snoops=true -hash_delay=1 -is_top_level=false -latency=10000 -max_miss_count=0 -mshrs=92 -prefetch_on_access=false -prefetcher=Null -prioritizeRequests=false -repl=Null -size=4194304 -subblock_size=0 -system=system -tgts_per_mshr=16 -trace_addr=0 -two_queue=false -write_buffers=8 -cpu_side=system.toL2Bus.master[0] -mem_side=system.membus.slave[3] - [system.membus] type=CoherentBus children=badaddr_responder @@ -1007,11 +1027,11 @@ use_default_range=false width=8 default=system.membus.badaddr_responder.pio master=system.physmem.port system.bridge.slave system.cpu.interrupts.pio system.cpu.interrupts.int_slave -slave=system.apicbridge.master system.system_port system.iocache.mem_side system.l2c.mem_side system.cpu.interrupts.int_master +slave=system.apicbridge.master system.system_port system.iocache.mem_side system.cpu.l2cache.mem_side system.cpu.interrupts.int_master [system.membus.badaddr_responder] type=IsaFake -clock=1 +clock=1000 fake_mem=false pio_addr=0 pio_latency=100000 @@ -1034,7 +1054,7 @@ system=system [system.pc.behind_pci] type=IsaFake -clock=1 +clock=1000 fake_mem=false pio_addr=9223372036854779128 pio_latency=100000 @@ -1052,7 +1072,7 @@ pio=system.iobus.master[12] [system.pc.com_1] type=Uart8250 children=terminal -clock=1 +clock=1000 pio_addr=9223372036854776824 pio_latency=100000 platform=system.pc @@ -1076,7 +1096,7 @@ port=3456 [system.pc.fake_com_2] type=IsaFake -clock=1 +clock=1000 fake_mem=false pio_addr=9223372036854776568 pio_latency=100000 @@ -1093,7 +1113,7 @@ pio=system.iobus.master[14] [system.pc.fake_com_3] type=IsaFake -clock=1 +clock=1000 fake_mem=false pio_addr=9223372036854776808 pio_latency=100000 @@ -1110,7 +1130,7 @@ pio=system.iobus.master[15] [system.pc.fake_com_4] type=IsaFake -clock=1 +clock=1000 fake_mem=false pio_addr=9223372036854776552 pio_latency=100000 @@ -1127,7 +1147,7 @@ pio=system.iobus.master[16] [system.pc.fake_floppy] type=IsaFake -clock=1 +clock=1000 fake_mem=false pio_addr=9223372036854776818 pio_latency=100000 @@ -1144,7 +1164,7 @@ pio=system.iobus.master[17] [system.pc.i_dont_exist] type=IsaFake -clock=1 +clock=1000 fake_mem=false pio_addr=9223372036854775936 pio_latency=100000 @@ -1162,7 +1182,7 @@ pio=system.iobus.master[11] [system.pc.pciconfig] type=PciConfigAll bus=0 -clock=1 +clock=1000 pio_latency=30000 platform=system.pc size=16777216 @@ -1185,7 +1205,7 @@ speaker=system.pc.south_bridge.speaker [system.pc.south_bridge.cmos] type=Cmos children=int_pin -clock=1 +clock=1000 int_pin=system.pc.south_bridge.cmos.int_pin pio_addr=9223372036854775920 pio_latency=100000 @@ -1198,7 +1218,7 @@ type=X86IntSourcePin [system.pc.south_bridge.dma1] type=I8237 -clock=1 +clock=1000 pio_addr=9223372036854775808 pio_latency=100000 system=system @@ -1245,7 +1265,7 @@ SubClassCode=1 SubsystemID=0 SubsystemVendorID=0 VendorID=32902 -clock=1 +clock=1000 config_latency=20000 ctrl_offset=0 disks=system.pc.south_bridge.ide.disks0 system.pc.south_bridge.ide.disks1 @@ -1277,7 +1297,7 @@ table_size=65536 [system.pc.south_bridge.ide.disks0.image.child] type=RawDiskImage -image_file=/scratch/nilay/GEM5/system/disks/linux-x86.img +image_file=/projects/pd/randd/dist/disks/linux-x86.img read_only=true [system.pc.south_bridge.ide.disks1] @@ -1297,7 +1317,7 @@ table_size=65536 [system.pc.south_bridge.ide.disks1.image.child] type=RawDiskImage -image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img +image_file=/projects/pd/randd/dist/disks/linux-bigswap2.img read_only=true [system.pc.south_bridge.int_lines0] @@ -1380,7 +1400,7 @@ number=12 [system.pc.south_bridge.io_apic] type=I82094AA apic_id=1 -clock=1 +clock=1000 external_int_pic=system.pc.south_bridge.pic1 int_latency=1000 pio_addr=4273995776 @@ -1392,7 +1412,7 @@ pio=system.iobus.master[10] [system.pc.south_bridge.keyboard] type=I8042 children=keyboard_int_pin mouse_int_pin -clock=1 +clock=1000 command_port=9223372036854775908 data_port=9223372036854775904 keyboard_int_pin=system.pc.south_bridge.keyboard.keyboard_int_pin @@ -1411,7 +1431,7 @@ type=X86IntSourcePin [system.pc.south_bridge.pic1] type=I8259 children=output -clock=1 +clock=1000 mode=I8259Master output=system.pc.south_bridge.pic1.output pio_addr=9223372036854775840 @@ -1426,7 +1446,7 @@ type=X86IntSourcePin [system.pc.south_bridge.pic2] type=I8259 children=output -clock=1 +clock=1000 mode=I8259Slave output=system.pc.south_bridge.pic2.output pio_addr=9223372036854775968 @@ -1441,7 +1461,7 @@ type=X86IntSourcePin [system.pc.south_bridge.pit] type=I8254 children=int_pin -clock=1 +clock=1000 int_pin=system.pc.south_bridge.pit.int_pin pio_addr=9223372036854775872 pio_latency=100000 @@ -1453,7 +1473,7 @@ type=X86IntSourcePin [system.pc.south_bridge.speaker] type=PcSpeaker -clock=1 +clock=1000 i8254=system.pc.south_bridge.pit pio_addr=9223372036854775905 pio_latency=100000 @@ -1461,15 +1481,28 @@ system=system pio=system.iobus.master[9] [system.physmem] -type=SimpleMemory -clock=1 +type=SimpleDRAM +addr_mapping=openmap +banks_per_rank=8 +clock=1000 conf_table_reported=false -file= in_addr_map=true -latency=30000 -latency_var=0 +lines_per_rowbuffer=64 +mem_sched_policy=fcfs null=false +page_policy=open range=0:134217727 +ranks_per_channel=2 +read_buffer_size=32 +tBURST=4000 +tCL=14000 +tRCD=14000 +tREFI=7800000 +tRFC=300000 +tRP=14000 +tWTR=1000 +write_buffer_size=32 +write_thresh_perc=70 zero=false port=system.membus.master[0] @@ -1494,13 +1527,3 @@ starting_addr_segment=0 vendor= version= -[system.toL2Bus] -type=CoherentBus -block_size=64 -clock=1000 -header_cycles=1 -use_default_range=false -width=8 -master=system.l2c.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb_walker_cache.mem_side system.cpu.dtb_walker_cache.mem_side - diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simerr b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simerr index 54a312ff8..8ce3a2233 100755 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simerr +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simerr @@ -5,9 +5,6 @@ warn: Don't know what interrupt to clear for console. warn: x86 cpuid: unknown family 0xbacc warn: x86 cpuid: unknown family 0xbacc warn: x86 cpuid: unknown family 0xbacc -warn: x86 cpuid: unknown family 0xbacc -warn: x86 cpuid: unknown family 0xbacc -warn: x86 cpuid: unknown family 0xbacc warn: instruction 'fxsave' unimplemented warn: x86 cpuid: unknown family 0x8086 warn: x86 cpuid: unknown family 0x8086 diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout index a7e5df44c..334789158 100755 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout @@ -1,15 +1,13 @@ -Redirecting stdout to build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing/simout -Redirecting stderr to build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 10 2012 22:29:00 -gem5 started Sep 10 2012 22:31:43 -gem5 executing on ribera.cs.wisc.edu +gem5 compiled Oct 30 2012 11:14:29 +gem5 started Oct 30 2012 18:26:17 +gem5 executing on u200540-lin command line: build/X86/gem5.opt -d build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing -re tests/run.py build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing warning: add_child('terminal'): child 'terminal' already has parent Global frequency set at 1000000000000 ticks per second -info: kernel located at: /scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9 +info: kernel located at: /projects/pd/randd/dist/binaries/x86_64-vmlinux-2.6.22.9 0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 5167941639500 because m5_exit instruction encountered +Exiting @ tick 5132789913000 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt index 46e54af4f..87b53a299 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt @@ -1,102 +1,102 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.132866 # Number of seconds simulated -sim_ticks 5132866386000 # Number of ticks simulated -final_tick 5132866386000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.132790 # Number of seconds simulated +sim_ticks 5132789913000 # Number of ticks simulated +final_tick 5132789913000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 195837 # Simulator instruction rate (inst/s) -host_op_rate 387119 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2464119438 # Simulator tick rate (ticks/s) -host_mem_usage 403620 # Number of bytes of host memory used -host_seconds 2083.04 # Real time elapsed on the host -sim_insts 407937545 # Number of instructions simulated -sim_ops 806384911 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::pc.south_bridge.ide 2474752 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 3328 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 384 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 1081536 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10883712 # Number of bytes read from this memory -system.physmem.bytes_read::total 14443712 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1081536 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1081536 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 9597376 # Number of bytes written to this memory -system.physmem.bytes_written::total 9597376 # Number of bytes written to this memory -system.physmem.num_reads::pc.south_bridge.ide 38668 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 52 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 6 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 16899 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 170058 # Number of read requests responded to by this memory -system.physmem.num_reads::total 225683 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 149959 # Number of write requests responded to by this memory -system.physmem.num_writes::total 149959 # Number of write requests responded to by this memory -system.physmem.bw_read::pc.south_bridge.ide 482138 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 648 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 75 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 210708 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2120397 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2813966 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 210708 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 210708 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1869789 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1869789 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1869789 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 482138 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 648 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 75 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 210708 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2120397 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4683755 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 225683 # Total number of read requests seen -system.physmem.writeReqs 149959 # Total number of write requests seen -system.physmem.cpureqs 389568 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 14443712 # Total number of bytes read from memory -system.physmem.bytesWritten 9597376 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 14443712 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 9597376 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 89 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 3846 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 13634 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 14670 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 13077 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 15197 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 13869 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 14751 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 12899 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 14175 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 13762 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 14847 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 14072 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 14685 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 13809 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 14671 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 12718 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 14758 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 8656 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 10128 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 8462 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 10559 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 9080 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 10102 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 8151 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 9598 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 8927 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 10197 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 9260 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 9975 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 8913 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 9909 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 8139 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 9903 # Track writes on a per bank basis +host_inst_rate 148899 # Simulator instruction rate (inst/s) +host_op_rate 294332 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1873578722 # Simulator tick rate (ticks/s) +host_mem_usage 406892 # Number of bytes of host memory used +host_seconds 2739.56 # Real time elapsed on the host +sim_insts 407917143 # Number of instructions simulated +sim_ops 806342485 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::pc.south_bridge.ide 2491072 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 3072 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 448 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 1075264 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10835456 # Number of bytes read from this memory +system.physmem.bytes_read::total 14405312 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1075264 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1075264 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 9578880 # Number of bytes written to this memory +system.physmem.bytes_written::total 9578880 # Number of bytes written to this memory +system.physmem.num_reads::pc.south_bridge.ide 38923 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 48 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 7 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 16801 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 169304 # Number of read requests responded to by this memory +system.physmem.num_reads::total 225083 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 149670 # Number of write requests responded to by this memory +system.physmem.num_writes::total 149670 # Number of write requests responded to by this memory +system.physmem.bw_read::pc.south_bridge.ide 485325 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 599 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 87 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 209489 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2111027 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2806527 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 209489 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 209489 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1866213 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1866213 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1866213 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 485325 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 599 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 87 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 209489 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2111027 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4672740 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 225083 # Total number of read requests seen +system.physmem.writeReqs 149670 # Total number of write requests seen +system.physmem.cpureqs 388719 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 14405312 # Total number of bytes read from memory +system.physmem.bytesWritten 9578880 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 14405312 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 9578880 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 75 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 4102 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 13654 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 14948 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 12919 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 15106 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 13327 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 14545 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 13326 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 14277 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 13582 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 14874 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 14098 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 14962 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 13282 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 14549 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 12658 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 14901 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 8775 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 10390 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 8311 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 10526 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 8491 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 9845 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 8546 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 9654 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 8818 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 10118 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 9236 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 10295 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 8519 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 9932 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 8008 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 10206 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 5132866305000 # Total gap between requests +system.physmem.numWrRetry 49 # Number of times wr buffer was full causing retry +system.physmem.totGap 5132789860500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 225683 # Categorize read packet sizes +system.physmem.readPktSize::6 225083 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -105,7 +105,7 @@ system.physmem.writePktSize::2 0 # ca system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 149959 # categorize write packet sizes +system.physmem.writePktSize::6 149719 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -114,31 +114,31 @@ system.physmem.neitherpktsize::2 0 # ca system.physmem.neitherpktsize::3 0 # categorize neither packet sizes system.physmem.neitherpktsize::4 0 # categorize neither packet sizes system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 3846 # categorize neither packet sizes +system.physmem.neitherpktsize::6 4102 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 177236 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 21627 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 8107 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 2832 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2887 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2147 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1315 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 176543 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 21526 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 8299 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 2898 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2824 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2164 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1338 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 1517 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1334 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1287 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1161 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1104 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1045 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 846 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 440 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 235 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 188 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 132 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 78 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 62 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 13 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1378 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1294 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1195 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1112 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1080 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 826 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 390 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 237 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 151 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 102 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 71 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 52 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 11 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see @@ -150,47 +150,47 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 5741 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 6370 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 6482 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 6504 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 6513 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 6518 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 6520 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 6520 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 6520 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 6520 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 6520 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 6520 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 6520 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 6520 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 6520 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 6520 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 6520 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 6520 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6520 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6520 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6520 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6520 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6519 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 779 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 150 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 38 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 5656 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 6362 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 6464 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 6486 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 6500 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 6503 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 6505 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 6506 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 6506 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 6507 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 6507 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 6507 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 6507 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 6507 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 6507 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 6507 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 6507 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 6507 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6507 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6507 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6507 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6507 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6507 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 852 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 146 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 44 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 22 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 3339090244 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 7604182244 # Sum of mem lat for all requests -system.physmem.totBusLat 902376000 # Total cycles spent in databus access -system.physmem.totBankLat 3362716000 # Total cycles spent in bank access -system.physmem.avgQLat 14801.33 # Average queueing delay per request -system.physmem.avgBankLat 14906.05 # Average bank access latency per request +system.physmem.totQLat 3269589754 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 7518085754 # Sum of mem lat for all requests +system.physmem.totBusLat 900032000 # Total cycles spent in databus access +system.physmem.totBankLat 3348464000 # Total cycles spent in bank access +system.physmem.avgQLat 14530.99 # Average queueing delay per request +system.physmem.avgBankLat 14881.53 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 33707.38 # Average memory access latency +system.physmem.avgMemAccLat 33412.53 # Average memory access latency system.physmem.avgRdBW 2.81 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 1.87 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 2.81 # Average consumed read bandwidth in MB/s @@ -198,45 +198,45 @@ system.physmem.avgConsumedWrBW 1.87 # Av system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time -system.physmem.avgWrQLen 10.11 # Average write queue length over time -system.physmem.readRowHits 199074 # Number of row buffer hits during reads -system.physmem.writeRowHits 88511 # Number of row buffer hits during writes -system.physmem.readRowHitRate 88.24 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 59.02 # Row buffer hit rate for writes -system.physmem.avgGap 13664250.28 # Average gap between requests -system.iocache.replacements 47575 # number of replacements -system.iocache.tagsinuse 0.103977 # Cycle average of tags in use +system.physmem.avgWrQLen 11.37 # Average write queue length over time +system.physmem.readRowHits 198566 # Number of row buffer hits during reads +system.physmem.writeRowHits 87960 # Number of row buffer hits during writes +system.physmem.readRowHitRate 88.25 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 58.77 # Row buffer hit rate for writes +system.physmem.avgGap 13696461.03 # Average gap between requests +system.iocache.replacements 47576 # number of replacements +system.iocache.tagsinuse 0.103964 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.sampled_refs 47591 # Sample count of references to valid blocks. +system.iocache.sampled_refs 47592 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 4991894063000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::pc.south_bridge.ide 0.103977 # Average occupied blocks per requestor -system.iocache.occ_percent::pc.south_bridge.ide 0.006499 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.006499 # Average percentage of cache occupancy -system.iocache.ReadReq_misses::pc.south_bridge.ide 910 # number of ReadReq misses -system.iocache.ReadReq_misses::total 910 # number of ReadReq misses +system.iocache.warmup_cycle 4991828572000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::pc.south_bridge.ide 0.103964 # Average occupied blocks per requestor +system.iocache.occ_percent::pc.south_bridge.ide 0.006498 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.006498 # Average percentage of cache occupancy +system.iocache.ReadReq_misses::pc.south_bridge.ide 911 # number of ReadReq misses +system.iocache.ReadReq_misses::total 911 # number of ReadReq misses system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses -system.iocache.demand_misses::pc.south_bridge.ide 47630 # number of demand (read+write) misses -system.iocache.demand_misses::total 47630 # number of demand (read+write) misses -system.iocache.overall_misses::pc.south_bridge.ide 47630 # number of overall misses -system.iocache.overall_misses::total 47630 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 143902932 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 143902932 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 9034164160 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 9034164160 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 9178067092 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 9178067092 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 9178067092 # number of overall miss cycles -system.iocache.overall_miss_latency::total 9178067092 # number of overall miss cycles -system.iocache.ReadReq_accesses::pc.south_bridge.ide 910 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 910 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::pc.south_bridge.ide 47631 # number of demand (read+write) misses +system.iocache.demand_misses::total 47631 # number of demand (read+write) misses +system.iocache.overall_misses::pc.south_bridge.ide 47631 # number of overall misses +system.iocache.overall_misses::total 47631 # number of overall misses +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 146267932 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 146267932 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 8962382160 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 8962382160 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 9108650092 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 9108650092 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 9108650092 # number of overall miss cycles +system.iocache.overall_miss_latency::total 9108650092 # number of overall miss cycles +system.iocache.ReadReq_accesses::pc.south_bridge.ide 911 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 911 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses) -system.iocache.demand_accesses::pc.south_bridge.ide 47630 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 47630 # number of demand (read+write) accesses -system.iocache.overall_accesses::pc.south_bridge.ide 47630 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 47630 # number of overall (read+write) accesses +system.iocache.demand_accesses::pc.south_bridge.ide 47631 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 47631 # number of demand (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 47631 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 47631 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses @@ -245,40 +245,40 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 158135.090110 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 158135.090110 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 193368.239726 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 193368.239726 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 192695.089062 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 192695.089062 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 192695.089062 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 192695.089062 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 60674 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 160557.554336 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 160557.554336 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 191831.809932 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 191831.809932 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 191233.652285 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 191233.652285 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 191233.652285 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 191233.652285 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 51554 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 7530 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 7256 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8.057636 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 7.105017 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 46667 # number of writebacks system.iocache.writebacks::total 46667 # number of writebacks -system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 910 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 910 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 911 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 911 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 46720 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses::pc.south_bridge.ide 47630 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 47630 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::pc.south_bridge.ide 47630 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 47630 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 96552990 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 96552990 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 6602427338 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 6602427338 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 6698980328 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 6698980328 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 6698980328 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 6698980328 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::pc.south_bridge.ide 47631 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 47631 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::pc.south_bridge.ide 47631 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 47631 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 98865990 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 98865990 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 6530591975 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 6530591975 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 6629457965 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 6629457965 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 6629457965 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 6629457965 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses @@ -287,14 +287,14 @@ system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 106102.186813 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 106102.186813 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 141319.078296 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 141319.078296 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 140646.238253 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 140646.238253 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 140646.238253 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 140646.238253 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 108524.687157 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 108524.687157 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 139781.506314 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 139781.506314 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 139183.682161 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 139183.682161 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 139183.682161 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 139183.682161 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). @@ -308,409 +308,409 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.cpu.numCycles 448858777 # number of cpu cycles simulated +system.cpu.numCycles 447650408 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 86511552 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 86511552 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 1187540 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 81908216 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 79448034 # Number of BTB hits +system.cpu.BPredUnit.lookups 86252473 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 86252473 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 1112360 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 81440812 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 79250759 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 28014488 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 427358956 # Number of instructions fetch has processed -system.cpu.fetch.Branches 86511552 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 79448034 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 164036376 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 5076610 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 125788 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 62760738 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 36372 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 61645 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 359 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 9269515 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 518863 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 3783 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 258886753 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 3.258580 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.418024 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 27455337 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 426133339 # Number of instructions fetch has processed +system.cpu.fetch.Branches 86252473 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 79250759 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 163637491 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 4749598 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 117040 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 62764723 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 36355 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 51011 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 275 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 9043493 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 487667 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 3497 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 257661797 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 3.265027 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.418216 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 95280988 36.80% 36.80% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1593075 0.62% 37.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 71954141 27.79% 65.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 971709 0.38% 65.59% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1620643 0.63% 66.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 2451488 0.95% 67.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1122205 0.43% 67.59% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1426657 0.55% 68.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 82465847 31.85% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 94448905 36.66% 36.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1567012 0.61% 37.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 71922195 27.91% 65.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 935544 0.36% 65.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1602565 0.62% 66.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 2433530 0.94% 67.11% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1078893 0.42% 67.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1381790 0.54% 68.06% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 82291363 31.94% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 258886753 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.192737 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.952101 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 31742461 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 60237035 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 159788942 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 3267328 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3850987 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 840289565 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 1231 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3850987 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 34512001 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 37373607 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 10738522 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 159961860 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 12449776 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 836423195 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 19229 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 5893988 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4723761 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 7727 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 998196840 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1816454110 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1816453462 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 648 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 964349930 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 33846903 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 467065 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 474165 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 28825004 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 17330743 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 10271430 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1207742 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 944493 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 829965735 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1256270 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 824405499 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 167750 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 23821216 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 36350655 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 203504 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 258886753 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 3.184425 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.385403 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 257661797 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.192678 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.951933 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 31146269 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 60227421 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 159444515 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 3244027 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3599565 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 838112106 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 919 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3599565 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 33887749 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 37302672 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 10848429 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 159621170 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 12402212 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 834448767 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 20383 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 5810954 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4749020 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 7935 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 996003699 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1811552283 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1811551779 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 504 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 964308271 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 31695421 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 457655 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 465271 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 28736743 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 17096853 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 10140380 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1243307 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 975146 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 828306292 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1248163 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 823283697 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 148415 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 22289625 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 33892420 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 195525 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 257661797 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 3.195211 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.383294 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 72013044 27.82% 27.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 15598777 6.03% 33.84% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 10365143 4.00% 37.85% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 7553925 2.92% 40.76% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 75959659 29.34% 70.10% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 3903196 1.51% 71.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 72545029 28.02% 99.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 793969 0.31% 99.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 154011 0.06% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 71201357 27.63% 27.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 15459797 6.00% 33.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 10286150 3.99% 37.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 7472850 2.90% 40.53% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 75924697 29.47% 69.99% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 3857138 1.50% 71.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 72522119 28.15% 99.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 785654 0.30% 99.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 152035 0.06% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 258886753 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 257661797 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 353413 33.31% 33.31% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 33.31% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 33.31% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 33.31% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 33.31% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 33.31% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 33.31% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 33.31% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 33.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 33.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 33.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 33.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 33.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 33.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 33.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 33.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 33.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 33.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 33.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 33.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 33.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 33.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 33.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 33.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 33.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 33.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 33.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 33.31% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 554407 52.25% 85.55% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 153287 14.45% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 364358 34.12% 34.12% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 34.12% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 34.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 34.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 34.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 34.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 34.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 34.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 34.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 34.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 34.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 34.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 34.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 34.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 34.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 34.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 34.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 34.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 34.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 34.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 34.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 34.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 34.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 34.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 34.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 34.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 34.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 34.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 34.12% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 552545 51.74% 85.86% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 150975 14.14% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 307308 0.04% 0.04% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 796584719 96.63% 96.66% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 96.66% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 96.66% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.66% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.66% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 96.66% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 96.66% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 96.66% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 96.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 96.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 96.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 96.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 96.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 96.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 96.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 96.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 96.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 96.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 96.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.66% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 18039231 2.19% 98.85% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 9474241 1.15% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 312887 0.04% 0.04% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 795710532 96.65% 96.69% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 96.69% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 96.69% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.69% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.69% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 96.69% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 96.69% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 96.69% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 96.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 96.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 96.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 96.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 96.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 96.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 96.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 96.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 96.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 96.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 96.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.69% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 17869782 2.17% 98.86% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 9390496 1.14% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 824405499 # Type of FU issued -system.cpu.iq.rate 1.836670 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1061107 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.001287 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1909060731 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 855053110 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 819712115 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 267 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 306 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 66 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 825159176 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 122 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1650601 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 823283697 # Type of FU issued +system.cpu.iq.rate 1.839122 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1067878 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.001297 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1905576298 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 851854038 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 818789401 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 203 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 230 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 54 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 824038596 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 92 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1642479 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 3355072 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 26592 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 11367 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1855422 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 3121524 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 22243 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 11430 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1726583 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 1932171 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 11828 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 1932632 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 11779 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3850987 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 26145840 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 2117101 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 831222005 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 328364 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 17330743 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 10271430 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 725551 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1616789 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 12654 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 11367 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 710665 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 625080 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1335745 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 822377334 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 17606524 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2028164 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3599565 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 26096083 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 2112224 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 829554455 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 302739 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 17096853 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 10140380 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 717341 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1614771 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 11695 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 11430 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 654771 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 594016 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1248787 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 821389011 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 17449263 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1894685 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 26829889 # number of memory reference insts executed -system.cpu.iew.exec_branches 83279279 # Number of branches executed -system.cpu.iew.exec_stores 9223365 # Number of stores executed -system.cpu.iew.exec_rate 1.832152 # Inst execution rate -system.cpu.iew.wb_sent 821869918 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 819712181 # cumulative count of insts written-back -system.cpu.iew.wb_producers 640562059 # num instructions producing a value -system.cpu.iew.wb_consumers 1046574799 # num instructions consuming a value +system.cpu.iew.exec_refs 26607287 # number of memory reference insts executed +system.cpu.iew.exec_branches 83217289 # Number of branches executed +system.cpu.iew.exec_stores 9158024 # Number of stores executed +system.cpu.iew.exec_rate 1.834889 # Inst execution rate +system.cpu.iew.wb_sent 820925784 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 818789455 # cumulative count of insts written-back +system.cpu.iew.wb_producers 639951171 # num instructions producing a value +system.cpu.iew.wb_consumers 1045809475 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.826214 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.612056 # average fanout of values written-back +system.cpu.iew.wb_rate 1.829082 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.611919 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 24730610 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1052764 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1192382 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 255051171 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 3.161659 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.853306 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 23105687 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1052636 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 1116569 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 254077625 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 3.173607 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.854352 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 83143291 32.60% 32.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 11860450 4.65% 37.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3961812 1.55% 38.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 74971665 29.39% 68.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 2481439 0.97% 69.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1489878 0.58% 69.75% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 950647 0.37% 70.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 70929098 27.81% 97.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5262891 2.06% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 82352974 32.41% 32.41% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 11796837 4.64% 37.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3872314 1.52% 38.58% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 74949594 29.50% 68.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2433419 0.96% 69.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1479159 0.58% 69.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 902635 0.36% 69.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 70918587 27.91% 97.89% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5372106 2.11% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 255051171 # Number of insts commited each cycle -system.cpu.commit.committedInsts 407937545 # Number of instructions committed -system.cpu.commit.committedOps 806384911 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 254077625 # Number of insts commited each cycle +system.cpu.commit.committedInsts 407917143 # Number of instructions committed +system.cpu.commit.committedOps 806342485 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 22391676 # Number of memory references committed -system.cpu.commit.loads 13975668 # Number of loads committed -system.cpu.commit.membars 473465 # Number of memory barriers committed -system.cpu.commit.branches 82190309 # Number of branches committed +system.cpu.commit.refs 22389123 # Number of memory references committed +system.cpu.commit.loads 13975326 # Number of loads committed +system.cpu.commit.membars 473463 # Number of memory barriers committed +system.cpu.commit.branches 82187715 # Number of branches committed system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu.commit.int_insts 735319938 # Number of committed integer instructions. +system.cpu.commit.int_insts 735283087 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5262891 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5372106 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1080825517 # The number of ROB reads -system.cpu.rob.rob_writes 1666103017 # The number of ROB writes -system.cpu.timesIdled 1222907 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 189972024 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 9816871415 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 407937545 # Number of Instructions Simulated -system.cpu.committedOps 806384911 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 407937545 # Number of Instructions Simulated -system.cpu.cpi 1.100312 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.100312 # CPI: Total CPI of All Threads -system.cpu.ipc 0.908833 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.908833 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1508250980 # number of integer regfile reads -system.cpu.int_regfile_writes 977858997 # number of integer regfile writes -system.cpu.fp_regfile_reads 66 # number of floating regfile reads -system.cpu.misc_regfile_reads 265171411 # number of misc regfile reads -system.cpu.misc_regfile_writes 402390 # number of misc regfile writes -system.cpu.icache.replacements 1072344 # number of replacements -system.cpu.icache.tagsinuse 510.326715 # Cycle average of tags in use -system.cpu.icache.total_refs 8127499 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1072855 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 7.575580 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 56079311000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 510.326715 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.996732 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.996732 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 8127499 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 8127499 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 8127499 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 8127499 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 8127499 # number of overall hits -system.cpu.icache.overall_hits::total 8127499 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1142014 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1142014 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1142014 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1142014 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1142014 # number of overall misses -system.cpu.icache.overall_misses::total 1142014 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 15424181989 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 15424181989 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 15424181989 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 15424181989 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 15424181989 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 15424181989 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 9269513 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 9269513 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 9269513 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 9269513 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 9269513 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 9269513 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.123201 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.123201 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.123201 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.123201 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.123201 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.123201 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13506.123383 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13506.123383 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13506.123383 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13506.123383 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13506.123383 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13506.123383 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 7378 # number of cycles access was blocked +system.cpu.rob.rob_reads 1078075497 # The number of ROB reads +system.cpu.rob.rob_writes 1662514782 # The number of ROB writes +system.cpu.timesIdled 1218897 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 189988611 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 9817926834 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 407917143 # Number of Instructions Simulated +system.cpu.committedOps 806342485 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 407917143 # Number of Instructions Simulated +system.cpu.cpi 1.097405 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.097405 # CPI: Total CPI of All Threads +system.cpu.ipc 0.911240 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.911240 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1506960736 # number of integer regfile reads +system.cpu.int_regfile_writes 976968921 # number of integer regfile writes +system.cpu.fp_regfile_reads 54 # number of floating regfile reads +system.cpu.misc_regfile_reads 264713842 # number of misc regfile reads +system.cpu.misc_regfile_writes 402218 # number of misc regfile writes +system.cpu.icache.replacements 1046081 # number of replacements +system.cpu.icache.tagsinuse 510.992308 # Cycle average of tags in use +system.cpu.icache.total_refs 7932749 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 1046593 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 7.579593 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 55992087000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 510.992308 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.998032 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.998032 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 7932749 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 7932749 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 7932749 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 7932749 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 7932749 # number of overall hits +system.cpu.icache.overall_hits::total 7932749 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1110744 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1110744 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1110744 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1110744 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1110744 # number of overall misses +system.cpu.icache.overall_misses::total 1110744 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 15035266490 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 15035266490 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 15035266490 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 15035266490 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 15035266490 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 15035266490 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 9043493 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 9043493 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 9043493 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 9043493 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 9043493 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 9043493 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.122822 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.122822 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.122822 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.122822 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.122822 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.122822 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13536.212206 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13536.212206 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13536.212206 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13536.212206 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13536.212206 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13536.212206 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 5934 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 254 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 274 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 29.047244 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 21.656934 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 66936 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 66936 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 66936 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 66936 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 66936 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 66936 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1075078 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1075078 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1075078 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1075078 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1075078 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1075078 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12692625989 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 12692625989 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12692625989 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 12692625989 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12692625989 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 12692625989 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.115980 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.115980 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.115980 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.115980 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.115980 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.115980 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11806.237305 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11806.237305 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11806.237305 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11806.237305 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11806.237305 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11806.237305 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 61679 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 61679 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 61679 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 61679 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 61679 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 61679 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1049065 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1049065 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1049065 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1049065 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1049065 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1049065 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12388903990 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 12388903990 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12388903990 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 12388903990 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12388903990 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 12388903990 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.116002 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.116002 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.116002 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.116002 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.116002 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.116002 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11809.472235 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11809.472235 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11809.472235 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11809.472235 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11809.472235 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11809.472235 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.itb_walker_cache.replacements 10190 # number of replacements -system.cpu.itb_walker_cache.tagsinuse 6.008148 # Cycle average of tags in use -system.cpu.itb_walker_cache.total_refs 29715 # Total number of references to valid blocks. -system.cpu.itb_walker_cache.sampled_refs 10203 # Sample count of references to valid blocks. -system.cpu.itb_walker_cache.avg_refs 2.912379 # Average number of references to valid blocks. -system.cpu.itb_walker_cache.warmup_cycle 5103977180500 # Cycle when the warmup percentage was hit. -system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 6.008148 # Average occupied blocks per requestor -system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.375509 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.occ_percent::total 0.375509 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 29719 # number of ReadReq hits -system.cpu.itb_walker_cache.ReadReq_hits::total 29719 # number of ReadReq hits +system.cpu.itb_walker_cache.replacements 9937 # number of replacements +system.cpu.itb_walker_cache.tagsinuse 6.006130 # Cycle average of tags in use +system.cpu.itb_walker_cache.total_refs 26086 # Total number of references to valid blocks. +system.cpu.itb_walker_cache.sampled_refs 9951 # Sample count of references to valid blocks. +system.cpu.itb_walker_cache.avg_refs 2.621445 # Average number of references to valid blocks. +system.cpu.itb_walker_cache.warmup_cycle 5106893785000 # Cycle when the warmup percentage was hit. +system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 6.006130 # Average occupied blocks per requestor +system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.375383 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.occ_percent::total 0.375383 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 26219 # number of ReadReq hits +system.cpu.itb_walker_cache.ReadReq_hits::total 26219 # number of ReadReq hits system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 3 # number of WriteReq hits system.cpu.itb_walker_cache.WriteReq_hits::total 3 # number of WriteReq hits -system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 29722 # number of demand (read+write) hits -system.cpu.itb_walker_cache.demand_hits::total 29722 # number of demand (read+write) hits -system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 29722 # number of overall hits -system.cpu.itb_walker_cache.overall_hits::total 29722 # number of overall hits -system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 11072 # number of ReadReq misses -system.cpu.itb_walker_cache.ReadReq_misses::total 11072 # number of ReadReq misses -system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 11072 # number of demand (read+write) misses -system.cpu.itb_walker_cache.demand_misses::total 11072 # number of demand (read+write) misses -system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 11072 # number of overall misses -system.cpu.itb_walker_cache.overall_misses::total 11072 # number of overall misses -system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 125220500 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.ReadReq_miss_latency::total 125220500 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 125220500 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::total 125220500 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 125220500 # number of overall miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::total 125220500 # number of overall miss cycles -system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 40791 # number of ReadReq accesses(hits+misses) -system.cpu.itb_walker_cache.ReadReq_accesses::total 40791 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 26222 # number of demand (read+write) hits +system.cpu.itb_walker_cache.demand_hits::total 26222 # number of demand (read+write) hits +system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 26222 # number of overall hits +system.cpu.itb_walker_cache.overall_hits::total 26222 # number of overall hits +system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 10817 # number of ReadReq misses +system.cpu.itb_walker_cache.ReadReq_misses::total 10817 # number of ReadReq misses +system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 10817 # number of demand (read+write) misses +system.cpu.itb_walker_cache.demand_misses::total 10817 # number of demand (read+write) misses +system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 10817 # number of overall misses +system.cpu.itb_walker_cache.overall_misses::total 10817 # number of overall misses +system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 116537500 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.ReadReq_miss_latency::total 116537500 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 116537500 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::total 116537500 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 116537500 # number of overall miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::total 116537500 # number of overall miss cycles +system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 37036 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.ReadReq_accesses::total 37036 # number of ReadReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 3 # number of WriteReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) -system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 40794 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.demand_accesses::total 40794 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 40794 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::total 40794 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.271432 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.271432 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.271412 # miss rate for demand accesses -system.cpu.itb_walker_cache.demand_miss_rate::total 0.271412 # miss rate for demand accesses -system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.271412 # miss rate for overall accesses -system.cpu.itb_walker_cache.overall_miss_rate::total 0.271412 # miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11309.654986 # average ReadReq miss latency -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11309.654986 # average ReadReq miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11309.654986 # average overall miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11309.654986 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11309.654986 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11309.654986 # average overall miss latency +system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 37039 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.demand_accesses::total 37039 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 37039 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::total 37039 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.292067 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.292067 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.292044 # miss rate for demand accesses +system.cpu.itb_walker_cache.demand_miss_rate::total 0.292044 # miss rate for demand accesses +system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.292044 # miss rate for overall accesses +system.cpu.itb_walker_cache.overall_miss_rate::total 0.292044 # miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 10773.550892 # average ReadReq miss latency +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 10773.550892 # average ReadReq miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 10773.550892 # average overall miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::total 10773.550892 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 10773.550892 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::total 10773.550892 # average overall miss latency system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -719,78 +719,78 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.itb_walker_cache.writebacks::writebacks 1966 # number of writebacks -system.cpu.itb_walker_cache.writebacks::total 1966 # number of writebacks -system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 11072 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 11072 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 11072 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::total 11072 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 11072 # number of overall MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::total 11072 # number of overall MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 103076500 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 103076500 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 103076500 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 103076500 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 103076500 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 103076500 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.271432 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.271432 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.271412 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.271412 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.271412 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.271412 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9309.654986 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9309.654986 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9309.654986 # average overall mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 9309.654986 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9309.654986 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9309.654986 # average overall mshr miss latency +system.cpu.itb_walker_cache.writebacks::writebacks 1872 # number of writebacks +system.cpu.itb_walker_cache.writebacks::total 1872 # number of writebacks +system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 10817 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 10817 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 10817 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::total 10817 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 10817 # number of overall MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::total 10817 # number of overall MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 94903500 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 94903500 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 94903500 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 94903500 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 94903500 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 94903500 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.292067 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.292067 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.292044 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.292044 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.292044 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.292044 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 8773.550892 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8773.550892 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 8773.550892 # average overall mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 8773.550892 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 8773.550892 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 8773.550892 # average overall mshr miss latency system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dtb_walker_cache.replacements 112521 # number of replacements -system.cpu.dtb_walker_cache.tagsinuse 12.957581 # Cycle average of tags in use -system.cpu.dtb_walker_cache.total_refs 137445 # Total number of references to valid blocks. -system.cpu.dtb_walker_cache.sampled_refs 112536 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.avg_refs 1.221343 # Average number of references to valid blocks. -system.cpu.dtb_walker_cache.warmup_cycle 5100518873000 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 12.957581 # Average occupied blocks per requestor -system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.809849 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.occ_percent::total 0.809849 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 137452 # number of ReadReq hits -system.cpu.dtb_walker_cache.ReadReq_hits::total 137452 # number of ReadReq hits -system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 137452 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::total 137452 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 137452 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::total 137452 # number of overall hits -system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 113500 # number of ReadReq misses -system.cpu.dtb_walker_cache.ReadReq_misses::total 113500 # number of ReadReq misses -system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 113500 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::total 113500 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 113500 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::total 113500 # number of overall misses -system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 1432388500 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 1432388500 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 1432388500 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::total 1432388500 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 1432388500 # number of overall miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::total 1432388500 # number of overall miss cycles -system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 250952 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.ReadReq_accesses::total 250952 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 250952 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::total 250952 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 250952 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::total 250952 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.452278 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.452278 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.452278 # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::total 0.452278 # miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.452278 # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::total 0.452278 # miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12620.162996 # average ReadReq miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12620.162996 # average ReadReq miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12620.162996 # average overall miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12620.162996 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12620.162996 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12620.162996 # average overall miss latency +system.cpu.dtb_walker_cache.replacements 113923 # number of replacements +system.cpu.dtb_walker_cache.tagsinuse 12.921985 # Cycle average of tags in use +system.cpu.dtb_walker_cache.total_refs 130116 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.sampled_refs 113938 # Sample count of references to valid blocks. +system.cpu.dtb_walker_cache.avg_refs 1.141990 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.warmup_cycle 5100448688500 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 12.921985 # Average occupied blocks per requestor +system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.807624 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.occ_percent::total 0.807624 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 130138 # number of ReadReq hits +system.cpu.dtb_walker_cache.ReadReq_hits::total 130138 # number of ReadReq hits +system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 130138 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::total 130138 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 130138 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::total 130138 # number of overall hits +system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 114896 # number of ReadReq misses +system.cpu.dtb_walker_cache.ReadReq_misses::total 114896 # number of ReadReq misses +system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 114896 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::total 114896 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 114896 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::total 114896 # number of overall misses +system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 1427497500 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 1427497500 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 1427497500 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::total 1427497500 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 1427497500 # number of overall miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::total 1427497500 # number of overall miss cycles +system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 245034 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.ReadReq_accesses::total 245034 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 245034 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::total 245034 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 245034 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::total 245034 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.468898 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.468898 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.468898 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::total 0.468898 # miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.468898 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::total 0.468898 # miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12424.257589 # average ReadReq miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12424.257589 # average ReadReq miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12424.257589 # average overall miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12424.257589 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12424.257589 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12424.257589 # average overall miss latency system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -799,146 +799,146 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.dtb_walker_cache.writebacks::writebacks 37324 # number of writebacks -system.cpu.dtb_walker_cache.writebacks::total 37324 # number of writebacks -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 113500 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 113500 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 113500 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::total 113500 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 113500 # number of overall MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::total 113500 # number of overall MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1205388500 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 1205388500 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 1205388500 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 1205388500 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 1205388500 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 1205388500 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.452278 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.452278 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.452278 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.452278 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.452278 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.452278 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10620.162996 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10620.162996 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10620.162996 # average overall mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10620.162996 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10620.162996 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10620.162996 # average overall mshr miss latency +system.cpu.dtb_walker_cache.writebacks::writebacks 35555 # number of writebacks +system.cpu.dtb_walker_cache.writebacks::total 35555 # number of writebacks +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 114896 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 114896 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 114896 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::total 114896 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 114896 # number of overall MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::total 114896 # number of overall MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1197705500 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 1197705500 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 1197705500 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 1197705500 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 1197705500 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 1197705500 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.468898 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.468898 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.468898 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.468898 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.468898 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.468898 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10424.257589 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10424.257589 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10424.257589 # average overall mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10424.257589 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10424.257589 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10424.257589 # average overall mshr miss latency system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1671903 # number of replacements -system.cpu.dcache.tagsinuse 511.996701 # Cycle average of tags in use -system.cpu.dcache.total_refs 19219910 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1672415 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 11.492309 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 27804000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 511.996701 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999994 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 11126974 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 11126974 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 8088054 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 8088054 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 19215028 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 19215028 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 19215028 # number of overall hits -system.cpu.dcache.overall_hits::total 19215028 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2267052 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2267052 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 318719 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 318719 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2585771 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2585771 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2585771 # number of overall misses -system.cpu.dcache.overall_misses::total 2585771 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 32362735000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 32362735000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 9617362993 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 9617362993 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 41980097993 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 41980097993 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 41980097993 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 41980097993 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 13394026 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 13394026 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 8406773 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 8406773 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 21800799 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 21800799 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 21800799 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 21800799 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.169258 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.169258 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037912 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.037912 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.118609 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.118609 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.118609 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.118609 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14275.250413 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14275.250413 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30175.053866 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 30175.053866 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 16235.040919 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 16235.040919 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 16235.040919 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 16235.040919 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 395929 # number of cycles access was blocked +system.cpu.dcache.replacements 1657882 # number of replacements +system.cpu.dcache.tagsinuse 511.998105 # Cycle average of tags in use +system.cpu.dcache.total_refs 19102953 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1658394 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 11.518947 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 27815000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 511.998105 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999996 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999996 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 11010989 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 11010989 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 8086819 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 8086819 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 19097808 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 19097808 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 19097808 # number of overall hits +system.cpu.dcache.overall_hits::total 19097808 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2233987 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2233987 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 317747 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 317747 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2551734 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2551734 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2551734 # number of overall misses +system.cpu.dcache.overall_misses::total 2551734 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 31818004500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 31818004500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 9564256493 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 9564256493 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 41382260993 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 41382260993 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 41382260993 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 41382260993 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 13244976 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 13244976 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 8404566 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 8404566 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 21649542 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 21649542 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 21649542 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 21649542 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.168667 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.168667 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037806 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.037806 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.117865 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.117865 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.117865 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.117865 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14242.699040 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14242.699040 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30100.225944 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 30100.225944 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 16217.309874 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 16217.309874 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 16217.309874 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 16217.309874 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 396326 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 42571 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 42512 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.300439 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.322685 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1571444 # number of writebacks -system.cpu.dcache.writebacks::total 1571444 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 884224 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 884224 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 24733 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 24733 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 908957 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 908957 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 908957 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 908957 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1382828 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1382828 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 293986 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 293986 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1676814 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1676814 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1676814 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1676814 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17466154000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 17466154000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8776924993 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8776924993 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26243078993 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 26243078993 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26243078993 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 26243078993 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 97296687500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 97296687500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2470134500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2470134500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 99766822000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 99766822000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.103242 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.103242 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034970 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034970 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.076915 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.076915 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076915 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.076915 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12630.749450 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12630.749450 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 29854.908033 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 29854.908033 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15650.560523 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 15650.560523 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15650.560523 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 15650.560523 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 1559612 # number of writebacks +system.cpu.dcache.writebacks::total 1559612 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 862458 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 862458 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 26265 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 26265 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 888723 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 888723 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 888723 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 888723 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1371529 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1371529 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 291482 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 291482 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1663011 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1663011 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1663011 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1663011 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17298488500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 17298488500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8726866493 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8726866493 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26025354993 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 26025354993 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26025354993 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 26025354993 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 97296677500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 97296677500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2469996000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2469996000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 99766673500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 99766673500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.103551 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.103551 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034681 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034681 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.076815 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.076815 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076815 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.076815 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12612.557591 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12612.557591 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 29939.641189 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 29939.641189 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15649.538694 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 15649.538694 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15649.538694 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 15649.538694 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -946,141 +946,141 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 114477 # number of replacements -system.cpu.l2cache.tagsinuse 64832.099181 # Cycle average of tags in use -system.cpu.l2cache.total_refs 3982953 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 178625 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 22.297847 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 113761 # number of replacements +system.cpu.l2cache.tagsinuse 64829.122340 # Cycle average of tags in use +system.cpu.l2cache.total_refs 3920006 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 178006 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 22.021763 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 50137.283412 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.dtb.walker 9.875444 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.154438 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 3167.346365 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 11517.439521 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.765034 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000151 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::writebacks 50212.838916 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.dtb.walker 12.458733 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.160012 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 3172.410316 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 11431.254363 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.766187 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000190 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.048330 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.175742 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.989259 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 106895 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 8720 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 1055914 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 1344492 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 2516021 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 1610734 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 1610734 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 350 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 350 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 156374 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 156374 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 106895 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 8720 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 1055914 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1500866 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2672395 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 106895 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 8720 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 1055914 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1500866 # number of overall hits -system.cpu.l2cache.overall_hits::total 2672395 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 52 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 6 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.inst 16902 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 37251 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 54211 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 3576 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 3576 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 133749 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 133749 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.dtb.walker 52 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.itb.walker 6 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 16902 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 171000 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 187960 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.dtb.walker 52 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.itb.walker 6 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 16902 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 171000 # number of overall misses -system.cpu.l2cache.overall_misses::total 187960 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 4573500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 414000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1004010500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2406198500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 3415196500 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 17041499 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 17041499 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6830930000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 6830930000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 4573500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 414000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 1004010500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 9237128500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 10246126500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 4573500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 414000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 1004010500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 9237128500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 10246126500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 106947 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 8726 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.inst 1072816 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1381743 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 2570232 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 1610734 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 1610734 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 3926 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 3926 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 290123 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 290123 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 106947 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.itb.walker 8726 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 1072816 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1671866 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2860355 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 106947 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.itb.walker 8726 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 1072816 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1671866 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2860355 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000486 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000688 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.015755 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026959 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.021092 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.910851 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.910851 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.461008 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.461008 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000486 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000688 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.015755 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.102281 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.065712 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000486 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000688 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.015755 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.102281 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.065712 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 87951.923077 # average ReadReq miss latency +system.cpu.l2cache.occ_percent::cpu.inst 0.048407 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.174427 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.989214 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 105856 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 7867 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 1029751 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 1333713 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 2477187 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 1597039 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 1597039 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 343 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 343 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 153883 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 153883 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.dtb.walker 105856 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.itb.walker 7867 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 1029751 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 1487596 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2631070 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.dtb.walker 105856 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.itb.walker 7867 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 1029751 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 1487596 # number of overall hits +system.cpu.l2cache.overall_hits::total 2631070 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 48 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 7 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 16802 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 36729 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 53586 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 3829 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 3829 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 133517 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 133517 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.dtb.walker 48 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.itb.walker 7 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 16802 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 170246 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 187103 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.dtb.walker 48 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.itb.walker 7 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.inst 16802 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 170246 # number of overall misses +system.cpu.l2cache.overall_misses::total 187103 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 3370500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 483000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 989785000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2361474498 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 3355112998 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 17665999 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 17665999 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6803302500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 6803302500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 3370500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 483000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 989785000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 9164776998 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 10158415498 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 3370500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 483000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 989785000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 9164776998 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 10158415498 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 105904 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 7874 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.inst 1046553 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 1370442 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 2530773 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 1597039 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 1597039 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 4172 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 4172 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 287400 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 287400 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.dtb.walker 105904 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.itb.walker 7874 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 1046553 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1657842 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2818173 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.dtb.walker 105904 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.itb.walker 7874 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 1046553 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1657842 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2818173 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000453 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000889 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016055 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026801 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.021174 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.917785 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.917785 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.464569 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.464569 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000453 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000889 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016055 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.102691 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.066392 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000453 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000889 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016055 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.102691 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.066392 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 70218.750000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 69000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 59401.875518 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 64594.198813 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 62998.219918 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 4765.519855 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 4765.519855 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 51072.755684 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 51072.755684 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 87951.923077 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 58908.760862 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 64294.549212 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 62611.745568 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 4613.737007 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 4613.737007 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 50954.578818 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 50954.578818 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 70218.750000 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 69000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59401.875518 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 54018.295322 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 54512.271228 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 87951.923077 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 58908.760862 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 53832.554057 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 54293.172734 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 70218.750000 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 69000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59401.875518 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 54018.295322 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 54512.271228 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 58908.760862 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 53832.554057 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 54293.172734 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1089,99 +1089,99 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 103292 # number of writebacks -system.cpu.l2cache.writebacks::total 103292 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 3 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 2 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 5 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 3 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 2 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 5 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 3 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 2 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 5 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 52 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 6 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 16899 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 37249 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 54206 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 3576 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 3576 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133749 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 133749 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 52 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 6 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 16899 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 170998 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 187955 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 52 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 6 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 16899 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 170998 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 187955 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 3912097 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 336012 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 790231830 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1936968675 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2731448614 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 36681056 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 36681056 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5103303450 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5103303450 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 3912097 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 336012 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 790231830 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7040272125 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 7834752064 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 3912097 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 336012 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 790231830 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7040272125 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 7834752064 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 89187406500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 89187406500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2308380500 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2308380500 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 91495787000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 91495787000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000486 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000688 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.015752 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026958 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.021090 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.910851 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.910851 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.461008 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.461008 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000486 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000688 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.015752 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.102280 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.065710 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000486 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000688 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.015752 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.102280 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.065710 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 75232.634615 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 56002 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 46762.046867 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 52000.555048 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 50390.152640 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10257.565996 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10257.565996 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 38155.825090 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 38155.825090 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 75232.634615 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 56002 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 46762.046867 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 41171.663557 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 41684.190705 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 75232.634615 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 56002 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 46762.046867 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 41171.663557 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 41684.190705 # average overall mshr miss latency +system.cpu.l2cache.writebacks::writebacks 103003 # number of writebacks +system.cpu.l2cache.writebacks::total 103003 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 2 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 1 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 2 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 1 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 2 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 48 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 7 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 16801 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 36728 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 53584 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 3829 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 3829 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133517 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 133517 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 48 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 7 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 16801 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 170245 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 187101 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 48 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 7 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 16801 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 170245 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 187101 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 2762092 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 393014 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 777293164 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1899198022 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2679646292 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 39323307 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 39323307 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5078674654 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5078674654 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 2762092 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 393014 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 777293164 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6977872676 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 7758320946 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 2762092 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 393014 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 777293164 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6977872676 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 7758320946 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 89187395500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 89187395500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2308293000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2308293000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 91495688500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 91495688500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000453 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000889 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016054 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026800 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.021173 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.917785 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.917785 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.464569 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.464569 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000453 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000889 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016054 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.102691 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.066391 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000453 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000889 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016054 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.102691 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.066391 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 57543.583333 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 56144.857143 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 46264.696387 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 51709.813276 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 50008.328830 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10269.863411 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10269.863411 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 38037.663024 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 38037.663024 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 57543.583333 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 56144.857143 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 46264.696387 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40987.240013 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 41465.951256 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 57543.583333 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 56144.857143 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 46264.696387 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40987.240013 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 41465.951256 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/config.ini index 0e8616cf5..8c8aecb35 100644 --- a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/config.ini +++ b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/config.ini @@ -10,6 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a +clock=1000 init_param=0 kernel= load_addr_mask=1099511627775 @@ -29,7 +30,7 @@ system_port=system.membus.slave[0] [system.cpu] type=InOrderCPU -children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload +children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 RASSize=16 @@ -54,8 +55,6 @@ do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb fetchBuffSize=4 -functionTrace=false -functionTraceStart=0 function_trace=false function_trace_start=0 globalCtrBits=2 @@ -63,6 +62,7 @@ globalHistoryBits=13 globalPredictorSize=8192 instShiftAmt=2 interrupts=system.cpu.interrupts +isa=system.cpu.isa itb=system.cpu.itb localCtrBits=2 localHistoryBits=11 @@ -76,7 +76,6 @@ memBlockSize=64 multLatency=1 multRepeatRate=1 numThreads=1 -phase=0 predType=tournament profile=0 progress_interval=0 @@ -94,20 +93,22 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=2 is_top_level=true -latency=1000 max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=2 size=262144 subblock_size=0 system=system -tgts_per_mshr=5 +tgts_per_mshr=20 trace_addr=0 two_queue=false write_buffers=8 @@ -123,20 +124,22 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=2 is_top_level=true -latency=1000 max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=2 size=131072 subblock_size=0 system=system -tgts_per_mshr=5 +tgts_per_mshr=20 trace_addr=0 two_queue=false write_buffers=8 @@ -146,6 +149,9 @@ mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=AlphaInterrupts +[system.cpu.isa] +type=AlphaISA + [system.cpu.itb] type=AlphaTLB size=48 @@ -153,22 +159,24 @@ size=48 [system.cpu.l2cache] type=BaseCache addr_ranges=0:18446744073709551615 -assoc=2 +assoc=8 block_size=64 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=20 is_top_level=false -latency=10000 max_miss_count=0 -mshrs=10 +mshrs=20 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=20 size=2097152 subblock_size=0 system=system -tgts_per_mshr=5 +tgts_per_mshr=12 trace_addr=0 two_queue=false write_buffers=8 @@ -178,10 +186,10 @@ mem_side=system.membus.slave[1] [system.cpu.toL2Bus] type=CoherentBus block_size=64 -clock=1000 +clock=500 header_cycles=1 use_default_range=false -width=8 +width=32 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side @@ -191,12 +199,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 -cwd=build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/inorder-timing +cwd=build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/inorder-timing egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/alpha/tru64/gzip +executable=/projects/pd/randd/dist/cpu2000/binaries/alpha/tru64/gzip gid=100 input=cin max_stack_size=67108864 @@ -214,18 +222,32 @@ clock=1000 header_cycles=1 use_default_range=false width=8 -master=system.physmem.port[0] +master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] -type=SimpleMemory +type=SimpleDRAM +addr_mapping=openmap +banks_per_rank=8 +clock=1000 conf_table_reported=false -file= in_addr_map=true -latency=30000 -latency_var=0 +lines_per_rowbuffer=64 +mem_sched_policy=fcfs null=false +page_policy=open range=0:134217727 +ranks_per_channel=2 +read_buffer_size=32 +tBURST=4000 +tCL=14000 +tRCD=14000 +tREFI=7800000 +tRFC=300000 +tRP=14000 +tWTR=1000 +write_buffer_size=32 +write_thresh_perc=70 zero=false port=system.membus.master[0] diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/simout b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/simout index 282b60660..5289b243e 100755 --- a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/simout +++ b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 2 2012 08:30:56 -gem5 started Jul 2 2012 09:09:56 -gem5 executing on zizzer -command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/inorder-timing +gem5 compiled Oct 30 2012 11:02:14 +gem5 started Oct 30 2012 11:21:21 +gem5 executing on u200540-lin +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. @@ -39,4 +39,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 274137499500 because target called exit() +Exiting @ tick 269661304500 because target called exit() diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt index 01d17fd64..e8752c3e3 100644 --- a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.269731 # Number of seconds simulated -sim_ticks 269730745500 # Number of ticks simulated -final_tick 269730745500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.269661 # Number of seconds simulated +sim_ticks 269661304500 # Number of ticks simulated +final_tick 269661304500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 168515 # Simulator instruction rate (inst/s) -host_op_rate 168515 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 75522303 # Simulator tick rate (ticks/s) -host_mem_usage 218132 # Number of bytes of host memory used -host_seconds 3571.54 # Real time elapsed on the host +host_inst_rate 125304 # Simulator instruction rate (inst/s) +host_op_rate 125304 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 56142087 # Simulator tick rate (ticks/s) +host_mem_usage 214336 # Number of bytes of host memory used +host_seconds 4803.19 # Real time elapsed on the host sim_insts 601856964 # Number of instructions simulated sim_ops 601856964 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 53824 # Number of bytes read from this memory @@ -23,17 +23,17 @@ system.physmem.num_reads::cpu.data 25453 # Nu system.physmem.num_reads::total 26294 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 1014 # Number of write requests responded to by this memory system.physmem.num_writes::total 1014 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 199547 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 6039326 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 6238873 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 199547 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 199547 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 240595 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 240595 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 240595 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 199547 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 6039326 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6479469 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 199599 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 6040882 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 6240480 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 199599 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 199599 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 240657 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 240657 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 240657 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 199599 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 6040882 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6481138 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 26294 # Total number of read requests seen system.physmem.writeReqs 1014 # Total number of write requests seen system.physmem.cpureqs 27308 # Reqs generatd by CPU via cache - shady @@ -77,7 +77,7 @@ system.physmem.perBankWrReqs::14 74 # Tr system.physmem.perBankWrReqs::15 69 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 269730693500 # Total gap between requests +system.physmem.totGap 269661252500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -105,9 +105,9 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 17613 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 6143 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 1651 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 17608 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 6157 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 1642 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 868 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -138,7 +138,7 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 42 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 41 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 44 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 44 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 44 # What write queue length does an incoming req see @@ -161,7 +161,7 @@ system.physmem.wrQLenPdf::19 44 # Wh system.physmem.wrQLenPdf::20 44 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 44 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 44 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 4 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see @@ -171,14 +171,14 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 360576187 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 1020404187 # Sum of mem lat for all requests +system.physmem.totQLat 364261179 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 1024159179 # Sum of mem lat for all requests system.physmem.totBusLat 105120000 # Total cycles spent in databus access -system.physmem.totBankLat 554708000 # Total cycles spent in bank access -system.physmem.avgQLat 13720.56 # Average queueing delay per request -system.physmem.avgBankLat 21107.61 # Average bank access latency per request +system.physmem.totBankLat 554778000 # Total cycles spent in bank access +system.physmem.avgQLat 13860.78 # Average queueing delay per request +system.physmem.avgBankLat 21110.27 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 38828.17 # Average memory access latency +system.physmem.avgMemAccLat 38971.05 # Average memory access latency system.physmem.avgRdBW 6.24 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.24 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 6.24 # Average consumed read bandwidth in MB/s @@ -187,31 +187,31 @@ system.physmem.peakBW 16000.00 # Th system.physmem.busUtil 0.04 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time system.physmem.avgWrQLen 12.19 # Average write queue length over time -system.physmem.readRowHits 17405 # Number of row buffer hits during reads +system.physmem.readRowHits 17406 # Number of row buffer hits during reads system.physmem.writeRowHits 51 # Number of row buffer hits during writes system.physmem.readRowHitRate 66.23 # Row buffer hit rate for reads system.physmem.writeRowHitRate 5.03 # Row buffer hit rate for writes -system.physmem.avgGap 9877350.72 # Average gap between requests +system.physmem.avgGap 9874807.84 # Average gap between requests system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 114517567 # DTB read hits +system.cpu.dtb.read_hits 114517568 # DTB read hits system.cpu.dtb.read_misses 2631 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 114520198 # DTB read accesses -system.cpu.dtb.write_hits 39453373 # DTB write hits +system.cpu.dtb.read_accesses 114520199 # DTB read accesses +system.cpu.dtb.write_hits 39453362 # DTB write hits system.cpu.dtb.write_misses 2302 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 39455675 # DTB write accesses -system.cpu.dtb.data_hits 153970940 # DTB hits +system.cpu.dtb.write_accesses 39455664 # DTB write accesses +system.cpu.dtb.data_hits 153970930 # DTB hits system.cpu.dtb.data_misses 4933 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 153975873 # DTB accesses -system.cpu.itb.fetch_hits 25065868 # ITB hits +system.cpu.dtb.data_accesses 153975863 # DTB accesses +system.cpu.itb.fetch_hits 24997854 # ITB hits system.cpu.itb.fetch_misses 22 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 25065890 # ITB accesses +system.cpu.itb.fetch_accesses 24997876 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -225,42 +225,42 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 539461492 # number of cpu cycles simulated +system.cpu.numCycles 539322610 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.branch_predictor.lookups 86297721 # Number of BP lookups -system.cpu.branch_predictor.condPredicted 81352852 # Number of conditional branches predicted -system.cpu.branch_predictor.condIncorrect 36357676 # Number of conditional branches incorrect -system.cpu.branch_predictor.BTBLookups 52914836 # Number of BTB lookups -system.cpu.branch_predictor.BTBHits 34319624 # Number of BTB hits +system.cpu.branch_predictor.lookups 86405274 # Number of BP lookups +system.cpu.branch_predictor.condPredicted 81476244 # Number of conditional branches predicted +system.cpu.branch_predictor.condIncorrect 36343014 # Number of conditional branches incorrect +system.cpu.branch_predictor.BTBLookups 44773910 # Number of BTB lookups +system.cpu.branch_predictor.BTBHits 34660000 # Number of BTB hits system.cpu.branch_predictor.usedRAS 1197609 # Number of times the RAS was used to get a target. system.cpu.branch_predictor.RASInCorrect 6 # Number of incorrect RAS predictions. -system.cpu.branch_predictor.BTBHitPct 64.858226 # BTB Hit Percentage -system.cpu.branch_predictor.predictedTaken 36896934 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 49400787 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 541636673 # Number of Reads from Int. Register File +system.cpu.branch_predictor.BTBHitPct 77.411153 # BTB Hit Percentage +system.cpu.branch_predictor.predictedTaken 37224652 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 49180622 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 541063714 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 463854846 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 1005491519 # Total Accesses (Read+Write) to the Int. Register File -system.cpu.regfile_manager.floatRegFileReads 161 # Number of Reads from FP Register File +system.cpu.regfile_manager.intRegFileAccesses 1004918560 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.floatRegFileReads 162 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 42 # Number of Writes to FP Register File -system.cpu.regfile_manager.floatRegFileAccesses 203 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 254989713 # Number of Registers Read Through Forwarding Logic -system.cpu.agen_unit.agens 155053642 # Number of Address Generations -system.cpu.execution_unit.predictedTakenIncorrect 33759621 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.execution_unit.predictedNotTakenIncorrect 2593068 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.execution_unit.mispredicted 36352689 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.predicted 26195221 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.mispredictPct 58.119750 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.executions 412334808 # Number of Instructions Executed. +system.cpu.regfile_manager.floatRegFileAccesses 204 # Total Accesses (Read+Write) to the FP Register File +system.cpu.regfile_manager.regForwards 255160193 # Number of Registers Read Through Forwarding Logic +system.cpu.agen_unit.agens 154928367 # Number of Address Generations +system.cpu.execution_unit.predictedTakenIncorrect 34132403 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.execution_unit.predictedNotTakenIncorrect 2205624 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.execution_unit.mispredicted 36338027 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.predicted 26209890 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.mispredictPct 58.096302 # Percentage of Incorrect Branches Predicts +system.cpu.execution_unit.executions 412128439 # Number of Instructions Executed. system.cpu.mult_div_unit.multiplies 6482 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 535900413 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 535759910 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 295985 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 50743768 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 488717724 # Number of cycles cpu stages are processed. -system.cpu.activity 90.593626 # Percentage of cycles cpu is active +system.cpu.timesIdled 295987 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 50789311 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 488533299 # Number of cycles cpu stages are processed. +system.cpu.activity 90.582759 # Percentage of cycles cpu is active system.cpu.comLoads 114514042 # Number of Load instructions committed system.cpu.comStores 39451321 # Number of Store instructions committed system.cpu.comBranches 62547159 # Number of Branches instructions committed @@ -272,72 +272,72 @@ system.cpu.committedInsts 601856964 # Nu system.cpu.committedOps 601856964 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 601856964 # Number of Instructions committed (Total) -system.cpu.cpi 0.896328 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 0.896098 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 0.896328 # CPI: Total CPI of All Threads -system.cpu.ipc 1.115663 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 0.896098 # CPI: Total CPI of All Threads +system.cpu.ipc 1.115950 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 1.115663 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 200698192 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 338763300 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 62.796568 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 228822575 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 310638917 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 57.583149 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 197865765 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 341595727 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 63.321615 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 428073840 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 111387652 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 20.647934 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 192651610 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 346809882 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 64.288163 # Percentage of cycles stage was utilized (processing insts). +system.cpu.ipc_total 1.115950 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 200593326 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 338729284 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 62.806431 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 228903212 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 310419398 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 57.557275 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 197757745 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 341564865 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 63.332198 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 427944093 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 111378517 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 20.651557 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 192521650 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 346800960 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 64.303063 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 30 # number of replacements -system.cpu.icache.tagsinuse 729.083311 # Cycle average of tags in use -system.cpu.icache.total_refs 25064833 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 729.842734 # Cycle average of tags in use +system.cpu.icache.total_refs 24996820 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 855 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 29315.594152 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 29236.046784 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 729.083311 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.355998 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.355998 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 25064833 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 25064833 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 25064833 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 25064833 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 25064833 # number of overall hits -system.cpu.icache.overall_hits::total 25064833 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1035 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1035 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1035 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1035 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1035 # number of overall misses -system.cpu.icache.overall_misses::total 1035 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 52854000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 52854000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 52854000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 52854000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 52854000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 52854000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 25065868 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 25065868 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 25065868 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 25065868 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 25065868 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 25065868 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 729.842734 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.356369 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.356369 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 24996820 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 24996820 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 24996820 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 24996820 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 24996820 # number of overall hits +system.cpu.icache.overall_hits::total 24996820 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1034 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1034 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1034 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1034 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1034 # number of overall misses +system.cpu.icache.overall_misses::total 1034 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 53126500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 53126500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 53126500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 53126500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 53126500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 53126500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 24997854 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 24997854 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 24997854 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 24997854 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 24997854 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 24997854 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000041 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000041 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000041 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000041 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000041 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000041 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 51066.666667 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 51066.666667 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 51066.666667 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 51066.666667 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 51066.666667 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 51066.666667 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 51379.593810 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 51379.593810 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 51379.593810 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 51379.593810 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 51379.593810 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 51379.593810 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 187 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked @@ -346,158 +346,50 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 93.500000 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 180 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 180 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 180 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 180 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 180 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 180 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 179 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 179 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 179 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 179 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 179 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 179 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 855 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 855 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 855 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 855 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 855 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 855 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 43286500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 43286500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 43286500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 43286500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 43286500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 43286500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 43645500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 43645500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 43645500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 43645500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 43645500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 43645500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000034 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000034 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000034 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50627.485380 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50627.485380 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50627.485380 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 50627.485380 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50627.485380 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 50627.485380 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51047.368421 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51047.368421 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51047.368421 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 51047.368421 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51047.368421 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 51047.368421 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 451299 # number of replacements -system.cpu.dcache.tagsinuse 4093.419858 # Cycle average of tags in use -system.cpu.dcache.total_refs 151786041 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 455395 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 333.306341 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 334129000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4093.419858 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999370 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999370 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 114120628 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 114120628 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 37665413 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 37665413 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 151786041 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 151786041 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 151786041 # number of overall hits -system.cpu.dcache.overall_hits::total 151786041 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 393414 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 393414 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1785908 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1785908 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2179322 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2179322 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2179322 # number of overall misses -system.cpu.dcache.overall_misses::total 2179322 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5991589500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5991589500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 22875440000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 22875440000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 28867029500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 28867029500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 28867029500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 28867029500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 114514042 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 114514042 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 39451321 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 39451321 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 153965363 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 153965363 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 153965363 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 153965363 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003436 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.003436 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.045269 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.045269 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.014155 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.014155 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.014155 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.014155 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15229.731275 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 15229.731275 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 12808.856895 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 12808.856895 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 13245.876240 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 13245.876240 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 13245.876240 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 13245.876240 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 165761 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 544 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 5600 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 9 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 29.600179 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 60.444444 # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 436887 # number of writebacks -system.cpu.dcache.writebacks::total 436887 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 192182 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 192182 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1531745 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1531745 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1723927 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1723927 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1723927 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1723927 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 201232 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 201232 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 254163 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 254163 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 455395 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 455395 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 455395 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 455395 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2645854500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2645854500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3731128500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3731128500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6376983000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6376983000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6376983000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6376983000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001757 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001757 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006442 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006442 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002958 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.002958 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002958 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.002958 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13148.279101 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13148.279101 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14680.061614 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14680.061614 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14003.190637 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 14003.190637 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14003.190637 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 14003.190637 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 1042 # number of replacements -system.cpu.l2cache.tagsinuse 22878.552216 # Cycle average of tags in use -system.cpu.l2cache.total_refs 531848 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 22879.132168 # Cycle average of tags in use +system.cpu.l2cache.total_refs 531830 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 23279 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 22.846686 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 22.845913 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 21684.756059 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 718.203653 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 475.592503 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.661766 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.021918 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.014514 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.698198 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::writebacks 21684.623478 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 718.963213 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 475.545477 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.661762 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.021941 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.014512 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.698216 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 14 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 197082 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 197096 # number of ReadReq hits @@ -522,17 +414,17 @@ system.cpu.l2cache.demand_misses::total 26294 # nu system.cpu.l2cache.overall_misses::cpu.inst 841 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 25453 # number of overall misses system.cpu.l2cache.overall_misses::total 26294 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 42280500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 472681500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 514962000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1146890000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1146890000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 42280500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 1619571500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 1661852000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 42280500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 1619571500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 1661852000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 42639500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 472401500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 515041000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1150527000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1150527000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 42639500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 1622928500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 1665568000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 42639500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 1622928500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 1665568000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 855 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 201207 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 202062 # number of ReadReq accesses(hits+misses) @@ -557,17 +449,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.057631 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.983626 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.055892 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.057631 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50274.078478 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 114589.454545 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 103697.543294 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 53773.912228 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 53773.912228 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50274.078478 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 63629.886457 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 63202.707842 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50274.078478 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 63629.886457 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 63202.707842 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50700.951249 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 114521.575758 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 103713.451470 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 53944.439235 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 53944.439235 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50700.951249 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 63761.776608 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 63344.032859 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50700.951249 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 63761.776608 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 63344.032859 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -589,17 +481,17 @@ system.cpu.l2cache.demand_mshr_misses::total 26294 system.cpu.l2cache.overall_mshr_misses::cpu.inst 841 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 25453 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 26294 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 31666859 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 419253922 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 450920781 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 877062534 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 877062534 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 31666859 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1296316456 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 1327983315 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 31666859 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1296316456 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 1327983315 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 32024355 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 418973423 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 450997778 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 880714009 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 880714009 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 32024355 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1299687432 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 1331711787 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 32024355 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1299687432 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 1331711787 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.983626 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.020501 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.024577 # mshr miss rate for ReadReq accesses @@ -611,17 +503,125 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.057631 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.983626 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.055892 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.057631 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37653.815696 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 101637.314424 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 90801.607128 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 41122.586928 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 41122.586928 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37653.815696 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50929.810081 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50505.184263 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37653.815696 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50929.810081 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50505.184263 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38078.900119 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 101569.314667 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 90817.111961 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 41293.792620 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 41293.792620 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38078.900119 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 51062.249322 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50646.983608 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38078.900119 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 51062.249322 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50646.983608 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.replacements 451299 # number of replacements +system.cpu.dcache.tagsinuse 4093.419207 # Cycle average of tags in use +system.cpu.dcache.total_refs 151786016 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 455395 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 333.306286 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 334129000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4093.419207 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999370 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999370 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 114120628 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 114120628 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 37665388 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 37665388 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 151786016 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 151786016 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 151786016 # number of overall hits +system.cpu.dcache.overall_hits::total 151786016 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 393414 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 393414 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1785933 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1785933 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2179347 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2179347 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2179347 # number of overall misses +system.cpu.dcache.overall_misses::total 2179347 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5991137000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5991137000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 22893915500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 22893915500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 28885052500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 28885052500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 28885052500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 28885052500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 114514042 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 114514042 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 39451321 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 39451321 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 153965363 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 153965363 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 153965363 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 153965363 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003436 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.003436 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.045269 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.045269 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.014155 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.014155 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.014155 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.014155 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15228.581088 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 15228.581088 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 12819.022606 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 12819.022606 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 13253.994201 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 13253.994201 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 13253.994201 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 13253.994201 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 167214 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 552 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 5590 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 9 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 29.913059 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 61.333333 # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 436887 # number of writebacks +system.cpu.dcache.writebacks::total 436887 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 192182 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 192182 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1531770 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1531770 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1723952 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1723952 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1723952 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1723952 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 201232 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 201232 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 254163 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 254163 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 455395 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 455395 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 455395 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 455395 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2645576500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2645576500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3734758000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3734758000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6380334500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6380334500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6380334500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6380334500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001757 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001757 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006442 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006442 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002958 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.002958 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002958 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.002958 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13146.897611 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13146.897611 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14694.341820 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14694.341820 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14010.550182 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 14010.550182 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14010.550182 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 14010.550182 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/config.ini index 5bc85930f..ba863cc04 100644 --- a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/config.ini @@ -10,6 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a +clock=1000 init_param=0 kernel= load_addr_mask=1099511627775 @@ -29,7 +30,7 @@ system_port=system.membus.slave[0] [system.cpu] type=DerivO3CPU -children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload +children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -77,6 +78,7 @@ iewToFetchDelay=1 iewToRenameDelay=1 instShiftAmt=2 interrupts=system.cpu.interrupts +isa=system.cpu.isa issueToExecuteDelay=1 issueWidth=8 itb=system.cpu.itb @@ -95,7 +97,6 @@ numPhysIntRegs=256 numROBEntries=192 numRobs=1 numThreads=1 -phase=0 predType=tournament profile=0 progress_interval=0 @@ -129,16 +130,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=2 is_top_level=true -latency=1000 max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=2 size=262144 subblock_size=0 system=system @@ -421,16 +424,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=2 is_top_level=true -latency=1000 max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=2 size=131072 subblock_size=0 system=system @@ -444,6 +449,9 @@ mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=AlphaInterrupts +[system.cpu.isa] +type=AlphaISA + [system.cpu.itb] type=AlphaTLB size=48 @@ -451,22 +459,24 @@ size=48 [system.cpu.l2cache] type=BaseCache addr_ranges=0:18446744073709551615 -assoc=2 +assoc=8 block_size=64 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=20 is_top_level=false -latency=1000 max_miss_count=0 -mshrs=10 +mshrs=20 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=20 size=2097152 subblock_size=0 system=system -tgts_per_mshr=5 +tgts_per_mshr=12 trace_addr=0 two_queue=false write_buffers=8 @@ -476,10 +486,10 @@ mem_side=system.membus.slave[1] [system.cpu.toL2Bus] type=CoherentBus block_size=64 -clock=1000 +clock=500 header_cycles=1 use_default_range=false -width=8 +width=32 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side @@ -489,12 +499,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 -cwd=build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/o3-timing +cwd=build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/o3-timing egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/alpha/tru64/gzip +executable=/projects/pd/randd/dist/cpu2000/binaries/alpha/tru64/gzip gid=100 input=cin max_stack_size=67108864 @@ -512,18 +522,32 @@ clock=1000 header_cycles=1 use_default_range=false width=8 -master=system.physmem.port[0] +master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] -type=SimpleMemory +type=SimpleDRAM +addr_mapping=openmap +banks_per_rank=8 +clock=1000 conf_table_reported=false -file= in_addr_map=true -latency=30000 -latency_var=0 +lines_per_rowbuffer=64 +mem_sched_policy=fcfs null=false +page_policy=open range=0:134217727 +ranks_per_channel=2 +read_buffer_size=32 +tBURST=4000 +tCL=14000 +tRCD=14000 +tREFI=7800000 +tRFC=300000 +tRP=14000 +tWTR=1000 +write_buffer_size=32 +write_thresh_perc=70 zero=false port=system.membus.master[0] diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/simout b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/simout index ddf76222f..396a60755 100755 --- a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 2 2012 08:30:56 -gem5 started Jul 2 2012 09:10:10 -gem5 executing on zizzer -command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/o3-timing +gem5 compiled Oct 30 2012 11:02:14 +gem5 started Oct 30 2012 11:21:56 +gem5 executing on u200540-lin +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. @@ -39,4 +39,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 135504709500 because target called exit() +Exiting @ tick 133778696500 because target called exit() diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt index 82eaca8c6..759350e06 100644 --- a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt @@ -1,63 +1,63 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.135739 # Number of seconds simulated -sim_ticks 135738546500 # Number of ticks simulated -final_tick 135738546500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.133779 # Number of seconds simulated +sim_ticks 133778696500 # Number of ticks simulated +final_tick 133778696500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 149707 # Simulator instruction rate (inst/s) -host_op_rate 149707 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 35931284 # Simulator tick rate (ticks/s) -host_mem_usage 219152 # Number of bytes of host memory used -host_seconds 3777.73 # Real time elapsed on the host +host_inst_rate 208111 # Simulator instruction rate (inst/s) +host_op_rate 208111 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 49227708 # Simulator tick rate (ticks/s) +host_mem_usage 215496 # Number of bytes of host memory used +host_seconds 2717.55 # Real time elapsed on the host sim_insts 565552443 # Number of instructions simulated sim_ops 565552443 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 61632 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1636160 # Number of bytes read from this memory -system.physmem.bytes_read::total 1697792 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 61632 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 61632 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 67072 # Number of bytes written to this memory -system.physmem.bytes_written::total 67072 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 963 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 25565 # Number of read requests responded to by this memory -system.physmem.num_reads::total 26528 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1048 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1048 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 454049 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 12053761 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 12507810 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 454049 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 454049 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 494126 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 494126 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 494126 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 454049 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 12053761 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 13001937 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 26528 # Total number of read requests seen -system.physmem.writeReqs 1048 # Total number of write requests seen -system.physmem.cpureqs 27576 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 1697792 # Total number of bytes read from memory -system.physmem.bytesWritten 67072 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 1697792 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 67072 # bytesWritten derated as per pkt->getSize() +system.physmem.bytes_read::cpu.inst 60864 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1636416 # Number of bytes read from this memory +system.physmem.bytes_read::total 1697280 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 60864 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 60864 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 67008 # Number of bytes written to this memory +system.physmem.bytes_written::total 67008 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 951 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 25569 # Number of read requests responded to by this memory +system.physmem.num_reads::total 26520 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1047 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1047 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 454960 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 12232262 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 12687222 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 454960 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 454960 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 500887 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 500887 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 500887 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 454960 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 12232262 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 13188109 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 26520 # Total number of read requests seen +system.physmem.writeReqs 1047 # Total number of write requests seen +system.physmem.cpureqs 27567 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 1697280 # Total number of bytes read from memory +system.physmem.bytesWritten 67008 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 1697280 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 67008 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 15 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed system.physmem.perBankRdReqs::0 1724 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 1737 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 1613 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 1736 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 1612 # Track reads on a per bank basis system.physmem.perBankRdReqs::3 1636 # Track reads on a per bank basis system.physmem.perBankRdReqs::4 1721 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 1640 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 1683 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 1642 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 1685 # Track reads on a per bank basis system.physmem.perBankRdReqs::7 1681 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 1569 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 1630 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 1617 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 1568 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 1629 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 1615 # Track reads on a per bank basis system.physmem.perBankRdReqs::11 1555 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 1665 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 1653 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 1711 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 1668 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 1651 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 1704 # Track reads on a per bank basis system.physmem.perBankRdReqs::15 1678 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 66 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 78 # Track writes on a per bank basis @@ -65,26 +65,26 @@ system.physmem.perBankWrReqs::2 55 # Tr system.physmem.perBankWrReqs::3 60 # Track writes on a per bank basis system.physmem.perBankWrReqs::4 75 # Track writes on a per bank basis system.physmem.perBankWrReqs::5 62 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 78 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 83 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 79 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 84 # Track writes on a per bank basis system.physmem.perBankWrReqs::8 54 # Track writes on a per bank basis system.physmem.perBankWrReqs::9 56 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 59 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 57 # Track writes on a per bank basis system.physmem.perBankWrReqs::11 48 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 63 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 64 # Track writes on a per bank basis system.physmem.perBankWrReqs::13 62 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 80 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 78 # Track writes on a per bank basis system.physmem.perBankWrReqs::15 69 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 135738512500 # Total gap between requests +system.physmem.totGap 133778628000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 26528 # Categorize read packet sizes +system.physmem.readPktSize::6 26520 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -93,7 +93,7 @@ system.physmem.writePktSize::2 0 # ca system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 1048 # categorize write packet sizes +system.physmem.writePktSize::6 1047 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -105,12 +105,12 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 10104 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 10480 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 4915 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 10090 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 10502 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 4903 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1000 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 12 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 10 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -150,7 +150,7 @@ system.physmem.wrQLenPdf::8 46 # Wh system.physmem.wrQLenPdf::9 46 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 46 # What write queue length does an incoming req see system.physmem.wrQLenPdf::11 46 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 46 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 45 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 45 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 45 # What write queue length does an incoming req see system.physmem.wrQLenPdf::15 45 # What write queue length does an incoming req see @@ -171,47 +171,47 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 656768415 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 1272742415 # Sum of mem lat for all requests -system.physmem.totBusLat 106052000 # Total cycles spent in databus access -system.physmem.totBankLat 509922000 # Total cycles spent in bank access -system.physmem.avgQLat 24771.56 # Average queueing delay per request -system.physmem.avgBankLat 19232.90 # Average bank access latency per request +system.physmem.totQLat 650833420 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 1266537420 # Sum of mem lat for all requests +system.physmem.totBusLat 106020000 # Total cycles spent in databus access +system.physmem.totBankLat 509684000 # Total cycles spent in bank access +system.physmem.avgQLat 24555.12 # Average queueing delay per request +system.physmem.avgBankLat 19229.73 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 48004.47 # Average memory access latency -system.physmem.avgRdBW 12.51 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 0.49 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 12.51 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 0.49 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 47784.85 # Average memory access latency +system.physmem.avgRdBW 12.69 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 0.50 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 12.69 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 0.50 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.08 # Data bus utilization in percentage system.physmem.avgRdQLen 0.01 # Average read queue length over time -system.physmem.avgWrQLen 10.03 # Average write queue length over time -system.physmem.readRowHits 18053 # Number of row buffer hits during reads -system.physmem.writeRowHits 56 # Number of row buffer hits during writes -system.physmem.readRowHitRate 68.09 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 5.34 # Row buffer hit rate for writes -system.physmem.avgGap 4922342.34 # Average gap between requests +system.physmem.avgWrQLen 10.37 # Average write queue length over time +system.physmem.readRowHits 18044 # Number of row buffer hits during reads +system.physmem.writeRowHits 53 # Number of row buffer hits during writes +system.physmem.readRowHitRate 68.08 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 5.06 # Row buffer hit rate for writes +system.physmem.avgGap 4852854.06 # Average gap between requests system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 123922794 # DTB read hits -system.cpu.dtb.read_misses 28366 # DTB read misses +system.cpu.dtb.read_hits 122603551 # DTB read hits +system.cpu.dtb.read_misses 28565 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 123951160 # DTB read accesses -system.cpu.dtb.write_hits 40833980 # DTB write hits -system.cpu.dtb.write_misses 25612 # DTB write misses +system.cpu.dtb.read_accesses 122632116 # DTB read accesses +system.cpu.dtb.write_hits 40753368 # DTB write hits +system.cpu.dtb.write_misses 25574 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 40859592 # DTB write accesses -system.cpu.dtb.data_hits 164756774 # DTB hits -system.cpu.dtb.data_misses 53978 # DTB misses +system.cpu.dtb.write_accesses 40778942 # DTB write accesses +system.cpu.dtb.data_hits 163356919 # DTB hits +system.cpu.dtb.data_misses 54139 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 164810752 # DTB accesses -system.cpu.itb.fetch_hits 66580671 # ITB hits -system.cpu.itb.fetch_misses 40 # ITB misses +system.cpu.dtb.data_accesses 163411058 # DTB accesses +system.cpu.itb.fetch_hits 65475592 # ITB hits +system.cpu.itb.fetch_misses 42 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 66580711 # ITB accesses +system.cpu.itb.fetch_accesses 65475634 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -225,246 +225,246 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 271477094 # number of cpu cycles simulated +system.cpu.numCycles 267557394 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 78553522 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 72909571 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 3050106 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 42863354 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 41672348 # Number of BTB hits +system.cpu.BPredUnit.lookups 76440222 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 70864810 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 2706098 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 43060392 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 41933015 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1629524 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 245 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 68542455 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 711581178 # Number of instructions fetch has processed -system.cpu.fetch.Branches 78553522 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 43301872 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 119313775 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 13045820 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 73380337 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 247 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1305 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 7 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 66580671 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 946763 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 271202747 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.623798 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.454049 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1604413 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 232 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 67119409 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 699052842 # Number of instructions fetch has processed +system.cpu.fetch.Branches 76440222 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 43537428 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 117782486 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 11617306 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 73490715 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 32 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1303 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 34 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 65475592 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 928038 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 267274328 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.615488 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.444547 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 151888972 56.01% 56.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 10373570 3.83% 59.83% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 11841110 4.37% 64.20% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 10622549 3.92% 68.11% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 7004922 2.58% 70.70% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 2671761 0.99% 71.68% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 3503178 1.29% 72.97% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 3113300 1.15% 74.12% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 70183385 25.88% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 149491842 55.93% 55.93% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 10342090 3.87% 59.80% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 11847639 4.43% 64.23% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 10563390 3.95% 68.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 7011808 2.62% 70.81% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 2869024 1.07% 71.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 3576964 1.34% 73.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 3101400 1.16% 74.38% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 68470171 25.62% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 271202747 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.289356 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.621146 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 86023061 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 57429003 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 104152322 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 13634796 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 9963565 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3909126 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 1128 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 702760367 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 4141 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 9963565 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 94304341 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 12784998 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 1531 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 104174044 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 49974268 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 690768624 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 416 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 38037873 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 5669894 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 527681051 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 907529781 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 907526811 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 2970 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 267274328 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.285697 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.612721 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 84240613 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 57793701 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 102635866 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 13724657 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 8879491 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3873839 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 920 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 691093913 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 3105 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 8879491 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 92211740 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 12790279 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 1241 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 103054645 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 50336932 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 680961604 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 408 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 38688874 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 5430085 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 520709674 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 896990234 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 896987596 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 2638 # Number of floating rename lookups system.cpu.rename.CommittedMaps 463854889 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 63826162 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 100 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 107 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 112138467 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 129142032 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 42466663 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 14842304 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 10368291 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 626932339 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 92 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 608621790 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 344229 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 60678365 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 33855512 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 75 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 271202747 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.244158 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.828491 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 56854785 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 64 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 69 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 112289485 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 126970724 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 42377686 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 14852387 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 10147583 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 621083354 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 56 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 604563100 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 299815 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 54897951 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 29938787 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 39 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 267274328 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.261957 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.823661 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 55518105 20.47% 20.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 55264401 20.38% 40.85% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 53914091 19.88% 60.73% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 37013789 13.65% 74.38% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 31720099 11.70% 86.07% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 23689667 8.74% 94.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 10003906 3.69% 98.50% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 3493839 1.29% 99.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 584850 0.22% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 52499760 19.64% 19.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 55875325 20.91% 40.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 53442699 20.00% 60.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 36269586 13.57% 74.11% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 31423380 11.76% 85.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 23799839 8.90% 94.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 9996979 3.74% 98.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 3415050 1.28% 99.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 551710 0.21% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 271202747 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 267274328 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 2803923 71.85% 71.85% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 36 0.00% 71.85% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 71.85% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 71.85% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 71.85% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 71.85% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 71.85% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 71.85% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 71.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 71.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 71.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 71.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 71.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 71.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 71.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 71.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 71.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 71.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 71.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 71.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 71.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 71.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 71.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 71.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 71.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 71.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 71.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 71.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 71.85% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 717323 18.38% 90.23% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 381401 9.77% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 2734710 70.93% 70.93% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 35 0.00% 70.93% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 70.93% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 70.93% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 70.93% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 70.93% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 70.93% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 70.93% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 70.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 70.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 70.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 70.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 70.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 70.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 70.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 70.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 70.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 70.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 70.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 70.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 70.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 70.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 70.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 70.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 70.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 70.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 70.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 70.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 70.93% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 729519 18.92% 89.85% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 391400 10.15% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 441148473 72.48% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 7331 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 29 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 5 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 5 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 4 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 126212456 20.74% 93.22% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 41253487 6.78% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 439055623 72.62% 72.62% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 7072 0.00% 72.62% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 72.62% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 32 0.00% 72.62% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 6 0.00% 72.62% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 5 0.00% 72.62% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 5 0.00% 72.62% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 72.62% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 72.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 72.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 72.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 72.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 72.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 72.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 72.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 72.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 72.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 72.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 72.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 72.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 72.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 72.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 72.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 72.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 72.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 72.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 72.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 72.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 72.62% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 124323040 20.56% 93.19% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 41177317 6.81% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 608621790 # Type of FU issued -system.cpu.iq.rate 2.241890 # Inst issue rate -system.cpu.iq.fu_busy_cnt 3902683 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.006412 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1492689315 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 687613743 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 598990581 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 3924 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 2505 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 1722 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 612522503 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 1970 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 12211500 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 604563100 # Type of FU issued +system.cpu.iq.rate 2.259564 # Inst issue rate +system.cpu.iq.fu_busy_cnt 3855664 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.006378 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1480552206 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 675984537 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 596489873 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 3801 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 2284 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 1738 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 608416848 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 1916 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 12282855 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 14627990 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 32965 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 5519 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 3015342 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 12456682 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 35904 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 5518 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2926365 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 6777 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 53391 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 6461 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 52889 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 9963565 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1456092 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 187737 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 670933978 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 1716868 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 129142032 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 42466663 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 92 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 140012 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 7404 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 5519 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1345446 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 2210203 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 3555649 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 602801961 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 123951309 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 5819829 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 8879491 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1456554 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 192142 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 663913486 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 1691538 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 126970724 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 42377686 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 56 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 144242 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 7408 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 5518 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1333964 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1804152 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 3138116 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 599464075 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 122632263 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 5099025 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 44001547 # number of nop insts executed -system.cpu.iew.exec_refs 164826908 # number of memory reference insts executed -system.cpu.iew.exec_branches 67037045 # Number of branches executed -system.cpu.iew.exec_stores 40875599 # Number of stores executed -system.cpu.iew.exec_rate 2.220452 # Inst execution rate -system.cpu.iew.wb_sent 600240253 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 598992303 # cumulative count of insts written-back -system.cpu.iew.wb_producers 417488059 # num instructions producing a value -system.cpu.iew.wb_consumers 532706701 # num instructions consuming a value +system.cpu.iew.exec_nop 42830076 # number of nop insts executed +system.cpu.iew.exec_refs 163429760 # number of memory reference insts executed +system.cpu.iew.exec_branches 66623337 # Number of branches executed +system.cpu.iew.exec_stores 40797497 # Number of stores executed +system.cpu.iew.exec_rate 2.240506 # Inst execution rate +system.cpu.iew.wb_sent 597426155 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 596491611 # cumulative count of insts written-back +system.cpu.iew.wb_producers 415927297 # num instructions producing a value +system.cpu.iew.wb_consumers 530215795 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.206419 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.783711 # average fanout of values written-back +system.cpu.iew.wb_rate 2.229397 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.784449 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 68955725 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 61932723 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 3049050 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 261239182 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.303854 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.691353 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 2705240 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 258394837 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.329214 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.691172 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 82351408 31.52% 31.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 72672063 27.82% 59.34% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 25867656 9.90% 69.24% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 8932880 3.42% 72.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 10297113 3.94% 76.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 20861196 7.99% 84.59% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 6530231 2.50% 87.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3837950 1.47% 88.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 29888685 11.44% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 79550578 30.79% 30.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 72525012 28.07% 58.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 25515345 9.87% 68.73% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 9289171 3.59% 72.32% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 10288497 3.98% 76.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 21029047 8.14% 84.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 6874256 2.66% 87.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3694459 1.43% 88.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 29628472 11.47% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 261239182 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 258394837 # Number of insts commited each cycle system.cpu.commit.committedInsts 601856963 # Number of instructions committed system.cpu.commit.committedOps 601856963 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -475,368 +475,368 @@ system.cpu.commit.branches 62547159 # Nu system.cpu.commit.fp_insts 1520 # Number of committed floating point instructions. system.cpu.commit.int_insts 563954763 # Number of committed integer instructions. system.cpu.commit.function_calls 1197610 # Number of function calls committed. -system.cpu.commit.bw_lim_events 29888685 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 29628472 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 902098796 # The number of ROB reads -system.cpu.rob.rob_writes 1351611788 # The number of ROB writes -system.cpu.timesIdled 34221 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 274347 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 892491662 # The number of ROB reads +system.cpu.rob.rob_writes 1336472901 # The number of ROB writes +system.cpu.timesIdled 34286 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 283066 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 565552443 # Number of Instructions Simulated system.cpu.committedOps 565552443 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 565552443 # Number of Instructions Simulated -system.cpu.cpi 0.480021 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.480021 # CPI: Total CPI of All Threads -system.cpu.ipc 2.083242 # IPC: Instructions Per Cycle -system.cpu.ipc_total 2.083242 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 848885274 # number of integer regfile reads -system.cpu.int_regfile_writes 492863541 # number of integer regfile writes -system.cpu.fp_regfile_reads 396 # number of floating regfile reads -system.cpu.fp_regfile_writes 49 # number of floating regfile writes +system.cpu.cpi 0.473090 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.473090 # CPI: Total CPI of All Threads +system.cpu.ipc 2.113761 # IPC: Instructions Per Cycle +system.cpu.ipc_total 2.113761 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 844970192 # number of integer regfile reads +system.cpu.int_regfile_writes 490533624 # number of integer regfile writes +system.cpu.fp_regfile_reads 397 # number of floating regfile reads +system.cpu.fp_regfile_writes 54 # number of floating regfile writes system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.icache.replacements 43 # number of replacements -system.cpu.icache.tagsinuse 832.109405 # Cycle average of tags in use -system.cpu.icache.total_refs 66579220 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 984 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 67661.808943 # Average number of references to valid blocks. +system.cpu.icache.replacements 36 # number of replacements +system.cpu.icache.tagsinuse 825.012562 # Cycle average of tags in use +system.cpu.icache.total_refs 65474211 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 965 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 67848.923316 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 832.109405 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.406303 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.406303 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 66579220 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 66579220 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 66579220 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 66579220 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 66579220 # number of overall hits -system.cpu.icache.overall_hits::total 66579220 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1449 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1449 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1449 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1449 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1449 # number of overall misses -system.cpu.icache.overall_misses::total 1449 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 74643000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 74643000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 74643000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 74643000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 74643000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 74643000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 66580669 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 66580669 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 66580669 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 66580669 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 66580669 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 66580669 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000022 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000022 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000022 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000022 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000022 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000022 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 51513.457557 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 51513.457557 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 51513.457557 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 51513.457557 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 51513.457557 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 51513.457557 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 293 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 825.012562 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.402838 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.402838 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 65474211 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 65474211 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 65474211 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 65474211 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 65474211 # number of overall hits +system.cpu.icache.overall_hits::total 65474211 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1381 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1381 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1381 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1381 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1381 # number of overall misses +system.cpu.icache.overall_misses::total 1381 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 68875500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 68875500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 68875500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 68875500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 68875500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 68875500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 65475592 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 65475592 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 65475592 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 65475592 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 65475592 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 65475592 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000021 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000021 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000021 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000021 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000021 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000021 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49873.642288 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 49873.642288 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 49873.642288 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 49873.642288 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 49873.642288 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 49873.642288 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 127 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 4 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 73.250000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 31.750000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 465 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 465 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 465 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 465 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 465 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 465 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 984 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 984 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 984 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 984 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 984 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 984 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 52158000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 52158000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 52158000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 52158000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 52158000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 52158000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 416 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 416 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 416 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 416 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 416 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 416 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 965 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 965 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 965 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 965 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 965 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 965 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 50216500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 50216500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 50216500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 50216500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 50216500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 50216500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000015 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000015 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000015 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000015 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000015 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000015 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53006.097561 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53006.097561 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53006.097561 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 53006.097561 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53006.097561 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 53006.097561 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52037.823834 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52037.823834 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52037.823834 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 52037.823834 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52037.823834 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 52037.823834 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 460800 # number of replacements -system.cpu.dcache.tagsinuse 4090.940281 # Cycle average of tags in use -system.cpu.dcache.total_refs 148282429 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 464896 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 318.958281 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 305241000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4090.940281 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.998765 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.998765 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 110633165 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 110633165 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 37649215 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 37649215 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 49 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 49 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 148282380 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 148282380 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 148282380 # number of overall hits -system.cpu.dcache.overall_hits::total 148282380 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1026018 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1026018 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1802106 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1802106 # number of WriteReq misses +system.cpu.l2cache.replacements 1079 # number of replacements +system.cpu.l2cache.tagsinuse 22916.104559 # Cycle average of tags in use +system.cpu.l2cache.total_refs 547186 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 23511 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 23.273617 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::writebacks 21469.480813 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 814.509586 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 632.114161 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.655197 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.024857 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.019291 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.699344 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 14 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 206252 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 206266 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 445099 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 445099 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 233316 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 233316 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 14 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 439568 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 439582 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 14 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 439568 # number of overall hits +system.cpu.l2cache.overall_hits::total 439582 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 951 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 4308 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 5259 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 21261 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 21261 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 951 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 25569 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 26520 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 951 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 25569 # number of overall misses +system.cpu.l2cache.overall_misses::total 26520 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 49100500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 424904500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 474005000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1450819500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1450819500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 49100500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 1875724000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 1924824500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 49100500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 1875724000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 1924824500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 965 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 210560 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 211525 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 445099 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 445099 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 254577 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 254577 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 965 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 465137 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 466102 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 965 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 465137 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 466102 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.985492 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.020460 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.024862 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.083515 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.083515 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.985492 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.054971 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.056897 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.985492 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.054971 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.056897 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 51630.389064 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 98631.499536 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 90132.154402 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 68238.535346 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68238.535346 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 51630.389064 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73359.302280 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 72580.109351 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 51630.389064 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73359.302280 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 72580.109351 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.writebacks::writebacks 1047 # number of writebacks +system.cpu.l2cache.writebacks::total 1047 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 951 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 4308 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 5259 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 21261 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 21261 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 951 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 25569 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 26520 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 951 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 25569 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 26520 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 37144486 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 369346804 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 406491290 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1184806153 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1184806153 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 37144486 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1554152957 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 1591297443 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 37144486 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1554152957 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 1591297443 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.985492 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.020460 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.024862 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.083515 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.083515 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.985492 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.054971 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.056897 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.985492 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.054971 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.056897 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39058.344900 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 85735.098422 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 77294.407682 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 55726.736889 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55726.736889 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39058.344900 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60782.703938 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60003.674321 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39058.344900 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60782.703938 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60003.674321 # average overall mshr miss latency +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.replacements 461041 # number of replacements +system.cpu.dcache.tagsinuse 4090.869171 # Cycle average of tags in use +system.cpu.dcache.total_refs 146891319 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 465137 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 315.802267 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 305775000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4090.869171 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.998747 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.998747 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 109242892 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 109242892 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 37648409 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 37648409 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 18 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 18 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 146891301 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 146891301 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 146891301 # number of overall hits +system.cpu.dcache.overall_hits::total 146891301 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1026587 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1026587 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1802912 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1802912 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 2828124 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2828124 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2828124 # number of overall misses -system.cpu.dcache.overall_misses::total 2828124 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 15421055000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 15421055000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 25889922656 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 25889922656 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 2829499 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2829499 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2829499 # number of overall misses +system.cpu.dcache.overall_misses::total 2829499 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 15441177000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 15441177000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 25867331616 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 25867331616 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 28500 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 28500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 41310977656 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 41310977656 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 41310977656 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 41310977656 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 111659183 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 111659183 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 41308508616 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 41308508616 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 41308508616 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 41308508616 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 110269479 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 110269479 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 39451321 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 39451321 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 52 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 52 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 151110504 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 151110504 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 151110504 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 151110504 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009189 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.009189 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.045679 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.045679 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.057692 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.057692 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.018716 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.018716 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.018716 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.018716 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15030.004347 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 15030.004347 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 14366.481581 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 14366.481581 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 21 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 21 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 149720800 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 149720800 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 149720800 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 149720800 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009310 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.009310 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.045700 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.045700 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.142857 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.142857 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.018899 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.018899 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.018899 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.018899 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15041.274631 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 15041.274631 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 14347.528674 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 14347.528674 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 9500 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 9500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 14607.201684 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 14607.201684 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 14607.201684 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 14607.201684 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 279576 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 531 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 17250 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 12 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 16.207304 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 44.250000 # average number of cycles each access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 14599.230682 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 14599.230682 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 14599.230682 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 14599.230682 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 277266 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 919 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 17305 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 11 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 16.022306 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 83.545455 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 445038 # number of writebacks -system.cpu.dcache.writebacks::total 445038 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 815637 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 815637 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1547591 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1547591 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 445099 # number of writebacks +system.cpu.dcache.writebacks::total 445099 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 816026 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 816026 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1548336 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1548336 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2363228 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2363228 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2363228 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2363228 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 210381 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 210381 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 254515 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 254515 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 464896 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 464896 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 464896 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 464896 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2700521500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2700521500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4051961986 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4051961986 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6752483486 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6752483486 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6752483486 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6752483486 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001884 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001884 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006451 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006451 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003077 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.003077 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003077 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.003077 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12836.337407 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12836.337407 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 15920.326841 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 15920.326841 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14524.718402 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 14524.718402 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14524.718402 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 14524.718402 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_hits::cpu.data 2364362 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2364362 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2364362 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2364362 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 210561 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 210561 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 254576 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 254576 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 465137 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 465137 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 465137 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 465137 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2703972000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2703972000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4046409990 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4046409990 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6750381990 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6750381990 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6750381990 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6750381990 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001910 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001910 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006453 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006453 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003107 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.003107 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003107 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.003107 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12841.751321 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12841.751321 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 15894.703311 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 15894.703311 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14512.674739 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 14512.674739 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14512.674739 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 14512.674739 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 1080 # number of replacements -system.cpu.l2cache.tagsinuse 22929.630995 # Cycle average of tags in use -system.cpu.l2cache.total_refs 547178 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 23523 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 23.261404 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 21483.752454 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 824.475298 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 621.403243 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.655632 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.025161 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.018964 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.699757 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 21 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 206090 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 206111 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 445038 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 445038 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 233241 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 233241 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 21 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 439331 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 439352 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 21 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 439331 # number of overall hits -system.cpu.l2cache.overall_hits::total 439352 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 963 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 4290 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 5253 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 21275 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 21275 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 963 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 25565 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 26528 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 963 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 25565 # number of overall misses -system.cpu.l2cache.overall_misses::total 26528 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 50946500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 423158500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 474105000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1457229500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1457229500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 50946500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 1880388000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 1931334500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 50946500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 1880388000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 1931334500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 984 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 210380 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 211364 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 445038 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 445038 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 254516 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 254516 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 984 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 464896 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 465880 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 984 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 464896 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 465880 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.978659 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.020392 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.024853 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.083590 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.083590 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.978659 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.054991 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.056942 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.978659 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.054991 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.056942 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52903.946002 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 98638.344988 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 90254.140491 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 68494.923619 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68494.923619 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52903.946002 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73553.217289 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 72803.622587 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52903.946002 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73553.217289 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 72803.622587 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 1049 # number of writebacks -system.cpu.l2cache.writebacks::total 1049 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 963 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 4290 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 5253 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 21275 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 21275 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 963 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 25565 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 26528 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 963 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 25565 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 26528 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 38838509 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 367821283 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 406659792 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1190995676 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1190995676 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 38838509 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1558816959 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 1597655468 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 38838509 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1558816959 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 1597655468 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.978659 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.020392 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.024853 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.083590 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.083590 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.978659 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.054991 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.056942 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.978659 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.054991 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.056942 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40330.746625 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 85739.226807 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 77414.770988 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 55980.995347 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55980.995347 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40330.746625 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60974.651242 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60225.251357 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40330.746625 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60974.651242 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60225.251357 # average overall mshr miss latency -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/config.ini b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/config.ini index 9953e7dde..c4518abcc 100644 --- a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/config.ini @@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a -clock=1 +clock=1000 init_param=0 kernel= load_addr_mask=1099511627775 @@ -30,7 +30,7 @@ system_port=system.membus.slave[0] [system.cpu] type=DerivO3CPU -children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload +children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -78,6 +78,7 @@ iewToFetchDelay=1 iewToRenameDelay=1 instShiftAmt=2 interrupts=system.cpu.interrupts +isa=system.cpu.isa issueToExecuteDelay=1 issueWidth=8 itb=system.cpu.itb @@ -129,18 +130,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=262144 subblock_size=0 system=system @@ -159,7 +160,7 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=ArmTableWalker -clock=1 +clock=500 num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[3] @@ -432,18 +433,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=131072 subblock_size=0 system=system @@ -457,6 +458,23 @@ mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=ArmInterrupts +[system.cpu.isa] +type=ArmISA +fpsid=1090793632 +id_isar0=34607377 +id_isar1=34677009 +id_isar2=555950401 +id_isar3=17899825 +id_isar4=268501314 +id_isar5=0 +id_mmfr0=3 +id_mmfr1=0 +id_mmfr2=19070976 +id_mmfr3=4027589137 +id_pfr0=49 +id_pfr1=1 +midr=890224640 + [system.cpu.itb] type=ArmTLB children=walker @@ -465,7 +483,7 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=ArmTableWalker -clock=1 +clock=500 num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[2] @@ -473,24 +491,24 @@ port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] type=BaseCache addr_ranges=0:18446744073709551615 -assoc=2 +assoc=8 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=20 is_top_level=false max_miss_count=0 -mshrs=10 +mshrs=20 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=20 size=2097152 subblock_size=0 system=system -tgts_per_mshr=5 +tgts_per_mshr=12 trace_addr=0 two_queue=false write_buffers=8 @@ -500,10 +518,10 @@ mem_side=system.membus.slave[1] [system.cpu.toL2Bus] type=CoherentBus block_size=64 -clock=1000 +clock=500 header_cycles=1 use_default_range=false -width=8 +width=32 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port @@ -540,15 +558,28 @@ master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] -type=SimpleMemory -bandwidth=73.000000 -clock=1 +type=SimpleDRAM +addr_mapping=openmap +banks_per_rank=8 +clock=1000 conf_table_reported=false in_addr_map=true -latency=30000 -latency_var=0 +lines_per_rowbuffer=64 +mem_sched_policy=fcfs null=false +page_policy=open range=0:134217727 +ranks_per_channel=2 +read_buffer_size=32 +tBURST=4000 +tCL=14000 +tRCD=14000 +tREFI=7800000 +tRFC=300000 +tRP=14000 +tWTR=1000 +write_buffer_size=32 +write_thresh_perc=70 zero=false port=system.membus.master[0] diff --git a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/simout b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/simout index 21a8a9bfd..5bcc38f1b 100755 --- a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/simout @@ -1,8 +1,8 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 21 2012 11:19:00 -gem5 started Sep 21 2012 12:54:44 +gem5 compiled Oct 30 2012 11:20:14 +gem5 started Oct 30 2012 18:59:47 gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/00.gzip/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/00.gzip/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second @@ -38,4 +38,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 164735271500 because target called exit() +Exiting @ tick 164568389500 because target called exit() diff --git a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt index ec201586b..d2efc8854 100644 --- a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt @@ -1,67 +1,67 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.165181 # Number of seconds simulated -sim_ticks 165180822000 # Number of ticks simulated -final_tick 165180822000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.164568 # Number of seconds simulated +sim_ticks 164568389500 # Number of ticks simulated +final_tick 164568389500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 196230 # Simulator instruction rate (inst/s) -host_op_rate 207352 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 56860513 # Simulator tick rate (ticks/s) -host_mem_usage 233444 # Number of bytes of host memory used -host_seconds 2905.02 # Real time elapsed on the host +host_inst_rate 155967 # Simulator instruction rate (inst/s) +host_op_rate 164807 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 45026221 # Simulator tick rate (ticks/s) +host_mem_usage 230908 # Number of bytes of host memory used +host_seconds 3654.95 # Real time elapsed on the host sim_insts 570052720 # Number of instructions simulated sim_ops 602360926 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 46976 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1702592 # Number of bytes read from this memory -system.physmem.bytes_read::total 1749568 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 46976 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 46976 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu.inst 47104 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1702080 # Number of bytes read from this memory +system.physmem.bytes_read::total 1749184 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 47104 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 47104 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 162368 # Number of bytes written to this memory system.physmem.bytes_written::total 162368 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 734 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 26603 # Number of read requests responded to by this memory -system.physmem.num_reads::total 27337 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 736 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 26595 # Number of read requests responded to by this memory +system.physmem.num_reads::total 27331 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 2537 # Number of write requests responded to by this memory system.physmem.num_writes::total 2537 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 284391 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 10307444 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 10591835 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 284391 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 284391 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 982971 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 982971 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 982971 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 284391 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 10307444 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 11574806 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 27339 # Total number of read requests seen +system.physmem.bw_read::cpu.inst 286228 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 10342691 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 10628919 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 286228 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 286228 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 986629 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 986629 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 986629 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 286228 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 10342691 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 11615548 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 27332 # Total number of read requests seen system.physmem.writeReqs 2537 # Total number of write requests seen -system.physmem.cpureqs 29876 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 1749568 # Total number of bytes read from memory +system.physmem.cpureqs 29869 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 1749184 # Total number of bytes read from memory system.physmem.bytesWritten 162368 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 1749568 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 1749184 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 162368 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 1702 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 1705 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 1738 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 1698 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 1679 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 1720 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 1741 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 1736 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 1724 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 1670 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 1743 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 1664 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 1696 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 1706 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 1737 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 1701 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 1675 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 1719 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 1745 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 1734 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 1725 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 1671 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 1739 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 1666 # Track reads on a per bank basis system.physmem.perBankRdReqs::12 1665 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 1719 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 1718 # Track reads on a per bank basis system.physmem.perBankRdReqs::14 1759 # Track reads on a per bank basis system.physmem.perBankRdReqs::15 1676 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 159 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 159 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 158 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 158 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 159 # Track writes on a per bank basis system.physmem.perBankWrReqs::3 159 # Track writes on a per bank basis system.physmem.perBankWrReqs::4 157 # Track writes on a per bank basis system.physmem.perBankWrReqs::5 159 # Track writes on a per bank basis @@ -77,14 +77,14 @@ system.physmem.perBankWrReqs::14 164 # Tr system.physmem.perBankWrReqs::15 157 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 165180805000 # Total gap between requests +system.physmem.totGap 164568371500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 27339 # Categorize read packet sizes +system.physmem.readPktSize::6 27332 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -105,10 +105,10 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 14846 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 2913 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 8786 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 787 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 14894 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 2844 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 8804 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 783 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see @@ -138,7 +138,7 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 92 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 93 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 111 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 111 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 111 # What write queue length does an incoming req see @@ -161,7 +161,7 @@ system.physmem.wrQLenPdf::19 110 # Wh system.physmem.wrQLenPdf::20 110 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 110 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 18 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see @@ -171,27 +171,27 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 952476989 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 1656324989 # Sum of mem lat for all requests -system.physmem.totBusLat 109352000 # Total cycles spent in databus access -system.physmem.totBankLat 594496000 # Total cycles spent in bank access -system.physmem.avgQLat 34839.50 # Average queueing delay per request -system.physmem.avgBankLat 21745.35 # Average bank access latency per request -system.physmem.avgBusLat 3999.85 # Average bus latency per request -system.physmem.avgMemAccLat 60584.70 # Average memory access latency -system.physmem.avgRdBW 10.59 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 0.98 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 10.59 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 0.98 # Average consumed write bandwidth in MB/s +system.physmem.totQLat 953340995 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 1657962995 # Sum of mem lat for all requests +system.physmem.totBusLat 109328000 # Total cycles spent in databus access +system.physmem.totBankLat 595294000 # Total cycles spent in bank access +system.physmem.avgQLat 34880.03 # Average queueing delay per request +system.physmem.avgBankLat 21780.11 # Average bank access latency per request +system.physmem.avgBusLat 4000.00 # Average bus latency per request +system.physmem.avgMemAccLat 60660.14 # Average memory access latency +system.physmem.avgRdBW 10.63 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 0.99 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 10.63 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 0.99 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.07 # Data bus utilization in percentage system.physmem.avgRdQLen 0.01 # Average read queue length over time -system.physmem.avgWrQLen 5.90 # Average write queue length over time -system.physmem.readRowHits 17775 # Number of row buffer hits during reads -system.physmem.writeRowHits 1102 # Number of row buffer hits during writes -system.physmem.readRowHitRate 65.02 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 43.44 # Row buffer hit rate for writes -system.physmem.avgGap 5528879.54 # Average gap between requests +system.physmem.avgWrQLen 6.05 # Average write queue length over time +system.physmem.readRowHits 17765 # Number of row buffer hits during reads +system.physmem.writeRowHits 1091 # Number of row buffer hits during writes +system.physmem.readRowHitRate 65.00 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 43.00 # Row buffer hit rate for writes +system.physmem.avgGap 5509671.28 # Average gap between requests system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -235,246 +235,247 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 48 # Number of system calls -system.cpu.numCycles 330361645 # number of cpu cycles simulated +system.cpu.numCycles 329136780 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 85614942 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 80408346 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 2411110 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 47313103 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 46933261 # Number of BTB hits +system.cpu.BPredUnit.lookups 85146783 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 79928286 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 2342158 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 47212748 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 46871026 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1438558 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 1082 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 68875257 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 669940715 # Number of instructions fetch has processed -system.cpu.fetch.Branches 85614942 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 48371819 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 130120406 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 13468606 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 119373897 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 577 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 67426910 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 785892 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 329401870 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.167030 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.195227 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1427560 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 1061 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 68501011 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 666829693 # Number of instructions fetch has processed +system.cpu.fetch.Branches 85146783 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 48298586 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 129620938 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 13095502 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 119329475 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 2 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 302 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 6 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 67084220 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 755001 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 328178874 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.165282 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.193965 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 199281685 60.50% 60.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 20931796 6.35% 66.85% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 4976114 1.51% 68.36% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 14405737 4.37% 72.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 8916437 2.71% 75.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 9491769 2.88% 78.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 4395407 1.33% 79.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 5797990 1.76% 81.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 61204935 18.58% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 198558185 60.50% 60.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 20911289 6.37% 66.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 4967188 1.51% 68.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 14345258 4.37% 72.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 8890662 2.71% 75.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 9436402 2.88% 78.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 4398507 1.34% 79.68% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 5788329 1.76% 81.45% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 60883054 18.55% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 329401870 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.259155 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.027901 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 93386530 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 96217512 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 108381185 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 20386445 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 11030198 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 4725688 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 1634 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 706212594 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 6047 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 11030198 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 107646383 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 14427218 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 44142 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 114436491 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 81817438 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 697478243 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 44 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 59322145 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 20349848 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 693 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 724191424 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3242851069 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3242850941 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 328178874 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.258697 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.025996 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 92947684 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 96199178 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 107899614 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 20406722 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 10725676 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 4737184 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 1561 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 703240498 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 5895 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 10725676 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 107135136 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 14450172 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 44143 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 114043084 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 81780663 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 694816427 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 60 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 59310091 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 20339427 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 673 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 721301804 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3230529001 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3230528873 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 128 # Number of floating rename lookups system.cpu.rename.CommittedMaps 627419189 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 96772235 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2137 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2090 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 170767366 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 172981751 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 80655031 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 21643688 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 28602277 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 682247714 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 3351 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 646916263 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1413678 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 79713119 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 198676272 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 420 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 329401870 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.963912 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.726446 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 93882615 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2064 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2020 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 170675831 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 172202980 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 80458110 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 21583677 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 28704390 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 679987725 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 3320 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 645601186 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1370428 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 77447824 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 193234107 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 389 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 328178874 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.967223 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.725262 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 68982651 20.94% 20.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 85413517 25.93% 46.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 75907397 23.04% 69.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 40996794 12.45% 82.36% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 28857883 8.76% 91.12% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 14995240 4.55% 95.67% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 5624116 1.71% 97.38% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 6449034 1.96% 99.34% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 2175238 0.66% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 68164683 20.77% 20.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 85309693 25.99% 46.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 75934594 23.14% 69.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 40814180 12.44% 82.34% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 28810425 8.78% 91.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 14904242 4.54% 95.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 5586841 1.70% 97.36% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 6537919 1.99% 99.36% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 2116297 0.64% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 329401870 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 328178874 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 209715 5.57% 5.57% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 5.57% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 5.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 5.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 5.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 5.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.57% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 2699537 71.67% 77.24% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 857291 22.76% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 216945 5.75% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2691247 71.35% 77.10% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 863918 22.90% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 403968416 62.45% 62.45% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 6570 0.00% 62.45% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.45% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.45% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.45% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.45% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.45% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.45% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 62.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.45% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 166149452 25.68% 88.13% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 76791822 11.87% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 403371869 62.48% 62.48% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 6568 0.00% 62.48% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.48% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.48% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.48% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.48% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.48% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.48% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 62.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.48% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 165559477 25.64% 88.13% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 76663269 11.87% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 646916263 # Type of FU issued -system.cpu.iq.rate 1.958206 # Inst issue rate -system.cpu.iq.fu_busy_cnt 3766543 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.005822 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1628414581 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 761976266 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 638610282 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 645601186 # Type of FU issued +system.cpu.iq.rate 1.961498 # Inst issue rate +system.cpu.iq.fu_busy_cnt 3772110 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.005843 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1624523748 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 757451010 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 637563052 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 650682786 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 649373276 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 30415737 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 30369655 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 24028931 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 122816 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 12363 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 10433791 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 23250160 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 123060 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 12375 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 10236870 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 12786 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 32242 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 12923 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 32784 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 11030198 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 797335 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 96405 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 682254196 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 711562 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 172981751 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 80655031 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 2002 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 33535 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 20290 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 12363 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1389918 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1519621 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 2909539 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 642699172 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 163997886 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 4217091 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 10725676 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 798492 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 92069 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 679994152 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 690727 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 172202980 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 80458110 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1965 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 32845 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 16029 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 12375 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1358556 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1460812 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 2819368 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 641523461 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 163490704 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 4077725 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 3131 # number of nop insts executed -system.cpu.iew.exec_refs 239992833 # number of memory reference insts executed -system.cpu.iew.exec_branches 74738268 # Number of branches executed -system.cpu.iew.exec_stores 75994947 # Number of stores executed -system.cpu.iew.exec_rate 1.945441 # Inst execution rate -system.cpu.iew.wb_sent 640075541 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 638610298 # cumulative count of insts written-back -system.cpu.iew.wb_producers 419218635 # num instructions producing a value -system.cpu.iew.wb_consumers 650818648 # num instructions consuming a value +system.cpu.iew.exec_nop 3107 # number of nop insts executed +system.cpu.iew.exec_refs 239380202 # number of memory reference insts executed +system.cpu.iew.exec_branches 74672586 # Number of branches executed +system.cpu.iew.exec_stores 75889498 # Number of stores executed +system.cpu.iew.exec_rate 1.949109 # Inst execution rate +system.cpu.iew.wb_sent 638973087 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 637563068 # cumulative count of insts written-back +system.cpu.iew.wb_producers 418509904 # num instructions producing a value +system.cpu.iew.wb_consumers 649810327 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.933064 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.644140 # average fanout of values written-back +system.cpu.iew.wb_rate 1.937076 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.644049 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 79903729 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 77641136 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 2931 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 2409576 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 318371673 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.892006 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.234894 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 2340694 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 317453199 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.897480 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.237382 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 93985379 29.52% 29.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 104446341 32.81% 62.33% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 43081844 13.53% 75.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 8825548 2.77% 78.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 25971107 8.16% 86.79% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 12926353 4.06% 90.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 7575563 2.38% 93.23% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1171571 0.37% 93.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 20387967 6.40% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 93244159 29.37% 29.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 104350587 32.87% 62.24% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 42987524 13.54% 75.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 8793922 2.77% 78.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 25958876 8.18% 86.73% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 12900336 4.06% 90.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 7627072 2.40% 93.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1171824 0.37% 93.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 20418899 6.43% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 318371673 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 317453199 # Number of insts commited each cycle system.cpu.commit.committedInsts 570052771 # Number of instructions committed system.cpu.commit.committedOps 602360977 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -485,317 +486,191 @@ system.cpu.commit.branches 70892751 # Nu system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. system.cpu.commit.int_insts 533523539 # Number of committed integer instructions. system.cpu.commit.function_calls 997573 # Number of function calls committed. -system.cpu.commit.bw_lim_events 20387967 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 20418899 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 980247800 # The number of ROB reads -system.cpu.rob.rob_writes 1375591081 # The number of ROB writes -system.cpu.timesIdled 40973 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 959775 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 977035801 # The number of ROB reads +system.cpu.rob.rob_writes 1370761733 # The number of ROB writes +system.cpu.timesIdled 41126 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 957906 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 570052720 # Number of Instructions Simulated system.cpu.committedOps 602360926 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 570052720 # Number of Instructions Simulated -system.cpu.cpi 0.579528 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.579528 # CPI: Total CPI of All Threads -system.cpu.ipc 1.725541 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.725541 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3210576810 # number of integer regfile reads -system.cpu.int_regfile_writes 664235164 # number of integer regfile writes +system.cpu.cpi 0.577380 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.577380 # CPI: Total CPI of All Threads +system.cpu.ipc 1.731963 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.731963 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3204362065 # number of integer regfile reads +system.cpu.int_regfile_writes 663044095 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.misc_regfile_reads 905305467 # number of misc regfile reads +system.cpu.misc_regfile_reads 901644614 # number of misc regfile reads system.cpu.misc_regfile_writes 3110 # number of misc regfile writes -system.cpu.icache.replacements 62 # number of replacements -system.cpu.icache.tagsinuse 692.874511 # Cycle average of tags in use -system.cpu.icache.total_refs 67425756 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 825 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 81728.189091 # Average number of references to valid blocks. +system.cpu.icache.replacements 60 # number of replacements +system.cpu.icache.tagsinuse 685.359263 # Cycle average of tags in use +system.cpu.icache.total_refs 67083066 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 820 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 81808.617073 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 692.874511 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.338318 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.338318 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 67425756 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 67425756 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 67425756 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 67425756 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 67425756 # number of overall hits -system.cpu.icache.overall_hits::total 67425756 # number of overall hits +system.cpu.icache.occ_blocks::cpu.inst 685.359263 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.334648 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.334648 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 67083066 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 67083066 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 67083066 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 67083066 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 67083066 # number of overall hits +system.cpu.icache.overall_hits::total 67083066 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 1154 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 1154 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 1154 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 1154 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 1154 # number of overall misses system.cpu.icache.overall_misses::total 1154 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 50922500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 50922500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 50922500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 50922500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 50922500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 50922500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 67426910 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 67426910 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 67426910 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 67426910 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 67426910 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 67426910 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 51351999 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 51351999 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 51351999 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 51351999 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 51351999 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 51351999 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 67084220 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 67084220 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 67084220 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 67084220 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 67084220 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 67084220 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000017 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000017 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000017 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000017 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000017 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000017 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 44126.949740 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 44126.949740 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 44126.949740 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 44126.949740 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 44126.949740 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 44126.949740 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 247 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 44499.132582 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 44499.132582 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 44499.132582 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 44499.132582 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 44499.132582 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 44499.132582 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 269 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 7 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 49.400000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 38.428571 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 328 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 328 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 328 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 328 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 328 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 328 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 826 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 826 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 826 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 826 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 826 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 826 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 38439500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 38439500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 38439500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 38439500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 38439500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 38439500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 334 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 334 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 334 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 334 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 334 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 334 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 820 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 820 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 820 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 820 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 820 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 820 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 38657999 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 38657999 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 38657999 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 38657999 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 38657999 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 38657999 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000012 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000012 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000012 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000012 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000012 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000012 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 46536.924939 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 46536.924939 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 46536.924939 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 46536.924939 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 46536.924939 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 46536.924939 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 47143.901220 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 47143.901220 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 47143.901220 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 47143.901220 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 47143.901220 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 47143.901220 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 440454 # number of replacements -system.cpu.dcache.tagsinuse 4091.536568 # Cycle average of tags in use -system.cpu.dcache.total_refs 198063046 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 444550 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 445.536039 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 319624000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4091.536568 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.998910 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.998910 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 131984010 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 131984010 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 66075783 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 66075783 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 1699 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 1699 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 1554 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 1554 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 198059793 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 198059793 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 198059793 # number of overall hits -system.cpu.dcache.overall_hits::total 198059793 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 341827 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 341827 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 3341748 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 3341748 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 23 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 23 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 3683575 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3683575 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3683575 # number of overall misses -system.cpu.dcache.overall_misses::total 3683575 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5150660000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5150660000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 40139382746 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 40139382746 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 405500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 405500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 45290042746 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 45290042746 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 45290042746 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 45290042746 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 132325837 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 132325837 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 69417531 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 69417531 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1722 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 1722 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 1554 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 1554 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 201743368 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 201743368 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 201743368 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 201743368 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002583 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.002583 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.048140 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.048140 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.013357 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.013357 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.018259 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.018259 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.018259 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.018259 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15068.031490 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 15068.031490 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 12011.493011 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 12011.493011 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 17630.434783 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 17630.434783 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 12295.132513 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 12295.132513 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 12295.132513 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 12295.132513 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 131789 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 15 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 4871 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 27.055841 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 7.500000 # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 421553 # number of writebacks -system.cpu.dcache.writebacks::total 421553 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 144386 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 144386 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3094637 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 3094637 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 23 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 23 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3239023 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3239023 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3239023 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3239023 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 197441 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 197441 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 247111 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 247111 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 444552 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 444552 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 444552 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 444552 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2877099000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2877099000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4061335300 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4061335300 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6938434300 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6938434300 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6938434300 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6938434300 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001492 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001492 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.003560 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.003560 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002204 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.002204 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002204 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.002204 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14571.943011 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14571.943011 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 16435.267147 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 16435.267147 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15607.700112 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 15607.700112 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15607.700112 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 15607.700112 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 2558 # number of replacements -system.cpu.l2cache.tagsinuse 22383.637112 # Cycle average of tags in use -system.cpu.l2cache.total_refs 517068 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 24174 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 21.389427 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 2559 # number of replacements +system.cpu.l2cache.tagsinuse 22365.188889 # Cycle average of tags in use +system.cpu.l2cache.total_refs 517231 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 24170 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 21.399710 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 20764.549268 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 650.758055 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 968.329789 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.633684 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.019860 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.029551 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.683094 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 89 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 192614 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 192703 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 421553 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 421553 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 225323 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 225323 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 89 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 417937 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 418026 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 89 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 417937 # number of overall hits -system.cpu.l2cache.overall_hits::total 418026 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 737 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 4824 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 5561 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 21791 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 21791 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 737 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 26615 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 27352 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 737 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 26615 # number of overall misses -system.cpu.l2cache.overall_misses::total 27352 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 36711500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 729185000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 765896500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1543567500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1543567500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 36711500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 2272752500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 2309464000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 36711500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 2272752500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 2309464000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 826 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 197438 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 198264 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 421553 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 421553 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 247114 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 247114 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 826 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 444552 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 445378 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 826 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 444552 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 445378 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.892252 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.024433 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.028048 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.088182 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.088182 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.892252 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.059869 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.061413 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.892252 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.059869 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.061413 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 49812.075984 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 151157.752902 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 137726.398130 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70835.092469 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70835.092469 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 49812.075984 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 85393.668984 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 84434.922492 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 49812.075984 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 85393.668984 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 84434.922492 # average overall miss latency +system.cpu.l2cache.occ_blocks::writebacks 20763.498620 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 646.825200 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 954.865069 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.633652 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.019740 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.029140 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.682531 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 81 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 192805 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 192886 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 421636 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 421636 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 225369 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 225369 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 81 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 418174 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 418255 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 81 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 418174 # number of overall hits +system.cpu.l2cache.overall_hits::total 418255 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 739 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 4814 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 5553 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 21790 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 21790 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 739 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 26604 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 27343 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 739 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 26604 # number of overall misses +system.cpu.l2cache.overall_misses::total 27343 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 37001500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 728778000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 765779500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1545376000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1545376000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 37001500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 2274154000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 2311155500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 37001500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 2274154000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 2311155500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 820 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 197619 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 198439 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 421636 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 421636 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 247159 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 247159 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 820 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 444778 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 445598 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 820 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 444778 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 445598 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.901220 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.024360 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.027983 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.088162 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.088162 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.901220 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.059814 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.061362 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.901220 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.059814 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.061362 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50069.688769 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 151387.203988 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 137903.745723 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70921.340064 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70921.340064 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50069.688769 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 85481.656894 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 84524.576674 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50069.688769 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 85481.656894 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 84524.576674 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -807,58 +682,184 @@ system.cpu.l2cache.cache_copies 0 # nu system.cpu.l2cache.writebacks::writebacks 2537 # number of writebacks system.cpu.l2cache.writebacks::total 2537 # number of writebacks system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 3 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 10 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 13 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 8 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 11 # number of ReadReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.inst 3 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 10 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 13 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 8 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 11 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.inst 3 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 10 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 13 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 734 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 4814 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 5548 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 21791 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 21791 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 734 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 26605 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 27339 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 734 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 26605 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 27339 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 27102664 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 668415074 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 695517738 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1272078673 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1272078673 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 27102664 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1940493747 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 1967596411 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 27102664 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1940493747 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 1967596411 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.888620 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.024382 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.027983 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.088182 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.088182 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.888620 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.059847 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.061384 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.888620 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.059847 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.061384 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 36924.610354 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 138848.166597 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 125363.687455 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58376.333027 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58376.333027 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 36924.610354 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72937.182748 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71970.313874 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 36924.610354 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72937.182748 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71970.313874 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_hits::cpu.data 8 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 11 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 736 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 4806 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 5542 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 21790 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 21790 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 736 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 26596 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 27332 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 736 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 26596 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 27332 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 27342673 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 668140562 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 695483235 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1273790796 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1273790796 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 27342673 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1941931358 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 1969274031 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 27342673 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1941931358 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 1969274031 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.897561 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.024320 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.027928 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.088162 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.088162 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.897561 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.059796 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.061338 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.897561 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.059796 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.061338 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37150.370924 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 139022.172701 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 125493.185673 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58457.585865 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58457.585865 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37150.370924 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73015.918108 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72050.125531 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37150.370924 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73015.918108 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72050.125531 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.replacements 440681 # number of replacements +system.cpu.dcache.tagsinuse 4091.500678 # Cycle average of tags in use +system.cpu.dcache.total_refs 197565955 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 444777 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 444.191033 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 320845000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4091.500678 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.998902 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.998902 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 131517978 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 131517978 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 66044747 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 66044747 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 1676 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 1676 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 1554 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 1554 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 197562725 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 197562725 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 197562725 # number of overall hits +system.cpu.dcache.overall_hits::total 197562725 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 342017 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 342017 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 3372784 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 3372784 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 22 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 22 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 3714801 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3714801 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3714801 # number of overall misses +system.cpu.dcache.overall_misses::total 3714801 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5159651000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5159651000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 40250551202 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 40250551202 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 339000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 339000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 45410202202 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 45410202202 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 45410202202 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 45410202202 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 131859995 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 131859995 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 69417531 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 69417531 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1698 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 1698 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 1554 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 1554 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 201277526 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 201277526 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 201277526 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 201277526 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002594 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.002594 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.048587 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.048587 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.012956 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.012956 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.018456 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.018456 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.018456 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.018456 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15085.948944 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 15085.948944 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 11933.924972 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 11933.924972 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15409.090909 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15409.090909 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 12224.127807 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 12224.127807 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 12224.127807 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 12224.127807 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 131795 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 20 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 5078 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 25.954116 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 10 # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 421636 # number of writebacks +system.cpu.dcache.writebacks::total 421636 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 144398 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 144398 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3125625 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3125625 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 22 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 22 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3270023 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3270023 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3270023 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3270023 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 197619 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 197619 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 247159 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 247159 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 444778 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 444778 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 444778 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 444778 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2875780500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2875780500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4060483756 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4060483756 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6936264256 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6936264256 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6936264256 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6936264256 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001499 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001499 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.003560 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.003560 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002210 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.002210 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002210 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.002210 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14552.145796 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14552.145796 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 16428.629975 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 16428.629975 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15594.890611 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 15594.890611 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15594.890611 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 15594.890611 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/config.ini b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/config.ini index ca675ac92..48dcd7446 100644 --- a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/config.ini +++ b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/config.ini @@ -10,6 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a +clock=1000 init_param=0 kernel= load_addr_mask=1099511627775 @@ -29,7 +30,7 @@ system_port=system.membus.slave[0] [system.cpu] type=DerivO3CPU -children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload +children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -77,6 +78,7 @@ iewToFetchDelay=1 iewToRenameDelay=1 instShiftAmt=2 interrupts=system.cpu.interrupts +isa=system.cpu.isa issueToExecuteDelay=1 issueWidth=8 itb=system.cpu.itb @@ -95,7 +97,6 @@ numPhysIntRegs=256 numROBEntries=192 numRobs=1 numThreads=1 -phase=0 predType=tournament profile=0 progress_interval=0 @@ -129,16 +130,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=2 is_top_level=true -latency=1000 max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=2 size=262144 subblock_size=0 system=system @@ -421,16 +424,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=2 is_top_level=true -latency=1000 max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=2 size=131072 subblock_size=0 system=system @@ -444,6 +449,9 @@ mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=SparcInterrupts +[system.cpu.isa] +type=SparcISA + [system.cpu.itb] type=SparcTLB size=64 @@ -451,22 +459,24 @@ size=64 [system.cpu.l2cache] type=BaseCache addr_ranges=0:18446744073709551615 -assoc=2 +assoc=8 block_size=64 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=20 is_top_level=false -latency=1000 max_miss_count=0 -mshrs=10 +mshrs=20 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=20 size=2097152 subblock_size=0 system=system -tgts_per_mshr=5 +tgts_per_mshr=12 trace_addr=0 two_queue=false write_buffers=8 @@ -476,10 +486,10 @@ mem_side=system.membus.slave[1] [system.cpu.toL2Bus] type=CoherentBus block_size=64 -clock=1000 +clock=500 header_cycles=1 use_default_range=false -width=8 +width=32 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side @@ -494,7 +504,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/sparc/linux/gzip +executable=/projects/pd/randd/dist/cpu2000/binaries/sparc/linux/gzip gid=100 input=cin max_stack_size=67108864 @@ -516,14 +526,28 @@ master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] -type=SimpleMemory +type=SimpleDRAM +addr_mapping=openmap +banks_per_rank=8 +clock=1000 conf_table_reported=false -file= in_addr_map=true -latency=30000 -latency_var=0 +lines_per_rowbuffer=64 +mem_sched_policy=fcfs null=false +page_policy=open range=0:134217727 +ranks_per_channel=2 +read_buffer_size=32 +tBURST=4000 +tCL=14000 +tRCD=14000 +tREFI=7800000 +tRFC=300000 +tRP=14000 +tWTR=1000 +write_buffer_size=32 +write_thresh_perc=70 zero=false port=system.membus.master[0] diff --git a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/simout b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/simout index 5518ac66c..10b614f5f 100755 --- a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/simout +++ b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 13 2012 17:04:37 -gem5 started Aug 13 2012 18:13:42 -gem5 executing on zizzer +gem5 compiled Oct 30 2012 11:11:57 +gem5 started Oct 30 2012 14:00:44 +gem5 executing on u200540-lin command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/o3-timing -re tests/run.py build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -38,4 +38,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 389171398000 because target called exit() +Exiting @ tick 387281648500 because target called exit() diff --git a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt index ef06efc76..c74d8b444 100644 --- a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt @@ -1,64 +1,64 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.389228 # Number of seconds simulated -sim_ticks 389227542000 # Number of ticks simulated -final_tick 389227542000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.387282 # Number of seconds simulated +sim_ticks 387281648500 # Number of ticks simulated +final_tick 387281648500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 219415 # Simulator instruction rate (inst/s) -host_op_rate 220107 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 60950012 # Simulator tick rate (ticks/s) -host_mem_usage 227096 # Number of bytes of host memory used -host_seconds 6386.01 # Real time elapsed on the host +host_inst_rate 171377 # Simulator instruction rate (inst/s) +host_op_rate 171918 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 47367883 # Simulator tick rate (ticks/s) +host_mem_usage 224920 # Number of bytes of host memory used +host_seconds 8176.04 # Real time elapsed on the host sim_insts 1401188945 # Number of instructions simulated sim_ops 1405604139 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 76992 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 76608 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 1678464 # Number of bytes read from this memory -system.physmem.bytes_read::total 1755456 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 76992 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 76992 # Number of instructions bytes read from this memory +system.physmem.bytes_read::total 1755072 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 76608 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 76608 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 162112 # Number of bytes written to this memory system.physmem.bytes_written::total 162112 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 1203 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 1197 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 26226 # Number of read requests responded to by this memory -system.physmem.num_reads::total 27429 # Number of read requests responded to by this memory +system.physmem.num_reads::total 27423 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 2533 # Number of write requests responded to by this memory system.physmem.num_writes::total 2533 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 197807 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 4312295 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4510102 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 197807 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 197807 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 416497 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 416497 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 416497 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 197807 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4312295 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4926599 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 27430 # Total number of read requests seen +system.physmem.bw_read::cpu.inst 197810 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 4333962 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4531772 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 197810 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 197810 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 418589 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 418589 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 418589 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 197810 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4333962 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4950361 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 27424 # Total number of read requests seen system.physmem.writeReqs 2533 # Total number of write requests seen -system.physmem.cpureqs 29963 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 1755456 # Total number of bytes read from memory +system.physmem.cpureqs 29957 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 1755072 # Total number of bytes read from memory system.physmem.bytesWritten 162112 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 1755456 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 1755072 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 162112 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 1701 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 1724 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 1698 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 1721 # Track reads on a per bank basis system.physmem.perBankRdReqs::2 1715 # Track reads on a per bank basis system.physmem.perBankRdReqs::3 1733 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 1803 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 1768 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 1805 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 1769 # Track reads on a per bank basis system.physmem.perBankRdReqs::6 1697 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 1668 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 1667 # Track reads on a per bank basis system.physmem.perBankRdReqs::8 1678 # Track reads on a per bank basis system.physmem.perBankRdReqs::9 1745 # Track reads on a per bank basis system.physmem.perBankRdReqs::10 1695 # Track reads on a per bank basis system.physmem.perBankRdReqs::11 1685 # Track reads on a per bank basis system.physmem.perBankRdReqs::12 1728 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 1754 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 1713 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 1623 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 1755 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 1712 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 1621 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 159 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 159 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 161 # Track writes on a per bank basis @@ -77,14 +77,14 @@ system.physmem.perBankWrReqs::14 158 # Tr system.physmem.perBankWrReqs::15 152 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 389227514000 # Total gap between requests +system.physmem.totGap 387281620500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 27430 # Categorize read packet sizes +system.physmem.readPktSize::6 27424 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -105,11 +105,11 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 8259 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 13045 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 5213 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 911 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 8242 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 13042 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 5223 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 916 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -171,265 +171,266 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 723930803 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 1405746803 # Sum of mem lat for all requests -system.physmem.totBusLat 109720000 # Total cycles spent in databus access -system.physmem.totBankLat 572096000 # Total cycles spent in bank access -system.physmem.avgQLat 26391.94 # Average queueing delay per request -system.physmem.avgBankLat 20856.58 # Average bank access latency per request +system.physmem.totQLat 722664308 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 1404176308 # Sum of mem lat for all requests +system.physmem.totBusLat 109696000 # Total cycles spent in databus access +system.physmem.totBankLat 571816000 # Total cycles spent in bank access +system.physmem.avgQLat 26351.53 # Average queueing delay per request +system.physmem.avgBankLat 20850.93 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 51248.52 # Average memory access latency -system.physmem.avgRdBW 4.51 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 51202.46 # Average memory access latency +system.physmem.avgRdBW 4.53 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.42 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 4.51 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 4.53 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.42 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time -system.physmem.avgWrQLen 17.21 # Average write queue length over time -system.physmem.readRowHits 18327 # Number of row buffer hits during reads -system.physmem.writeRowHits 1092 # Number of row buffer hits during writes +system.physmem.avgWrQLen 17.43 # Average write queue length over time +system.physmem.readRowHits 18322 # Number of row buffer hits during reads +system.physmem.writeRowHits 1102 # Number of row buffer hits during writes system.physmem.readRowHitRate 66.81 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 43.11 # Row buffer hit rate for writes -system.physmem.avgGap 12990271.80 # Average gap between requests +system.physmem.writeRowHitRate 43.51 # Row buffer hit rate for writes +system.physmem.avgGap 12927917.36 # Average gap between requests system.cpu.workload.num_syscalls 49 # Number of system calls -system.cpu.numCycles 778455085 # number of cpu cycles simulated +system.cpu.numCycles 774563298 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 98229199 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 88445613 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 3785118 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 66042302 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 65687206 # Number of BTB hits +system.cpu.BPredUnit.lookups 97756783 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 88046378 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 3616115 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 65822232 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 65492473 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1416 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 222 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 165941423 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1649243289 # Number of instructions fetch has processed -system.cpu.fetch.Branches 98229199 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 65688622 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 330524246 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 21752869 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 264030512 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 127 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 3232 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 162872893 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 756309 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 778243541 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.125156 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.146469 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1334 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 221 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 164852368 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1642212446 # Number of instructions fetch has processed +system.cpu.fetch.Branches 97756783 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 65493807 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 329195647 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 20823123 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 263322100 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 67 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 2527 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 12 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 161933661 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 734964 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 774355546 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.126740 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.146682 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 447719295 57.53% 57.53% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 74411347 9.56% 67.09% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 37980792 4.88% 71.97% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 9095898 1.17% 73.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 28164996 3.62% 76.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 18829907 2.42% 79.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 11517848 1.48% 80.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 3875799 0.50% 81.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 146647659 18.84% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 445159899 57.49% 57.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 74061304 9.56% 67.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 37898461 4.89% 71.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 9077519 1.17% 73.12% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 28105677 3.63% 76.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 18773272 2.42% 79.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 11484924 1.48% 80.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 3792333 0.49% 81.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 146002157 18.85% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 778243541 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.126185 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.118611 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 217164629 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 215069073 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 285415505 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 42850333 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 17744001 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 1642995255 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 17744001 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 241214952 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 36881220 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 52262769 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 303103685 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 127036914 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 1631617640 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 159 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 30927214 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 74044181 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 3148431 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 1361239803 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 2756565281 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 2722455578 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 34109703 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 774355546 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.126209 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.120178 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 215883064 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 214466469 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 284208572 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 42814616 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 16982825 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 1636500589 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 16982825 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 239715972 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 36727743 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 52434063 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 302057850 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 126437093 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 1625611071 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 165 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 30924044 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 73480825 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 3128707 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 1356294088 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 2746297990 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 2712224165 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 34073825 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1244770439 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 116469364 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2680762 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2695576 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 273321719 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 438834936 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 180276836 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 255914047 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 82184887 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1517277053 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2635551 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1461048176 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 49743 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 113961410 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 136888972 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 391880 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 778243541 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.877366 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.430181 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 111523649 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2645349 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2664178 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 271657434 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 436922066 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 179745095 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 254298230 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 83339884 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1512454597 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2610820 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1459325981 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 53748 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 109158045 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 130052751 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 367149 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 774355546 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.884568 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.432012 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 147640445 18.97% 18.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 185782276 23.87% 42.84% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 210767336 27.08% 69.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 131005887 16.83% 86.76% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 70732163 9.09% 95.85% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 20418483 2.62% 98.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 7758324 1.00% 99.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 3966460 0.51% 99.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 172167 0.02% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 145671235 18.81% 18.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 184692846 23.85% 42.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 209497548 27.05% 69.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 131299597 16.96% 86.67% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 70722781 9.13% 95.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 20304331 2.62% 98.43% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 8026000 1.04% 99.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 3959195 0.51% 99.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 182013 0.02% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 778243541 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 774355546 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 96825 5.83% 5.83% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 5.83% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 5.83% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 95727 5.76% 11.58% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.58% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.58% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 11.58% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.58% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 11.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 11.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.58% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1146892 69.00% 80.58% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 322714 19.42% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 90752 5.46% 5.46% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 5.46% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 5.46% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 95014 5.72% 11.18% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.18% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.18% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 11.18% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.18% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 11.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 11.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.18% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1160014 69.81% 80.99% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 315922 19.01% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 867232738 59.36% 59.36% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 59.36% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 59.36% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2645576 0.18% 59.54% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.54% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.54% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.54% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.54% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.54% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 419895345 28.74% 88.28% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 171274517 11.72% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 866438962 59.37% 59.37% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 59.37% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 59.37% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2644873 0.18% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 419117163 28.72% 88.27% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 171124983 11.73% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1461048176 # Type of FU issued -system.cpu.iq.rate 1.876856 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1662158 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.001138 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 3684211603 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 1624908064 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1444562282 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 17840191 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 9203552 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 8548837 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1453579294 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 9131040 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 215356561 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1459325981 # Type of FU issued +system.cpu.iq.rate 1.884063 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1661702 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.001139 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 3676896998 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 1615267495 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1443201042 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 17825960 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 9193607 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 8546616 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1451866721 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 9120962 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 215450617 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 36322093 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 55076 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 245947 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 13428694 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 34409223 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 57798 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 244556 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 12896953 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 3648 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 92141 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 3310 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 91608 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 17744001 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 3080372 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 245510 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1614123458 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 4140274 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 438834936 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 180276836 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 2549819 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 147701 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 1738 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 245947 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 2356068 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1563417 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 3919485 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1455490088 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 417172237 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 5558088 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 16982825 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 3082295 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 247112 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1608751818 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 4125389 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 436922066 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 179745095 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 2527727 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 148822 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 1680 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 244556 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 2270064 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1474247 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 3744311 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1454009970 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 416570645 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 5316011 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 94210854 # number of nop insts executed -system.cpu.iew.exec_refs 587755640 # number of memory reference insts executed -system.cpu.iew.exec_branches 89119477 # Number of branches executed -system.cpu.iew.exec_stores 170583403 # Number of stores executed -system.cpu.iew.exec_rate 1.869716 # Inst execution rate -system.cpu.iew.wb_sent 1454027442 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1453111119 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1154511485 # num instructions producing a value -system.cpu.iew.wb_consumers 1205709259 # num instructions consuming a value +system.cpu.iew.exec_nop 93686401 # number of nop insts executed +system.cpu.iew.exec_refs 587021920 # number of memory reference insts executed +system.cpu.iew.exec_branches 89037548 # Number of branches executed +system.cpu.iew.exec_stores 170451275 # Number of stores executed +system.cpu.iew.exec_rate 1.877200 # Inst execution rate +system.cpu.iew.wb_sent 1452636193 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1451747658 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1153420359 # num instructions producing a value +system.cpu.iew.wb_consumers 1204679279 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.866660 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.957537 # average fanout of values written-back +system.cpu.iew.wb_rate 1.874279 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.957450 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 124505734 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 119133058 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 2243671 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 3785118 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 760500151 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.958610 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.504084 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 3616115 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 757373332 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.966696 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.509453 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 241986025 31.82% 31.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 276568961 36.37% 68.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 42982436 5.65% 73.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 54874417 7.22% 81.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 19672131 2.59% 83.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 13330795 1.75% 85.39% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 30549094 4.02% 89.41% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 10561201 1.39% 90.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 69975091 9.20% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 239955150 31.68% 31.68% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 275777678 36.41% 68.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 42556583 5.62% 73.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 54728215 7.23% 80.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 19718156 2.60% 83.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 13293088 1.76% 85.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 30577311 4.04% 89.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 10491345 1.39% 90.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 70275806 9.28% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 760500151 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 757373332 # Number of insts commited each cycle system.cpu.commit.committedInsts 1485108088 # Number of instructions committed system.cpu.commit.committedOps 1489523282 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -440,374 +441,374 @@ system.cpu.commit.branches 86248928 # Nu system.cpu.commit.fp_insts 8452036 # Number of committed floating point instructions. system.cpu.commit.int_insts 1319476376 # Number of committed integer instructions. system.cpu.commit.function_calls 1206914 # Number of function calls committed. -system.cpu.commit.bw_lim_events 69975091 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 70275806 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 2304489206 # The number of ROB reads -system.cpu.rob.rob_writes 3245826636 # The number of ROB writes -system.cpu.timesIdled 25902 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 211544 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 2295688996 # The number of ROB reads +system.cpu.rob.rob_writes 3234318218 # The number of ROB writes +system.cpu.timesIdled 25993 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 207752 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1401188945 # Number of Instructions Simulated system.cpu.committedOps 1405604139 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 1401188945 # Number of Instructions Simulated -system.cpu.cpi 0.555568 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.555568 # CPI: Total CPI of All Threads -system.cpu.ipc 1.799961 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.799961 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1980833855 # number of integer regfile reads -system.cpu.int_regfile_writes 1276392600 # number of integer regfile writes -system.cpu.fp_regfile_reads 16967472 # number of floating regfile reads -system.cpu.fp_regfile_writes 10493116 # number of floating regfile writes -system.cpu.misc_regfile_reads 593429000 # number of misc regfile reads +system.cpu.cpi 0.552790 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.552790 # CPI: Total CPI of All Threads +system.cpu.ipc 1.809005 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.809005 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1979115545 # number of integer regfile reads +system.cpu.int_regfile_writes 1275157860 # number of integer regfile writes +system.cpu.fp_regfile_reads 16963296 # number of floating regfile reads +system.cpu.fp_regfile_writes 10491838 # number of floating regfile writes +system.cpu.misc_regfile_reads 592677531 # number of misc regfile reads system.cpu.misc_regfile_writes 2190883 # number of misc regfile writes -system.cpu.icache.replacements 221 # number of replacements -system.cpu.icache.tagsinuse 1044.865694 # Cycle average of tags in use -system.cpu.icache.total_refs 162870916 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1368 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 119057.687135 # Average number of references to valid blocks. +system.cpu.icache.replacements 190 # number of replacements +system.cpu.icache.tagsinuse 1035.892325 # Cycle average of tags in use +system.cpu.icache.total_refs 161931728 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 1331 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 121661.703982 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1044.865694 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.510188 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.510188 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 162870916 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 162870916 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 162870916 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 162870916 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 162870916 # number of overall hits -system.cpu.icache.overall_hits::total 162870916 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1977 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1977 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1977 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1977 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1977 # number of overall misses -system.cpu.icache.overall_misses::total 1977 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 82311500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 82311500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 82311500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 82311500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 82311500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 82311500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 162872893 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 162872893 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 162872893 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 162872893 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 162872893 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 162872893 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 1035.892325 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.505807 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.505807 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 161931728 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 161931728 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 161931728 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 161931728 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 161931728 # number of overall hits +system.cpu.icache.overall_hits::total 161931728 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1933 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1933 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1933 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1933 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1933 # number of overall misses +system.cpu.icache.overall_misses::total 1933 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 80019500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 80019500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 80019500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 80019500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 80019500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 80019500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 161933661 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 161933661 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 161933661 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 161933661 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 161933661 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 161933661 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000012 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000012 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000012 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000012 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000012 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000012 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 41634.547294 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 41634.547294 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 41634.547294 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 41634.547294 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 41634.547294 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 41634.547294 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 76 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 41396.533885 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 41396.533885 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 41396.533885 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 41396.533885 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 41396.533885 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 41396.533885 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 129 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 4 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 38 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 32.250000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 608 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 608 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 608 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 608 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 608 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 608 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1369 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1369 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1369 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1369 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1369 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1369 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 60349500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 60349500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 60349500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 60349500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 60349500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 60349500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 601 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 601 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 601 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 601 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 601 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 601 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1332 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1332 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1332 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1332 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1332 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1332 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 58461000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 58461000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 58461000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 58461000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 58461000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 58461000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000008 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000008 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000008 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000008 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000008 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000008 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 44082.907232 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 44082.907232 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 44082.907232 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 44082.907232 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 44082.907232 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 44082.907232 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 43889.639640 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 43889.639640 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 43889.639640 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 43889.639640 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 43889.639640 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 43889.639640 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 458014 # number of replacements -system.cpu.dcache.tagsinuse 4093.836666 # Cycle average of tags in use -system.cpu.dcache.total_refs 365740775 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 462110 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 791.458257 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 344026000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4093.836666 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999472 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999472 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 200780850 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 200780850 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 164958606 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 164958606 # number of WriteReq hits +system.cpu.l2cache.replacements 2556 # number of replacements +system.cpu.l2cache.tagsinuse 22450.499541 # Cycle average of tags in use +system.cpu.l2cache.total_refs 550174 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 24271 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 22.667958 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::writebacks 20742.731551 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 1060.708507 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 647.059483 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.633018 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.032370 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.019747 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.685135 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 134 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 196304 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 196438 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 443776 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 443776 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 240583 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 240583 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 134 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 436887 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 437021 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 134 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 436887 # number of overall hits +system.cpu.l2cache.overall_hits::total 437021 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 1198 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 4435 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 5633 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 21791 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 21791 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 1198 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 26226 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 27424 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 1198 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 26226 # number of overall misses +system.cpu.l2cache.overall_misses::total 27424 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 55773000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 468174000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 523947000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1550343500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1550343500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 55773000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 2018517500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 2074290500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 55773000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 2018517500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 2074290500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 1332 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 200739 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 202071 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 443776 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 443776 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 262374 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 262374 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 1332 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 463113 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 464445 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 1332 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 463113 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 464445 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.899399 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.022093 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.027876 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.083053 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.083053 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.899399 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.056630 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.059047 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.899399 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.056630 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.059047 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 46555.091820 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 105563.472379 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 93013.846973 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71146.046533 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71146.046533 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 46555.091820 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76966.273927 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 75637.780776 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 46555.091820 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76966.273927 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 75637.780776 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.writebacks::writebacks 2533 # number of writebacks +system.cpu.l2cache.writebacks::total 2533 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1198 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 4435 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 5633 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 21791 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 21791 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 1198 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 26226 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 27424 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 1198 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 26226 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 27424 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 40693954 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 412667734 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 453361688 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1276994111 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1276994111 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 40693954 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1689661845 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 1730355799 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 40693954 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1689661845 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 1730355799 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.899399 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.022093 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.027876 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.083053 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.083053 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.899399 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.056630 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.059047 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.899399 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.056630 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.059047 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 33968.242070 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 93047.967080 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 80483.168472 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58601.904961 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58601.904961 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 33968.242070 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64426.974949 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63096.404573 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 33968.242070 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64426.974949 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63096.404573 # average overall mshr miss latency +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.replacements 459017 # number of replacements +system.cpu.dcache.tagsinuse 4093.828969 # Cycle average of tags in use +system.cpu.dcache.total_refs 365038721 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 463113 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 788.228188 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 342772000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4093.828969 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999470 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999470 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 200081459 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 200081459 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 164955943 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 164955943 # number of WriteReq hits system.cpu.dcache.SwapReq_hits::cpu.data 1319 # number of SwapReq hits system.cpu.dcache.SwapReq_hits::total 1319 # number of SwapReq hits -system.cpu.dcache.demand_hits::cpu.data 365739456 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 365739456 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 365739456 # number of overall hits -system.cpu.dcache.overall_hits::total 365739456 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 929575 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 929575 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1888210 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1888210 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 365037402 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 365037402 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 365037402 # number of overall hits +system.cpu.dcache.overall_hits::total 365037402 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 927524 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 927524 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1890873 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1890873 # number of WriteReq misses system.cpu.dcache.SwapReq_misses::cpu.data 7 # number of SwapReq misses system.cpu.dcache.SwapReq_misses::total 7 # number of SwapReq misses -system.cpu.dcache.demand_misses::cpu.data 2817785 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2817785 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2817785 # number of overall misses -system.cpu.dcache.overall_misses::total 2817785 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 14994299000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 14994299000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 31871156950 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 31871156950 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 2818397 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2818397 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2818397 # number of overall misses +system.cpu.dcache.overall_misses::total 2818397 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 14988914500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 14988914500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 31918196457 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 31918196457 # number of WriteReq miss cycles system.cpu.dcache.SwapReq_miss_latency::cpu.data 122000 # number of SwapReq miss cycles system.cpu.dcache.SwapReq_miss_latency::total 122000 # number of SwapReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 46865455950 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 46865455950 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 46865455950 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 46865455950 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 201710425 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 201710425 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 46907110957 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 46907110957 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 46907110957 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 46907110957 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 201008983 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 201008983 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 166846816 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 166846816 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SwapReq_accesses::cpu.data 1326 # number of SwapReq accesses(hits+misses) system.cpu.dcache.SwapReq_accesses::total 1326 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 368557241 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 368557241 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 368557241 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 368557241 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004608 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.004608 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.011317 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.011317 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 367855799 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 367855799 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 367855799 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 367855799 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004614 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.004614 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.011333 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.011333 # miss rate for WriteReq accesses system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.005279 # miss rate for SwapReq accesses system.cpu.dcache.SwapReq_miss_rate::total 0.005279 # miss rate for SwapReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.007645 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.007645 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.007645 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.007645 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16130.273512 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 16130.273512 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 16879.031967 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 16879.031967 # average WriteReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.007662 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.007662 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.007662 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.007662 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16160.136557 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 16160.136557 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 16880.137617 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 16880.137617 # average WriteReq miss latency system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 17428.571429 # average SwapReq miss latency system.cpu.dcache.SwapReq_avg_miss_latency::total 17428.571429 # average SwapReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 16632.019813 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 16632.019813 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 16632.019813 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 16632.019813 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 577430 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 18 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 35655 # number of cycles access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 16643.187939 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 16643.187939 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 16643.187939 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 16643.187939 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 574305 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 10 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 35651 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 16.194924 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 18 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 16.109085 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 10 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 442964 # number of writebacks -system.cpu.dcache.writebacks::total 442964 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 729519 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 729519 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1626163 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1626163 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2355682 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2355682 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2355682 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2355682 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 200056 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 200056 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 262047 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 262047 # number of WriteReq MSHR misses +system.cpu.dcache.writebacks::writebacks 443776 # number of writebacks +system.cpu.dcache.writebacks::total 443776 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 726784 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 726784 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1628507 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1628507 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2355291 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2355291 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2355291 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2355291 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 200740 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 200740 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 262366 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 262366 # number of WriteReq MSHR misses system.cpu.dcache.SwapReq_mshr_misses::cpu.data 7 # number of SwapReq MSHR misses system.cpu.dcache.SwapReq_mshr_misses::total 7 # number of SwapReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 462103 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 462103 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 462103 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 462103 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2627957000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2627957000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4314187000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4314187000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 463106 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 463106 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 463106 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 463106 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2634282500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2634282500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4319277500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4319277500 # number of WriteReq MSHR miss cycles system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 108000 # number of SwapReq MSHR miss cycles system.cpu.dcache.SwapReq_mshr_miss_latency::total 108000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6942144000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6942144000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6942144000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6942144000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000992 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000992 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001571 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.001571 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6953560000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6953560000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6953560000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6953560000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000999 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000999 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001572 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.001572 # mshr miss rate for WriteReq accesses system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.005279 # mshr miss rate for SwapReq accesses system.cpu.dcache.SwapReq_mshr_miss_rate::total 0.005279 # mshr miss rate for SwapReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001254 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.001254 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001254 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.001254 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13136.106890 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13136.106890 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 16463.409236 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 16463.409236 # average WriteReq mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001259 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.001259 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001259 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.001259 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13122.857926 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13122.857926 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 16462.794341 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 16462.794341 # average WriteReq mshr miss latency system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 15428.571429 # average SwapReq mshr miss latency system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 15428.571429 # average SwapReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15022.936445 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 15022.936445 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15022.936445 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 15022.936445 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15015.050550 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 15015.050550 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15015.050550 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 15015.050550 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 2556 # number of replacements -system.cpu.l2cache.tagsinuse 22458.024259 # Cycle average of tags in use -system.cpu.l2cache.total_refs 548899 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 24278 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 22.608905 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 20744.377954 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 1070.274135 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 643.372169 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.633068 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.032662 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.019634 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.685365 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 165 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 195629 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 195794 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 442964 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 442964 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 240255 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 240255 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 165 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 435884 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 436049 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 165 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 435884 # number of overall hits -system.cpu.l2cache.overall_hits::total 436049 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 1204 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 4426 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 5630 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 21800 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 21800 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 1204 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 26226 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 27430 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 1204 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 26226 # number of overall misses -system.cpu.l2cache.overall_misses::total 27430 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 57312000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 469280500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 526592500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1549286000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1549286000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 57312000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 2018566500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 2075878500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 57312000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 2018566500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 2075878500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 1369 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 200055 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 201424 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 442964 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 442964 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 262055 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 262055 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 1369 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 462110 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 463479 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 1369 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 462110 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 463479 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.879474 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.022124 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.027951 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.083189 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.083189 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.879474 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.056753 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.059183 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.879474 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.056753 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.059183 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 47601.328904 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 106028.129236 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 93533.303730 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71068.165138 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71068.165138 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 47601.328904 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76968.142302 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 75679.128691 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 47601.328904 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76968.142302 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 75679.128691 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 2533 # number of writebacks -system.cpu.l2cache.writebacks::total 2533 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1204 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 4426 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 5630 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 21800 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 21800 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 1204 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 26226 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 27430 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 1204 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 26226 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 27430 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 42159963 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 413894207 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 456054170 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1275808135 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1275808135 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 42159963 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1689702342 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 1731862305 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 42159963 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1689702342 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 1731862305 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.879474 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.022124 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.027951 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.083189 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.083189 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.879474 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.056753 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.059183 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.879474 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.056753 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.059183 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 35016.580565 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 93514.280840 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 81004.293073 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58523.308945 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58523.308945 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 35016.580565 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64428.519103 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63137.524790 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 35016.580565 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64428.519103 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63137.524790 # average overall mshr miss latency -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/config.ini b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/config.ini index abf2e74d2..f6f519501 100644 --- a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/config.ini +++ b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/config.ini @@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a -clock=1 +clock=1000 init_param=0 kernel= load_addr_mask=1099511627775 @@ -30,7 +30,7 @@ system_port=system.membus.slave[0] [system.cpu] type=DerivO3CPU -children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload +children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -78,6 +78,7 @@ iewToFetchDelay=1 iewToRenameDelay=1 instShiftAmt=2 interrupts=system.cpu.interrupts +isa=system.cpu.isa issueToExecuteDelay=1 issueWidth=8 itb=system.cpu.itb @@ -129,17 +130,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=2 is_top_level=true -latency=1000 max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=2 size=262144 subblock_size=0 system=system @@ -158,7 +160,7 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=X86PagetableWalker -clock=1 +clock=500 system=system port=system.cpu.toL2Bus.slave[3] @@ -430,17 +432,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=2 is_top_level=true -latency=1000 max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=2 size=131072 subblock_size=0 system=system @@ -453,7 +456,7 @@ mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=X86LocalApic -clock=1 +clock=500 int_latency=1000 pio_addr=2305843009213693952 pio_latency=100000 @@ -462,6 +465,9 @@ int_master=system.membus.slave[2] int_slave=system.membus.master[2] pio=system.membus.master[1] +[system.cpu.isa] +type=X86ISA + [system.cpu.itb] type=X86TLB children=walker @@ -470,30 +476,31 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=X86PagetableWalker -clock=1 +clock=500 system=system port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] type=BaseCache addr_ranges=0:18446744073709551615 -assoc=2 +assoc=8 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=20 is_top_level=false -latency=1000 max_miss_count=0 -mshrs=10 +mshrs=20 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=20 size=2097152 subblock_size=0 system=system -tgts_per_mshr=5 +tgts_per_mshr=12 trace_addr=0 two_queue=false write_buffers=8 @@ -503,10 +510,10 @@ mem_side=system.membus.slave[1] [system.cpu.toL2Bus] type=CoherentBus block_size=64 -clock=1000 +clock=500 header_cycles=1 use_default_range=false -width=8 +width=32 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port @@ -521,7 +528,7 @@ egid=100 env= errout=cerr euid=100 -executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/gzip +executable=/projects/pd/randd/dist/cpu2000/binaries/x86/linux/gzip gid=100 input=cin max_stack_size=67108864 @@ -543,15 +550,28 @@ master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_s slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master [system.physmem] -type=SimpleMemory -clock=1 +type=SimpleDRAM +addr_mapping=openmap +banks_per_rank=8 +clock=1000 conf_table_reported=false -file= in_addr_map=true -latency=30000 -latency_var=0 +lines_per_rowbuffer=64 +mem_sched_policy=fcfs null=false +page_policy=open range=0:134217727 +ranks_per_channel=2 +read_buffer_size=32 +tBURST=4000 +tCL=14000 +tRCD=14000 +tREFI=7800000 +tRFC=300000 +tRP=14000 +tWTR=1000 +write_buffer_size=32 +write_thresh_perc=70 zero=false port=system.membus.master[0] diff --git a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout index dbf6b4770..48eb9aa0f 100755 --- a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout +++ b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout @@ -1,11 +1,9 @@ -Redirecting stdout to build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing/simout -Redirecting stderr to build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 10 2012 22:29:00 -gem5 started Sep 10 2012 22:44:55 -gem5 executing on ribera.cs.wisc.edu +gem5 compiled Oct 30 2012 11:14:29 +gem5 started Oct 30 2012 16:17:19 +gem5 executing on u200540-lin command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -20,10 +18,10 @@ Uncompressing Data info: Increasing stack size by one page. Uncompressed data 1048576 bytes in length Uncompressed data compared correctly -info: Increasing stack size by one page. Compressing Input Data, level 3 Compressed data 97831 bytes in length Uncompressing Data +info: Increasing stack size by one page. Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Compressing Input Data, level 5 @@ -42,4 +40,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 609566727000 because target called exit() +Exiting @ tick 607235830000 because target called exit() diff --git a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt index 43ee6670c..74f46e926 100644 --- a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt @@ -1,63 +1,63 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.610645 # Number of seconds simulated -sim_ticks 610645123000 # Number of ticks simulated -final_tick 610645123000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.607236 # Number of seconds simulated +sim_ticks 607235830000 # Number of ticks simulated +final_tick 607235830000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 90668 # Simulator instruction rate (inst/s) -host_op_rate 167061 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 62914134 # Simulator tick rate (ticks/s) -host_mem_usage 229848 # Number of bytes of host memory used -host_seconds 9706.01 # Real time elapsed on the host +host_inst_rate 71722 # Simulator instruction rate (inst/s) +host_op_rate 132152 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 49489751 # Simulator tick rate (ticks/s) +host_mem_usage 226812 # Number of bytes of host memory used +host_seconds 12269.93 # Real time elapsed on the host sim_insts 880025277 # Number of instructions simulated sim_ops 1621493925 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 58048 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1693312 # Number of bytes read from this memory -system.physmem.bytes_read::total 1751360 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 58048 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 58048 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 162176 # Number of bytes written to this memory -system.physmem.bytes_written::total 162176 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 907 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 26458 # Number of read requests responded to by this memory -system.physmem.num_reads::total 27365 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 2534 # Number of write requests responded to by this memory -system.physmem.num_writes::total 2534 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 95060 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2772989 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2868049 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 95060 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 95060 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 265581 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 265581 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 265581 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 95060 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2772989 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3133630 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 27367 # Total number of read requests seen -system.physmem.writeReqs 2534 # Total number of write requests seen -system.physmem.cpureqs 29901 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 1751360 # Total number of bytes read from memory -system.physmem.bytesWritten 162176 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 1751360 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 162176 # bytesWritten derated as per pkt->getSize() +system.physmem.bytes_read::cpu.inst 57472 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1693120 # Number of bytes read from this memory +system.physmem.bytes_read::total 1750592 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 57472 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 57472 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 162112 # Number of bytes written to this memory +system.physmem.bytes_written::total 162112 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 898 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 26455 # Number of read requests responded to by this memory +system.physmem.num_reads::total 27353 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 2533 # Number of write requests responded to by this memory +system.physmem.num_writes::total 2533 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 94645 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2788241 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2882887 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 94645 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 94645 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 266967 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 266967 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 266967 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 94645 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2788241 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3149854 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 27355 # Total number of read requests seen +system.physmem.writeReqs 2533 # Total number of write requests seen +system.physmem.cpureqs 29888 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 1750592 # Total number of bytes read from memory +system.physmem.bytesWritten 162112 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 1750592 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 162112 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 1748 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 1688 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 1674 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 1747 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 1689 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 1672 # Track reads on a per bank basis system.physmem.perBankRdReqs::3 1754 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 1756 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 1780 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 1754 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 1779 # Track reads on a per bank basis system.physmem.perBankRdReqs::6 1777 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 1811 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 1808 # Track reads on a per bank basis system.physmem.perBankRdReqs::8 1712 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 1665 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 1637 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 1661 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 1664 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 1638 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 1660 # Track reads on a per bank basis system.physmem.perBankRdReqs::12 1666 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 1670 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 1692 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 1668 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 1691 # Track reads on a per bank basis system.physmem.perBankRdReqs::15 1676 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 162 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 157 # Track writes on a per bank basis @@ -72,19 +72,19 @@ system.physmem.perBankWrReqs::9 158 # Tr system.physmem.perBankWrReqs::10 154 # Track writes on a per bank basis system.physmem.perBankWrReqs::11 153 # Track writes on a per bank basis system.physmem.perBankWrReqs::12 154 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 155 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 154 # Track writes on a per bank basis system.physmem.perBankWrReqs::14 156 # Track writes on a per bank basis system.physmem.perBankWrReqs::15 156 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 610645109000 # Total gap between requests +system.physmem.totGap 607235813000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 27367 # Categorize read packet sizes +system.physmem.readPktSize::6 27355 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -93,7 +93,7 @@ system.physmem.writePktSize::2 0 # ca system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 2534 # categorize write packet sizes +system.physmem.writePktSize::6 2533 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -105,11 +105,11 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 26902 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 346 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 97 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 20 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 26898 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 336 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 95 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 23 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -141,7 +141,7 @@ system.physmem.rdQLenPdf::32 0 # Wh system.physmem.wrQLenPdf::0 111 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 111 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 110 # What write queue length does an incoming req see system.physmem.wrQLenPdf::4 110 # What write queue length does an incoming req see system.physmem.wrQLenPdf::5 110 # What write queue length does an incoming req see system.physmem.wrQLenPdf::6 110 # What write queue length does an incoming req see @@ -171,264 +171,264 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 68648669 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 822368669 # Sum of mem lat for all requests -system.physmem.totBusLat 109468000 # Total cycles spent in databus access -system.physmem.totBankLat 644252000 # Total cycles spent in bank access -system.physmem.avgQLat 2508.45 # Average queueing delay per request -system.physmem.avgBankLat 23541.20 # Average bank access latency per request +system.physmem.totQLat 67414668 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 820820668 # Sum of mem lat for all requests +system.physmem.totBusLat 109420000 # Total cycles spent in databus access +system.physmem.totBankLat 643986000 # Total cycles spent in bank access +system.physmem.avgQLat 2464.44 # Average queueing delay per request +system.physmem.avgBankLat 23541.80 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 30049.65 # Average memory access latency -system.physmem.avgRdBW 2.87 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 30006.24 # Average memory access latency +system.physmem.avgRdBW 2.88 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.27 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 2.87 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 2.88 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.27 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time -system.physmem.avgWrQLen 9.42 # Average write queue length over time -system.physmem.readRowHits 17709 # Number of row buffer hits during reads -system.physmem.writeRowHits 1083 # Number of row buffer hits during writes -system.physmem.readRowHitRate 64.71 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 42.74 # Row buffer hit rate for writes -system.physmem.avgGap 20422230.33 # Average gap between requests +system.physmem.avgWrQLen 4.32 # Average write queue length over time +system.physmem.readRowHits 17706 # Number of row buffer hits during reads +system.physmem.writeRowHits 1086 # Number of row buffer hits during writes +system.physmem.readRowHitRate 64.73 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 42.87 # Row buffer hit rate for writes +system.physmem.avgGap 20317044.06 # Average gap between requests system.cpu.workload.num_syscalls 48 # Number of system calls -system.cpu.numCycles 1221290247 # number of cpu cycles simulated +system.cpu.numCycles 1214471661 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 153796448 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 153796448 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 26699295 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 76444965 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 76044325 # Number of BTB hits +system.cpu.BPredUnit.lookups 158566645 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 158566645 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 26386333 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 83466743 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 83279512 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 180218290 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1484873312 # Number of instructions fetch has processed -system.cpu.fetch.Branches 153796448 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 76044325 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 400561886 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 92153015 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 574855756 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 55 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 434 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 186235545 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 9536973 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1220934154 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.078258 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.273787 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 179036467 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1457944289 # Number of instructions fetch has processed +system.cpu.fetch.Branches 158566645 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 83279512 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 399021545 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 88092537 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 574509498 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 50 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 341 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 186960601 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 10940939 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1214117357 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.059847 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.253407 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 827594377 67.78% 67.78% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 24117068 1.98% 69.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 15648261 1.28% 71.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 17796387 1.46% 72.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 26716755 2.19% 74.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 18183763 1.49% 76.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 28386980 2.33% 78.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 39418545 3.23% 81.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 223072018 18.27% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 822311931 67.73% 67.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 26973525 2.22% 69.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 13085420 1.08% 71.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 20645432 1.70% 72.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 26636403 2.19% 74.92% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 18254688 1.50% 76.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 31306986 2.58% 79.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 39069186 3.22% 82.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 215833786 17.78% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1220934154 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.125929 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.215823 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 289407961 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 498246191 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 275145699 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 92836570 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 65297733 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 2356719721 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 65297733 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 337924282 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 123917110 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 2381 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 305534064 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 388258584 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2260509367 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 337 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 242606329 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 120880984 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 2627145665 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 5770220684 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 5770216108 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 4576 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 1214117357 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.130564 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.200476 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 288149545 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 497851788 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 274001581 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 92564987 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 61549456 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 2343342483 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 61549456 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 336776305 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 124136399 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 2472 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 303957244 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 387695481 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2247540252 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 338 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 242690737 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 120190709 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 2617793255 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 5721514338 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 5721508630 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 5708 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1886895257 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 740250408 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 92 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 92 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 731279841 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 542420235 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 220423040 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 348990798 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 145234295 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2013682993 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 521 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1784560921 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 286575 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 391758246 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 817229320 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 471 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1220934154 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.461636 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.419528 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 730897998 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 87 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 87 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 731315186 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 531685334 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 219218078 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 341957322 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 144669482 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1993566712 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 286 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1783999852 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 259167 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 371673921 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 759176081 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 236 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1214117357 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.469380 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.421908 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 365719162 29.95% 29.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 365027224 29.90% 59.85% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 234751927 19.23% 79.08% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 141361627 11.58% 90.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 60962306 4.99% 95.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 39637127 3.25% 98.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 10977510 0.90% 99.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1933125 0.16% 99.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 564146 0.05% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 360157334 29.66% 29.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 364096004 29.99% 59.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 234218772 19.29% 78.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 141579875 11.66% 90.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 60576135 4.99% 95.59% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 39770363 3.28% 98.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 11069235 0.91% 99.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 2042198 0.17% 99.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 607441 0.05% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1220934154 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1214117357 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 457693 15.95% 15.95% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 15.95% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 15.95% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 15.95% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 15.95% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 15.95% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 15.95% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 15.95% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 15.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 15.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 15.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 15.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 15.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 15.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 15.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 15.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 15.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 15.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 15.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 15.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 15.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 15.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 15.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 15.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 15.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 15.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 15.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 15.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 15.95% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 2209699 77.01% 92.96% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 202113 7.04% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 448044 15.51% 15.51% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 15.51% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 15.51% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 15.51% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 15.51% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 15.51% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 15.51% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 15.51% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 15.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 15.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 15.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 15.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 15.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 15.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 15.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 15.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 15.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 15.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 15.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 15.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 15.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 15.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 15.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 15.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 15.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 15.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 15.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 15.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 15.51% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2239769 77.53% 93.04% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 201121 6.96% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 46812464 2.62% 2.62% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1065891237 59.73% 62.35% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 62.35% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.35% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.35% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.35% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.35% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.35% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.35% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.35% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 479189352 26.85% 89.20% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 192667868 10.80% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 46812236 2.62% 2.62% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1065749303 59.74% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 478900937 26.84% 89.21% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 192537376 10.79% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1784560921 # Type of FU issued -system.cpu.iq.rate 1.461210 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2869505 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.001608 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 4793211641 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2405618854 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1725377736 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 435 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1480 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 90 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1740617772 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 190 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 209954463 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1783999852 # Type of FU issued +system.cpu.iq.rate 1.468951 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2888934 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.001619 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 4785264711 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2365417546 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1724692001 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 451 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 1804 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 116 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1740076331 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 219 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 209988104 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 123378114 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 38587 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 183844 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 32236983 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 112643213 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 39222 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 182717 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 31032021 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2078 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 49 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 2338 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 61 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 65297733 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1143885 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 111744 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2013683514 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 63490304 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 542420235 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 220423040 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 86 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 55193 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 2862 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 183844 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 2121921 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 24727534 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 26849455 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1766386720 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 474113432 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 18174201 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 61549456 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1140639 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 111456 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1993566998 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 62891461 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 531685334 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 219218078 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 82 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 54713 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 2863 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 182717 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 2045566 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 24470672 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 26516238 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1766182455 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 474610807 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 17817397 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 665931472 # number of memory reference insts executed -system.cpu.iew.exec_branches 110216269 # Number of branches executed -system.cpu.iew.exec_stores 191818040 # Number of stores executed -system.cpu.iew.exec_rate 1.446328 # Inst execution rate -system.cpu.iew.wb_sent 1726595079 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1725377826 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1268018973 # num instructions producing a value -system.cpu.iew.wb_consumers 1829950696 # num instructions consuming a value +system.cpu.iew.exec_refs 666317556 # number of memory reference insts executed +system.cpu.iew.exec_branches 110350315 # Number of branches executed +system.cpu.iew.exec_stores 191706749 # Number of stores executed +system.cpu.iew.exec_rate 1.454281 # Inst execution rate +system.cpu.iew.wb_sent 1725793430 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1724692117 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1267138729 # num instructions producing a value +system.cpu.iew.wb_consumers 1828924593 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.412750 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.692925 # average fanout of values written-back +system.cpu.iew.wb_rate 1.420117 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.692833 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 392192006 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 372074312 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 50 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 26699352 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1155636421 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.403118 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.832114 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 26386383 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1152567901 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.406853 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.830346 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 422545803 36.56% 36.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 413097230 35.75% 72.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 87361742 7.56% 79.87% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 122290747 10.58% 90.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 24514270 2.12% 92.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 22708378 1.97% 94.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 18848985 1.63% 96.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 12046038 1.04% 97.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 32223228 2.79% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 417955350 36.26% 36.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 415054079 36.01% 72.27% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 86939331 7.54% 79.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 122127082 10.60% 90.41% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 24184880 2.10% 92.51% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 25402622 2.20% 94.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 16383099 1.42% 96.14% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 12042950 1.04% 97.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 32478508 2.82% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1155636421 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1152567901 # Number of insts commited each cycle system.cpu.commit.committedInsts 880025277 # Number of instructions committed system.cpu.commit.committedOps 1621493925 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -439,148 +439,290 @@ system.cpu.commit.branches 107161574 # Nu system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. system.cpu.commit.int_insts 1621354435 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 32223228 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 32478508 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3137099124 # The number of ROB reads -system.cpu.rob.rob_writes 4092706915 # The number of ROB writes -system.cpu.timesIdled 59218 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 356093 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 3113657630 # The number of ROB reads +system.cpu.rob.rob_writes 4048721682 # The number of ROB writes +system.cpu.timesIdled 59087 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 354304 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 880025277 # Number of Instructions Simulated system.cpu.committedOps 1621493925 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 880025277 # Number of Instructions Simulated -system.cpu.cpi 1.387790 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.387790 # CPI: Total CPI of All Threads -system.cpu.ipc 0.720570 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.720570 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3541569732 # number of integer regfile reads -system.cpu.int_regfile_writes 1975385267 # number of integer regfile writes -system.cpu.fp_regfile_reads 90 # number of floating regfile reads -system.cpu.misc_regfile_reads 910403293 # number of misc regfile reads -system.cpu.icache.replacements 20 # number of replacements -system.cpu.icache.tagsinuse 822.205718 # Cycle average of tags in use -system.cpu.icache.total_refs 186234150 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 919 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 202648.694233 # Average number of references to valid blocks. +system.cpu.cpi 1.380042 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.380042 # CPI: Total CPI of All Threads +system.cpu.ipc 0.724616 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.724616 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3542913524 # number of integer regfile reads +system.cpu.int_regfile_writes 1974599259 # number of integer regfile writes +system.cpu.fp_regfile_reads 116 # number of floating regfile reads +system.cpu.misc_regfile_reads 910763104 # number of misc regfile reads +system.cpu.icache.replacements 26 # number of replacements +system.cpu.icache.tagsinuse 814.074374 # Cycle average of tags in use +system.cpu.icache.total_refs 186959214 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 915 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 204327.009836 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 822.205718 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.401468 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.401468 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 186234151 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 186234151 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 186234151 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 186234151 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 186234151 # number of overall hits -system.cpu.icache.overall_hits::total 186234151 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1394 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1394 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1394 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1394 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1394 # number of overall misses -system.cpu.icache.overall_misses::total 1394 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 63295000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 63295000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 63295000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 63295000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 63295000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 63295000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 186235545 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 186235545 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 186235545 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 186235545 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 186235545 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 186235545 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 814.074374 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.397497 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.397497 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 186959220 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 186959220 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 186959220 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 186959220 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 186959220 # number of overall hits +system.cpu.icache.overall_hits::total 186959220 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1381 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1381 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1381 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1381 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1381 # number of overall misses +system.cpu.icache.overall_misses::total 1381 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 63796500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 63796500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 63796500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 63796500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 63796500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 63796500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 186960601 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 186960601 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 186960601 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 186960601 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 186960601 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 186960601 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000007 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000007 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000007 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000007 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000007 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000007 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 45405.308465 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 45405.308465 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 45405.308465 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 45405.308465 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 45405.308465 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 45405.308465 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 127 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 46195.872556 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 46195.872556 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 46195.872556 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 46195.872556 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 46195.872556 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 46195.872556 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 249 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 3 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 42.333333 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 49.800000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 472 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 472 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 472 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 472 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 472 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 472 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 459 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 459 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 459 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 459 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 459 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 459 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 922 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 922 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 922 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 922 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 922 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 922 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 46053000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 46053000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 46053000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 46053000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 46053000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 46053000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 45726500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 45726500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 45726500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 45726500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 45726500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 45726500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000005 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000005 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000005 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000005 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000005 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000005 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 49949.023861 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 49949.023861 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 49949.023861 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 49949.023861 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 49949.023861 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 49949.023861 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 49594.902386 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 49594.902386 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 49594.902386 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 49594.902386 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 49594.902386 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 49594.902386 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 445401 # number of replacements -system.cpu.dcache.tagsinuse 4092.926016 # Cycle average of tags in use -system.cpu.dcache.total_refs 451884939 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 449497 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 1005.312469 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 828056000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4092.926016 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999250 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999250 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 263945150 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 263945150 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 187939786 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 187939786 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 451884936 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 451884936 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 451884936 # number of overall hits -system.cpu.dcache.overall_hits::total 451884936 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 210668 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 210668 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 246271 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 246271 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 456939 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 456939 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 456939 # number of overall misses -system.cpu.dcache.overall_misses::total 456939 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 3009925000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 3009925000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 4061663000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 4061663000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 7071588000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 7071588000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 7071588000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 7071588000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 264155818 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 264155818 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.replacements 2555 # number of replacements +system.cpu.l2cache.tagsinuse 22258.583797 # Cycle average of tags in use +system.cpu.l2cache.total_refs 531214 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 24187 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 21.962790 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::writebacks 20782.457781 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 797.735724 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 678.390292 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.634230 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.024345 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.020703 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.679278 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 17 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 199139 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 199156 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 428923 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 428923 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 7 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 7 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 224444 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 224444 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 17 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 423583 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 423600 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 17 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 423583 # number of overall hits +system.cpu.l2cache.overall_hits::total 423600 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 898 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 4559 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 5457 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 21898 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 21898 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 898 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 26457 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 27355 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 898 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 26457 # number of overall misses +system.cpu.l2cache.overall_misses::total 27355 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 44614000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 325457500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 370071500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1078494000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1078494000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 44614000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 1403951500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 1448565500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 44614000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 1403951500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 1448565500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 915 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 203698 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 204613 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 428923 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 428923 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 7 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 7 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 246342 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 246342 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 915 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 450040 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 450955 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 915 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 450040 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 450955 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.981421 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.022381 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.026670 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.088893 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.088893 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.981421 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.058788 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.060660 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.981421 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.058788 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.060660 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 49681.514477 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 71387.914016 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 67815.924501 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 49250.799160 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 49250.799160 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 49681.514477 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 53065.408021 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52954.322793 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 49681.514477 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 53065.408021 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52954.322793 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.writebacks::writebacks 2533 # number of writebacks +system.cpu.l2cache.writebacks::total 2533 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 898 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 4559 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 5457 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 21898 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 21898 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 898 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 26457 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 27355 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 898 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 26457 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 27355 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 33304929 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 267346944 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 300651873 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 795907105 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 795907105 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 33304929 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1063254049 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 1096558978 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 33304929 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1063254049 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 1096558978 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.981421 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.022381 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.026670 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.088893 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.088893 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.981421 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.058788 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.060660 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.981421 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.058788 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.060660 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37087.894209 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 58641.575784 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55094.717427 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36346.109462 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36346.109462 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37087.894209 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40188.005027 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40086.235716 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37087.894209 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40188.005027 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40086.235716 # average overall mshr miss latency +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.replacements 445942 # number of replacements +system.cpu.dcache.tagsinuse 4092.900957 # Cycle average of tags in use +system.cpu.dcache.total_refs 452347877 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 450038 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 1005.132627 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 828955000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4092.900957 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999243 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999243 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 264408234 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 264408234 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 187939636 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 187939636 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 452347870 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 452347870 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 452347870 # number of overall hits +system.cpu.dcache.overall_hits::total 452347870 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 211131 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 211131 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 246421 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 246421 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 457552 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 457552 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 457552 # number of overall misses +system.cpu.dcache.overall_misses::total 457552 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 3015479500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 3015479500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 4062855500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 4062855500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 7078335000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 7078335000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 7078335000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 7078335000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 264619365 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 264619365 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 188186057 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 188186057 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 452341875 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 452341875 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 452341875 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 452341875 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 452805422 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 452805422 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 452805422 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 452805422 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000798 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000798 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001309 # miss rate for WriteReq accesses @@ -589,206 +731,64 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.001010 system.cpu.dcache.demand_miss_rate::total 0.001010 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.001010 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.001010 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14287.528243 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14287.528243 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 16492.656464 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 16492.656464 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 15476.000079 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 15476.000079 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 15476.000079 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 15476.000079 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 339 # number of cycles access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14282.504701 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14282.504701 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 16487.456426 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 16487.456426 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 15470.012152 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 15470.012152 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 15470.012152 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 15470.012152 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 438 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 37 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 42 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.162162 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 10.428571 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 428512 # number of writebacks -system.cpu.dcache.writebacks::total 428512 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 7369 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 7369 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 67 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 67 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 7436 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 7436 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 7436 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 7436 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 203299 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 203299 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 246204 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 246204 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 449503 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 449503 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 449503 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 449503 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2518009500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2518009500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3568493000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3568493000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6086502500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6086502500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6086502500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6086502500 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 428923 # number of writebacks +system.cpu.dcache.writebacks::total 428923 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 7428 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 7428 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 77 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 77 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 7505 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 7505 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 7505 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 7505 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 203703 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 203703 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 246344 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 246344 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 450047 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 450047 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 450047 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 450047 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2522412000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2522412000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3569338500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3569338500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6091750500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6091750500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6091750500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6091750500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000770 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000770 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001308 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.001308 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001309 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.001309 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000994 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.000994 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000994 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000994 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12385.744642 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12385.744642 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14494.049650 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14494.049650 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13540.515859 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 13540.515859 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13540.515859 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 13540.515859 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12382.792595 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12382.792595 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14489.244715 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14489.244715 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13535.809593 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 13535.809593 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13535.809593 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 13535.809593 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 2556 # number of replacements -system.cpu.l2cache.tagsinuse 22261.498307 # Cycle average of tags in use -system.cpu.l2cache.total_refs 530423 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 24197 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 21.921023 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 20782.532445 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 804.542121 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 674.423741 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.634233 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.024553 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.020582 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.679367 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 12 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 198746 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 198758 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 428512 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 428512 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 3 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 3 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 224294 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 224294 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 12 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 423040 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 423052 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 12 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 423040 # number of overall hits -system.cpu.l2cache.overall_hits::total 423052 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 907 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 4543 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 5450 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 21917 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 21917 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 907 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 26460 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 27367 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 907 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 26460 # number of overall misses -system.cpu.l2cache.overall_misses::total 27367 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 44997500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 325370000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 370367500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1079389000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1079389000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 44997500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 1404759000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 1449756500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 44997500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 1404759000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 1449756500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 919 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 203289 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 204208 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 428512 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 428512 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 3 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 3 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 246211 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 246211 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 919 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 449500 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 450419 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 919 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 449500 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 450419 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.986942 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.022347 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.026688 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.089017 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.089017 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.986942 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.058865 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.060759 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.986942 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.058865 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.060759 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 49611.356119 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 71620.074840 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 67957.339450 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 49248.939180 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 49248.939180 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 49611.356119 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 53089.909297 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52974.622721 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 49611.356119 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 53089.909297 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52974.622721 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 2534 # number of writebacks -system.cpu.l2cache.writebacks::total 2534 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 907 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 4543 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 5450 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 21917 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 21917 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 907 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 26460 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 27367 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 907 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 26460 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 27367 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 33582421 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 267466906 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 301049327 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 797222639 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 797222639 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 33582421 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1064689545 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 1098271966 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 33582421 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1064689545 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 1098271966 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.986942 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.022347 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.026688 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.089017 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.089017 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.986942 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.058865 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.060759 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.986942 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.058865 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.060759 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37025.822492 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 58874.511556 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55238.408624 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36374.624219 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36374.624219 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37025.822492 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40237.700113 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40131.251727 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37025.822492 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40237.700113 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40131.251727 # average overall mshr miss latency -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini index 9dfc48f3b..31bcf2795 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini @@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a -clock=1 +clock=1000 init_param=0 kernel= load_addr_mask=1099511627775 @@ -30,7 +30,7 @@ system_port=system.membus.slave[0] [system.cpu] type=DerivO3CPU -children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload +children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -78,6 +78,7 @@ iewToFetchDelay=1 iewToRenameDelay=1 instShiftAmt=2 interrupts=system.cpu.interrupts +isa=system.cpu.isa issueToExecuteDelay=1 issueWidth=8 itb=system.cpu.itb @@ -129,18 +130,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=262144 subblock_size=0 system=system @@ -159,7 +160,7 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=ArmTableWalker -clock=1 +clock=500 num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[3] @@ -432,18 +433,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=131072 subblock_size=0 system=system @@ -457,6 +458,23 @@ mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=ArmInterrupts +[system.cpu.isa] +type=ArmISA +fpsid=1090793632 +id_isar0=34607377 +id_isar1=34677009 +id_isar2=555950401 +id_isar3=17899825 +id_isar4=268501314 +id_isar5=0 +id_mmfr0=3 +id_mmfr1=0 +id_mmfr2=19070976 +id_mmfr3=4027589137 +id_pfr0=49 +id_pfr1=1 +midr=890224640 + [system.cpu.itb] type=ArmTLB children=walker @@ -465,7 +483,7 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=ArmTableWalker -clock=1 +clock=500 num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[2] @@ -473,24 +491,24 @@ port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] type=BaseCache addr_ranges=0:18446744073709551615 -assoc=2 +assoc=8 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=20 is_top_level=false max_miss_count=0 -mshrs=10 +mshrs=20 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=20 size=2097152 subblock_size=0 system=system -tgts_per_mshr=5 +tgts_per_mshr=12 trace_addr=0 two_queue=false write_buffers=8 @@ -500,10 +518,10 @@ mem_side=system.membus.slave[1] [system.cpu.toL2Bus] type=CoherentBus block_size=64 -clock=1000 +clock=500 header_cycles=1 use_default_range=false -width=8 +width=32 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port @@ -540,15 +558,28 @@ master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] -type=SimpleMemory -bandwidth=73.000000 -clock=1 +type=SimpleDRAM +addr_mapping=openmap +banks_per_rank=8 +clock=1000 conf_table_reported=false in_addr_map=true -latency=30000 -latency_var=0 +lines_per_rowbuffer=64 +mem_sched_policy=fcfs null=false +page_policy=open range=0:268435455 +ranks_per_channel=2 +read_buffer_size=32 +tBURST=4000 +tCL=14000 +tRCD=14000 +tREFI=7800000 +tRFC=300000 +tRP=14000 +tWTR=1000 +write_buffer_size=32 +write_thresh_perc=70 zero=false port=system.membus.master[0] diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout index 62518a9bb..15ba3aa9f 100755 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout @@ -1,8 +1,8 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 21 2012 11:19:00 -gem5 started Sep 21 2012 11:53:48 +gem5 compiled Oct 30 2012 11:20:14 +gem5 started Oct 30 2012 19:23:29 gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second @@ -23,4 +23,4 @@ simplex iterations : 2663 flow value : 3080014995 checksum : 68389 optimal -Exiting @ tick 28505597000 because target called exit() +Exiting @ tick 26786364500 because target called exit() diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt index 7f5474242..c26c8db9e 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt @@ -1,57 +1,57 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.027092 # Number of seconds simulated -sim_ticks 27092156000 # Number of ticks simulated -final_tick 27092156000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.026786 # Number of seconds simulated +sim_ticks 26786364500 # Number of ticks simulated +final_tick 26786364500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 163409 # Simulator instruction rate (inst/s) -host_op_rate 164582 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 48864627 # Simulator tick rate (ticks/s) -host_mem_usage 366512 # Number of bytes of host memory used -host_seconds 554.43 # Real time elapsed on the host -sim_insts 90599363 # Number of instructions simulated -sim_ops 91249916 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 45696 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 947584 # Number of bytes read from this memory -system.physmem.bytes_read::total 993280 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 45696 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 45696 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 714 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 14806 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15520 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1686687 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 34976323 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 36663011 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1686687 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1686687 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1686687 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 34976323 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 36663011 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15520 # Total number of read requests seen +host_inst_rate 151377 # Simulator instruction rate (inst/s) +host_op_rate 152464 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 44755705 # Simulator tick rate (ticks/s) +host_mem_usage 363280 # Number of bytes of host memory used +host_seconds 598.50 # Real time elapsed on the host +sim_insts 90599358 # Number of instructions simulated +sim_ops 91249911 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 45248 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 947520 # Number of bytes read from this memory +system.physmem.bytes_read::total 992768 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 45248 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 45248 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 707 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 14805 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15512 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1689218 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 35373221 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 37062439 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1689218 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1689218 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1689218 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 35373221 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 37062439 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15512 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 15520 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 993280 # Total number of bytes read from memory +system.physmem.cpureqs 15514 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 992768 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 993280 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 992768 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 1012 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 1000 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 965 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 878 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 903 # Track reads on a per bank basis +system.physmem.neitherReadNorWrite 2 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 1014 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 997 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 967 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 877 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 902 # Track reads on a per bank basis system.physmem.perBankRdReqs::5 974 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 937 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 938 # Track reads on a per bank basis system.physmem.perBankRdReqs::7 992 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 942 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 1013 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 941 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 1012 # Track reads on a per bank basis system.physmem.perBankRdReqs::10 1040 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 931 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 935 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 1022 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 999 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 977 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 928 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 933 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 1021 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 998 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 978 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis @@ -70,14 +70,14 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 27092026500 # Total gap between requests +system.physmem.totGap 26786185500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 15520 # Categorize read packet sizes +system.physmem.readPktSize::6 15512 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -95,16 +95,16 @@ system.physmem.neitherpktsize::2 0 # ca system.physmem.neitherpktsize::3 0 # categorize neither packet sizes system.physmem.neitherpktsize::4 0 # categorize neither packet sizes system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 0 # categorize neither packet sizes +system.physmem.neitherpktsize::6 2 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 10854 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 4463 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 174 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 17 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 10748 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 4565 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 172 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 16 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see @@ -164,27 +164,27 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 41952001 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 275602001 # Sum of mem lat for all requests -system.physmem.totBusLat 62080000 # Total cycles spent in databus access -system.physmem.totBankLat 171570000 # Total cycles spent in bank access -system.physmem.avgQLat 2703.09 # Average queueing delay per request -system.physmem.avgBankLat 11054.77 # Average bank access latency per request +system.physmem.totQLat 45050979 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 279102979 # Sum of mem lat for all requests +system.physmem.totBusLat 62048000 # Total cycles spent in databus access +system.physmem.totBankLat 172004000 # Total cycles spent in bank access +system.physmem.avgQLat 2904.27 # Average queueing delay per request +system.physmem.avgBankLat 11088.45 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 17757.86 # Average memory access latency -system.physmem.avgRdBW 36.66 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 17992.71 # Average memory access latency +system.physmem.avgRdBW 37.06 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 36.66 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 37.06 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.23 # Data bus utilization in percentage system.physmem.avgRdQLen 0.01 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 15093 # Number of row buffer hits during reads +system.physmem.readRowHits 15087 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 97.25 # Row buffer hit rate for reads +system.physmem.readRowHitRate 97.26 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 1745620.26 # Average gap between requests +system.physmem.avgGap 1726804.12 # Average gap between requests system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -228,569 +228,451 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 442 # Number of system calls -system.cpu.numCycles 54184313 # number of cpu cycles simulated +system.cpu.numCycles 53572730 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 26986209 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 22240935 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 891955 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 11647054 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 11461257 # Number of BTB hits +system.cpu.BPredUnit.lookups 26681190 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 22001511 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 842165 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 11371976 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 11281654 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 72758 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 485 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 14421407 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 129482789 # Number of instructions fetch has processed -system.cpu.fetch.Branches 26986209 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 11534015 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 24364148 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 4949387 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 11145499 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 135 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 27 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 33 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 14072424 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 353920 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 53972527 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.416768 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.215873 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 70159 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 177 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 14169802 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 127871795 # Number of instructions fetch has processed +system.cpu.fetch.Branches 26681190 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 11351813 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 24032420 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 4759415 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 11256916 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 95 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 11 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 9 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 13841949 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 329938 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 53360207 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.412919 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.215578 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 29646325 54.93% 54.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 3454402 6.40% 61.33% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2035756 3.77% 65.10% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1585198 2.94% 68.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1689643 3.13% 71.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 2992855 5.55% 76.71% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1501294 2.78% 79.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1109449 2.06% 81.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 9957605 18.45% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 29366337 55.03% 55.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 3387610 6.35% 61.38% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2027655 3.80% 65.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1555895 2.92% 68.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1666559 3.12% 71.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 2918525 5.47% 76.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1512890 2.84% 79.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1090822 2.04% 81.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 9833914 18.43% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 53972527 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.498045 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.389673 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 17207234 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 9007840 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 22744655 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 980413 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 4032385 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 4494708 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 9020 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 127545337 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 43010 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 4032385 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 19020781 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 3479230 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 185856 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 21813074 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 5441201 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 124457435 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 13 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 413531 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4571711 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 1235 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 145128165 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 542105971 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 542097092 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 8879 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 107429490 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 37698675 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 6572 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 6570 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12467133 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 29726886 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 5575716 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 2113972 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1267479 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 119141743 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 10445 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 105694934 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 87169 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 27699731 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 68149614 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 314 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 53972527 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.958310 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.906959 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 53360207 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.498037 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.386882 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 16933273 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 9104448 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 22449831 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 980264 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3892391 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 4441470 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 8659 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 126048465 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 42747 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3892391 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 18713903 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 3544404 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 187474 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 21547168 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 5474867 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 123140443 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 22 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 417251 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4594278 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 1244 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 143600920 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 536395589 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 536390601 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 4988 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 107429482 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 36171438 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 6558 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 6556 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12502916 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 29470902 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 5524793 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 2121904 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1282766 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 118150173 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 10438 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 105160593 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 79722 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 26714603 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 65515716 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 308 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 53360207 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.970768 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.910908 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 15655199 29.01% 29.01% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 11785517 21.84% 50.84% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 8331092 15.44% 66.28% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 6816137 12.63% 78.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4950230 9.17% 88.08% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2999113 5.56% 93.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 2477964 4.59% 98.23% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 523647 0.97% 99.20% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 433628 0.80% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 15336122 28.74% 28.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 11634873 21.80% 50.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 8272987 15.50% 66.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 6735590 12.62% 78.67% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4978396 9.33% 88.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2962958 5.55% 93.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 2475458 4.64% 98.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 518730 0.97% 99.17% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 445093 0.83% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 53972527 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 53360207 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 46062 6.88% 6.88% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 27 0.00% 6.88% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 6.88% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.88% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.88% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.88% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 6.88% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.88% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 6.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 6.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.88% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 347309 51.84% 58.72% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 276528 41.28% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 45281 6.85% 6.85% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 27 0.00% 6.85% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 6.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 6.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 6.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 6.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.85% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 340422 51.49% 58.35% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 275350 41.65% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 74789995 70.76% 70.76% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 10964 0.01% 70.77% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.77% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.77% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.77% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.77% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.77% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.77% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.77% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.77% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.77% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.77% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.77% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.77% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.77% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.77% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.77% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.77% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.77% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.77% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.77% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.77% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 1 0.00% 70.77% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 273 0.00% 70.77% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.77% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 352 0.00% 70.77% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.77% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 4 0.00% 70.77% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.77% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 25743831 24.36% 95.13% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 5149514 4.87% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 74420683 70.77% 70.77% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 10977 0.01% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 1 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 148 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 190 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 4 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 25610261 24.35% 95.13% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 5118329 4.87% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 105694934 # Type of FU issued -system.cpu.iq.rate 1.950656 # Inst issue rate -system.cpu.iq.fu_busy_cnt 669926 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.006338 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 266118166 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 146855539 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 103065096 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 1324 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1913 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 572 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 106364200 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 660 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 431890 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 105160593 # Type of FU issued +system.cpu.iq.rate 1.962950 # Inst issue rate +system.cpu.iq.fu_busy_cnt 661080 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.006286 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 264421445 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 144879638 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 102686211 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 750 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 1049 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 331 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 105821300 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 373 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 443954 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 7151007 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 8111 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 6407 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 828959 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 6895024 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 7123 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 6272 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 778037 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 2 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 30712 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 31249 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 4032385 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 880978 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 122273 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 119164915 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 339993 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 29726886 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 5575716 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 6543 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 65097 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 6980 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 6407 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 480710 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 474427 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 955137 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 104665581 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 25412111 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1029353 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3892391 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 925499 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 127080 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 118173306 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 309093 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 29470902 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 5524793 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 6532 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 66339 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 6977 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 6272 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 446356 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 445453 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 891809 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 104181304 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 25288567 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 979289 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 12727 # number of nop insts executed -system.cpu.iew.exec_refs 30497033 # number of memory reference insts executed -system.cpu.iew.exec_branches 21398144 # Number of branches executed -system.cpu.iew.exec_stores 5084922 # Number of stores executed -system.cpu.iew.exec_rate 1.931658 # Inst execution rate -system.cpu.iew.wb_sent 103359257 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 103065668 # cumulative count of insts written-back -system.cpu.iew.wb_producers 62382767 # num instructions producing a value -system.cpu.iew.wb_consumers 104584630 # num instructions consuming a value +system.cpu.iew.exec_nop 12695 # number of nop insts executed +system.cpu.iew.exec_refs 30349931 # number of memory reference insts executed +system.cpu.iew.exec_branches 21325057 # Number of branches executed +system.cpu.iew.exec_stores 5061364 # Number of stores executed +system.cpu.iew.exec_rate 1.944670 # Inst execution rate +system.cpu.iew.wb_sent 102965645 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 102686542 # cumulative count of insts written-back +system.cpu.iew.wb_producers 62242061 # num instructions producing a value +system.cpu.iew.wb_consumers 104289210 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.902131 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.596481 # average fanout of values written-back +system.cpu.iew.wb_rate 1.916769 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.596822 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 27905407 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 10131 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 883062 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 49940143 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.827438 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.524426 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 26913567 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 10130 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 833602 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 49467817 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.844887 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.541636 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 20246507 40.54% 40.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 13253757 26.54% 67.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4242903 8.50% 75.58% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 3506121 7.02% 82.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1547134 3.10% 85.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 741508 1.48% 87.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 927602 1.86% 89.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 253977 0.51% 89.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5220634 10.45% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 19986876 40.40% 40.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 13133000 26.55% 66.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4163273 8.42% 75.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 3434953 6.94% 82.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1533681 3.10% 85.41% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 739386 1.49% 86.91% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 948988 1.92% 88.83% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 248747 0.50% 89.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5278913 10.67% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 49940143 # Number of insts commited each cycle -system.cpu.commit.committedInsts 90611972 # Number of instructions committed -system.cpu.commit.committedOps 91262525 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 49467817 # Number of insts commited each cycle +system.cpu.commit.committedInsts 90611967 # Number of instructions committed +system.cpu.commit.committedOps 91262520 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 27322636 # Number of memory references committed -system.cpu.commit.loads 22575879 # Number of loads committed +system.cpu.commit.refs 27322634 # Number of memory references committed +system.cpu.commit.loads 22575878 # Number of loads committed system.cpu.commit.membars 3888 # Number of memory barriers committed -system.cpu.commit.branches 18734217 # Number of branches committed +system.cpu.commit.branches 18734216 # Number of branches committed system.cpu.commit.fp_insts 48 # Number of committed floating point instructions. -system.cpu.commit.int_insts 72533326 # Number of committed integer instructions. +system.cpu.commit.int_insts 72533322 # Number of committed integer instructions. system.cpu.commit.function_calls 56148 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5220634 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5278913 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 163881707 # The number of ROB reads -system.cpu.rob.rob_writes 242387570 # The number of ROB writes -system.cpu.timesIdled 40508 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 211786 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 90599363 # Number of Instructions Simulated -system.cpu.committedOps 91249916 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 90599363 # Number of Instructions Simulated -system.cpu.cpi 0.598065 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.598065 # CPI: Total CPI of All Threads -system.cpu.ipc 1.672059 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.672059 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 497610089 # number of integer regfile reads -system.cpu.int_regfile_writes 120987803 # number of integer regfile writes -system.cpu.fp_regfile_reads 263 # number of floating regfile reads -system.cpu.fp_regfile_writes 760 # number of floating regfile writes -system.cpu.misc_regfile_reads 183141130 # number of misc regfile reads -system.cpu.misc_regfile_writes 11610 # number of misc regfile writes -system.cpu.icache.replacements 2 # number of replacements -system.cpu.icache.tagsinuse 641.121517 # Cycle average of tags in use -system.cpu.icache.total_refs 14071405 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 743 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 18938.633917 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 162359257 # The number of ROB reads +system.cpu.rob.rob_writes 240263976 # The number of ROB writes +system.cpu.timesIdled 43500 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 212523 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 90599358 # Number of Instructions Simulated +system.cpu.committedOps 91249911 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 90599358 # Number of Instructions Simulated +system.cpu.cpi 0.591315 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.591315 # CPI: Total CPI of All Threads +system.cpu.ipc 1.691147 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.691147 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 495578845 # number of integer regfile reads +system.cpu.int_regfile_writes 120555497 # number of integer regfile writes +system.cpu.fp_regfile_reads 176 # number of floating regfile reads +system.cpu.fp_regfile_writes 427 # number of floating regfile writes +system.cpu.misc_regfile_reads 181219036 # number of misc regfile reads +system.cpu.misc_regfile_writes 11608 # number of misc regfile writes +system.cpu.icache.replacements 4 # number of replacements +system.cpu.icache.tagsinuse 632.599736 # Cycle average of tags in use +system.cpu.icache.total_refs 13840965 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 735 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 18831.244898 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 641.121517 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.313048 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.313048 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 14071405 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 14071405 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 14071405 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 14071405 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 14071405 # number of overall hits -system.cpu.icache.overall_hits::total 14071405 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1017 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1017 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1017 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1017 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1017 # number of overall misses -system.cpu.icache.overall_misses::total 1017 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 47244499 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 47244499 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 47244499 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 47244499 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 47244499 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 47244499 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 14072422 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 14072422 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 14072422 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 14072422 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 14072422 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 14072422 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000072 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000072 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000072 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000072 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000072 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000072 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 46454.767945 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 46454.767945 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 46454.767945 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 46454.767945 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 46454.767945 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 46454.767945 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 500 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 632.599736 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.308887 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.308887 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 13840965 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 13840965 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 13840965 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 13840965 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 13840965 # number of overall hits +system.cpu.icache.overall_hits::total 13840965 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 983 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 983 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 983 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 983 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 983 # number of overall misses +system.cpu.icache.overall_misses::total 983 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 48291499 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 48291499 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 48291499 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 48291499 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 48291499 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 48291499 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 13841948 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 13841948 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 13841948 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 13841948 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 13841948 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 13841948 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000071 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000071 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000071 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000071 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000071 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000071 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49126.652085 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 49126.652085 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 49126.652085 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 49126.652085 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 49126.652085 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 49126.652085 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 1099 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 11 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 9 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 45.454545 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 122.111111 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 274 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 274 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 274 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 274 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 274 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 274 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 743 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 743 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 743 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 743 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 743 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 743 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 36064499 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 36064499 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 36064499 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 36064499 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 36064499 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 36064499 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 244 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 244 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 244 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 244 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 244 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 244 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 739 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 739 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 739 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 739 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 739 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 739 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 36763999 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 36763999 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 36763999 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 36763999 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 36763999 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 36763999 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000053 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000053 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000053 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 48539.029610 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 48539.029610 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 48539.029610 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 48539.029610 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 48539.029610 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 48539.029610 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 49748.307172 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 49748.307172 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 49748.307172 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 49748.307172 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 49748.307172 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 49748.307172 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 943610 # number of replacements -system.cpu.dcache.tagsinuse 3668.756958 # Cycle average of tags in use -system.cpu.dcache.total_refs 28277834 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 947706 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 29.838192 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 8133068000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 3668.756958 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.895693 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.895693 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 23721969 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 23721969 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 4544209 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4544209 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 5856 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 5856 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 5800 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 5800 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 28266178 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 28266178 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 28266178 # number of overall hits -system.cpu.dcache.overall_hits::total 28266178 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1182969 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1182969 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 190772 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 190772 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 6 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 6 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1373741 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1373741 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1373741 # number of overall misses -system.cpu.dcache.overall_misses::total 1373741 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 13927378500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 13927378500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 5211268429 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 5211268429 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 191000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 191000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 19138646929 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 19138646929 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 19138646929 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 19138646929 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 24904938 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 24904938 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5862 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 5862 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 5800 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 5800 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 29639919 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 29639919 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 29639919 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 29639919 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.047499 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.047499 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.040290 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.040290 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001024 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.001024 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.046348 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.046348 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.046348 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.046348 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11773.240465 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 11773.240465 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27316.736361 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 27316.736361 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 31833.333333 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 31833.333333 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 13931.772386 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 13931.772386 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 13931.772386 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 13931.772386 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 151113 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 23634 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 6.393882 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 942971 # number of writebacks -system.cpu.dcache.writebacks::total 942971 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 275787 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 275787 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 150248 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 150248 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 6 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 6 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 426035 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 426035 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 426035 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 426035 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 907182 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 907182 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 40524 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 40524 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 947706 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 947706 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 947706 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 947706 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10023226500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 10023226500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 922752968 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 922752968 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10945979468 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10945979468 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10945979468 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10945979468 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.036426 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.036426 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.008558 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.008558 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.031974 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.031974 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.031974 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.031974 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11048.749314 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11048.749314 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22770.530254 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22770.530254 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11549.973798 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 11549.973798 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11549.973798 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 11549.973798 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 10724.733108 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1834762 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 15503 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 118.348836 # Average number of references to valid blocks. +system.cpu.l2cache.tagsinuse 10757.788342 # Cycle average of tags in use +system.cpu.l2cache.total_refs 1831577 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 15495 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 118.204389 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 9870.615236 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 623.470728 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 230.647144 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.301227 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.019027 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.007039 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.327293 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 28 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 906888 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 906916 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 942971 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 942971 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 26002 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 26002 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 28 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 932890 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 932918 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 28 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 932890 # number of overall hits -system.cpu.l2cache.overall_hits::total 932918 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 715 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 279 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 994 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 14537 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 14537 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 715 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 14816 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 15531 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 715 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 14816 # number of overall misses -system.cpu.l2cache.overall_misses::total 15531 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 35034500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 14031000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 49065500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 601080500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 601080500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 35034500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 615111500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 650146000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 35034500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 615111500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 650146000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 743 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 907167 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 907910 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 942971 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 942971 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 40539 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 40539 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 743 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 947706 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 948449 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 743 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 947706 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 948449 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.962315 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000308 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.001095 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.358593 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.358593 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.962315 # miss rate for demand accesses +system.cpu.l2cache.occ_blocks::writebacks 9910.182329 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 617.983134 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 229.622878 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.302435 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.018859 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.007008 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.328302 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 27 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 903798 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 903825 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 942892 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 942892 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 2 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 2 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 28978 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 28978 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 27 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 932776 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 932803 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 27 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 932776 # number of overall hits +system.cpu.l2cache.overall_hits::total 932803 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 708 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 277 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 985 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 2 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 2 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 14538 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 14538 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 708 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 14815 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 15523 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 708 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 14815 # number of overall misses +system.cpu.l2cache.overall_misses::total 15523 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 35741000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 14541500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 50282500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 602811500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 602811500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 35741000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 617353000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 653094000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 35741000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 617353000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 653094000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 735 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 904075 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 904810 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 942892 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 942892 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 4 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 4 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 43516 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 43516 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 735 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 947591 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 948326 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 735 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 947591 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 948326 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.963265 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000306 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.001089 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.500000 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.500000 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.334084 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.334084 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.963265 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.015634 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.016375 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.962315 # miss rate for overall accesses +system.cpu.l2cache.demand_miss_rate::total 0.016369 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.963265 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.015634 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.016375 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 48999.300699 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 50290.322581 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 49361.670020 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 41348.318085 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 41348.318085 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 48999.300699 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 41516.704914 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 41861.180864 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 48999.300699 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 41516.704914 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 41861.180864 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::total 0.016369 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50481.638418 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52496.389892 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 51048.223350 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 41464.541202 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 41464.541202 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50481.638418 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 41670.806615 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 42072.666366 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50481.638418 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 41670.806615 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 42072.666366 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -808,50 +690,184 @@ system.cpu.l2cache.demand_mshr_hits::total 11 # system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 10 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 11 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 714 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 269 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 983 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14537 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 14537 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 714 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 14806 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 15520 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 714 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 14806 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 15520 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 26001093 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 10248888 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 36249981 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 418962782 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 418962782 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 26001093 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 429211670 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 455212763 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 26001093 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 429211670 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 455212763 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.960969 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000297 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001083 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.358593 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.358593 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.960969 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015623 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.016364 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.960969 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015623 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.016364 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 36416.096639 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 38099.955390 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 36876.888098 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 28820.443145 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 28820.443145 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 36416.096639 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 28989.036202 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 29330.719265 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 36416.096639 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 28989.036202 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 29330.719265 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 707 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 267 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 974 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 2 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14538 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 14538 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 707 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 14805 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 15512 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 707 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 14805 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 15512 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 26819084 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 10783379 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 37602463 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 20002 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 20002 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 420800342 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 420800342 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 26819084 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 431583721 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 458402805 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 26819084 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 431583721 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 458402805 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.961905 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000295 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001076 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.500000 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.334084 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.334084 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.961905 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015624 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.016357 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.961905 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015624 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.016357 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37933.640736 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40387.187266 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 38606.224846 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 28944.857752 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 28944.857752 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37933.640736 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 29151.213847 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 29551.495939 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37933.640736 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 29151.213847 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 29551.495939 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.replacements 943495 # number of replacements +system.cpu.dcache.tagsinuse 3673.924289 # Cycle average of tags in use +system.cpu.dcache.total_refs 28145440 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 947591 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 29.702097 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 7941416000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 3673.924289 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.896954 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.896954 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 23596473 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 23596473 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 4537302 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4537302 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 5856 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 5856 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 5799 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 5799 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 28133775 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 28133775 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 28133775 # number of overall hits +system.cpu.dcache.overall_hits::total 28133775 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1173127 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1173127 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 197679 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 197679 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 6 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 6 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1370806 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1370806 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1370806 # number of overall misses +system.cpu.dcache.overall_misses::total 1370806 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 13880183500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 13880183500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 5370097404 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 5370097404 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 191000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 191000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 19250280904 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 19250280904 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 19250280904 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 19250280904 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 24769600 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 24769600 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5862 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 5862 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 5799 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 5799 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 29504581 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 29504581 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 29504581 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 29504581 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.047362 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.047362 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.041749 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.041749 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001024 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.001024 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.046461 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.046461 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.046461 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.046461 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11831.782492 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 11831.782492 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27165.745496 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 27165.745496 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 31833.333333 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 31833.333333 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 14043.038113 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 14043.038113 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 14043.038113 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 14043.038113 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 152379 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 23821 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 6.396835 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 942892 # number of writebacks +system.cpu.dcache.writebacks::total 942892 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 269039 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 269039 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 154172 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 154172 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 6 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 6 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 423211 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 423211 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 423211 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 423211 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 904088 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 904088 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43507 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 43507 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 947595 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 947595 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 947595 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 947595 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9989577500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 9989577500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 957542952 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 957542952 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10947120452 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10947120452 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10947120452 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10947120452 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.036500 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.036500 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009188 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009188 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.032117 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.032117 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032117 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.032117 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11049.341989 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11049.341989 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22008.939987 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22008.939987 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11552.530830 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 11552.530830 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11552.530830 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 11552.530830 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini index b61f2399d..b0792be17 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini +++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini @@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a -clock=1 +clock=1000 init_param=0 kernel= load_addr_mask=1099511627775 @@ -30,7 +30,7 @@ system_port=system.membus.slave[0] [system.cpu] type=DerivO3CPU -children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload +children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -78,6 +78,7 @@ iewToFetchDelay=1 iewToRenameDelay=1 instShiftAmt=2 interrupts=system.cpu.interrupts +isa=system.cpu.isa issueToExecuteDelay=1 issueWidth=8 itb=system.cpu.itb @@ -129,17 +130,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=2 is_top_level=true -latency=1000 max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=2 size=262144 subblock_size=0 system=system @@ -158,7 +160,7 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=X86PagetableWalker -clock=1 +clock=500 system=system port=system.cpu.toL2Bus.slave[3] @@ -430,17 +432,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=2 is_top_level=true -latency=1000 max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=2 size=131072 subblock_size=0 system=system @@ -453,7 +456,7 @@ mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=X86LocalApic -clock=1 +clock=500 int_latency=1000 pio_addr=2305843009213693952 pio_latency=100000 @@ -462,6 +465,9 @@ int_master=system.membus.slave[2] int_slave=system.membus.master[2] pio=system.membus.master[1] +[system.cpu.isa] +type=X86ISA + [system.cpu.itb] type=X86TLB children=walker @@ -470,30 +476,31 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=X86PagetableWalker -clock=1 +clock=500 system=system port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] type=BaseCache addr_ranges=0:18446744073709551615 -assoc=2 +assoc=8 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=20 is_top_level=false -latency=1000 max_miss_count=0 -mshrs=10 +mshrs=20 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=20 size=2097152 subblock_size=0 system=system -tgts_per_mshr=5 +tgts_per_mshr=12 trace_addr=0 two_queue=false write_buffers=8 @@ -503,10 +510,10 @@ mem_side=system.membus.slave[1] [system.cpu.toL2Bus] type=CoherentBus block_size=64 -clock=1000 +clock=500 header_cycles=1 use_default_range=false -width=8 +width=32 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port @@ -521,9 +528,9 @@ egid=100 env= errout=cerr euid=100 -executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/mcf +executable=/projects/pd/randd/dist/cpu2000/binaries/x86/linux/mcf gid=100 -input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in +input=/projects/pd/randd/dist/cpu2000/data/mcf/smred/input/mcf.in max_stack_size=67108864 output=cout pid=100 @@ -543,15 +550,28 @@ master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_s slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master [system.physmem] -type=SimpleMemory -clock=1 +type=SimpleDRAM +addr_mapping=openmap +banks_per_rank=8 +clock=1000 conf_table_reported=false -file= in_addr_map=true -latency=30000 -latency_var=0 +lines_per_rowbuffer=64 +mem_sched_policy=fcfs null=false +page_policy=open range=0:268435455 +ranks_per_channel=2 +read_buffer_size=32 +tBURST=4000 +tCL=14000 +tRCD=14000 +tREFI=7800000 +tRFC=300000 +tRP=14000 +tWTR=1000 +write_buffer_size=32 +write_thresh_perc=70 zero=false port=system.membus.master[0] diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout index 70c115e37..d71b96b19 100755 --- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout +++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout @@ -1,11 +1,9 @@ -Redirecting stdout to build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing/simout -Redirecting stderr to build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 10 2012 22:29:00 -gem5 started Sep 10 2012 23:05:45 -gem5 executing on ribera.cs.wisc.edu +gem5 compiled Oct 30 2012 11:14:29 +gem5 started Oct 30 2012 16:29:18 +gem5 executing on u200540-lin command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -18,7 +16,6 @@ All Rights Reserved. nodes : 500 active arcs : 1905 simplex iterations : 1502 -info: Increasing stack size by one page. flow value : 4990014995 new implicit arcs : 23867 active arcs : 25772 @@ -26,4 +23,4 @@ simplex iterations : 2663 flow value : 3080014995 checksum : 68389 optimal -Exiting @ tick 64346039000 because target called exit() +Exiting @ tick 66000220500 because target called exit() diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt index 973686ac9..80c10d75b 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt @@ -1,90 +1,90 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.067525 # Number of seconds simulated -sim_ticks 67525253000 # Number of ticks simulated -final_tick 67525253000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.066000 # Number of seconds simulated +sim_ticks 66000220500 # Number of ticks simulated +final_tick 66000220500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 116144 # Simulator instruction rate (inst/s) -host_op_rate 204512 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 49640781 # Simulator tick rate (ticks/s) -host_mem_usage 364964 # Number of bytes of host memory used -host_seconds 1360.28 # Real time elapsed on the host +host_inst_rate 92408 # Simulator instruction rate (inst/s) +host_op_rate 162716 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 38603772 # Simulator tick rate (ticks/s) +host_mem_usage 361664 # Number of bytes of host memory used +host_seconds 1709.68 # Real time elapsed on the host sim_insts 157988547 # Number of instructions simulated sim_ops 278192462 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 66944 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1886080 # Number of bytes read from this memory -system.physmem.bytes_read::total 1953024 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 66944 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 66944 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 13568 # Number of bytes written to this memory -system.physmem.bytes_written::total 13568 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 1046 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 29470 # Number of read requests responded to by this memory -system.physmem.num_reads::total 30516 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 212 # Number of write requests responded to by this memory -system.physmem.num_writes::total 212 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 991392 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 27931476 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 28922868 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 991392 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 991392 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 200932 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 200932 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 200932 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 991392 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 27931476 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 29123801 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 30518 # Total number of read requests seen -system.physmem.writeReqs 212 # Total number of write requests seen -system.physmem.cpureqs 30733 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 1953024 # Total number of bytes read from memory -system.physmem.bytesWritten 13568 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 1953024 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 13568 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 63 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 3 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 1916 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 1956 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 2028 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 2002 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 1974 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 1871 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 1873 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 1862 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 1925 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 1905 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 1826 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 1883 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 1914 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 1878 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 1871 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 1771 # Track reads on a per bank basis +system.physmem.bytes_read::cpu.inst 64832 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1881344 # Number of bytes read from this memory +system.physmem.bytes_read::total 1946176 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 64832 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 64832 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 9344 # Number of bytes written to this memory +system.physmem.bytes_written::total 9344 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 1013 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 29396 # Number of read requests responded to by this memory +system.physmem.num_reads::total 30409 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 146 # Number of write requests responded to by this memory +system.physmem.num_writes::total 146 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 982300 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 28505117 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 29487417 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 982300 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 982300 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 141575 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 141575 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 141575 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 982300 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 28505117 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 29628992 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 30411 # Total number of read requests seen +system.physmem.writeReqs 146 # Total number of write requests seen +system.physmem.cpureqs 30558 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 1946176 # Total number of bytes read from memory +system.physmem.bytesWritten 9344 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 1946176 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 9344 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 46 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 1 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 1914 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 2026 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 1920 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 1999 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 1961 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 1870 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 1865 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 1859 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 1922 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 1899 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 1824 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 1881 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 1910 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 1876 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 1869 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 1770 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 7 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 119 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 7 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 23 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 1 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 17 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 2 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 93 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 5 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 4 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 12 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::8 6 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 12 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 7 # Track writes on a per bank basis system.physmem.perBankWrReqs::10 7 # Track writes on a per bank basis system.physmem.perBankWrReqs::11 1 # Track writes on a per bank basis system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 10 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 11 # Track writes on a per bank basis system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 67525239000 # Total gap between requests +system.physmem.totGap 66000206500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 30518 # Categorize read packet sizes +system.physmem.readPktSize::6 30411 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -93,7 +93,7 @@ system.physmem.writePktSize::2 0 # ca system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 212 # categorize write packet sizes +system.physmem.writePktSize::6 146 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -102,13 +102,13 @@ system.physmem.neitherpktsize::2 0 # ca system.physmem.neitherpktsize::3 0 # categorize neither packet sizes system.physmem.neitherpktsize::4 0 # categorize neither packet sizes system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 3 # categorize neither packet sizes +system.physmem.neitherpktsize::6 1 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 29919 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 398 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 104 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 29 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 29839 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 401 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 98 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 22 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -138,29 +138,29 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see @@ -171,266 +171,265 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 11553430 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 574779430 # Sum of mem lat for all requests -system.physmem.totBusLat 121820000 # Total cycles spent in databus access -system.physmem.totBankLat 441406000 # Total cycles spent in bank access -system.physmem.avgQLat 379.36 # Average queueing delay per request -system.physmem.avgBankLat 14493.71 # Average bank access latency per request +system.physmem.totQLat 10043842 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 570319842 # Sum of mem lat for all requests +system.physmem.totBusLat 121460000 # Total cycles spent in databus access +system.physmem.totBankLat 438816000 # Total cycles spent in bank access +system.physmem.avgQLat 330.77 # Average queueing delay per request +system.physmem.avgBankLat 14451.37 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 18873.07 # Average memory access latency -system.physmem.avgRdBW 28.92 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 0.20 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 28.92 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 0.20 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 18782.15 # Average memory access latency +system.physmem.avgRdBW 29.49 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 0.14 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 29.49 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 0.14 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 0.18 # Data bus utilization in percentage +system.physmem.busUtil 0.19 # Data bus utilization in percentage system.physmem.avgRdQLen 0.01 # Average read queue length over time -system.physmem.avgWrQLen 2.27 # Average write queue length over time -system.physmem.readRowHits 29673 # Number of row buffer hits during reads -system.physmem.writeRowHits 71 # Number of row buffer hits during writes -system.physmem.readRowHitRate 97.43 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 33.49 # Row buffer hit rate for writes -system.physmem.avgGap 2197371.92 # Average gap between requests +system.physmem.avgWrQLen 11.23 # Average write queue length over time +system.physmem.readRowHits 29628 # Number of row buffer hits during reads +system.physmem.writeRowHits 33 # Number of row buffer hits during writes +system.physmem.readRowHitRate 97.57 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 22.60 # Row buffer hit rate for writes +system.physmem.avgGap 2159904.65 # Average gap between requests system.cpu.workload.num_syscalls 444 # Number of system calls -system.cpu.numCycles 135050507 # number of cpu cycles simulated +system.cpu.numCycles 132000442 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 35279612 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 35279612 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 1097690 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 25134949 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 25035866 # Number of BTB hits +system.cpu.BPredUnit.lookups 34554509 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 34554509 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 911394 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 24765022 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 24662055 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 27689493 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 190877273 # Number of instructions fetch has processed -system.cpu.fetch.Branches 35279612 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 25035866 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 58050662 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 7148119 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 43215578 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 39 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 200 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 11 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 26932643 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 266231 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 134969887 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.491492 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.329843 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 26596332 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 185596643 # Number of instructions fetch has processed +system.cpu.fetch.Branches 34554509 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 24662055 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 56507097 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 6124499 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 43643381 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 31 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 161 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 25948459 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 189220 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 131924094 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.485407 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.326719 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 79660068 59.02% 59.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2061386 1.53% 60.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 3001296 2.22% 62.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 4024404 2.98% 65.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 7960578 5.90% 71.65% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 4856128 3.60% 75.25% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 2895673 2.15% 77.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1440638 1.07% 78.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 29069716 21.54% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 77963907 59.10% 59.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1995685 1.51% 60.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2954745 2.24% 62.85% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 3921734 2.97% 65.82% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 7794021 5.91% 71.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 4758298 3.61% 75.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2730030 2.07% 77.41% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1578417 1.20% 78.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 28227257 21.40% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 134969887 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.261233 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.413377 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 38714097 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 35595607 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 46068800 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 8577479 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 6013904 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 332373669 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 6013904 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 44296876 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 8440142 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 9061 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 48816518 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 27393386 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 327323595 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 229 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 40548 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 25654370 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 357 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 329853596 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 868074055 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 868071866 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 2189 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 131924094 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.261776 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.406030 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 37436709 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 35891345 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 44770440 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 8648508 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 5177092 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 324637130 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 5177092 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 43002137 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 8530644 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 9064 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 47590207 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 27614950 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 320247590 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 230 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 56685 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 25740543 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 371 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 322254877 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 849337194 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 849335025 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 2169 # Number of floating rename lookups system.cpu.rename.CommittedMaps 279212744 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 50640852 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 483 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 476 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 61788867 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 104142858 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 36158946 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 40039032 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 6050954 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 321707041 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1738 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 307032101 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 190555 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 42805778 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 61072777 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1292 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 134969887 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.274819 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.710764 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 43042133 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 470 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 464 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 62360742 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 102568175 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 35245114 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 39579817 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 6021711 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 315893152 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1659 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 302191539 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 115107 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 37070468 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 54283440 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1213 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 131924094 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.290647 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.699813 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 26262527 19.46% 19.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 23269182 17.24% 36.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 26059494 19.31% 56.01% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 26258264 19.45% 75.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 19354972 14.34% 89.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 8435024 6.25% 96.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 4232889 3.14% 99.19% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 903483 0.67% 99.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 194052 0.14% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 24546585 18.61% 18.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 23206107 17.59% 36.20% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 25921610 19.65% 55.85% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 25807341 19.56% 75.41% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 18909357 14.33% 89.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 8337371 6.32% 96.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 4135132 3.13% 99.20% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 899614 0.68% 99.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 160977 0.12% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 134969887 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 131924094 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 32987 1.63% 1.63% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 1.63% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 1.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 1.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 1.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 1.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.63% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1843971 90.87% 92.50% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 152228 7.50% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 38482 1.96% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1831710 93.52% 95.49% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 88409 4.51% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 31299 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 174160366 56.72% 56.73% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 56.73% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 56.73% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 56 0.00% 56.73% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 56.73% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 56.73% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 56.73% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 56.73% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.73% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 99035655 32.26% 88.99% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 33804725 11.01% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 31296 0.01% 0.01% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 171161443 56.64% 56.65% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 56.65% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 56.65% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 35 0.00% 56.65% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 56.65% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 56.65% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 56.65% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 56.65% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.65% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.65% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.65% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.65% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.65% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.65% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.65% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.65% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.65% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.65% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.65% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.65% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.65% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.65% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.65% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.65% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.65% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.65% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.65% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.65% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.65% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 97760077 32.35% 89.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 33238688 11.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 307032101 # Type of FU issued -system.cpu.iq.rate 2.273461 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2029186 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.006609 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 751253230 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 364547081 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 303801599 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 600 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1091 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 195 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 309029699 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 289 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 54104965 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 302191539 # Type of FU issued +system.cpu.iq.rate 2.289322 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1958601 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.006481 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 738380204 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 352997189 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 299552936 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 676 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 1019 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 193 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 304118533 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 311 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 53992044 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 13363474 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 46851 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 34646 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 4719195 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 11788791 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 25892 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 34061 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 3805363 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 3287 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 8523 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 3223 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 8493 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 6013904 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1728221 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 160274 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 321708779 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 372174 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 104142858 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 36158946 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 475 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 3195 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 73111 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 34646 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 603719 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 587627 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1191346 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 304994543 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 98411821 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2037558 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 5177092 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1727451 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 159578 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 315894811 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 195834 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 102568175 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 35245114 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 465 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 3211 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 73329 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 34061 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 522882 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 446154 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 969036 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 300573249 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 97290254 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1618290 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 131928718 # number of memory reference insts executed -system.cpu.iew.exec_branches 31180940 # Number of branches executed -system.cpu.iew.exec_stores 33516897 # Number of stores executed -system.cpu.iew.exec_rate 2.258374 # Inst execution rate -system.cpu.iew.wb_sent 304306961 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 303801794 # cumulative count of insts written-back -system.cpu.iew.wb_producers 222946371 # num instructions producing a value -system.cpu.iew.wb_consumers 302902430 # num instructions consuming a value +system.cpu.iew.exec_refs 130308372 # number of memory reference insts executed +system.cpu.iew.exec_branches 30889144 # Number of branches executed +system.cpu.iew.exec_stores 33018118 # Number of stores executed +system.cpu.iew.exec_rate 2.277062 # Inst execution rate +system.cpu.iew.wb_sent 299980860 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 299553129 # cumulative count of insts written-back +system.cpu.iew.wb_producers 219502976 # num instructions producing a value +system.cpu.iew.wb_consumers 298002309 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.249542 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.736034 # average fanout of values written-back +system.cpu.iew.wb_rate 2.269334 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.736581 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 43529723 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 37715212 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 446 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1097716 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 128955983 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.157267 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.943706 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 911415 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 126747002 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.194864 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.965405 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 59867865 46.43% 46.43% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 19620961 15.22% 61.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 11973021 9.28% 70.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 9656574 7.49% 78.41% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1838556 1.43% 79.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 2079674 1.61% 81.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1347744 1.05% 82.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 756025 0.59% 83.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 21815563 16.92% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 58171175 45.90% 45.90% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 19282988 15.21% 61.11% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 11825828 9.33% 70.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 9598483 7.57% 78.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1735999 1.37% 79.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 2077835 1.64% 81.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1295284 1.02% 82.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 717786 0.57% 82.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 22041624 17.39% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 128955983 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 126747002 # Number of insts commited each cycle system.cpu.commit.committedInsts 157988547 # Number of instructions committed system.cpu.commit.committedOps 278192462 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -441,307 +440,197 @@ system.cpu.commit.branches 29309705 # Nu system.cpu.commit.fp_insts 40 # Number of committed floating point instructions. system.cpu.commit.int_insts 278186170 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 21815563 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 22041624 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 428862605 # The number of ROB reads -system.cpu.rob.rob_writes 649464240 # The number of ROB writes -system.cpu.timesIdled 14220 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 80620 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 420613052 # The number of ROB reads +system.cpu.rob.rob_writes 636997439 # The number of ROB writes +system.cpu.timesIdled 13642 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 76348 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 157988547 # Number of Instructions Simulated system.cpu.committedOps 278192462 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 157988547 # Number of Instructions Simulated -system.cpu.cpi 0.854812 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.854812 # CPI: Total CPI of All Threads -system.cpu.ipc 1.169848 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.169848 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 599211234 # number of integer regfile reads -system.cpu.int_regfile_writes 304304879 # number of integer regfile writes -system.cpu.fp_regfile_reads 178 # number of floating regfile reads -system.cpu.fp_regfile_writes 115 # number of floating regfile writes -system.cpu.misc_regfile_reads 195413561 # number of misc regfile reads -system.cpu.icache.replacements 78 # number of replacements -system.cpu.icache.tagsinuse 851.671106 # Cycle average of tags in use -system.cpu.icache.total_refs 26931242 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1068 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 25216.518727 # Average number of references to valid blocks. +system.cpu.cpi 0.835506 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.835506 # CPI: Total CPI of All Threads +system.cpu.ipc 1.196879 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.196879 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 592880828 # number of integer regfile reads +system.cpu.int_regfile_writes 300217894 # number of integer regfile writes +system.cpu.fp_regfile_reads 180 # number of floating regfile reads +system.cpu.fp_regfile_writes 79 # number of floating regfile writes +system.cpu.misc_regfile_reads 192706911 # number of misc regfile reads +system.cpu.icache.replacements 61 # number of replacements +system.cpu.icache.tagsinuse 834.549611 # Cycle average of tags in use +system.cpu.icache.total_refs 25947121 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 1029 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 25215.861030 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 851.671106 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.415855 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.415855 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 26931243 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 26931243 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 26931243 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 26931243 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 26931243 # number of overall hits -system.cpu.icache.overall_hits::total 26931243 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1400 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1400 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1400 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1400 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1400 # number of overall misses -system.cpu.icache.overall_misses::total 1400 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 66418500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 66418500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 66418500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 66418500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 66418500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 66418500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 26932643 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 26932643 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 26932643 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 26932643 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 26932643 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 26932643 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 834.549611 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.407495 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.407495 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 25947121 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 25947121 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 25947121 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 25947121 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 25947121 # number of overall hits +system.cpu.icache.overall_hits::total 25947121 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1338 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1338 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1338 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1338 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1338 # number of overall misses +system.cpu.icache.overall_misses::total 1338 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 65589000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 65589000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 65589000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 65589000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 65589000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 65589000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 25948459 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 25948459 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 25948459 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 25948459 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 25948459 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 25948459 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000052 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000052 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000052 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000052 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000052 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000052 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 47441.785714 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 47441.785714 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 47441.785714 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 47441.785714 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 47441.785714 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 47441.785714 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 168 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49020.179372 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 49020.179372 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 49020.179372 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 49020.179372 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 49020.179372 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 49020.179372 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 78 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 6 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 4 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 28 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 19.500000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 328 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 328 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 328 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 328 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 328 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 328 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1072 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1072 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1072 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1072 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1072 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1072 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 52640000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 52640000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 52640000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 52640000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 52640000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 52640000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 308 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 308 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 308 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 308 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 308 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 308 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1030 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1030 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1030 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1030 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1030 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1030 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 51699000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 51699000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 51699000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 51699000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 51699000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 51699000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000040 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000040 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000040 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 49104.477612 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 49104.477612 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 49104.477612 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 49104.477612 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 49104.477612 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 49104.477612 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50193.203883 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50193.203883 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50193.203883 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 50193.203883 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50193.203883 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 50193.203883 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 2072134 # number of replacements -system.cpu.dcache.tagsinuse 4072.225954 # Cycle average of tags in use -system.cpu.dcache.total_refs 72984548 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 2076230 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 35.152439 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 22141542000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4072.225954 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.994196 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.994196 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 41643096 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 41643096 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 31341442 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 31341442 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 72984538 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 72984538 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 72984538 # number of overall hits -system.cpu.dcache.overall_hits::total 72984538 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2617976 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2617976 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 98309 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 98309 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2716285 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2716285 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2716285 # number of overall misses -system.cpu.dcache.overall_misses::total 2716285 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 31291069500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 31291069500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 2090661498 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 2090661498 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 33381730998 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 33381730998 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 33381730998 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 33381730998 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 44261072 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 44261072 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 31439751 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 31439751 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 75700823 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 75700823 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 75700823 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 75700823 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.059148 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.059148 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003127 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.003127 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.035882 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.035882 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.035882 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.035882 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11952.389747 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 11952.389747 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 21266.226876 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 21266.226876 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 12289.480300 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 12289.480300 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 12289.480300 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 12289.480300 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 32223 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 9490 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 3.395469 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2065967 # number of writebacks -system.cpu.dcache.writebacks::total 2065967 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 623929 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 623929 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16120 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 16120 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 640049 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 640049 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 640049 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 640049 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1994047 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1994047 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 82189 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 82189 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2076236 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2076236 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2076236 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2076236 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21985403000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 21985403000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1815582998 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1815582998 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23800985998 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 23800985998 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23800985998 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 23800985998 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.045052 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.045052 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002614 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002614 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.027427 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.027427 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.027427 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.027427 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11025.518957 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11025.518957 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22090.340532 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22090.340532 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11463.526303 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 11463.526303 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11463.526303 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 11463.526303 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 547 # number of replacements -system.cpu.l2cache.tagsinuse 20637.745612 # Cycle average of tags in use -system.cpu.l2cache.total_refs 4028284 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 30500 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 132.074885 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 454 # number of replacements +system.cpu.l2cache.tagsinuse 20802.546521 # Cycle average of tags in use +system.cpu.l2cache.total_refs 4028808 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 30388 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 132.578913 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 19684.475463 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 703.345334 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 249.924814 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.600723 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.021464 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.007627 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.629814 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 22 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 1993488 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1993510 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 2065967 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 2065967 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 1 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 1 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 53272 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 53272 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 22 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 2046760 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2046782 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 22 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 2046760 # number of overall hits -system.cpu.l2cache.overall_hits::total 2046782 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 1046 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 467 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 1513 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 3 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 3 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 29005 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 29005 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 1046 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 29472 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 30518 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 1046 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 29472 # number of overall misses -system.cpu.l2cache.overall_misses::total 30518 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 51338000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 23339500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 74677500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1201148000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1201148000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 51338000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 1224487500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 1275825500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 51338000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 1224487500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 1275825500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 1068 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1993955 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 1995023 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 2065967 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 2065967 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 4 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 4 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 82277 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 82277 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 1068 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 2076232 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2077300 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 1068 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 2076232 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2077300 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.979401 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000234 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.000758 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.750000 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.750000 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.352529 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.352529 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.979401 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.014195 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.014691 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.979401 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.014195 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.014691 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 49080.305927 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 49977.516060 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 49357.237277 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 41411.756594 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 41411.756594 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 49080.305927 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 41547.485749 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 41805.672062 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 49080.305927 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 41547.485749 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 41805.672062 # average overall miss latency +system.cpu.l2cache.occ_blocks::writebacks 19868.628609 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 689.608154 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 244.309758 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.606342 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.021045 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.007456 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.634843 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 16 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 1993542 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1993558 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 2066445 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 2066445 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 53246 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 53246 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 16 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 2046788 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2046804 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 16 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 2046788 # number of overall hits +system.cpu.l2cache.overall_hits::total 2046804 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 1013 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 400 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 1413 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 1 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 1 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 28998 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 28998 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 1013 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 29398 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 30411 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 1013 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 29398 # number of overall misses +system.cpu.l2cache.overall_misses::total 30411 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 50503000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 19675000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 70178000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1198959000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1198959000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 50503000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 1218634000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 1269137000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 50503000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 1218634000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 1269137000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 1029 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 1993942 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 1994971 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 2066445 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 2066445 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 1 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 82244 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 82244 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 1029 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 2076186 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2077215 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 1029 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 2076186 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2077215 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.984451 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000201 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.000708 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.352585 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.352585 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.984451 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.014160 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.014640 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.984451 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.014160 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.014640 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 49854.886476 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 49187.500000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 49665.958953 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 41346.265260 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 41346.265260 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 49854.886476 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 41452.955983 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 41732.826938 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 49854.886476 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 41452.955983 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 41732.826938 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -750,60 +639,168 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 212 # number of writebacks -system.cpu.l2cache.writebacks::total 212 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1046 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 467 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 1513 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 3 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 3 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 29005 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 29005 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 1046 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 29472 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 30518 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 1046 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 29472 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 30518 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 38163141 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 17461725 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 55624866 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 30003 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 30003 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 826405394 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 826405394 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 38163141 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 843867119 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 882030260 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 38163141 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 843867119 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 882030260 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.979401 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000234 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000758 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.750000 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.750000 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.352529 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.352529 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.979401 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014195 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.014691 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.979401 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014195 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.014691 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 36484.838432 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 37391.274090 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 36764.617317 # average ReadReq mshr miss latency +system.cpu.l2cache.writebacks::writebacks 146 # number of writebacks +system.cpu.l2cache.writebacks::total 146 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1013 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 400 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1413 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 1 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 28998 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 28998 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 1013 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 29398 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 30411 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 1013 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 29398 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 30411 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 37745579 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 14639611 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 52385190 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 10001 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 10001 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 824070390 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 824070390 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 37745579 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 838710001 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 876455580 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 37745579 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 838710001 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 876455580 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.984451 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000201 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000708 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.352585 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.352585 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.984451 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014160 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.014640 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.984451 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014160 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.014640 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37261.183613 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 36599.027500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 37073.736730 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 28491.825340 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 28491.825340 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 36484.838432 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 28632.841986 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 28901.968019 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 36484.838432 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 28632.841986 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 28901.968019 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 28418.180219 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 28418.180219 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37261.183613 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 28529.491836 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 28820.347243 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37261.183613 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 28529.491836 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 28820.347243 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.replacements 2072087 # number of replacements +system.cpu.dcache.tagsinuse 4072.565599 # Cycle average of tags in use +system.cpu.dcache.total_refs 71969114 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 2076183 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 34.664148 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 21167717000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4072.565599 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.994279 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.994279 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 40627633 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 40627633 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 31341474 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 31341474 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 71969107 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 71969107 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 71969107 # number of overall hits +system.cpu.dcache.overall_hits::total 71969107 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2625254 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2625254 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 98277 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 98277 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2723531 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2723531 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2723531 # number of overall misses +system.cpu.dcache.overall_misses::total 2723531 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 31319760000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 31319760000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 2088062998 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 2088062998 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 33407822998 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 33407822998 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 33407822998 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 33407822998 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 43252887 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 43252887 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 31439751 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 31439751 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 74692638 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 74692638 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 74692638 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 74692638 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.060695 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.060695 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003126 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.003126 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.036463 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.036463 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.036463 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.036463 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11930.182756 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 11930.182756 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 21246.710807 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 21246.710807 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 12266.364142 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 12266.364142 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 12266.364142 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 12266.364142 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 32155 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 9466 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 3.396894 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 2066445 # number of writebacks +system.cpu.dcache.writebacks::total 2066445 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 631206 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 631206 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16138 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 16138 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 647344 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 647344 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 647344 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 647344 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1994048 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1994048 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 82139 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 82139 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2076187 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2076187 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2076187 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2076187 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21982292500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 21982292500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1812892498 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1812892498 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23795184998 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 23795184998 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23795184998 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 23795184998 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.046102 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.046102 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002613 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002613 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.027796 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.027796 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.027796 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.027796 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11023.953536 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11023.953536 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22071.032007 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22071.032007 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11461.002789 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 11461.002789 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11461.002789 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 11461.002789 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini b/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini index 0d4631b4b..b3fd6699b 100644 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini @@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a -clock=1 +clock=1000 init_param=0 kernel= load_addr_mask=1099511627775 @@ -30,7 +30,7 @@ system_port=system.membus.slave[0] [system.cpu] type=DerivO3CPU -children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload +children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -78,6 +78,7 @@ iewToFetchDelay=1 iewToRenameDelay=1 instShiftAmt=2 interrupts=system.cpu.interrupts +isa=system.cpu.isa issueToExecuteDelay=1 issueWidth=8 itb=system.cpu.itb @@ -129,18 +130,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=262144 subblock_size=0 system=system @@ -159,7 +160,7 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=ArmTableWalker -clock=1 +clock=500 num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[3] @@ -432,18 +433,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=131072 subblock_size=0 system=system @@ -457,6 +458,23 @@ mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=ArmInterrupts +[system.cpu.isa] +type=ArmISA +fpsid=1090793632 +id_isar0=34607377 +id_isar1=34677009 +id_isar2=555950401 +id_isar3=17899825 +id_isar4=268501314 +id_isar5=0 +id_mmfr0=3 +id_mmfr1=0 +id_mmfr2=19070976 +id_mmfr3=4027589137 +id_pfr0=49 +id_pfr1=1 +midr=890224640 + [system.cpu.itb] type=ArmTLB children=walker @@ -465,7 +483,7 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=ArmTableWalker -clock=1 +clock=500 num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[2] @@ -473,24 +491,24 @@ port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] type=BaseCache addr_ranges=0:18446744073709551615 -assoc=2 +assoc=8 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=20 is_top_level=false max_miss_count=0 -mshrs=10 +mshrs=20 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=20 size=2097152 subblock_size=0 system=system -tgts_per_mshr=5 +tgts_per_mshr=12 trace_addr=0 two_queue=false write_buffers=8 @@ -500,10 +518,10 @@ mem_side=system.membus.slave[1] [system.cpu.toL2Bus] type=CoherentBus block_size=64 -clock=1000 +clock=500 header_cycles=1 use_default_range=false -width=8 +width=32 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port @@ -540,15 +558,28 @@ master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] -type=SimpleMemory -bandwidth=73.000000 -clock=1 +type=SimpleDRAM +addr_mapping=openmap +banks_per_rank=8 +clock=1000 conf_table_reported=false in_addr_map=true -latency=30000 -latency_var=0 +lines_per_rowbuffer=64 +mem_sched_policy=fcfs null=false +page_policy=open range=0:134217727 +ranks_per_channel=2 +read_buffer_size=32 +tBURST=4000 +tCL=14000 +tRCD=14000 +tREFI=7800000 +tRFC=300000 +tRP=14000 +tWTR=1000 +write_buffer_size=32 +write_thresh_perc=70 zero=false port=system.membus.master[0] diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/simerr b/tests/long/se/20.parser/ref/arm/linux/o3-timing/simerr index b4d96e4ea..374965c0a 100755 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/simerr +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/simerr @@ -1,3 +1,4 @@ warn: Sockets disabled, not accepting gdb connections warn: CP14 unimplemented crn[8], opc1[2], crm[9], opc2[4] +warn: CP14 unimplemented crn[15], opc1[7], crm[5], opc2[7] hack: be nice to actually delete the event here diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout b/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout index ccc3391a2..c76d776a9 100755 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout @@ -1,8 +1,8 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 21 2012 11:19:00 -gem5 started Sep 21 2012 12:11:01 +gem5 compiled Oct 30 2012 11:20:14 +gem5 started Oct 30 2012 19:35:49 gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second @@ -67,4 +67,4 @@ info: Increasing stack size by one page. about 2 million people attended the five best costumes got prizes No errors! -Exiting @ tick 205972871500 because target called exit() +Exiting @ tick 206019870500 because target called exit() diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt index c7236dc45..7f8080346 100644 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt @@ -1,90 +1,90 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.209792 # Number of seconds simulated -sim_ticks 209791572500 # Number of ticks simulated -final_tick 209791572500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.206020 # Number of seconds simulated +sim_ticks 206019870500 # Number of ticks simulated +final_tick 206019870500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 156369 # Simulator instruction rate (inst/s) -host_op_rate 176151 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 64455547 # Simulator tick rate (ticks/s) -host_mem_usage 260364 # Number of bytes of host memory used -host_seconds 3254.83 # Real time elapsed on the host -sim_insts 508955223 # Number of instructions simulated -sim_ops 573341783 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 217152 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9263872 # Number of bytes read from this memory -system.physmem.bytes_read::total 9481024 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 217152 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 217152 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6251520 # Number of bytes written to this memory -system.physmem.bytes_written::total 6251520 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 3393 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 144748 # Number of read requests responded to by this memory -system.physmem.num_reads::total 148141 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 97680 # Number of write requests responded to by this memory -system.physmem.num_writes::total 97680 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 1035084 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 44157503 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 45192588 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1035084 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1035084 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 29798718 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 29798718 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 29798718 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1035084 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 44157503 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 74991306 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 148142 # Total number of read requests seen -system.physmem.writeReqs 97680 # Total number of write requests seen -system.physmem.cpureqs 245829 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 9481024 # Total number of bytes read from memory -system.physmem.bytesWritten 6251520 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 9481024 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 6251520 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 73 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 7 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 9201 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 9165 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 9345 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 8789 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 9221 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 8969 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 9229 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 9489 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 9153 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 10287 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 9703 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 9687 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 9133 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 8953 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 8996 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 8749 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 5968 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 6117 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 6110 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 5946 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 6121 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 5961 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 6032 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 6371 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 5972 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 6670 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 6298 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 6310 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 6055 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 6063 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 5907 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 5779 # Track writes on a per bank basis +host_inst_rate 121571 # Simulator instruction rate (inst/s) +host_op_rate 136951 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 49210675 # Simulator tick rate (ticks/s) +host_mem_usage 259828 # Number of bytes of host memory used +host_seconds 4186.49 # Real time elapsed on the host +sim_insts 508955243 # Number of instructions simulated +sim_ops 573341803 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 217536 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9265600 # Number of bytes read from this memory +system.physmem.bytes_read::total 9483136 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 217536 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 217536 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 6247936 # Number of bytes written to this memory +system.physmem.bytes_written::total 6247936 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 3399 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 144775 # Number of read requests responded to by this memory +system.physmem.num_reads::total 148174 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 97624 # Number of write requests responded to by this memory +system.physmem.num_writes::total 97624 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 1055898 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 44974303 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 46030201 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1055898 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1055898 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 30326861 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 30326861 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 30326861 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1055898 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 44974303 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 76357062 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 148175 # Total number of read requests seen +system.physmem.writeReqs 97624 # Total number of write requests seen +system.physmem.cpureqs 245816 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 9483136 # Total number of bytes read from memory +system.physmem.bytesWritten 6247936 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 9483136 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 6247936 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 95 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 17 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 9231 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 9188 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 9343 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 8790 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 9223 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 8971 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 9240 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 9470 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 9143 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 10294 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 9679 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 9702 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 9116 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 8946 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 9014 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 8730 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 5976 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 6116 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 6116 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 5942 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 6120 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 5953 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 6022 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 6372 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 5971 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 6671 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 6280 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 6315 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 6042 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 6059 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 5905 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 5764 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 209791554000 # Total gap between requests +system.physmem.totGap 206019849500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 148142 # Categorize read packet sizes +system.physmem.readPktSize::6 148175 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -93,7 +93,7 @@ system.physmem.writePktSize::2 0 # ca system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 97680 # categorize write packet sizes +system.physmem.writePktSize::6 97624 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -102,15 +102,15 @@ system.physmem.neitherpktsize::2 0 # ca system.physmem.neitherpktsize::3 0 # categorize neither packet sizes system.physmem.neitherpktsize::4 0 # categorize neither packet sizes system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 7 # categorize neither packet sizes +system.physmem.neitherpktsize::6 17 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 138253 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 9192 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 138261 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 9196 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 546 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 67 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 9 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 68 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 8 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -138,31 +138,31 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 4238 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 4246 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4247 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 4247 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 4247 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 4247 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 4247 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 4247 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 4247 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 4247 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 4247 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 4247 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 4247 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 4247 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 4247 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 4247 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 4247 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4247 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4247 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4247 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4247 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4247 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4246 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 4239 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 4242 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4245 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 4245 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 4245 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 4245 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 4245 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 4245 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 4245 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 4245 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 4245 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 4245 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 4244 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 4244 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 4244 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 4244 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 4244 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4244 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4244 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4244 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4244 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4244 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4244 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 3 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see @@ -171,27 +171,27 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 1634133662 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 4706663662 # Sum of mem lat for all requests -system.physmem.totBusLat 592276000 # Total cycles spent in databus access -system.physmem.totBankLat 2480254000 # Total cycles spent in bank access -system.physmem.avgQLat 11036.30 # Average queueing delay per request -system.physmem.avgBankLat 16750.66 # Average bank access latency per request +system.physmem.totQLat 1627412180 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 4699930180 # Sum of mem lat for all requests +system.physmem.totBusLat 592320000 # Total cycles spent in databus access +system.physmem.totBankLat 2480198000 # Total cycles spent in bank access +system.physmem.avgQLat 10990.09 # Average queueing delay per request +system.physmem.avgBankLat 16749.04 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 31786.96 # Average memory access latency -system.physmem.avgRdBW 45.19 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 29.80 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 45.19 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 29.80 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 31739.13 # Average memory access latency +system.physmem.avgRdBW 46.03 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 30.33 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 46.03 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 30.33 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 0.47 # Data bus utilization in percentage +system.physmem.busUtil 0.48 # Data bus utilization in percentage system.physmem.avgRdQLen 0.02 # Average read queue length over time -system.physmem.avgWrQLen 8.47 # Average write queue length over time -system.physmem.readRowHits 128571 # Number of row buffer hits during reads -system.physmem.writeRowHits 35065 # Number of row buffer hits during writes +system.physmem.avgWrQLen 8.48 # Average write queue length over time +system.physmem.readRowHits 128585 # Number of row buffer hits during reads +system.physmem.writeRowHits 35174 # Number of row buffer hits during writes system.physmem.readRowHitRate 86.83 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 35.90 # Row buffer hit rate for writes -system.physmem.avgGap 853428.72 # Average gap between requests +system.physmem.writeRowHitRate 36.03 # Row buffer hit rate for writes +system.physmem.avgGap 838163.90 # Average gap between requests system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -235,576 +235,454 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 548 # Number of system calls -system.cpu.numCycles 419583146 # number of cpu cycles simulated +system.cpu.numCycles 412039742 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 184787901 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 144275662 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 7821695 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 98666438 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 90672892 # Number of BTB hits +system.cpu.BPredUnit.lookups 182071983 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 142381295 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 7268299 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 93564777 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 88700041 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 12865720 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 116804 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 120063384 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 775942019 # Number of instructions fetch has processed -system.cpu.fetch.Branches 184787901 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 103538612 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 174228692 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 37833268 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 88961490 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 89 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 441 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 46 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 115656461 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 2629290 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 412465751 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.114116 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.961632 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 12685099 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 116083 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 117148048 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 763048101 # Number of instructions fetch has processed +system.cpu.fetch.Branches 182071983 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 101385140 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 170894035 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 35686363 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 89221488 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 22 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 506 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 45 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 113043343 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 2441081 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 404881843 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.113466 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.961359 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 238249907 57.76% 57.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 14509257 3.52% 61.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 23515530 5.70% 66.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 23126111 5.61% 72.59% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 21084782 5.11% 77.70% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 13401568 3.25% 80.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 13317687 3.23% 84.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 12258730 2.97% 87.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 53002179 12.85% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 234000478 57.79% 57.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 14180958 3.50% 61.30% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 22900692 5.66% 66.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 22746852 5.62% 72.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 20902415 5.16% 77.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 13082439 3.23% 80.97% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 13044714 3.22% 84.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 11995563 2.96% 87.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 52027732 12.85% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 412465751 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.440408 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.849316 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 130727660 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 83050170 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 164137621 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 5414105 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 29136195 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 26733440 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 78480 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 847595839 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 313311 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 29136195 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 139084470 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 9565310 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 58010596 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 161019235 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 15649945 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 817254433 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 1177 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 3017136 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 8708482 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 277 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 973333611 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3577975971 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3577974311 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1660 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 672200291 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 301133320 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 3043156 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 3043152 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 48850446 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 173854149 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 75418146 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 27836757 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 16204833 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 768087050 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 4468097 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 675015149 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1537645 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 197142364 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 504679775 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 746965 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 412465751 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.636536 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.726020 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 404881843 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.441880 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.851880 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 127553544 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 83254868 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 161072807 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 5457053 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 27543571 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 26128616 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 76844 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 833018746 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 296404 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 27543571 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 135629156 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 9608106 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 57992007 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 158279608 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 15829395 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 804332023 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 1038 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 3062506 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 8833795 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 346 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 960234545 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3519895125 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3519893415 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1710 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 672200323 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 288034222 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 3037420 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 3037417 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 49050394 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 170961338 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 74175754 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 28008123 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 15620624 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 757949088 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 4467543 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 668974363 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1389643 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 187239707 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 479750925 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 746407 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 404881843 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.652271 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.728361 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 150311678 36.44% 36.44% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 76712349 18.60% 55.04% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 69700446 16.90% 71.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 54263544 13.16% 85.10% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 31204898 7.57% 92.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 16238502 3.94% 96.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 9395018 2.28% 98.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 3385462 0.82% 99.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1253854 0.30% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 145293299 35.89% 35.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 75809300 18.72% 54.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 69100310 17.07% 71.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 53699574 13.26% 84.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 30880132 7.63% 92.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 16168967 3.99% 96.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 9289317 2.29% 98.85% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 3363096 0.83% 99.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1277848 0.32% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 412465751 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 404881843 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 459279 4.79% 4.79% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 4.79% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 4.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 4.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 4.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 4.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.79% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 6599656 68.89% 73.68% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 2521285 26.32% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 478346 4.98% 4.98% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 4.98% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 4.98% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.98% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.98% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.98% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 4.98% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.98% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 4.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 4.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.98% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 6550639 68.20% 73.18% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 2576691 26.82% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 453432070 67.17% 67.17% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 386675 0.06% 67.23% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.23% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 120 0.00% 67.23% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.23% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.23% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.23% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.23% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.23% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 156063229 23.12% 90.35% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 65133052 9.65% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 449945039 67.26% 67.26% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 383598 0.06% 67.32% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 120 0.00% 67.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.32% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 154114870 23.04% 90.35% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 64530733 9.65% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 675015149 # Type of FU issued -system.cpu.iq.rate 1.608776 # Inst issue rate -system.cpu.iq.fu_busy_cnt 9580220 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.014193 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1773613639 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 970503516 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 654104832 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 668974363 # Type of FU issued +system.cpu.iq.rate 1.623568 # Inst issue rate +system.cpu.iq.fu_busy_cnt 9605676 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.014359 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1753825613 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 950462588 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 649623996 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 275 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 376 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 684595230 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 678579900 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 139 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 8576140 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 8555633 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 47081094 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 45082 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 810201 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 17814169 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 44188279 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 40573 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 810259 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 16571773 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 19569 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 4173 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 19511 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 4184 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 29136195 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 4987646 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 377782 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 774132367 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 1246249 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 173854149 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 75418146 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 2979362 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 225001 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 11770 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 810201 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 4778565 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 4193502 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 8972067 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 664703563 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 152403506 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 10311586 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 27543571 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 4982601 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 373964 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 763975241 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 1120254 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 170961338 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 74175754 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 2978807 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 219858 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 11158 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 810259 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 4340256 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 4003229 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 8343485 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 659478369 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 150829210 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 9495994 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1577220 # number of nop insts executed -system.cpu.iew.exec_refs 216142633 # number of memory reference insts executed -system.cpu.iew.exec_branches 139998635 # Number of branches executed -system.cpu.iew.exec_stores 63739127 # Number of stores executed -system.cpu.iew.exec_rate 1.584200 # Inst execution rate -system.cpu.iew.wb_sent 659363122 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 654104848 # cumulative count of insts written-back -system.cpu.iew.wb_producers 377540372 # num instructions producing a value -system.cpu.iew.wb_consumers 650138040 # num instructions consuming a value +system.cpu.iew.exec_nop 1558610 # number of nop insts executed +system.cpu.iew.exec_refs 214064543 # number of memory reference insts executed +system.cpu.iew.exec_branches 139194602 # Number of branches executed +system.cpu.iew.exec_stores 63235333 # Number of stores executed +system.cpu.iew.exec_rate 1.600521 # Inst execution rate +system.cpu.iew.wb_sent 654596597 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 649624012 # cumulative count of insts written-back +system.cpu.iew.wb_producers 375406719 # num instructions producing a value +system.cpu.iew.wb_consumers 646267574 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.558940 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.580708 # average fanout of values written-back +system.cpu.iew.wb_rate 1.576605 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.580884 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 199474656 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 3721132 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 7746281 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 383329557 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.499195 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.189163 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 189315872 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 3721136 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 7194171 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 377338273 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.522999 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.206666 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 170483153 44.47% 44.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 103125969 26.90% 71.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 34389586 8.97% 80.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 19012192 4.96% 85.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 16256916 4.24% 89.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 7587599 1.98% 91.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 6965408 1.82% 93.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3084029 0.80% 94.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 22424705 5.85% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 165593996 43.88% 43.88% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 102356552 27.13% 71.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 34023160 9.02% 80.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 18860248 5.00% 85.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 16133947 4.28% 89.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 7612237 2.02% 91.32% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 6942439 1.84% 93.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3075088 0.81% 93.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 22740606 6.03% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 383329557 # Number of insts commited each cycle -system.cpu.commit.committedInsts 510299107 # Number of instructions committed -system.cpu.commit.committedOps 574685667 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 377338273 # Number of insts commited each cycle +system.cpu.commit.committedInsts 510299127 # Number of instructions committed +system.cpu.commit.committedOps 574685687 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 184377032 # Number of memory references committed -system.cpu.commit.loads 126773055 # Number of loads committed +system.cpu.commit.refs 184377040 # Number of memory references committed +system.cpu.commit.loads 126773059 # Number of loads committed system.cpu.commit.membars 1488542 # Number of memory barriers committed -system.cpu.commit.branches 122291801 # Number of branches committed +system.cpu.commit.branches 122291805 # Number of branches committed system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. -system.cpu.commit.int_insts 473701693 # Number of committed integer instructions. +system.cpu.commit.int_insts 473701709 # Number of committed integer instructions. system.cpu.commit.function_calls 9757362 # Number of function calls committed. -system.cpu.commit.bw_lim_events 22424705 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 22740606 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1135058037 # The number of ROB reads -system.cpu.rob.rob_writes 1577598411 # The number of ROB writes -system.cpu.timesIdled 306064 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 7117395 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 508955223 # Number of Instructions Simulated -system.cpu.committedOps 573341783 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 508955223 # Number of Instructions Simulated -system.cpu.cpi 0.824401 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.824401 # CPI: Total CPI of All Threads -system.cpu.ipc 1.213002 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.213002 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3101759208 # number of integer regfile reads -system.cpu.int_regfile_writes 762565130 # number of integer regfile writes +system.cpu.rob.rob_reads 1118592088 # The number of ROB reads +system.cpu.rob.rob_writes 1555667472 # The number of ROB writes +system.cpu.timesIdled 306583 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 7157899 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 508955243 # Number of Instructions Simulated +system.cpu.committedOps 573341803 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 508955243 # Number of Instructions Simulated +system.cpu.cpi 0.809580 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.809580 # CPI: Total CPI of All Threads +system.cpu.ipc 1.235209 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.235209 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3078155858 # number of integer regfile reads +system.cpu.int_regfile_writes 757766233 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.misc_regfile_reads 1004803161 # number of misc regfile reads -system.cpu.misc_regfile_writes 4464084 # number of misc regfile writes -system.cpu.icache.replacements 15462 # number of replacements -system.cpu.icache.tagsinuse 1099.228607 # Cycle average of tags in use -system.cpu.icache.total_refs 115634831 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 17331 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 6672.138422 # Average number of references to valid blocks. +system.cpu.misc_regfile_reads 990216760 # number of misc regfile reads +system.cpu.misc_regfile_writes 4464092 # number of misc regfile writes +system.cpu.icache.replacements 14932 # number of replacements +system.cpu.icache.tagsinuse 1085.088818 # Cycle average of tags in use +system.cpu.icache.total_refs 113022367 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 16785 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 6733.533929 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1099.228607 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.536733 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.536733 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 115634831 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 115634831 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 115634831 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 115634831 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 115634831 # number of overall hits -system.cpu.icache.overall_hits::total 115634831 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 21629 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 21629 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 21629 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 21629 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 21629 # number of overall misses -system.cpu.icache.overall_misses::total 21629 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 475311000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 475311000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 475311000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 475311000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 475311000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 475311000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 115656460 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 115656460 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 115656460 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 115656460 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 115656460 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 115656460 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000187 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000187 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000187 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000187 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000187 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000187 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21975.634565 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 21975.634565 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 21975.634565 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 21975.634565 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 21975.634565 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 21975.634565 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 436 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 1085.088818 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.529829 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.529829 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 113022367 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 113022367 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 113022367 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 113022367 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 113022367 # number of overall hits +system.cpu.icache.overall_hits::total 113022367 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 20976 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 20976 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 20976 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 20976 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 20976 # number of overall misses +system.cpu.icache.overall_misses::total 20976 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 467556999 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 467556999 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 467556999 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 467556999 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 467556999 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 467556999 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 113043343 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 113043343 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 113043343 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 113043343 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 113043343 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 113043343 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000186 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000186 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000186 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000186 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000186 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000186 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22290.093392 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 22290.093392 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 22290.093392 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 22290.093392 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 22290.093392 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 22290.093392 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 1102 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 10 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 12 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 43.600000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 91.833333 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 4227 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 4227 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 4227 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 4227 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 4227 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 4227 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 17402 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 17402 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 17402 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 17402 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 17402 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 17402 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 349731500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 349731500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 349731500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 349731500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 349731500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 349731500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000150 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000150 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000150 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000150 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000150 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000150 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20097.201471 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20097.201471 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20097.201471 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 20097.201471 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20097.201471 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 20097.201471 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 4107 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 4107 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 4107 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 4107 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 4107 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 4107 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 16869 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 16869 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 16869 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 16869 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 16869 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 16869 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 341781999 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 341781999 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 341781999 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 341781999 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 341781999 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 341781999 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000149 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000149 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000149 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000149 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000149 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000149 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20260.951983 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20260.951983 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20260.951983 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 20260.951983 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20260.951983 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 20260.951983 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1191468 # number of replacements -system.cpu.dcache.tagsinuse 4055.451159 # Cycle average of tags in use -system.cpu.dcache.total_refs 193136730 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1195564 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 161.544451 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 4668381000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4055.451159 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.990100 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.990100 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 137669566 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 137669566 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 51001637 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 51001637 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 2233291 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 2233291 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 2232041 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 2232041 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 188671203 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 188671203 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 188671203 # number of overall hits -system.cpu.dcache.overall_hits::total 188671203 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1694127 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1694127 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 3237669 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 3237669 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 43 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 43 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 4931796 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 4931796 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 4931796 # number of overall misses -system.cpu.dcache.overall_misses::total 4931796 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 25989593000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 25989593000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 58741692947 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 58741692947 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 673500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 673500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 84731285947 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 84731285947 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 84731285947 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 84731285947 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 139363693 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 139363693 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 2233334 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 2233334 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 2232041 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 2232041 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 193602999 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 193602999 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 193602999 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 193602999 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012156 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.012156 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.059692 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.059692 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000019 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000019 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.025474 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.025474 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.025474 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.025474 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15340.994506 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 15340.994506 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 18143.205172 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 18143.205172 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15662.790698 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15662.790698 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 17180.614516 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 17180.614516 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 17180.614516 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 17180.614516 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 15718 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 14943 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1597 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 604 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.842204 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 24.740066 # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1109851 # number of writebacks -system.cpu.dcache.writebacks::total 1109851 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 846782 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 846782 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2889379 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2889379 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 43 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 43 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3736161 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3736161 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3736161 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3736161 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 847345 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 847345 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 348290 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 348290 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1195635 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1195635 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1195635 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1195635 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 11450908500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 11450908500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8277361494 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8277361494 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 19728269994 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 19728269994 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 19728269994 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 19728269994 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006080 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006080 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006421 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006421 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006176 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.006176 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006176 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.006176 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13513.868023 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13513.868023 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 23765.716771 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 23765.716771 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16500.244635 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 16500.244635 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16500.244635 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 16500.244635 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 115394 # number of replacements -system.cpu.l2cache.tagsinuse 26924.508284 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1779847 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 146649 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 12.136782 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 108175523000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 22883.739397 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 368.975633 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 3671.793254 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.698356 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.011260 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.112054 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.821671 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 13925 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 803306 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 817231 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 1109851 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 1109851 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 63 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 63 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 247487 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 247487 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 13925 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1050793 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1064718 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 13925 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1050793 # number of overall hits -system.cpu.l2cache.overall_hits::total 1064718 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 3397 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 43505 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 46902 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 7 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 7 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 101267 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 101267 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 3397 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 144772 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 148169 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 3397 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 144772 # number of overall misses -system.cpu.l2cache.overall_misses::total 148169 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 192541000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2532706500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 2725247500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5404683000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 5404683000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 192541000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 7937389500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 8129930500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 192541000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 7937389500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 8129930500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 17322 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 846811 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 864133 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 1109851 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 1109851 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 70 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 70 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 348754 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 348754 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 17322 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1195565 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 1212887 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 17322 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1195565 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 1212887 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.196109 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.051375 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.054276 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.100000 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.100000 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.290368 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.290368 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.196109 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.121091 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.122162 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.196109 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.121091 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.122162 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 56679.717398 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 58216.446385 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 58105.144770 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 53370.624191 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 53370.624191 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 56679.717398 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 54826.827701 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 54869.308020 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 56679.717398 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 54826.827701 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 54869.308020 # average overall miss latency +system.cpu.l2cache.replacements 115429 # number of replacements +system.cpu.l2cache.tagsinuse 26914.468199 # Cycle average of tags in use +system.cpu.l2cache.total_refs 1780391 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 146682 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 12.137761 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 106781718500 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::writebacks 22891.161180 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 363.700346 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 3659.606672 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.698583 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.011099 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.111682 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.821364 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 13362 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 804051 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 817413 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 1110628 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 1110628 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 67 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 67 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 247445 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 247445 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 13362 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 1051496 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 1064858 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 13362 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 1051496 # number of overall hits +system.cpu.l2cache.overall_hits::total 1064858 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 3407 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 43491 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 46898 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 16 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 16 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 101307 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 101307 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 3407 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 144798 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 148205 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 3407 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 144798 # number of overall misses +system.cpu.l2cache.overall_misses::total 148205 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 190701000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2548389999 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 2739090999 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 46000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 46000 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5385063000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 5385063000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 190701000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 7933452999 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 8124153999 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 190701000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 7933452999 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 8124153999 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 16769 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 847542 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 864311 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 1110628 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 1110628 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 83 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 83 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 348752 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 348752 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 16769 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1196294 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 1213063 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 16769 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1196294 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 1213063 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.203173 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.051314 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.054261 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.192771 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.192771 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.290484 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.290484 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.203173 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.121039 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.122174 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.203173 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.121039 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.122174 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 55973.290285 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 58595.801407 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 58405.283786 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 2875 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 2875 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 53155.882614 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 53155.882614 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 55973.290285 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 54789.796813 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 54817.003468 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 55973.290285 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 54789.796813 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 54817.003468 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -813,69 +691,195 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 97680 # number of writebacks -system.cpu.l2cache.writebacks::total 97680 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 4 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 23 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 27 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 4 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 23 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 27 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 4 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 23 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 27 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3393 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 43482 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 46875 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 7 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 7 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 101267 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 101267 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3393 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 144749 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 148142 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3393 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 144749 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 148142 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 149378245 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1976833843 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2126212088 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 70007 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 70007 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4117136823 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4117136823 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 149378245 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6093970666 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 6243348911 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 149378245 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6093970666 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 6243348911 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.195878 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.051348 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.054245 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.100000 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.100000 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.290368 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.290368 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.195878 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.121072 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.122140 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.195878 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.121072 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.122140 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 44025.418509 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 45463.268548 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 45359.191211 # average ReadReq mshr miss latency +system.cpu.l2cache.writebacks::writebacks 97624 # number of writebacks +system.cpu.l2cache.writebacks::total 97624 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 7 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 22 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 29 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 7 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 22 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 29 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 7 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 22 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 29 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3400 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 43469 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 46869 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 16 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 16 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 101307 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 101307 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3400 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 144776 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 148176 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3400 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 144776 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 148176 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 147345791 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1992861298 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2140207089 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 160016 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 160016 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4096834986 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4096834986 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 147345791 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6089696284 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 6237042075 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 147345791 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6089696284 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 6237042075 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.202755 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.051288 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.054227 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.192771 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.192771 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.290484 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.290484 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.202755 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.121020 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.122150 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.202755 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.121020 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.122150 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 43336.997353 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 45845.574961 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 45663.596172 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40656.253498 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40656.253498 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 44025.418509 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42100.260907 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42144.354140 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 44025.418509 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42100.260907 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42144.354140 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40439.801652 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40439.801652 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 43336.997353 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42062.885312 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42092.120688 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 43336.997353 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42062.885312 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42092.120688 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.replacements 1192198 # number of replacements +system.cpu.dcache.tagsinuse 4054.757782 # Cycle average of tags in use +system.cpu.dcache.total_refs 191677610 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1196294 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 160.226173 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 4661028000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4054.757782 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.989931 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.989931 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 136219311 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 136219311 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 50992877 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 50992877 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 2233119 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 2233119 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 2232045 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 2232045 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 187212188 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 187212188 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 187212188 # number of overall hits +system.cpu.dcache.overall_hits::total 187212188 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1693600 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1693600 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 3246429 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 3246429 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 39 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 39 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 4940029 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 4940029 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 4940029 # number of overall misses +system.cpu.dcache.overall_misses::total 4940029 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 25893319000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 25893319000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 58743058946 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 58743058946 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 632500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 632500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 84636377946 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 84636377946 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 84636377946 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 84636377946 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 137912911 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 137912911 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 2233158 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 2233158 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 2232045 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 2232045 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 192152217 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 192152217 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 192152217 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 192152217 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012280 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.012280 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.059854 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.059854 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000017 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000017 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.025709 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.025709 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.025709 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.025709 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15288.922414 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 15288.922414 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 18094.669234 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 18094.669234 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16217.948718 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16217.948718 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 17132.769453 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 17132.769453 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 17132.769453 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 17132.769453 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 16010 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 16009 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1643 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 605 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.744370 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 26.461157 # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 1110628 # number of writebacks +system.cpu.dcache.writebacks::total 1110628 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 845499 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 845499 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2898153 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2898153 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 39 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 39 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3743652 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3743652 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3743652 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3743652 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 848101 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 848101 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 348276 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 348276 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1196377 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1196377 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1196377 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1196377 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 11475197000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 11475197000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8257593997 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8257593997 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 19732790997 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 19732790997 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 19732790997 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 19732790997 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006150 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006150 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006421 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006421 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006226 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.006226 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006226 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.006226 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13530.460405 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13530.460405 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 23709.913968 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 23709.913968 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16493.789998 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 16493.789998 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16493.789998 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 16493.789998 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini b/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini index 7d5241595..39d5d8c7f 100644 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini @@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a -clock=1 +clock=1000 init_param=0 kernel= load_addr_mask=1099511627775 @@ -30,7 +30,7 @@ system_port=system.membus.slave[0] [system.cpu] type=DerivO3CPU -children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload +children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -78,6 +78,7 @@ iewToFetchDelay=1 iewToRenameDelay=1 instShiftAmt=2 interrupts=system.cpu.interrupts +isa=system.cpu.isa issueToExecuteDelay=1 issueWidth=8 itb=system.cpu.itb @@ -129,17 +130,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=2 is_top_level=true -latency=1000 max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=2 size=262144 subblock_size=0 system=system @@ -158,7 +160,7 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=X86PagetableWalker -clock=1 +clock=500 system=system port=system.cpu.toL2Bus.slave[3] @@ -430,17 +432,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=2 is_top_level=true -latency=1000 max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=2 size=131072 subblock_size=0 system=system @@ -453,7 +456,7 @@ mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=X86LocalApic -clock=1 +clock=500 int_latency=1000 pio_addr=2305843009213693952 pio_latency=100000 @@ -462,6 +465,9 @@ int_master=system.membus.slave[2] int_slave=system.membus.master[2] pio=system.membus.master[1] +[system.cpu.isa] +type=X86ISA + [system.cpu.itb] type=X86TLB children=walker @@ -470,30 +476,31 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=X86PagetableWalker -clock=1 +clock=500 system=system port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] type=BaseCache addr_ranges=0:18446744073709551615 -assoc=2 +assoc=8 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=20 is_top_level=false -latency=1000 max_miss_count=0 -mshrs=10 +mshrs=20 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=20 size=2097152 subblock_size=0 system=system -tgts_per_mshr=5 +tgts_per_mshr=12 trace_addr=0 two_queue=false write_buffers=8 @@ -503,10 +510,10 @@ mem_side=system.membus.slave[1] [system.cpu.toL2Bus] type=CoherentBus block_size=64 -clock=1000 +clock=500 header_cycles=1 use_default_range=false -width=8 +width=32 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port @@ -521,9 +528,9 @@ egid=100 env= errout=cerr euid=100 -executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/parser +executable=/projects/pd/randd/dist/cpu2000/binaries/x86/linux/parser gid=100 -input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/parser/mdred/input/parser.in +input=/projects/pd/randd/dist/cpu2000/data/parser/mdred/input/parser.in max_stack_size=67108864 output=cout pid=100 @@ -543,15 +550,28 @@ master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_s slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master [system.physmem] -type=SimpleMemory -clock=1 +type=SimpleDRAM +addr_mapping=openmap +banks_per_rank=8 +clock=1000 conf_table_reported=false -file= in_addr_map=true -latency=30000 -latency_var=0 +lines_per_rowbuffer=64 +mem_sched_policy=fcfs null=false +page_policy=open range=0:134217727 +ranks_per_channel=2 +read_buffer_size=32 +tBURST=4000 +tCL=14000 +tRCD=14000 +tREFI=7800000 +tRFC=300000 +tRP=14000 +tWTR=1000 +write_buffer_size=32 +write_thresh_perc=70 zero=false port=system.membus.master[0] diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout b/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout index 31324de53..f635f915d 100755 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout @@ -1,17 +1,15 @@ -Redirecting stdout to build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing/simout -Redirecting stderr to build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 10 2012 22:29:00 -gem5 started Sep 10 2012 22:33:09 -gem5 executing on ribera.cs.wisc.edu +gem5 compiled Oct 30 2012 11:14:29 +gem5 started Oct 30 2012 16:49:35 +gem5 executing on u200540-lin command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. Reading the dictionary files: *********info: Increasing stack size by one page. +**************************************info: Increasing stack size by one page. info: Increasing stack size by one page. info: Increasing stack size by one page. info: Increasing stack size by one page. @@ -24,7 +22,7 @@ info: Increasing stack size by one page. info: Increasing stack size by one page. info: Increasing stack size by one page. info: Increasing stack size by one page. -**************************************** +** 58924 words stored in 3784810 bytes @@ -82,4 +80,4 @@ Echoing of input sentence turned on. about 2 million people attended the five best costumes got prizes No errors! -Exiting @ tick 433562236500 because target called exit() +Exiting @ tick 434496110500 because target called exit() diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt index 0b91be0ea..05261b47d 100644 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt @@ -1,90 +1,90 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.447151 # Number of seconds simulated -sim_ticks 447151291000 # Number of ticks simulated -final_tick 447151291000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.434496 # Number of seconds simulated +sim_ticks 434496110500 # Number of ticks simulated +final_tick 434496110500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 99582 # Simulator instruction rate (inst/s) -host_op_rate 184139 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 53851139 # Simulator tick rate (ticks/s) -host_mem_usage 337048 # Number of bytes of host memory used -host_seconds 8303.47 # Real time elapsed on the host +host_inst_rate 78440 # Simulator instruction rate (inst/s) +host_op_rate 145045 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 41217689 # Simulator tick rate (ticks/s) +host_mem_usage 343084 # Number of bytes of host memory used +host_seconds 10541.50 # Real time elapsed on the host sim_insts 826877109 # Number of instructions simulated sim_ops 1528988699 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 207040 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24466624 # Number of bytes read from this memory -system.physmem.bytes_read::total 24673664 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 207040 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 207040 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 18786368 # Number of bytes written to this memory -system.physmem.bytes_written::total 18786368 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 3235 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 382291 # Number of read requests responded to by this memory -system.physmem.num_reads::total 385526 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 293537 # Number of write requests responded to by this memory -system.physmem.num_writes::total 293537 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 463020 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 54716657 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 55179677 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 463020 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 463020 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 42013449 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 42013449 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 42013449 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 463020 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 54716657 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 97193127 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 385528 # Total number of read requests seen -system.physmem.writeReqs 293537 # Total number of write requests seen -system.physmem.cpureqs 863596 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 24673664 # Total number of bytes read from memory -system.physmem.bytesWritten 18786368 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 24673664 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 18786368 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 164 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 184531 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 24996 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 23035 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 24534 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 25301 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 24892 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 24563 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 23920 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 24683 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 22800 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 23577 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 23208 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 23396 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 24161 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 24133 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 24010 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 24155 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 19354 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 17947 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 18690 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 18990 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 19041 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 18723 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 18099 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 18501 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 17450 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 17927 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 17723 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 17609 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 18440 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 18279 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 18321 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 18443 # Track writes on a per bank basis +system.physmem.bytes_read::cpu.inst 205760 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24473920 # Number of bytes read from this memory +system.physmem.bytes_read::total 24679680 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 205760 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 205760 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 18793728 # Number of bytes written to this memory +system.physmem.bytes_written::total 18793728 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 3215 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 382405 # Number of read requests responded to by this memory +system.physmem.num_reads::total 385620 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 293652 # Number of write requests responded to by this memory +system.physmem.num_writes::total 293652 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 473560 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 56327133 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 56800693 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 473560 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 473560 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 43254076 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 43254076 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 43254076 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 473560 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 56327133 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 100054769 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 385622 # Total number of read requests seen +system.physmem.writeReqs 293652 # Total number of write requests seen +system.physmem.cpureqs 889960 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 24679680 # Total number of bytes read from memory +system.physmem.bytesWritten 18793728 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 24679680 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 18793728 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 136 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 210686 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 24775 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 22937 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 24964 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 25246 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 24873 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 24535 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 23841 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 24700 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 22880 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 23587 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 23221 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 23429 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 24164 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 24144 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 24092 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 24098 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 19149 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 17956 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 18934 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 18992 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 19023 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 18726 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 18089 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 18519 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 17452 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 17936 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 17736 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 17628 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 18448 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 18286 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 18332 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 18446 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 447151273000 # Total gap between requests +system.physmem.totGap 434496092500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 385528 # Categorize read packet sizes +system.physmem.readPktSize::6 385622 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -93,7 +93,7 @@ system.physmem.writePktSize::2 0 # ca system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 293537 # categorize write packet sizes +system.physmem.writePktSize::6 293652 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -102,16 +102,16 @@ system.physmem.neitherpktsize::2 0 # ca system.physmem.neitherpktsize::3 0 # categorize neither packet sizes system.physmem.neitherpktsize::4 0 # categorize neither packet sizes system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 184531 # categorize neither packet sizes +system.physmem.neitherpktsize::6 210686 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 380682 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 4205 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 406 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 54 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 11 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 380872 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 4191 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 366 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 51 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see @@ -138,31 +138,31 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 12758 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 12762 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 12763 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 12763 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 12763 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 12763 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 12763 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 12763 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 12763 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 12763 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 12763 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 12762 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 12762 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 12762 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 12762 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 12762 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 12762 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 12762 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 12762 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 12762 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 12762 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 12762 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 12762 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 12765 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 12768 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 12768 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 12768 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 12768 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 12768 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 12768 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 12768 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 12768 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 12768 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 12768 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 12767 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 12767 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 12767 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 12767 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 12767 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 12767 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 12767 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 12767 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 12767 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 12767 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 12767 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 12767 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see @@ -171,266 +171,267 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 3526127005 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 11592689005 # Sum of mem lat for all requests -system.physmem.totBusLat 1541456000 # Total cycles spent in databus access -system.physmem.totBankLat 6525106000 # Total cycles spent in bank access -system.physmem.avgQLat 9150.12 # Average queueing delay per request -system.physmem.avgBankLat 16932.32 # Average bank access latency per request +system.physmem.totQLat 3490991093 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 11561975093 # Sum of mem lat for all requests +system.physmem.totBusLat 1541944000 # Total cycles spent in databus access +system.physmem.totBankLat 6529040000 # Total cycles spent in bank access +system.physmem.avgQLat 9056.08 # Average queueing delay per request +system.physmem.avgBankLat 16937.17 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 30082.44 # Average memory access latency -system.physmem.avgRdBW 55.18 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 42.01 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 55.18 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 42.01 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 29993.24 # Average memory access latency +system.physmem.avgRdBW 56.80 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 43.25 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 56.80 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 43.25 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 0.61 # Data bus utilization in percentage +system.physmem.busUtil 0.63 # Data bus utilization in percentage system.physmem.avgRdQLen 0.03 # Average read queue length over time -system.physmem.avgWrQLen 8.93 # Average write queue length over time -system.physmem.readRowHits 340552 # Number of row buffer hits during reads -system.physmem.writeRowHits 151633 # Number of row buffer hits during writes -system.physmem.readRowHitRate 88.37 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 51.66 # Row buffer hit rate for writes -system.physmem.avgGap 658480.81 # Average gap between requests +system.physmem.avgWrQLen 9.57 # Average write queue length over time +system.physmem.readRowHits 340592 # Number of row buffer hits during reads +system.physmem.writeRowHits 151278 # Number of row buffer hits during writes +system.physmem.readRowHitRate 88.35 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 51.52 # Row buffer hit rate for writes +system.physmem.avgGap 639647.76 # Average gap between requests system.cpu.workload.num_syscalls 551 # Number of system calls -system.cpu.numCycles 894302583 # number of cpu cycles simulated +system.cpu.numCycles 868992222 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 221834419 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 221834419 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 14438837 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 157195941 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 152967077 # Number of BTB hits +system.cpu.BPredUnit.lookups 214993851 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 214993851 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 13132727 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 150483811 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 147870058 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 187305514 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1233712111 # Number of instructions fetch has processed -system.cpu.fetch.Branches 221834419 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 152967077 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 383213555 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 92482547 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 231997744 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 31125 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 302541 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 64 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 179659779 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 4113909 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 880638441 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.600745 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.391861 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 180595819 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1193570142 # Number of instructions fetch has processed +system.cpu.fetch.Branches 214993851 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 147870058 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 371300946 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 83432044 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 232898189 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 32611 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 320539 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 60 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 173489759 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 3820168 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 855191197 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.591382 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.388294 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 501847528 56.99% 56.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 25496575 2.90% 59.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 28121767 3.19% 63.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 29451767 3.34% 66.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 18987914 2.16% 68.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 25123088 2.85% 71.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 31720196 3.60% 75.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 30784274 3.50% 78.53% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 189105332 21.47% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 488292980 57.10% 57.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 24712697 2.89% 59.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 27343487 3.20% 63.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 28814936 3.37% 66.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 18484341 2.16% 68.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 24598023 2.88% 71.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 30669616 3.59% 75.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 28863276 3.38% 78.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 183411841 21.45% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 880638441 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.248053 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.379524 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 244537844 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 188536263 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 324191261 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 45585175 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 77787898 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 2236907904 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 77787898 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 278585274 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 54813178 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 15041 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 333395312 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 136041738 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2184748951 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 34526 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 20261515 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 101530735 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 116 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 2284488026 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 5524710294 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 5524485031 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 225263 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 855191197 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.247406 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.373511 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 237057033 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 189447507 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 313514348 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 45129276 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 70043033 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 2167224659 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 2 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 70043033 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 270477979 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 55455808 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 15344 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 322737561 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 136461472 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2120443257 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 31742 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 21271807 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 100951250 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 96 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 2216845941 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 5356850652 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 5356713794 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 136858 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1614040851 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 670447175 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1310 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1291 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 328673064 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 528947917 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 211077156 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 202192665 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 58804191 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2090539379 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 34704 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1836706736 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 960329 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 555260187 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 919296135 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 34151 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 880638441 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.085654 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.886104 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 602805090 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1368 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1337 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 329763590 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 512746819 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 204948217 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 196647356 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 55718334 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2034222855 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 23204 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1808269086 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 840688 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 499770877 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 818821894 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 22651 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 855191197 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.114462 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.887618 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 249855133 28.37% 28.37% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 147643393 16.77% 45.14% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 139523467 15.84% 60.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 137737388 15.64% 76.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 97163823 11.03% 87.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 59916022 6.80% 94.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 34917189 3.96% 98.42% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 11990499 1.36% 99.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1891527 0.21% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 234669237 27.44% 27.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 145408124 17.00% 44.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 138604269 16.21% 60.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 132699771 15.52% 76.17% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 96142027 11.24% 87.41% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 58835818 6.88% 94.29% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 34929865 4.08% 98.37% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 11989965 1.40% 99.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1912121 0.22% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 880638441 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 855191197 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 5040061 32.96% 32.96% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 32.96% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 32.96% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.96% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.96% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.96% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 32.96% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.96% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 32.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 32.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.96% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 7632140 49.91% 82.87% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 2619273 17.13% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 4982607 32.47% 32.47% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 32.47% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 32.47% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.47% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.47% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.47% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 32.47% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.47% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 32.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 32.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.47% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 7772291 50.65% 83.11% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 2591536 16.89% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 2704214 0.15% 0.15% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1211533027 65.96% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 444457178 24.20% 90.31% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 178012317 9.69% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 2719540 0.15% 0.15% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1190958422 65.86% 66.01% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 66.01% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.01% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 66.01% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.01% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.01% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.01% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.01% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.01% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 438908111 24.27% 90.28% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 175683013 9.72% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1836706736 # Type of FU issued -system.cpu.iq.rate 2.053787 # Inst issue rate -system.cpu.iq.fu_busy_cnt 15291474 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.008325 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 4570263035 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2646020420 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1794037475 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 40681 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 76210 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 9614 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1849275039 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 18957 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 170130474 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1808269086 # Type of FU issued +system.cpu.iq.rate 2.080881 # Inst issue rate +system.cpu.iq.fu_busy_cnt 15346434 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.008487 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 4487893952 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2534230949 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1768791787 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 22539 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 44036 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 5119 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1820885356 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 10624 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 170553013 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 144845761 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 503638 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 274982 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 61917680 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 128644663 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 472582 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 269715 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 55788376 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 10585 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 592 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 12339 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1555 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 77787898 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 17508647 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 2908748 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2090574083 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 2437552 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 528947917 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 211077865 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 5687 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1841603 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 73588 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 274982 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 10048689 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 4929582 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 14978271 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1806703840 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 436137965 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 30002896 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 70043033 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 17673850 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 2842089 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2034246059 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 2370262 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 512746819 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 204948561 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 6149 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1800682 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 76001 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 269715 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 9110771 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 4492681 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 13603452 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1780575608 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 431395989 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 27693478 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 608784008 # number of memory reference insts executed -system.cpu.iew.exec_branches 171260555 # Number of branches executed -system.cpu.iew.exec_stores 172646043 # Number of stores executed -system.cpu.iew.exec_rate 2.020238 # Inst execution rate -system.cpu.iew.wb_sent 1801373489 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1794047089 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1362133405 # num instructions producing a value -system.cpu.iew.wb_consumers 1992639116 # num instructions consuming a value +system.cpu.iew.exec_refs 602081251 # number of memory reference insts executed +system.cpu.iew.exec_branches 169281204 # Number of branches executed +system.cpu.iew.exec_stores 170685262 # Number of stores executed +system.cpu.iew.exec_rate 2.049012 # Inst execution rate +system.cpu.iew.wb_sent 1775484026 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1768796906 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1341657182 # num instructions producing a value +system.cpu.iew.wb_consumers 1964610476 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.006085 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.683583 # average fanout of values written-back +system.cpu.iew.wb_rate 2.035458 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.682913 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 561620004 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 505293245 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 553 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 14469462 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 802850543 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.904450 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.430311 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 13164973 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 785148164 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.947389 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.457160 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 304835163 37.97% 37.97% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 198905096 24.77% 62.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 63436109 7.90% 70.65% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 92154984 11.48% 82.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 26044111 3.24% 85.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 29384573 3.66% 89.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 9423573 1.17% 90.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 10229786 1.27% 91.48% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 68437148 8.52% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 291743548 37.16% 37.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 195452528 24.89% 62.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 62380641 7.95% 70.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 92170452 11.74% 81.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 25089847 3.20% 84.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 28355719 3.61% 88.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 9376881 1.19% 89.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 10764120 1.37% 91.11% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 69814428 8.89% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 802850543 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 785148164 # Number of insts commited each cycle system.cpu.commit.committedInsts 826877109 # Number of instructions committed system.cpu.commit.committedOps 1528988699 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -441,311 +442,203 @@ system.cpu.commit.branches 149758583 # Nu system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. system.cpu.commit.int_insts 1528317557 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 68437148 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 69814428 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 2825022098 # The number of ROB reads -system.cpu.rob.rob_writes 4259228710 # The number of ROB writes -system.cpu.timesIdled 301112 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 13664142 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 2749615680 # The number of ROB reads +system.cpu.rob.rob_writes 4138789024 # The number of ROB writes +system.cpu.timesIdled 344205 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 13801025 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 826877109 # Number of Instructions Simulated system.cpu.committedOps 1528988699 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 826877109 # Number of Instructions Simulated -system.cpu.cpi 1.081542 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.081542 # CPI: Total CPI of All Threads -system.cpu.ipc 0.924606 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.924606 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3392416402 # number of integer regfile reads -system.cpu.int_regfile_writes 1873878910 # number of integer regfile writes -system.cpu.fp_regfile_reads 9612 # number of floating regfile reads -system.cpu.fp_regfile_writes 2 # number of floating regfile writes -system.cpu.misc_regfile_reads 993805261 # number of misc regfile reads -system.cpu.icache.replacements 5664 # number of replacements -system.cpu.icache.tagsinuse 1040.414195 # Cycle average of tags in use -system.cpu.icache.total_refs 179444520 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 7258 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 24723.686966 # Average number of references to valid blocks. +system.cpu.cpi 1.050933 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.050933 # CPI: Total CPI of All Threads +system.cpu.ipc 0.951536 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.951536 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3357495880 # number of integer regfile reads +system.cpu.int_regfile_writes 1848564966 # number of integer regfile writes +system.cpu.fp_regfile_reads 5116 # number of floating regfile reads +system.cpu.fp_regfile_writes 3 # number of floating regfile writes +system.cpu.misc_regfile_reads 980239891 # number of misc regfile reads +system.cpu.icache.replacements 5389 # number of replacements +system.cpu.icache.tagsinuse 1038.396160 # Cycle average of tags in use +system.cpu.icache.total_refs 173252420 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 6992 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 24778.664188 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1040.414195 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.508015 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.508015 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 179464097 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 179464097 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 179464097 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 179464097 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 179464097 # number of overall hits -system.cpu.icache.overall_hits::total 179464097 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 195682 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 195682 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 195682 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 195682 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 195682 # number of overall misses -system.cpu.icache.overall_misses::total 195682 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 1231899498 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 1231899498 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 1231899498 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 1231899498 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 1231899498 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 1231899498 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 179659779 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 179659779 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 179659779 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 179659779 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 179659779 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 179659779 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001089 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.001089 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.001089 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.001089 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.001089 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.001089 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 6295.415511 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 6295.415511 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 6295.415511 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 6295.415511 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 6295.415511 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 6295.415511 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 959 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 1038.396160 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.507029 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.507029 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 173268230 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 173268230 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 173268230 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 173268230 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 173268230 # number of overall hits +system.cpu.icache.overall_hits::total 173268230 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 221529 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 221529 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 221529 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 221529 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 221529 # number of overall misses +system.cpu.icache.overall_misses::total 221529 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 1367876999 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 1367876999 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 1367876999 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 1367876999 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 1367876999 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 1367876999 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 173489759 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 173489759 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 173489759 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 173489759 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 173489759 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 173489759 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001277 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.001277 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.001277 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.001277 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.001277 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.001277 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 6174.708499 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 6174.708499 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 6174.708499 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 6174.708499 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 6174.708499 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 6174.708499 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 496 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 17 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 18 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 56.411765 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 27.555556 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2352 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 2352 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 2352 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 2352 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 2352 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 2352 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 193330 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 193330 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 193330 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 193330 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 193330 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 193330 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 781617498 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 781617498 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 781617498 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 781617498 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 781617498 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 781617498 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001076 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001076 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001076 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.001076 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001076 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.001076 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 4042.918833 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 4042.918833 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 4042.918833 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 4042.918833 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 4042.918833 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 4042.918833 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2325 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 2325 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 2325 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 2325 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 2325 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 2325 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 219204 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 219204 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 219204 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 219204 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 219204 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 219204 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 865886999 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 865886999 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 865886999 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 865886999 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 865886999 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 865886999 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001263 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001263 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001263 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.001263 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001263 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.001263 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 3950.142329 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 3950.142329 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 3950.142329 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 3950.142329 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 3950.142329 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 3950.142329 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 2529793 # number of replacements -system.cpu.dcache.tagsinuse 4087.981859 # Cycle average of tags in use -system.cpu.dcache.total_refs 410271543 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 2533889 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 161.913779 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 1794023000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4087.981859 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.998042 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.998042 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 261613799 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 261613799 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 148186041 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 148186041 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 409799840 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 409799840 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 409799840 # number of overall hits -system.cpu.dcache.overall_hits::total 409799840 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2816252 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2816252 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 974160 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 974160 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 3790412 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3790412 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3790412 # number of overall misses -system.cpu.dcache.overall_misses::total 3790412 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 49180630000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 49180630000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 23742046000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 23742046000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 72922676000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 72922676000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 72922676000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 72922676000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 264430051 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 264430051 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 149160201 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 149160201 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 413590252 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 413590252 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 413590252 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 413590252 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.010650 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.010650 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006531 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.006531 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.009165 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.009165 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.009165 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.009165 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17463.149605 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 17463.149605 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24371.813665 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 24371.813665 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 19238.720224 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 19238.720224 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 19238.720224 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 19238.720224 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 6306 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 671 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.397914 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2331455 # number of writebacks -system.cpu.dcache.writebacks::total 2331455 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1053646 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1053646 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16861 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 16861 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1070507 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1070507 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1070507 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1070507 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1762606 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1762606 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 957299 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 957299 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2719905 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2719905 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2719905 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2719905 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 26907249500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 26907249500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 21627560000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 21627560000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 48534809500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 48534809500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 48534809500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 48534809500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006666 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006666 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006418 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006418 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006576 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.006576 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006576 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.006576 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15265.606437 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15265.606437 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22592.272634 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22592.272634 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17844.303202 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 17844.303202 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17844.303202 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 17844.303202 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 352840 # number of replacements -system.cpu.l2cache.tagsinuse 29572.307883 # Cycle average of tags in use -system.cpu.l2cache.total_refs 3696862 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 385170 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 9.598001 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 211000207000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 21064.458635 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 238.476437 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 8269.372811 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.642836 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.007278 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.252361 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.902475 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 3978 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 1586642 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1590620 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 2331455 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 2331455 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 1524 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 1524 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 564916 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 564916 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 3978 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 2151558 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2155536 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 3978 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 2151558 # number of overall hits -system.cpu.l2cache.overall_hits::total 2155536 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 3236 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 175667 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 178903 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 184491 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 184491 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 206666 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 206666 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 3236 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 382333 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 385569 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 3236 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 382333 # number of overall misses -system.cpu.l2cache.overall_misses::total 385569 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 187805000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 9240729957 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 9428534957 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 7282500 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 7282500 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10987147000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 10987147000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 187805000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 20227876957 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 20415681957 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 187805000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 20227876957 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 20415681957 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 7214 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1762309 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 1769523 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 2331455 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 2331455 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 186015 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 186015 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 771582 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 771582 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 7214 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 2533891 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2541105 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 7214 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 2533891 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2541105 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.448572 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.099680 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.101102 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.991807 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.991807 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.267847 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.267847 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.448572 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.150888 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.151733 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.448572 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.150888 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.151733 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 58036.155748 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52603.676029 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52701.938799 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 39.473470 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 39.473470 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 53163.786012 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 53163.786012 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 58036.155748 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52906.437469 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52949.490122 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 58036.155748 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52906.437469 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52949.490122 # average overall miss latency +system.cpu.l2cache.replacements 352935 # number of replacements +system.cpu.l2cache.tagsinuse 29621.088782 # Cycle average of tags in use +system.cpu.l2cache.total_refs 3697485 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 385298 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 9.596429 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 201835510000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::writebacks 21057.332027 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 231.203913 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 8332.552842 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.642619 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.007056 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.254289 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.903964 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 3731 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 1586467 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1590198 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 2331049 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 2331049 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 1506 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 1506 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 564628 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 564628 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 3731 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 2151095 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2154826 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 3731 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 2151095 # number of overall hits +system.cpu.l2cache.overall_hits::total 2154826 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 3216 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 175678 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 178894 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 210659 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 210659 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 206756 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 206756 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 3216 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 382434 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 385650 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 3216 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 382434 # number of overall misses +system.cpu.l2cache.overall_misses::total 385650 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 180593000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 9239203954 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 9419796954 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 7234500 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 7234500 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10965110500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 10965110500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 180593000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 20204314454 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 20384907454 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 180593000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 20204314454 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 20384907454 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 6947 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 1762145 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 1769092 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 2331049 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 2331049 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 212165 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 212165 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 771384 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 771384 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 6947 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 2533529 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2540476 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 6947 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 2533529 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2540476 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.462934 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.099696 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.101122 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.992902 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.992902 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.268033 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.268033 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.462934 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.150949 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.151802 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.462934 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.150949 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.151802 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 56154.539801 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52591.695910 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52655.745604 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 34.342231 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 34.342231 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 53034.061889 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 53034.061889 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 56154.539801 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52830.853047 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52858.569828 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 56154.539801 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52830.853047 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52858.569828 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -754,60 +647,168 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 293537 # number of writebacks -system.cpu.l2cache.writebacks::total 293537 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3236 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 175667 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 178903 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 184491 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 184491 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206666 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 206666 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3236 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 382333 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 385569 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3236 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 382333 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 385569 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 146938362 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6979134954 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 7126073316 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1849956331 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1849956331 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8352740653 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8352740653 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 146938362 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 15331875607 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 15478813969 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 146938362 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 15331875607 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 15478813969 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.448572 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.099680 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.101102 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.991807 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.991807 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.267847 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.267847 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.448572 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.150888 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.151733 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.448572 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.150888 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.151733 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 45407.404821 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 39729.345603 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39832.050418 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10027.352722 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10027.352722 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40416.617407 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40416.617407 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 45407.404821 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40100.843001 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40145.379865 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 45407.404821 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40100.843001 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40145.379865 # average overall mshr miss latency +system.cpu.l2cache.writebacks::writebacks 293652 # number of writebacks +system.cpu.l2cache.writebacks::total 293652 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3216 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 175678 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 178894 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 210659 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 210659 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206756 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 206756 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3216 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 382434 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 385650 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3216 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 382434 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 385650 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 139955386 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6977520482 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 7117475868 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 2112120744 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 2112120744 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8331237791 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8331237791 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 139955386 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 15308758273 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 15448713659 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 139955386 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 15308758273 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 15448713659 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.462934 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.099696 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.101122 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.992902 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.992902 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.268033 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.268033 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.462934 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.150949 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.151802 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.462934 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.150949 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.151802 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 43518.465796 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 39717.668018 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39785.995439 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10026.254487 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10026.254487 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40295.023076 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40295.023076 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 43518.465796 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40029.804549 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40058.897080 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 43518.465796 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40029.804549 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40058.897080 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.replacements 2529431 # number of replacements +system.cpu.dcache.tagsinuse 4087.842516 # Cycle average of tags in use +system.cpu.dcache.total_refs 405341407 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 2533527 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 159.990956 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 1787438000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4087.842516 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.998008 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.998008 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 256611582 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 256611582 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 148160067 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 148160067 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 404771649 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 404771649 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 404771649 # number of overall hits +system.cpu.dcache.overall_hits::total 404771649 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2888518 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2888518 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1000134 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1000134 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 3888652 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3888652 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3888652 # number of overall misses +system.cpu.dcache.overall_misses::total 3888652 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 49903831500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 49903831500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 24367147000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 24367147000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 74270978500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 74270978500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 74270978500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 74270978500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 259500100 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 259500100 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 149160201 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 149160201 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 408660301 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 408660301 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 408660301 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 408660301 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011131 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.011131 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006705 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.006705 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.009516 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.009516 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.009516 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.009516 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17276.621264 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 17276.621264 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24363.882240 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 24363.882240 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 19099.415042 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 19099.415042 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 19099.415042 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 19099.415042 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 7749 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 632 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 12.261076 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 2331049 # number of writebacks +system.cpu.dcache.writebacks::total 2331049 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1126114 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1126114 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16846 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 16846 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1142960 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1142960 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1142960 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1142960 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1762404 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1762404 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 983288 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 983288 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2745692 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2745692 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2745692 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2745692 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 26902331000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 26902331000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 22198368000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 22198368000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 49100699000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 49100699000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 49100699000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 49100699000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006792 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006792 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006592 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006592 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006719 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.006719 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006719 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.006719 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15264.565332 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15264.565332 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22575.652301 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22575.652301 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17882.813877 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 17882.813877 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17882.813877 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 17882.813877 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/config.ini index d73c26c02..d18ed7c2f 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/config.ini +++ b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/config.ini @@ -10,6 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a +clock=1000 init_param=0 kernel= load_addr_mask=1099511627775 @@ -29,7 +30,7 @@ system_port=system.membus.slave[0] [system.cpu] type=InOrderCPU -children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload +children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 RASSize=16 @@ -54,8 +55,6 @@ do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb fetchBuffSize=4 -functionTrace=false -functionTraceStart=0 function_trace=false function_trace_start=0 globalCtrBits=2 @@ -63,6 +62,7 @@ globalHistoryBits=13 globalPredictorSize=8192 instShiftAmt=2 interrupts=system.cpu.interrupts +isa=system.cpu.isa itb=system.cpu.itb localCtrBits=2 localHistoryBits=11 @@ -76,7 +76,6 @@ memBlockSize=64 multLatency=1 multRepeatRate=1 numThreads=1 -phase=0 predType=tournament profile=0 progress_interval=0 @@ -94,20 +93,22 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=2 is_top_level=true -latency=1000 max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=2 size=262144 subblock_size=0 system=system -tgts_per_mshr=5 +tgts_per_mshr=20 trace_addr=0 two_queue=false write_buffers=8 @@ -123,20 +124,22 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=2 is_top_level=true -latency=1000 max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=2 size=131072 subblock_size=0 system=system -tgts_per_mshr=5 +tgts_per_mshr=20 trace_addr=0 two_queue=false write_buffers=8 @@ -146,6 +149,9 @@ mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=AlphaInterrupts +[system.cpu.isa] +type=AlphaISA + [system.cpu.itb] type=AlphaTLB size=48 @@ -153,22 +159,24 @@ size=48 [system.cpu.l2cache] type=BaseCache addr_ranges=0:18446744073709551615 -assoc=2 +assoc=8 block_size=64 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=20 is_top_level=false -latency=10000 max_miss_count=0 -mshrs=10 +mshrs=20 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=20 size=2097152 subblock_size=0 system=system -tgts_per_mshr=5 +tgts_per_mshr=12 trace_addr=0 two_queue=false write_buffers=8 @@ -178,10 +186,10 @@ mem_side=system.membus.slave[1] [system.cpu.toL2Bus] type=CoherentBus block_size=64 -clock=1000 +clock=500 header_cycles=1 use_default_range=false -width=8 +width=32 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side @@ -191,12 +199,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook -cwd=build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/inorder-timing +cwd=build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/inorder-timing egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/alpha/tru64/eon +executable=/projects/pd/randd/dist/cpu2000/binaries/alpha/tru64/eon gid=100 input=cin max_stack_size=67108864 @@ -214,18 +222,32 @@ clock=1000 header_cycles=1 use_default_range=false width=8 -master=system.physmem.port[0] +master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] -type=SimpleMemory +type=SimpleDRAM +addr_mapping=openmap +banks_per_rank=8 +clock=1000 conf_table_reported=false -file= in_addr_map=true -latency=30000 -latency_var=0 +lines_per_rowbuffer=64 +mem_sched_policy=fcfs null=false +page_policy=open range=0:134217727 +ranks_per_channel=2 +read_buffer_size=32 +tBURST=4000 +tCL=14000 +tRCD=14000 +tREFI=7800000 +tRFC=300000 +tRP=14000 +tWTR=1000 +write_buffer_size=32 +write_thresh_perc=70 zero=false port=system.membus.master[0] diff --git a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/simout b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/simout index f78d992b7..063caa36a 100755 --- a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/simout +++ b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/simout @@ -1,14 +1,14 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 2 2012 08:30:56 -gem5 started Jul 2 2012 09:12:34 -gem5 executing on zizzer -command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/inorder-timing +gem5 compiled Oct 30 2012 11:02:14 +gem5 started Oct 30 2012 11:24:52 +gem5 executing on u200540-lin +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Eon, Version 1.1 info: Increasing stack size by one page. OO-style eon Time= 0.133333 -Exiting @ tick 141187061500 because target called exit() +Exiting @ tick 139846906500 because target called exit() diff --git a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt index a158074c5..1ee5829a5 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.141089 # Number of seconds simulated -sim_ticks 141089296500 # Number of ticks simulated -final_tick 141089296500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.139847 # Number of seconds simulated +sim_ticks 139846906500 # Number of ticks simulated +final_tick 139846906500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 83115 # Simulator instruction rate (inst/s) -host_op_rate 83115 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 29414893 # Simulator tick rate (ticks/s) -host_mem_usage 223012 # Number of bytes of host memory used -host_seconds 4796.53 # Real time elapsed on the host +host_inst_rate 122154 # Simulator instruction rate (inst/s) +host_op_rate 122154 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 42850332 # Simulator tick rate (ticks/s) +host_mem_usage 220236 # Number of bytes of host memory used +host_seconds 3263.61 # Real time elapsed on the host sim_insts 398664595 # Number of instructions simulated sim_ops 398664595 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 214976 # Number of bytes read from this memory @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 214976 # Nu system.physmem.num_reads::cpu.inst 3359 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 3969 # Number of read requests responded to by this memory system.physmem.num_reads::total 7328 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1523688 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1800392 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3324079 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1523688 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1523688 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1523688 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1800392 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3324079 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1537224 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1816386 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3353610 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1537224 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1537224 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1537224 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1816386 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3353610 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 7328 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen system.physmem.cpureqs 7328 # Reqs generatd by CPU via cache - shady @@ -37,7 +37,7 @@ system.physmem.bytesConsumedWr 0 # by system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed system.physmem.perBankRdReqs::0 465 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 464 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 465 # Track reads on a per bank basis system.physmem.perBankRdReqs::2 518 # Track reads on a per bank basis system.physmem.perBankRdReqs::3 520 # Track reads on a per bank basis system.physmem.perBankRdReqs::4 382 # Track reads on a per bank basis @@ -48,7 +48,7 @@ system.physmem.perBankRdReqs::8 407 # Tr system.physmem.perBankRdReqs::9 457 # Track reads on a per bank basis system.physmem.perBankRdReqs::10 588 # Track reads on a per bank basis system.physmem.perBankRdReqs::11 397 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 529 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 528 # Track reads on a per bank basis system.physmem.perBankRdReqs::13 418 # Track reads on a per bank basis system.physmem.perBankRdReqs::14 396 # Track reads on a per bank basis system.physmem.perBankRdReqs::15 488 # Track reads on a per bank basis @@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 141089244500 # Total gap between requests +system.physmem.totGap 139846854500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -98,11 +98,11 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 4661 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1890 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 520 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 190 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 66 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 4654 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1888 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 524 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 196 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 65 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -164,47 +164,47 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 39617295 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 175175295 # Sum of mem lat for all requests +system.physmem.totQLat 39390791 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 174626791 # Sum of mem lat for all requests system.physmem.totBusLat 29312000 # Total cycles spent in databus access -system.physmem.totBankLat 106246000 # Total cycles spent in bank access -system.physmem.avgQLat 5406.29 # Average queueing delay per request -system.physmem.avgBankLat 14498.64 # Average bank access latency per request +system.physmem.totBankLat 105924000 # Total cycles spent in bank access +system.physmem.avgQLat 5375.38 # Average queueing delay per request +system.physmem.avgBankLat 14454.69 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 23904.93 # Average memory access latency -system.physmem.avgRdBW 3.32 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 23830.08 # Average memory access latency +system.physmem.avgRdBW 3.35 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 3.32 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 3.35 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 6442 # Number of row buffer hits during reads +system.physmem.readRowHits 6444 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 87.91 # Row buffer hit rate for reads +system.physmem.readRowHitRate 87.94 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 19253444.94 # Average gap between requests +system.physmem.avgGap 19083904.82 # Average gap between requests system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 94754611 # DTB read hits +system.cpu.dtb.read_hits 94754613 # DTB read hits system.cpu.dtb.read_misses 21 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 94754632 # DTB read accesses -system.cpu.dtb.write_hits 73521102 # DTB write hits +system.cpu.dtb.read_accesses 94754634 # DTB read accesses +system.cpu.dtb.write_hits 73521103 # DTB write hits system.cpu.dtb.write_misses 35 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 73521137 # DTB write accesses -system.cpu.dtb.data_hits 168275713 # DTB hits +system.cpu.dtb.write_accesses 73521138 # DTB write accesses +system.cpu.dtb.data_hits 168275716 # DTB hits system.cpu.dtb.data_misses 56 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 168275769 # DTB accesses -system.cpu.itb.fetch_hits 49091192 # ITB hits -system.cpu.itb.fetch_misses 88817 # ITB misses +system.cpu.dtb.data_accesses 168275772 # DTB accesses +system.cpu.itb.fetch_hits 48611354 # ITB hits +system.cpu.itb.fetch_misses 44520 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 49180009 # ITB accesses +system.cpu.itb.fetch_accesses 48655874 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -218,42 +218,42 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 215 # Number of system calls -system.cpu.numCycles 282178594 # number of cpu cycles simulated +system.cpu.numCycles 279693814 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.branch_predictor.lookups 53863325 # Number of BP lookups -system.cpu.branch_predictor.condPredicted 30909619 # Number of conditional branches predicted -system.cpu.branch_predictor.condIncorrect 16029157 # Number of conditional branches incorrect -system.cpu.branch_predictor.BTBLookups 33388385 # Number of BTB lookups -system.cpu.branch_predictor.BTBHits 15622160 # Number of BTB hits +system.cpu.branch_predictor.lookups 53489670 # Number of BP lookups +system.cpu.branch_predictor.condPredicted 30685393 # Number of conditional branches predicted +system.cpu.branch_predictor.condIncorrect 15149659 # Number of conditional branches incorrect +system.cpu.branch_predictor.BTBLookups 32882351 # Number of BTB lookups +system.cpu.branch_predictor.BTBHits 15212538 # Number of BTB hits system.cpu.branch_predictor.usedRAS 8007516 # Number of times the RAS was used to get a target. -system.cpu.branch_predictor.RASInCorrect 19 # Number of incorrect RAS predictions. -system.cpu.branch_predictor.BTBHitPct 46.789205 # BTB Hit Percentage -system.cpu.branch_predictor.predictedTaken 29654286 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 24209039 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 280812298 # Number of Reads from Int. Register File +system.cpu.branch_predictor.RASInCorrect 20 # Number of incorrect RAS predictions. +system.cpu.branch_predictor.BTBHitPct 46.263535 # BTB Hit Percentage +system.cpu.branch_predictor.predictedTaken 29230505 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 24259165 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 280386588 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 159335859 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 440148157 # Total Accesses (Read+Write) to the Int. Register File -system.cpu.regfile_manager.floatRegFileReads 119908557 # Number of Reads from FP Register File +system.cpu.regfile_manager.intRegFileAccesses 439722447 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.floatRegFileReads 119631948 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 100196481 # Number of Writes to FP Register File -system.cpu.regfile_manager.floatRegFileAccesses 220105038 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 100451904 # Number of Registers Read Through Forwarding Logic -system.cpu.agen_unit.agens 168699560 # Number of Address Generations -system.cpu.execution_unit.predictedTakenIncorrect 14461353 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.execution_unit.predictedNotTakenIncorrect 1567145 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.execution_unit.mispredicted 16028498 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.predicted 28559053 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.mispredictPct 35.948370 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.executions 205751378 # Number of Instructions Executed. -system.cpu.mult_div_unit.multiplies 2124332 # Number of Multipy Operations Executed +system.cpu.regfile_manager.floatRegFileAccesses 219828429 # Total Accesses (Read+Write) to the FP Register File +system.cpu.regfile_manager.regForwards 100484563 # Number of Registers Read Through Forwarding Logic +system.cpu.agen_unit.agens 168485322 # Number of Address Generations +system.cpu.execution_unit.predictedTakenIncorrect 14315634 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.execution_unit.predictedNotTakenIncorrect 833366 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.execution_unit.mispredicted 15149000 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.predicted 29438551 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.mispredictPct 33.975851 # Percentage of Incorrect Branches Predicts +system.cpu.execution_unit.executions 205475782 # Number of Instructions Executed. +system.cpu.mult_div_unit.multiplies 2124323 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 281883987 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 279400729 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 7632 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 13336617 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 268841977 # Number of cycles cpu stages are processed. -system.cpu.activity 95.273696 # Percentage of cycles cpu is active +system.cpu.timesIdled 7654 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 13387179 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 266306635 # Number of cycles cpu stages are processed. +system.cpu.activity 95.213631 # Percentage of cycles cpu is active system.cpu.comLoads 94754489 # Number of Load instructions committed system.cpu.comStores 73520729 # Number of Store instructions committed system.cpu.comBranches 44587532 # Number of Branches instructions committed @@ -265,245 +265,137 @@ system.cpu.committedInsts 398664595 # Nu system.cpu.committedOps 398664595 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 398664595 # Number of Instructions committed (Total) -system.cpu.cpi 0.707810 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 0.701577 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 0.707810 # CPI: Total CPI of All Threads -system.cpu.ipc 1.412809 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 0.701577 # CPI: Total CPI of All Threads +system.cpu.ipc 1.425361 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 1.412809 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 78396963 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 203781631 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 72.217254 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 108683745 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 173494849 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 61.484058 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 104474173 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 177704421 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 62.975869 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 183396585 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 98782009 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 35.006911 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 92487828 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 189690766 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 67.223656 # Percentage of cycles stage was utilized (processing insts). -system.cpu.icache.replacements 1982 # number of replacements -system.cpu.icache.tagsinuse 1831.235862 # Cycle average of tags in use -system.cpu.icache.total_refs 49086683 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 3910 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 12554.138875 # Average number of references to valid blocks. +system.cpu.ipc_total 1.425361 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 77946120 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 201747694 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 72.131625 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 107042067 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 172651747 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 61.728840 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 102478598 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 177215216 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 63.360435 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 180949238 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 98744576 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 35.304526 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 90225845 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 189467969 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 67.741208 # Percentage of cycles stage was utilized (processing insts). +system.cpu.icache.replacements 1975 # number of replacements +system.cpu.icache.tagsinuse 1831.257835 # Cycle average of tags in use +system.cpu.icache.total_refs 48606847 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 3903 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 12453.714322 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1831.235862 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.894158 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.894158 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 49086683 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 49086683 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 49086683 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 49086683 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 49086683 # number of overall hits -system.cpu.icache.overall_hits::total 49086683 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 4508 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 4508 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 4508 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 4508 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 4508 # number of overall misses -system.cpu.icache.overall_misses::total 4508 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 196984000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 196984000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 196984000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 196984000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 196984000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 196984000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 49091191 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 49091191 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 49091191 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 49091191 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 49091191 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 49091191 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000092 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000092 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000092 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000092 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000092 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000092 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 43696.539485 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 43696.539485 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 43696.539485 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 43696.539485 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 43696.539485 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 43696.539485 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 220 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 1831.257835 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.894169 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.894169 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 48606847 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 48606847 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 48606847 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 48606847 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 48606847 # number of overall hits +system.cpu.icache.overall_hits::total 48606847 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 4507 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 4507 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 4507 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 4507 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 4507 # number of overall misses +system.cpu.icache.overall_misses::total 4507 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 195448500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 195448500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 195448500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 195448500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 195448500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 195448500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 48611354 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 48611354 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 48611354 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 48611354 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 48611354 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 48611354 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000093 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000093 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000093 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000093 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000093 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000093 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 43365.542489 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 43365.542489 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 43365.542489 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 43365.542489 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 43365.542489 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 43365.542489 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 202 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 4 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 3 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 55 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 67.333333 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 598 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 598 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 598 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 598 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 598 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 598 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 3910 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 3910 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 3910 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 3910 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 3910 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 3910 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 172100500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 172100500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 172100500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 172100500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 172100500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 172100500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 604 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 604 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 604 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 604 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 604 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 604 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 3903 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 3903 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 3903 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 3903 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 3903 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 3903 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 170297500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 170297500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 170297500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 170297500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 170297500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 170297500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000080 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000080 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000080 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000080 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000080 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000080 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 44015.473146 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 44015.473146 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 44015.473146 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 44015.473146 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 44015.473146 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 44015.473146 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 43632.462209 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 43632.462209 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 43632.462209 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 43632.462209 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 43632.462209 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 43632.462209 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 764 # number of replacements -system.cpu.dcache.tagsinuse 3285.555145 # Cycle average of tags in use -system.cpu.dcache.total_refs 168254416 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 4152 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 40523.703276 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 3285.555145 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.802137 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.802137 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 94753185 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 94753185 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 73501231 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 73501231 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 168254416 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 168254416 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 168254416 # number of overall hits -system.cpu.dcache.overall_hits::total 168254416 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1304 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1304 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 19498 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 19498 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 20802 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 20802 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 20802 # number of overall misses -system.cpu.dcache.overall_misses::total 20802 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 64930000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 64930000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 710139000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 710139000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 775069000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 775069000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 775069000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 775069000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 94754489 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 94754489 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 73520729 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 73520729 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 168275218 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 168275218 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 168275218 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 168275218 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000014 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000014 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000265 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000265 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000124 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000124 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000124 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000124 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 49792.944785 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 49792.944785 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 36421.120115 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 36421.120115 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 37259.350062 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 37259.350062 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 37259.350062 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 37259.350062 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 15899 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 535 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 29.717757 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 649 # number of writebacks -system.cpu.dcache.writebacks::total 649 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 354 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 354 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16296 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 16296 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 16650 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 16650 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 16650 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 16650 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 950 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 950 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3202 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 3202 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 4152 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 4152 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 4152 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 4152 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 48068500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 48068500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 153897000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 153897000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 201965500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 201965500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 201965500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 201965500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000044 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 50598.421053 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 50598.421053 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 48062.773267 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 48062.773267 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 48642.943160 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 48642.943160 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 48642.943160 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 48642.943160 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 3908.656926 # Cycle average of tags in use -system.cpu.l2cache.total_refs 760 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 3907.773744 # Cycle average of tags in use +system.cpu.l2cache.total_refs 753 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 4717 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.161119 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.159635 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 370.653922 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 2910.300742 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 627.702262 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.011311 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.088815 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::writebacks 370.670185 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 2909.388487 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 627.715072 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.011312 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.088787 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.019156 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.119283 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 551 # number of ReadReq hits +system.cpu.l2cache.occ_percent::total 0.119256 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 544 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 123 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 674 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 667 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 649 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 649 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits::cpu.data 60 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 60 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 551 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 544 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.data 183 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 734 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 551 # number of overall hits +system.cpu.l2cache.demand_hits::total 727 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 544 # number of overall hits system.cpu.l2cache.overall_hits::cpu.data 183 # number of overall hits -system.cpu.l2cache.overall_hits::total 734 # number of overall hits +system.cpu.l2cache.overall_hits::total 727 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.inst 3359 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.data 824 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::total 4183 # number of ReadReq misses @@ -515,52 +407,52 @@ system.cpu.l2cache.demand_misses::total 7328 # nu system.cpu.l2cache.overall_misses::cpu.inst 3359 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 3969 # number of overall misses system.cpu.l2cache.overall_misses::total 7328 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 162633000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 45642500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 208275500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 150126000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 150126000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 162633000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 195768500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 358401500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 162633000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 195768500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 358401500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 3910 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 160908500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 45014500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 205923000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 151967500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 151967500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 160908500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 196982000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 357890500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 160908500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 196982000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 357890500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 3903 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 947 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 4857 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 4850 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 649 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 649 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 3205 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 3205 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 3910 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 3903 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 4152 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 8062 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 3910 # number of overall (read+write) accesses +system.cpu.l2cache.demand_accesses::total 8055 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 3903 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 4152 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 8062 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.859079 # miss rate for ReadReq accesses +system.cpu.l2cache.overall_accesses::total 8055 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.860620 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.870116 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.861231 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.862474 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.981279 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.981279 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.859079 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.860620 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.955925 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.908956 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.859079 # miss rate for overall accesses +system.cpu.l2cache.demand_miss_rate::total 0.909745 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.860620 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.955925 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.908956 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 48417.088419 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 55391.383495 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 49790.939517 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 47734.817170 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 47734.817170 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 48417.088419 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 49324.389015 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 48908.501638 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 48417.088419 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 49324.389015 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 48908.501638 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::total 0.909745 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 47903.691575 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 54629.247573 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 49228.544107 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 48320.349762 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 48320.349762 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 47903.691575 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 49630.133535 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 48838.769105 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 47903.691575 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 49630.133535 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 48838.769105 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -580,39 +472,147 @@ system.cpu.l2cache.demand_mshr_misses::total 7328 system.cpu.l2cache.overall_mshr_misses::cpu.inst 3359 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 3969 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 7328 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 120134545 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 35298214 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 155432759 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 111138322 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 111138322 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 120134545 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 146436536 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 266571081 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 120134545 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 146436536 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 266571081 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.859079 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 118404553 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 34670717 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 153075270 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 112966799 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 112966799 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 118404553 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 147637516 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 266042069 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 118404553 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 147637516 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 266042069 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.860620 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.870116 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.861231 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.862474 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.981279 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.981279 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.859079 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.860620 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.955925 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.908956 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.859079 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.909745 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.860620 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.955925 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.908956 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 35764.973206 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42837.638350 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 37158.202008 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 35338.099205 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 35338.099205 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 35764.973206 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 36895.070799 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 36377.057997 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 35764.973206 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 36895.070799 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 36377.057997 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.909745 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 35249.941352 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42076.112864 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 36594.613913 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 35919.490938 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 35919.490938 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 35249.941352 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 37197.660872 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 36304.867495 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 35249.941352 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 37197.660872 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 36304.867495 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.replacements 764 # number of replacements +system.cpu.dcache.tagsinuse 3285.615449 # Cycle average of tags in use +system.cpu.dcache.total_refs 168254423 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 4152 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 40523.704961 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 3285.615449 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.802152 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.802152 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 94753185 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 94753185 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 73501238 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 73501238 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 168254423 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 168254423 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 168254423 # number of overall hits +system.cpu.dcache.overall_hits::total 168254423 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1304 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1304 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 19491 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 19491 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 20795 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 20795 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 20795 # number of overall misses +system.cpu.dcache.overall_misses::total 20795 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 64310000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 64310000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 715525500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 715525500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 779835500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 779835500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 779835500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 779835500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 94754489 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 94754489 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 73520729 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 73520729 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 168275218 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 168275218 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 168275218 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 168275218 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000014 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000014 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000265 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000265 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000124 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000124 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000124 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000124 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 49317.484663 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 49317.484663 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 36710.558719 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 36710.558719 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 37501.106035 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 37501.106035 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 37501.106035 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 37501.106035 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 16708 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 535 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 31.229907 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 649 # number of writebacks +system.cpu.dcache.writebacks::total 649 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 354 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 354 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16289 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 16289 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 16643 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 16643 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 16643 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 16643 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 950 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 950 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3202 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 3202 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 4152 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 4152 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 4152 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 4152 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 47442500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 47442500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 155739500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 155739500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 203182000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 203182000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 203182000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 203182000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000044 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 49939.473684 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 49939.473684 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 48638.194878 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 48638.194878 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 48935.934489 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 48935.934489 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 48935.934489 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 48935.934489 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini index 50694257d..8e356eaf5 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini @@ -10,6 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a +clock=1000 init_param=0 kernel= load_addr_mask=1099511627775 @@ -29,7 +30,7 @@ system_port=system.membus.slave[0] [system.cpu] type=DerivO3CPU -children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload +children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -77,6 +78,7 @@ iewToFetchDelay=1 iewToRenameDelay=1 instShiftAmt=2 interrupts=system.cpu.interrupts +isa=system.cpu.isa issueToExecuteDelay=1 issueWidth=8 itb=system.cpu.itb @@ -95,7 +97,6 @@ numPhysIntRegs=256 numROBEntries=192 numRobs=1 numThreads=1 -phase=0 predType=tournament profile=0 progress_interval=0 @@ -129,16 +130,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=2 is_top_level=true -latency=1000 max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=2 size=262144 subblock_size=0 system=system @@ -421,16 +424,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=2 is_top_level=true -latency=1000 max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=2 size=131072 subblock_size=0 system=system @@ -444,6 +449,9 @@ mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=AlphaInterrupts +[system.cpu.isa] +type=AlphaISA + [system.cpu.itb] type=AlphaTLB size=48 @@ -451,22 +459,24 @@ size=48 [system.cpu.l2cache] type=BaseCache addr_ranges=0:18446744073709551615 -assoc=2 +assoc=8 block_size=64 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=20 is_top_level=false -latency=1000 max_miss_count=0 -mshrs=10 +mshrs=20 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=20 size=2097152 subblock_size=0 system=system -tgts_per_mshr=5 +tgts_per_mshr=12 trace_addr=0 two_queue=false write_buffers=8 @@ -476,10 +486,10 @@ mem_side=system.membus.slave[1] [system.cpu.toL2Bus] type=CoherentBus block_size=64 -clock=1000 +clock=500 header_cycles=1 use_default_range=false -width=8 +width=32 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side @@ -489,12 +499,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook -cwd=build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/o3-timing +cwd=build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/o3-timing egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/alpha/tru64/eon +executable=/projects/pd/randd/dist/cpu2000/binaries/alpha/tru64/eon gid=100 input=cin max_stack_size=67108864 @@ -512,18 +522,32 @@ clock=1000 header_cycles=1 use_default_range=false width=8 -master=system.physmem.port[0] +master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] -type=SimpleMemory +type=SimpleDRAM +addr_mapping=openmap +banks_per_rank=8 +clock=1000 conf_table_reported=false -file= in_addr_map=true -latency=30000 -latency_var=0 +lines_per_rowbuffer=64 +mem_sched_policy=fcfs null=false +page_policy=open range=0:134217727 +ranks_per_channel=2 +read_buffer_size=32 +tBURST=4000 +tCL=14000 +tRCD=14000 +tREFI=7800000 +tRFC=300000 +tRP=14000 +tWTR=1000 +write_buffer_size=32 +write_thresh_perc=70 zero=false port=system.membus.master[0] diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simout b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simout index cf6e41473..c6043774f 100755 --- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simout @@ -1,14 +1,14 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 2 2012 08:30:56 -gem5 started Jul 2 2012 09:15:17 -gem5 executing on zizzer -command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/o3-timing +gem5 compiled Oct 30 2012 11:02:14 +gem5 started Oct 30 2012 11:29:31 +gem5 executing on u200540-lin +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Eon, Version 1.1 info: Increasing stack size by one page. OO-style eon Time= 0.066667 -Exiting @ tick 80362284000 because target called exit() +Exiting @ tick 77336466500 because target called exit() diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt index 698b9cfa0..d6188dabe 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt @@ -1,57 +1,57 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.080478 # Number of seconds simulated -sim_ticks 80478305500 # Number of ticks simulated -final_tick 80478305500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.077336 # Number of seconds simulated +sim_ticks 77336466500 # Number of ticks simulated +final_tick 77336466500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 240864 # Simulator instruction rate (inst/s) -host_op_rate 240864 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 51612452 # Simulator tick rate (ticks/s) -host_mem_usage 224036 # Number of bytes of host memory used -host_seconds 1559.28 # Real time elapsed on the host +host_inst_rate 195499 # Simulator instruction rate (inst/s) +host_op_rate 195499 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 40256068 # Simulator tick rate (ticks/s) +host_mem_usage 221208 # Number of bytes of host memory used +host_seconds 1921.11 # Real time elapsed on the host sim_insts 375574808 # Number of instructions simulated sim_ops 375574808 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 222272 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 255360 # Number of bytes read from this memory -system.physmem.bytes_read::total 477632 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 222272 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 222272 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3473 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 3990 # Number of read requests responded to by this memory -system.physmem.num_reads::total 7463 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 2761887 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3173029 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 5934916 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2761887 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2761887 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2761887 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3173029 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 5934916 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 7463 # Total number of read requests seen +system.physmem.bytes_read::cpu.inst 220800 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 255488 # Number of bytes read from this memory +system.physmem.bytes_read::total 476288 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 220800 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 220800 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3450 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 3992 # Number of read requests responded to by this memory +system.physmem.num_reads::total 7442 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 2855057 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3303590 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 6158647 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2855057 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2855057 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2855057 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3303590 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6158647 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 7442 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 7463 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 477632 # Total number of bytes read from memory +system.physmem.cpureqs 7442 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 476288 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 477632 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 476288 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 488 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 483 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 481 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 480 # Track reads on a per bank basis system.physmem.perBankRdReqs::2 530 # Track reads on a per bank basis system.physmem.perBankRdReqs::3 529 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 388 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 386 # Track reads on a per bank basis system.physmem.perBankRdReqs::5 401 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 460 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 447 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 457 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 448 # Track reads on a per bank basis system.physmem.perBankRdReqs::8 405 # Track reads on a per bank basis system.physmem.perBankRdReqs::9 456 # Track reads on a per bank basis system.physmem.perBankRdReqs::10 590 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 408 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 548 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 428 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 407 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 545 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 424 # Track reads on a per bank basis system.physmem.perBankRdReqs::14 399 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 503 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 504 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis @@ -70,14 +70,14 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 80478237000 # Total gap between requests +system.physmem.totGap 77336398000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 7463 # Categorize read packet sizes +system.physmem.readPktSize::6 7442 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -98,10 +98,10 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 4283 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 2068 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 746 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 275 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 4251 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 2073 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 754 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 273 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 88 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -164,47 +164,47 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 40041940 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 178323940 # Sum of mem lat for all requests -system.physmem.totBusLat 29852000 # Total cycles spent in databus access -system.physmem.totBankLat 108430000 # Total cycles spent in bank access -system.physmem.avgQLat 5365.39 # Average queueing delay per request -system.physmem.avgBankLat 14529.01 # Average bank access latency per request +system.physmem.totQLat 40921923 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 178783923 # Sum of mem lat for all requests +system.physmem.totBusLat 29768000 # Total cycles spent in databus access +system.physmem.totBankLat 108094000 # Total cycles spent in bank access +system.physmem.avgQLat 5498.78 # Average queueing delay per request +system.physmem.avgBankLat 14524.86 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 23894.40 # Average memory access latency -system.physmem.avgRdBW 5.93 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 24023.64 # Average memory access latency +system.physmem.avgRdBW 6.16 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 5.93 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 6.16 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.04 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 6524 # Number of row buffer hits during reads +system.physmem.readRowHits 6502 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 87.42 # Row buffer hit rate for reads +system.physmem.readRowHitRate 87.37 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 10783630.85 # Average gap between requests +system.physmem.avgGap 10391883.63 # Average gap between requests system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 103426473 # DTB read hits -system.cpu.dtb.read_misses 88806 # DTB read misses -system.cpu.dtb.read_acv 48603 # DTB read access violations -system.cpu.dtb.read_accesses 103515279 # DTB read accesses -system.cpu.dtb.write_hits 79003400 # DTB write hits -system.cpu.dtb.write_misses 1622 # DTB write misses -system.cpu.dtb.write_acv 2 # DTB write access violations -system.cpu.dtb.write_accesses 79005022 # DTB write accesses -system.cpu.dtb.data_hits 182429873 # DTB hits -system.cpu.dtb.data_misses 90428 # DTB misses -system.cpu.dtb.data_acv 48605 # DTB access violations -system.cpu.dtb.data_accesses 182520301 # DTB accesses -system.cpu.itb.fetch_hits 52621913 # ITB hits -system.cpu.itb.fetch_misses 460 # ITB misses +system.cpu.dtb.read_hits 101791760 # DTB read hits +system.cpu.dtb.read_misses 77689 # DTB read misses +system.cpu.dtb.read_acv 48604 # DTB read access violations +system.cpu.dtb.read_accesses 101869449 # DTB read accesses +system.cpu.dtb.write_hits 78414713 # DTB write hits +system.cpu.dtb.write_misses 1485 # DTB write misses +system.cpu.dtb.write_acv 3 # DTB write access violations +system.cpu.dtb.write_accesses 78416198 # DTB write accesses +system.cpu.dtb.data_hits 180206473 # DTB hits +system.cpu.dtb.data_misses 79174 # DTB misses +system.cpu.dtb.data_acv 48607 # DTB access violations +system.cpu.dtb.data_accesses 180285647 # DTB accesses +system.cpu.itb.fetch_hits 50234226 # ITB hits +system.cpu.itb.fetch_misses 374 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 52622373 # ITB accesses +system.cpu.itb.fetch_accesses 50234600 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -218,246 +218,246 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 215 # Number of system calls -system.cpu.numCycles 160956613 # number of cpu cycles simulated +system.cpu.numCycles 154672935 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 52100857 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 30315970 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 1626186 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 28771875 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 24368935 # Number of BTB hits +system.cpu.BPredUnit.lookups 50254079 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 29238788 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 1202354 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 26185724 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 23237791 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 9361706 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 1114 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 53696929 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 462928228 # Number of instructions fetch has processed -system.cpu.fetch.Branches 52100857 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 33730641 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 81620286 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 7858922 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 19257347 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 187 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 9632 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 29 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 52621913 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 634331 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 160777203 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.879315 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.313319 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 9009650 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 1041 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 51121474 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 448760218 # Number of instructions fetch has processed +system.cpu.fetch.Branches 50254079 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 32247441 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 78789768 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 6120508 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 19691338 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 182 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 9175 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 31 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 50234226 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 409224 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 154491833 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.904750 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.325280 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 79156917 49.23% 49.23% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 4375069 2.72% 51.96% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 7280350 4.53% 56.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 5649836 3.51% 60.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 12467952 7.75% 67.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 8098174 5.04% 72.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 5694595 3.54% 76.33% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1921777 1.20% 77.53% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 36132533 22.47% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 75702065 49.00% 49.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 4283300 2.77% 51.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 6877325 4.45% 56.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 5367764 3.47% 59.70% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 11752749 7.61% 67.31% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 7805511 5.05% 72.36% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 5606089 3.63% 75.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1832349 1.19% 77.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 35264681 22.83% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 160777203 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.323695 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.876106 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 59247838 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 14720272 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 76811336 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 3809242 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 6188515 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 9757922 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 4354 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 457314858 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 12387 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 6188515 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 62549995 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 4761260 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 404034 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 77430709 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 9442690 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 451606730 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 77 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 23776 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 7810662 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 295220073 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 593857298 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 314533396 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 279323902 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 154491833 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.324905 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.901349 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 56470400 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 15041439 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 74166392 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 3937938 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 4875664 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 9475904 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 4278 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 444843868 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 12237 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 4875664 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 59604786 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 4871643 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 401502 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 75064420 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 9673818 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 440376827 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 86 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 19255 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 7994088 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 287328410 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 578957076 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 306311574 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 272645502 # Number of floating rename lookups system.cpu.rename.CommittedMaps 259532329 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 35687744 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 38419 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 331 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 27285006 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 107056185 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 81810329 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 8900910 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 6383401 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 416688223 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 322 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 407927915 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1196295 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 40854151 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 20088069 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 107 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 160777203 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.537225 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.006885 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 27796081 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 36810 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 298 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 27798585 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 104665260 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 80564409 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 8907082 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 6393839 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 408148309 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 288 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 401749536 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 973581 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 32442077 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 15221672 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 73 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 154491833 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.600458 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.995634 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 32206126 20.03% 20.03% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 26582948 16.53% 36.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 26044704 16.20% 52.76% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 24850018 15.46% 68.22% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 21542644 13.40% 81.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 15495200 9.64% 91.26% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 8651076 5.38% 96.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 4083423 2.54% 99.18% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1321064 0.82% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 28272588 18.30% 18.30% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 25828142 16.72% 35.02% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 25544882 16.53% 51.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 24283906 15.72% 67.27% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 21283015 13.78% 81.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 15483551 10.02% 91.07% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 8467826 5.48% 96.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 4000243 2.59% 99.14% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1327680 0.86% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 160777203 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 154491833 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 35727 0.30% 0.30% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 0.30% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 0.30% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 75761 0.64% 0.94% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 4382 0.04% 0.98% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 3108 0.03% 1.01% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 1825209 15.42% 16.43% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 1783394 15.07% 31.49% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 31.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 31.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 31.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 31.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 31.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 31.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 31.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 31.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 31.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 31.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 31.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 31.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 31.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 31.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 31.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 31.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 31.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 31.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 31.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 31.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 31.49% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 5084367 42.96% 74.45% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 3023635 25.55% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 34079 0.29% 0.29% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 0.29% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 0.29% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 57868 0.49% 0.78% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 5831 0.05% 0.83% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 5354 0.05% 0.87% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 1930027 16.34% 17.21% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 1748928 14.81% 32.02% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 32.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 32.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.02% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 5061323 42.85% 74.87% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 2967669 25.13% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 33581 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 158069721 38.75% 38.76% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2126542 0.52% 39.28% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 39.28% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 33490518 8.21% 47.49% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 7849895 1.92% 49.41% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 2841429 0.70% 50.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 16561983 4.06% 54.17% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 1589872 0.39% 54.56% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 54.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 54.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 54.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 54.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 54.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 54.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 54.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 54.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 54.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 54.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 54.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 54.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 54.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 54.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 54.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 54.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 54.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 54.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 54.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 54.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 54.56% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 105338931 25.82% 80.38% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 80025443 19.62% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 155748072 38.77% 38.78% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2126114 0.53% 39.31% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 39.31% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 32812204 8.17% 47.47% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 7499410 1.87% 49.34% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 2793875 0.70% 50.03% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 16556840 4.12% 54.16% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 1578743 0.39% 54.55% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 54.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 54.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 54.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 54.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 54.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 54.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 54.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 54.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 54.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 54.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 54.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 54.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 54.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 54.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 54.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 54.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 54.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 54.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 54.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 54.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 54.55% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 103369723 25.73% 80.28% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 79230974 19.72% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 407927915 # Type of FU issued -system.cpu.iq.rate 2.534397 # Inst issue rate -system.cpu.iq.fu_busy_cnt 11835583 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.029014 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 648317888 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 270248085 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 237722545 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 341347023 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 187344847 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 162957273 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 245426205 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 174303712 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 14794032 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 401749536 # Type of FU issued +system.cpu.iq.rate 2.597413 # Inst issue rate +system.cpu.iq.fu_busy_cnt 11811079 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.029399 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 634008068 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 260192564 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 234721556 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 336767497 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 180447135 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 161345688 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 241449037 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 172077997 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 15060402 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 12301698 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 125436 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 50278 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 8289600 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 9910773 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 111367 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 49045 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 7043680 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 260794 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 2630 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 260907 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 2589 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 6188515 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 2498531 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 365597 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 441640864 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 208656 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 107056185 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 81810329 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 322 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 105 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 92 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 50278 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1277121 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 568437 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1845558 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 403336755 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 103563942 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 4591160 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 4875664 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 2512017 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 367237 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 432932337 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 125430 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 104665260 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 80564409 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 288 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 91 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 94 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 49045 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 948042 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 404840 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1352882 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 398223090 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 101918095 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 3526446 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 24952319 # number of nop insts executed -system.cpu.iew.exec_refs 182568992 # number of memory reference insts executed -system.cpu.iew.exec_branches 47207101 # Number of branches executed -system.cpu.iew.exec_stores 79005050 # Number of stores executed -system.cpu.iew.exec_rate 2.505873 # Inst execution rate -system.cpu.iew.wb_sent 401526892 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 400679818 # cumulative count of insts written-back -system.cpu.iew.wb_producers 195200441 # num instructions producing a value -system.cpu.iew.wb_consumers 273221552 # num instructions consuming a value +system.cpu.iew.exec_nop 24783740 # number of nop insts executed +system.cpu.iew.exec_refs 180334326 # number of memory reference insts executed +system.cpu.iew.exec_branches 46552042 # Number of branches executed +system.cpu.iew.exec_stores 78416231 # Number of stores executed +system.cpu.iew.exec_rate 2.574614 # Inst execution rate +system.cpu.iew.wb_sent 396695169 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 396067244 # cumulative count of insts written-back +system.cpu.iew.wb_producers 193570018 # num instructions producing a value +system.cpu.iew.wb_consumers 271138332 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.489365 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.714440 # average fanout of values written-back +system.cpu.iew.wb_rate 2.560676 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.713916 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 43021782 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 34296903 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 215 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1621908 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 154588688 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.578873 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.965339 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1198153 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 149616169 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.664582 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.996061 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 58995602 38.16% 38.16% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 23401293 15.14% 53.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 13308874 8.61% 61.91% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 11694068 7.56% 69.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 8446337 5.46% 74.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 5505575 3.56% 78.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 5146283 3.33% 81.83% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3352831 2.17% 84.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 24737825 16.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 55282421 36.95% 36.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 22517619 15.05% 52.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 13057157 8.73% 60.73% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 11465050 7.66% 68.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 8178831 5.47% 73.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 5460295 3.65% 77.51% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 5171821 3.46% 80.96% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3274025 2.19% 83.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 25208950 16.85% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 154588688 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 149616169 # Number of insts commited each cycle system.cpu.commit.committedInsts 398664583 # Number of instructions committed system.cpu.commit.committedOps 398664583 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -468,204 +468,340 @@ system.cpu.commit.branches 44587533 # Nu system.cpu.commit.fp_insts 155295106 # Number of committed floating point instructions. system.cpu.commit.int_insts 316365839 # Number of committed integer instructions. system.cpu.commit.function_calls 8007752 # Number of function calls committed. -system.cpu.commit.bw_lim_events 24737825 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 25208950 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 571534251 # The number of ROB reads -system.cpu.rob.rob_writes 889574996 # The number of ROB writes -system.cpu.timesIdled 3393 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 179410 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 557365728 # The number of ROB reads +system.cpu.rob.rob_writes 870806965 # The number of ROB writes +system.cpu.timesIdled 3403 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 181102 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 375574808 # Number of Instructions Simulated system.cpu.committedOps 375574808 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 375574808 # Number of Instructions Simulated -system.cpu.cpi 0.428561 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.428561 # CPI: Total CPI of All Threads -system.cpu.ipc 2.333392 # IPC: Instructions Per Cycle -system.cpu.ipc_total 2.333392 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 402843963 # number of integer regfile reads -system.cpu.int_regfile_writes 172601197 # number of integer regfile writes -system.cpu.fp_regfile_reads 158371131 # number of floating regfile reads -system.cpu.fp_regfile_writes 105217877 # number of floating regfile writes +system.cpu.cpi 0.411830 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.411830 # CPI: Total CPI of All Threads +system.cpu.ipc 2.428187 # IPC: Instructions Per Cycle +system.cpu.ipc_total 2.428187 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 398054965 # number of integer regfile reads +system.cpu.int_regfile_writes 170113807 # number of integer regfile writes +system.cpu.fp_regfile_reads 156515246 # number of floating regfile reads +system.cpu.fp_regfile_writes 104037972 # number of floating regfile writes system.cpu.misc_regfile_reads 350572 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.icache.replacements 2196 # number of replacements -system.cpu.icache.tagsinuse 1834.742216 # Cycle average of tags in use -system.cpu.icache.total_refs 52616364 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 4124 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 12758.575170 # Average number of references to valid blocks. +system.cpu.icache.replacements 2129 # number of replacements +system.cpu.icache.tagsinuse 1832.082194 # Cycle average of tags in use +system.cpu.icache.total_refs 50228789 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 4056 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 12383.823718 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1834.742216 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.895870 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.895870 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 52616364 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 52616364 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 52616364 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 52616364 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 52616364 # number of overall hits -system.cpu.icache.overall_hits::total 52616364 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 5549 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 5549 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 5549 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 5549 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 5549 # number of overall misses -system.cpu.icache.overall_misses::total 5549 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 228035499 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 228035499 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 228035499 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 228035499 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 228035499 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 228035499 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 52621913 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 52621913 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 52621913 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 52621913 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 52621913 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 52621913 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000105 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000105 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000105 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000105 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000105 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000105 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 41094.881781 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 41094.881781 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 41094.881781 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 41094.881781 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 41094.881781 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 41094.881781 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 278 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 1832.082194 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.894571 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.894571 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 50228789 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 50228789 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 50228789 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 50228789 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 50228789 # number of overall hits +system.cpu.icache.overall_hits::total 50228789 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 5437 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 5437 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 5437 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 5437 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 5437 # number of overall misses +system.cpu.icache.overall_misses::total 5437 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 226400000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 226400000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 226400000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 226400000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 226400000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 226400000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 50234226 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 50234226 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 50234226 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 50234226 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 50234226 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 50234226 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000108 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000108 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000108 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000108 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000108 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000108 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 41640.610631 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 41640.610631 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 41640.610631 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 41640.610631 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 41640.610631 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 41640.610631 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 238 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 6 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 4 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 46.333333 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 59.500000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1425 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1425 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1425 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1425 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1425 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1425 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4124 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 4124 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 4124 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 4124 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 4124 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 4124 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 176594499 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 176594499 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 176594499 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 176594499 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 176594499 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 176594499 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000078 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000078 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000078 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000078 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000078 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000078 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 42821.168526 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 42821.168526 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 42821.168526 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 42821.168526 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 42821.168526 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 42821.168526 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1381 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1381 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1381 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1381 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1381 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1381 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4056 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 4056 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 4056 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 4056 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 4056 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 4056 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 175832000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 175832000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 175832000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 175832000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 175832000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 175832000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000081 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000081 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000081 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000081 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000081 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000081 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 43351.084813 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 43351.084813 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 43351.084813 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 43351.084813 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 43351.084813 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 43351.084813 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 785 # number of replacements -system.cpu.dcache.tagsinuse 3296.121228 # Cycle average of tags in use -system.cpu.dcache.total_refs 161868539 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 4185 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 38678.264994 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 0 # number of replacements +system.cpu.l2cache.tagsinuse 4007.668584 # Cycle average of tags in use +system.cpu.l2cache.total_refs 823 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 4847 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.169796 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::writebacks 372.532696 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 2973.483231 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 661.652657 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.011369 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.090744 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.020192 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.122304 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 606 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 130 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 736 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 657 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 657 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 60 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 60 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 606 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 190 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 796 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 606 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 190 # number of overall hits +system.cpu.l2cache.overall_hits::total 796 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 3450 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 861 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 4311 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 3131 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 3131 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 3450 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 3992 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 7442 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 3450 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 3992 # number of overall misses +system.cpu.l2cache.overall_misses::total 7442 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 165703500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 49209000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 214912500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 151131500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 151131500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 165703500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 200340500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 366044000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 165703500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 200340500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 366044000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 4056 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 991 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 5047 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 657 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 657 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 3191 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 3191 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 4056 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 4182 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 8238 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 4056 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 4182 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 8238 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.850592 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.868819 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.854171 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.981197 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.981197 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.850592 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.954567 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.903375 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.850592 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.954567 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.903375 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 48030 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 57153.310105 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 49852.122477 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 48269.402747 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 48269.402747 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 48030 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 50185.495992 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 49186.240258 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 48030 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 50185.495992 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 49186.240258 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3450 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 861 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 4311 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3131 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 3131 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3450 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 3992 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 7442 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3450 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 3992 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 7442 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 122247748 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 38514499 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 160762247 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 112485998 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 112485998 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 122247748 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 151000497 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 273248245 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 122247748 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 151000497 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 273248245 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.850592 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.868819 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.854171 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.981197 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.981197 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.850592 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.954567 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.903375 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.850592 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.954567 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.903375 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 35434.129855 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 44732.286876 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 37291.173046 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 35926.540402 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 35926.540402 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 35434.129855 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 37825.775802 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 36717.044477 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 35434.129855 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 37825.775802 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 36717.044477 # average overall mshr miss latency +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.replacements 780 # number of replacements +system.cpu.dcache.tagsinuse 3297.205890 # Cycle average of tags in use +system.cpu.dcache.total_refs 159967351 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 4182 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 38251.399091 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 3296.121228 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.804717 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.804717 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 88367648 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 88367648 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 73500876 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 73500876 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 15 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 15 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 161868524 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 161868524 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 161868524 # number of overall hits -system.cpu.dcache.overall_hits::total 161868524 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1780 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1780 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 19853 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 19853 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 21633 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 21633 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 21633 # number of overall misses -system.cpu.dcache.overall_misses::total 21633 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 82604000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 82604000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 720118126 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 720118126 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 802722126 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 802722126 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 802722126 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 802722126 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 88369428 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 88369428 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.occ_blocks::cpu.data 3297.205890 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.804982 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.804982 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 86466482 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 86466482 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 73500862 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 73500862 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 7 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 7 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 159967344 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 159967344 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 159967344 # number of overall hits +system.cpu.dcache.overall_hits::total 159967344 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1810 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1810 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 19867 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 19867 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 21677 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 21677 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 21677 # number of overall misses +system.cpu.dcache.overall_misses::total 21677 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 83400000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 83400000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 721598130 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 721598130 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 804998130 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 804998130 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 804998130 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 804998130 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 86468292 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 86468292 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 73520729 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 73520729 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 15 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 161890157 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 161890157 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 161890157 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 161890157 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000020 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000020 # miss rate for ReadReq accesses +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 7 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 7 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 159989021 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 159989021 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 159989021 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 159989021 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000021 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000021 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000270 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.000270 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000134 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000134 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000134 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000134 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 46406.741573 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 46406.741573 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 36272.509243 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 36272.509243 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 37106.371100 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 37106.371100 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 37106.371100 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 37106.371100 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 23536 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.000135 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000135 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000135 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000135 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 46077.348066 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 46077.348066 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 36321.444103 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 36321.444103 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 37136.048807 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 37136.048807 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 37136.048807 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 37136.048807 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 23923 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 627 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 631 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 37.537480 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 37.912837 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 663 # number of writebacks -system.cpu.dcache.writebacks::total 663 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 792 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 792 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16656 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 16656 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 17448 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 17448 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 17448 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 17448 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 988 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 988 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3197 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 3197 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 4185 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 4185 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 4185 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 4185 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 51049000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 51049000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 155266000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 155266000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 206315000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 206315000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 206315000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 206315000 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 657 # number of writebacks +system.cpu.dcache.writebacks::total 657 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 819 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 819 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16676 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 16676 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 17495 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 17495 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 17495 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 17495 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 991 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 991 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3191 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 3191 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 4182 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 4182 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 4182 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 4182 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 51550500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 51550500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 155023000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 155023000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 206573500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 206573500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 206573500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 206573500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000011 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000011 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000043 # mshr miss rate for WriteReq accesses @@ -674,150 +810,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000026 system.cpu.dcache.demand_mshr_miss_rate::total 0.000026 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000026 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000026 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 51669.028340 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 51669.028340 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 48566.155771 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 48566.155771 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 49298.685783 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 49298.685783 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 49298.685783 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 49298.685783 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 52018.668012 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 52018.668012 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 48581.322469 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 48581.322469 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 49395.863223 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 49395.863223 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 49395.863223 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 49395.863223 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 4033.088389 # Cycle average of tags in use -system.cpu.l2cache.total_refs 872 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 4868 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.179129 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 372.600673 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 3001.103813 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 659.383903 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.011371 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.091586 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.020123 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.123080 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 651 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 130 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 781 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 663 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 663 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 65 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 65 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 651 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 195 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 846 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 651 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 195 # number of overall hits -system.cpu.l2cache.overall_hits::total 846 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 3473 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 858 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 4331 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 3132 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 3132 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 3473 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 3990 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 7463 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 3473 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 3990 # number of overall misses -system.cpu.l2cache.overall_misses::total 7463 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 165942000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 48709500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 214651500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 151316000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 151316000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 165942000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 200025500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 365967500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 165942000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 200025500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 365967500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 4124 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 988 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 5112 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 663 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 663 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 3197 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 3197 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 4124 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 4185 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 8309 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 4124 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 4185 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 8309 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.842144 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.868421 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.847222 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.979668 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.979668 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.842144 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.953405 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.898183 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.842144 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.953405 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.898183 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 47780.593147 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 56770.979021 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 49561.648580 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 48312.899106 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 48312.899106 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 47780.593147 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 50131.704261 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 49037.585421 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 47780.593147 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 50131.704261 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 49037.585421 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3473 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 858 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 4331 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3132 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 3132 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3473 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 3990 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 7463 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3473 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 3990 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 7463 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 122186799 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 38051999 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 160238798 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 112625004 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 112625004 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 122186799 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 150677003 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 272863802 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 122186799 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 150677003 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 272863802 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.842144 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.868421 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.847222 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.979668 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.979668 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.842144 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.953405 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.898183 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.842144 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.953405 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.898183 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 35181.917363 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 44349.649184 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 36998.106211 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 35959.452107 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 35959.452107 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 35181.917363 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 37763.659900 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 36562.213855 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 35181.917363 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 37763.659900 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 36562.213855 # average overall mshr miss latency -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini b/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini index ca4ea2a9a..f736a3c63 100644 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini @@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a -clock=1 +clock=1000 init_param=0 kernel= load_addr_mask=1099511627775 @@ -30,7 +30,7 @@ system_port=system.membus.slave[0] [system.cpu] type=DerivO3CPU -children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload +children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -78,6 +78,7 @@ iewToFetchDelay=1 iewToRenameDelay=1 instShiftAmt=2 interrupts=system.cpu.interrupts +isa=system.cpu.isa issueToExecuteDelay=1 issueWidth=8 itb=system.cpu.itb @@ -129,18 +130,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=262144 subblock_size=0 system=system @@ -159,7 +160,7 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=ArmTableWalker -clock=1 +clock=500 num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[3] @@ -432,18 +433,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=131072 subblock_size=0 system=system @@ -457,6 +458,23 @@ mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=ArmInterrupts +[system.cpu.isa] +type=ArmISA +fpsid=1090793632 +id_isar0=34607377 +id_isar1=34677009 +id_isar2=555950401 +id_isar3=17899825 +id_isar4=268501314 +id_isar5=0 +id_mmfr0=3 +id_mmfr1=0 +id_mmfr2=19070976 +id_mmfr3=4027589137 +id_pfr0=49 +id_pfr1=1 +midr=890224640 + [system.cpu.itb] type=ArmTLB children=walker @@ -465,7 +483,7 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=ArmTableWalker -clock=1 +clock=500 num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[2] @@ -473,24 +491,24 @@ port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] type=BaseCache addr_ranges=0:18446744073709551615 -assoc=2 +assoc=8 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=20 is_top_level=false max_miss_count=0 -mshrs=10 +mshrs=20 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=20 size=2097152 subblock_size=0 system=system -tgts_per_mshr=5 +tgts_per_mshr=12 trace_addr=0 two_queue=false write_buffers=8 @@ -500,10 +518,10 @@ mem_side=system.membus.slave[1] [system.cpu.toL2Bus] type=CoherentBus block_size=64 -clock=1000 +clock=500 header_cycles=1 use_default_range=false -width=8 +width=32 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port @@ -540,15 +558,28 @@ master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] -type=SimpleMemory -bandwidth=73.000000 -clock=1 +type=SimpleDRAM +addr_mapping=openmap +banks_per_rank=8 +clock=1000 conf_table_reported=false in_addr_map=true -latency=30000 -latency_var=0 +lines_per_rowbuffer=64 +mem_sched_policy=fcfs null=false +page_policy=open range=0:134217727 +ranks_per_channel=2 +read_buffer_size=32 +tBURST=4000 +tCL=14000 +tRCD=14000 +tREFI=7800000 +tRFC=300000 +tRP=14000 +tWTR=1000 +write_buffer_size=32 +write_thresh_perc=70 zero=false port=system.membus.master[0] diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout b/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout index 2e2e5579e..4b90608f0 100755 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout @@ -1,8 +1,8 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 21 2012 11:19:00 -gem5 started Sep 21 2012 13:21:28 +gem5 compiled Oct 30 2012 11:20:14 +gem5 started Oct 30 2012 19:45:28 gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second @@ -12,5 +12,5 @@ Eon, Version 1.1 info: Increasing stack size by one page. info: Increasing stack size by one page. info: Increasing stack size by one page. -OO-style eon Time= 0.070000 -Exiting @ tick 70907303500 because target called exit() +OO-style eon Time= 0.060000 +Exiting @ tick 68267465500 because target called exit() diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt index d021c65df..e8af9a733 100644 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt @@ -1,57 +1,57 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.071124 # Number of seconds simulated -sim_ticks 71123520500 # Number of ticks simulated -final_tick 71123520500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.068267 # Number of seconds simulated +sim_ticks 68267465500 # Number of ticks simulated +final_tick 68267465500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 165652 # Simulator instruction rate (inst/s) -host_op_rate 211776 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 43149002 # Simulator tick rate (ticks/s) -host_mem_usage 241844 # Number of bytes of host memory used -host_seconds 1648.32 # Real time elapsed on the host -sim_insts 273048466 # Number of instructions simulated -sim_ops 349076190 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 194944 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 272832 # Number of bytes read from this memory -system.physmem.bytes_read::total 467776 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 194944 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 194944 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3046 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 4263 # Number of read requests responded to by this memory -system.physmem.num_reads::total 7309 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 2740922 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3836031 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 6576952 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2740922 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2740922 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2740922 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3836031 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6576952 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 7309 # Total number of read requests seen +host_inst_rate 130031 # Simulator instruction rate (inst/s) +host_op_rate 166236 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 32510221 # Simulator tick rate (ticks/s) +host_mem_usage 238756 # Number of bytes of host memory used +host_seconds 2099.88 # Real time elapsed on the host +sim_insts 273048375 # Number of instructions simulated +sim_ops 349076099 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 193920 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 273088 # Number of bytes read from this memory +system.physmem.bytes_read::total 467008 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 193920 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 193920 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3030 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 4267 # Number of read requests responded to by this memory +system.physmem.num_reads::total 7297 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 2840592 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 4000266 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 6840857 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2840592 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2840592 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2840592 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4000266 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6840857 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 7297 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 7309 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 467776 # Total number of bytes read from memory +system.physmem.cpureqs 7297 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 467008 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 467776 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 467008 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 346 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 470 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 344 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 467 # Track reads on a per bank basis system.physmem.perBankRdReqs::2 514 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 578 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 477 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 456 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 440 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 507 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 480 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 494 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 484 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 551 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 365 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 581 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 475 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 457 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 437 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 505 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 483 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 495 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 481 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 558 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 359 # Track reads on a per bank basis system.physmem.perBankRdReqs::13 416 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 368 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 363 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 365 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 360 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis @@ -70,14 +70,14 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 71123348000 # Total gap between requests +system.physmem.totGap 68267282000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 7309 # Categorize read packet sizes +system.physmem.readPktSize::6 7297 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -98,12 +98,12 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 4384 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 2130 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 552 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 174 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 67 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 4347 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 2135 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 568 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 183 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 64 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -164,27 +164,27 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 38077286 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 170549286 # Sum of mem lat for all requests -system.physmem.totBusLat 29236000 # Total cycles spent in databus access -system.physmem.totBankLat 103236000 # Total cycles spent in bank access -system.physmem.avgQLat 5209.64 # Average queueing delay per request -system.physmem.avgBankLat 14124.50 # Average bank access latency per request +system.physmem.totQLat 36802775 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 167840775 # Sum of mem lat for all requests +system.physmem.totBusLat 29188000 # Total cycles spent in databus access +system.physmem.totBankLat 101850000 # Total cycles spent in bank access +system.physmem.avgQLat 5043.55 # Average queueing delay per request +system.physmem.avgBankLat 13957.79 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 23334.15 # Average memory access latency -system.physmem.avgRdBW 6.58 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 23001.34 # Average memory access latency +system.physmem.avgRdBW 6.84 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 6.58 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 6.84 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.04 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 6380 # Number of row buffer hits during reads +system.physmem.readRowHits 6392 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 87.29 # Row buffer hit rate for reads +system.physmem.readRowHitRate 87.60 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 9730927.35 # Average gap between requests +system.physmem.avgGap 9355527.20 # Average gap between requests system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -228,108 +228,108 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 191 # Number of system calls -system.cpu.numCycles 142247042 # number of cpu cycles simulated +system.cpu.numCycles 136534932 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 43100384 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 21816758 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 2115490 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 28214597 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 17877846 # Number of BTB hits +system.cpu.BPredUnit.lookups 41739250 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 21065104 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 1640413 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 26027262 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 16735646 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 6960493 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 7483 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 41104486 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 329097721 # Number of instructions fetch has processed -system.cpu.fetch.Branches 43100384 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 24838339 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 73741038 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 8424830 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 20890852 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 101 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 3376 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 52 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 39439386 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 697861 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 142038328 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.976886 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.453881 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 6736138 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 7270 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 38860071 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 317518566 # Number of instructions fetch has processed +system.cpu.fetch.Branches 41739250 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 23471784 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 70794265 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 6760095 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 21559516 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 34 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1854 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 30 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 37487912 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 519564 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 136324280 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.989165 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.456365 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 68979513 48.56% 48.56% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 7395782 5.21% 53.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 5795573 4.08% 57.85% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 6270161 4.41% 62.27% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 4963047 3.49% 65.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 4315752 3.04% 68.80% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 3304919 2.33% 71.12% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 4334607 3.05% 74.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 36678974 25.82% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 66156807 48.53% 48.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 6761816 4.96% 53.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 5641032 4.14% 57.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 6022575 4.42% 62.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 4881557 3.58% 65.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 4156543 3.05% 68.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 3204825 2.35% 71.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 4146681 3.04% 74.07% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 35352444 25.93% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 142038328 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.302997 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.313565 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 47965638 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 16109831 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 69363004 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 2371211 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 6228644 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 7501471 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 70557 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 414890822 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 218836 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 6228644 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 53736634 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 1580220 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 347679 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 65886950 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 14258201 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 404388597 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 136 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1669522 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 10203430 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 860 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 443737755 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 2388674830 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1302452182 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1086222648 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 384584986 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 59152769 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 14467 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 14465 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 35681480 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 105493757 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 93214934 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 4606734 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 5678105 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 392069014 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 25544 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 378019437 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1377395 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 42071369 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 110527513 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1062 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 142038328 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.661390 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.043453 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 136324280 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.305704 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.325548 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 45389084 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 16729555 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 66615921 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 2549925 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 5039795 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 7269016 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 69099 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 401164000 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 213330 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 5039795 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 50891753 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 1911896 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 347462 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 63595531 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 14537843 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 393365757 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 50 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1668272 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 10291112 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 1086 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 431881386 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 2329985493 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1257436076 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1072549417 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 384584833 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 47296553 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 14334 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 14333 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 36353497 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 103432229 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 91356063 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 4280154 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 5359345 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 383896453 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 25411 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 373948163 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1224653 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 34098402 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 84823076 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 961 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 136324280 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.743078 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.023492 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 29008018 20.42% 20.42% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 20551186 14.47% 34.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 20935508 14.74% 49.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 18224796 12.83% 62.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 24071271 16.95% 79.41% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 15985787 11.25% 90.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 9045864 6.37% 97.03% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 3293540 2.32% 99.35% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 922358 0.65% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 24852306 18.23% 18.23% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 19962410 14.64% 32.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 20554570 15.08% 47.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 18105177 13.28% 61.23% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 23977307 17.59% 78.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 15767707 11.57% 90.39% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 8831817 6.48% 96.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 3361471 2.47% 99.33% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 911515 0.67% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 142038328 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 136324280 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 9132 0.05% 0.05% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 4698 0.03% 0.08% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 8956 0.05% 0.05% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 4688 0.03% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.08% # attempts to use FU when none available @@ -348,349 +348,494 @@ system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.08% # at system.cpu.iq.fu_full::SimdShift 0 0.00% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.08% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 45614 0.25% 0.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 7807 0.04% 0.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 399 0.00% 0.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 3 0.00% 0.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 193826 1.08% 1.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 4889 0.03% 1.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 240972 1.34% 2.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.82% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 9466915 52.66% 55.48% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 8004617 44.52% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 46185 0.26% 0.34% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.34% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 7671 0.04% 0.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 470 0.00% 0.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 2 0.00% 0.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 190051 1.07% 1.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 6041 0.03% 1.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 241741 1.36% 2.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.84% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 9330966 52.43% 55.27% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 7960919 44.73% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 128267116 33.93% 33.93% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2174674 0.58% 34.51% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 34.51% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 34.51% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 34.51% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 34.51% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 34.51% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 34.51% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 34.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 34.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 34.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 34.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 34.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 34.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 34.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 34.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 34.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 34.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 34.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 34.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 6840592 1.81% 36.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 36.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 8692743 2.30% 38.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 3457219 0.91% 39.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 1621907 0.43% 39.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 21346208 5.65% 45.61% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 7171870 1.90% 47.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 7135741 1.89% 49.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 175286 0.05% 49.44% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 102459140 27.10% 76.54% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 88676941 23.46% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 126153074 33.74% 33.74% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2174128 0.58% 34.32% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 34.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 34.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 34.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 34.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 34.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 34.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 34.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 34.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 34.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 34.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 34.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 34.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 34.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 34.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 34.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 34.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 34.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 34.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 6786226 1.81% 36.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 36.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 8470375 2.27% 38.40% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 3426412 0.92% 39.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 1600673 0.43% 39.74% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 20911148 5.59% 45.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 7171927 1.92% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 7134560 1.91% 49.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 175286 0.05% 49.21% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 101505429 27.14% 76.35% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 88438925 23.65% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 378019437 # Type of FU issued -system.cpu.iq.rate 2.657485 # Inst issue rate -system.cpu.iq.fu_busy_cnt 17978872 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.047561 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 666289235 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 301587031 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 252300909 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 251144234 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 132592793 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 118832927 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 266512180 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 129486129 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 10875090 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 373948163 # Type of FU issued +system.cpu.iq.rate 2.738846 # Inst issue rate +system.cpu.iq.fu_busy_cnt 17797690 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.047594 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 653530496 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 287597541 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 249877083 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 249712453 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 130436942 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 118161488 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 262975786 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 128770067 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 11107823 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 10842660 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 119827 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 14278 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 10836994 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 8781151 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 113920 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 14326 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 8978150 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 19866 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1167 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 176383 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1158 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 6228644 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 80063 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 4890 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 392103714 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 1113019 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 105493757 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 93214934 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 14372 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 353 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 361 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 14278 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1696490 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 500488 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 2196978 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 373371007 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 101101213 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 4648430 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 5039795 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 281091 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 41482 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 383923458 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 951525 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 103432229 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 91356063 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 14236 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 345 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 384 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 14326 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1283309 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 356464 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1639773 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 370071311 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 100289689 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 3876852 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 9156 # number of nop insts executed -system.cpu.iew.exec_refs 188456752 # number of memory reference insts executed -system.cpu.iew.exec_branches 38701393 # Number of branches executed -system.cpu.iew.exec_stores 87355539 # Number of stores executed -system.cpu.iew.exec_rate 2.624807 # Inst execution rate -system.cpu.iew.wb_sent 371934669 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 371133836 # cumulative count of insts written-back -system.cpu.iew.wb_producers 184775670 # num instructions producing a value -system.cpu.iew.wb_consumers 367646771 # num instructions consuming a value +system.cpu.iew.exec_nop 1594 # number of nop insts executed +system.cpu.iew.exec_refs 187642898 # number of memory reference insts executed +system.cpu.iew.exec_branches 38279004 # Number of branches executed +system.cpu.iew.exec_stores 87353209 # Number of stores executed +system.cpu.iew.exec_rate 2.710451 # Inst execution rate +system.cpu.iew.wb_sent 368702519 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 368038571 # cumulative count of insts written-back +system.cpu.iew.wb_producers 182991065 # num instructions producing a value +system.cpu.iew.wb_consumers 363891400 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.609079 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.502590 # average fanout of values written-back +system.cpu.iew.wb_rate 2.695563 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.502873 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 43027028 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 24482 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 2045711 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 135809685 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.570338 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.654112 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 34846819 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 24450 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 1571698 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 131284486 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.658933 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.660928 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 38417531 28.29% 28.29% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 29199317 21.50% 49.79% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 13525216 9.96% 59.75% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 11128430 8.19% 67.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 13789447 10.15% 78.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 7275712 5.36% 83.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 3957925 2.91% 86.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3970991 2.92% 89.29% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 14545116 10.71% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 34526115 26.30% 26.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 28464962 21.68% 47.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 13313072 10.14% 58.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 11375196 8.66% 66.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 13798040 10.51% 77.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 7398451 5.64% 82.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 3831320 2.92% 85.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3930958 2.99% 88.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 14646372 11.16% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 135809685 # Number of insts commited each cycle -system.cpu.commit.committedInsts 273049078 # Number of instructions committed -system.cpu.commit.committedOps 349076802 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 131284486 # Number of insts commited each cycle +system.cpu.commit.committedInsts 273048987 # Number of instructions committed +system.cpu.commit.committedOps 349076711 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 177029037 # Number of memory references committed -system.cpu.commit.loads 94651097 # Number of loads committed +system.cpu.commit.refs 177028991 # Number of memory references committed +system.cpu.commit.loads 94651078 # Number of loads committed system.cpu.commit.membars 11033 # Number of memory barriers committed -system.cpu.commit.branches 36549060 # Number of branches committed +system.cpu.commit.branches 36549040 # Number of branches committed system.cpu.commit.fp_insts 114216705 # Number of committed floating point instructions. -system.cpu.commit.int_insts 279594003 # Number of committed integer instructions. +system.cpu.commit.int_insts 279593931 # Number of committed integer instructions. system.cpu.commit.function_calls 6225112 # Number of function calls committed. -system.cpu.commit.bw_lim_events 14545116 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 14646372 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 513365876 # The number of ROB reads -system.cpu.rob.rob_writes 790440754 # The number of ROB writes -system.cpu.timesIdled 6359 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 208714 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 273048466 # Number of Instructions Simulated -system.cpu.committedOps 349076190 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 273048466 # Number of Instructions Simulated -system.cpu.cpi 0.520959 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.520959 # CPI: Total CPI of All Threads -system.cpu.ipc 1.919537 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.919537 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1783321389 # number of integer regfile reads -system.cpu.int_regfile_writes 236147934 # number of integer regfile writes -system.cpu.fp_regfile_reads 189806588 # number of floating regfile reads -system.cpu.fp_regfile_writes 133619756 # number of floating regfile writes -system.cpu.misc_regfile_reads 991070858 # number of misc regfile reads -system.cpu.misc_regfile_writes 34426479 # number of misc regfile writes -system.cpu.icache.replacements 14002 # number of replacements -system.cpu.icache.tagsinuse 1857.450296 # Cycle average of tags in use -system.cpu.icache.total_refs 39422164 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 15897 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 2479.849280 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 500559121 # The number of ROB reads +system.cpu.rob.rob_writes 772890927 # The number of ROB writes +system.cpu.timesIdled 6411 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 210652 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 273048375 # Number of Instructions Simulated +system.cpu.committedOps 349076099 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 273048375 # Number of Instructions Simulated +system.cpu.cpi 0.500039 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.500039 # CPI: Total CPI of All Threads +system.cpu.ipc 1.999843 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.999843 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1769305779 # number of integer regfile reads +system.cpu.int_regfile_writes 232713829 # number of integer regfile writes +system.cpu.fp_regfile_reads 188383123 # number of floating regfile reads +system.cpu.fp_regfile_writes 132609484 # number of floating regfile writes +system.cpu.misc_regfile_reads 973808735 # number of misc regfile reads +system.cpu.misc_regfile_writes 34426415 # number of misc regfile writes +system.cpu.icache.replacements 13908 # number of replacements +system.cpu.icache.tagsinuse 1849.811927 # Cycle average of tags in use +system.cpu.icache.total_refs 37470862 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 15795 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 2372.324280 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1857.450296 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.906958 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.906958 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 39422164 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 39422164 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 39422164 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 39422164 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 39422164 # number of overall hits -system.cpu.icache.overall_hits::total 39422164 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 17219 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 17219 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 17219 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 17219 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 17219 # number of overall misses -system.cpu.icache.overall_misses::total 17219 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 362034000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 362034000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 362034000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 362034000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 362034000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 362034000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 39439383 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 39439383 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 39439383 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 39439383 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 39439383 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 39439383 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000437 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000437 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000437 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000437 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000437 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000437 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21025.262791 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 21025.262791 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 21025.262791 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 21025.262791 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 21025.262791 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 21025.262791 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 660 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 1849.811927 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.903228 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.903228 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 37470862 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 37470862 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 37470862 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 37470862 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 37470862 # number of overall hits +system.cpu.icache.overall_hits::total 37470862 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 17049 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 17049 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 17049 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 17049 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 17049 # number of overall misses +system.cpu.icache.overall_misses::total 17049 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 356549497 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 356549497 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 356549497 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 356549497 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 356549497 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 356549497 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 37487911 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 37487911 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 37487911 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 37487911 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 37487911 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 37487911 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000455 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000455 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000455 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000455 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000455 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000455 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20913.220541 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 20913.220541 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 20913.220541 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 20913.220541 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 20913.220541 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 20913.220541 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 585 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 15 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 19 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 44 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 30.789474 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1322 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1322 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1322 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1322 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1322 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1322 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15897 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 15897 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 15897 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 15897 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 15897 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 15897 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 295359000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 295359000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 295359000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 295359000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 295359000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 295359000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000403 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000403 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000403 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000403 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000403 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000403 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18579.543310 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18579.543310 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18579.543310 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 18579.543310 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18579.543310 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 18579.543310 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1254 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1254 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1254 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1254 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1254 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1254 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15795 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 15795 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 15795 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 15795 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 15795 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 15795 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 291702997 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 291702997 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 291702997 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 291702997 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 291702997 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 291702997 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000421 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000421 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000421 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000421 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000421 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000421 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18468.059323 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18468.059323 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18468.059323 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 18468.059323 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18468.059323 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 18468.059323 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1413 # number of replacements -system.cpu.dcache.tagsinuse 3122.832455 # Cycle average of tags in use -system.cpu.dcache.total_refs 172062891 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 4620 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 37243.050000 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 0 # number of replacements +system.cpu.l2cache.tagsinuse 3959.582107 # Cycle average of tags in use +system.cpu.l2cache.total_refs 13162 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 5412 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 2.432003 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::writebacks 367.644751 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 2774.541574 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 817.395782 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.011220 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.084672 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.024945 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.120837 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 12753 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 299 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 13052 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 1040 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 1040 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 18 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 18 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 12753 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 317 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 13070 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 12753 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 317 # number of overall hits +system.cpu.l2cache.overall_hits::total 13070 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 3042 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 1512 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 4554 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 2795 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 2795 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 3042 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 4307 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 7349 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 3042 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 4307 # number of overall misses +system.cpu.l2cache.overall_misses::total 7349 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 148332000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 74801500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 223133500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 128955500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 128955500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 148332000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 203757000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 352089000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 148332000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 203757000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 352089000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 15795 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 1811 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 17606 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 1040 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 1040 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 2813 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 2813 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 15795 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 4624 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 20419 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 15795 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 4624 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 20419 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.192593 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.834898 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.258662 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.993601 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.993601 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.192593 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.931445 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.359910 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.192593 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.931445 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.359910 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 48761.341223 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 49471.891534 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 48997.255160 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 46137.924866 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 46137.924866 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 48761.341223 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 47308.335268 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 47909.783644 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 48761.341223 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 47308.335268 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 47909.783644 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 12 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 40 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 52 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 12 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 40 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 52 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 12 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 40 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 52 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3030 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1472 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 4502 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 2795 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 2795 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3030 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 4267 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 7297 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3030 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 4267 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 7297 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 109506099 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 54676221 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 164182320 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 94308882 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 94308882 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 109506099 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 148985103 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 258491202 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 109506099 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 148985103 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 258491202 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.191833 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.812811 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.255708 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.993601 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.993601 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.191833 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.922794 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.357363 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.191833 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.922794 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.357363 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 36140.626733 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 37144.171875 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 36468.751666 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 33741.997138 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 33741.997138 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 36140.626733 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 34915.655730 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 35424.311635 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 36140.626733 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 34915.655730 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 35424.311635 # average overall mshr miss latency +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.replacements 1414 # number of replacements +system.cpu.dcache.tagsinuse 3122.405383 # Cycle average of tags in use +system.cpu.dcache.total_refs 170873491 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 4624 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 36953.609645 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 3122.832455 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.762410 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.762410 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 90004626 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 90004626 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 82031443 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 82031443 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 13565 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 13565 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 13257 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 13257 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 172036069 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 172036069 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 172036069 # number of overall hits -system.cpu.dcache.overall_hits::total 172036069 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 4061 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 4061 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 21217 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 21217 # number of WriteReq misses +system.cpu.dcache.occ_blocks::cpu.data 3122.405383 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.762306 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.762306 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 88815229 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 88815229 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 82031562 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 82031562 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 13475 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 13475 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 13225 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 13225 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 170846791 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 170846791 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 170846791 # number of overall hits +system.cpu.dcache.overall_hits::total 170846791 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 4046 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 4046 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 21103 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 21103 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 25278 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 25278 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 25278 # number of overall misses -system.cpu.dcache.overall_misses::total 25278 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 164288500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 164288500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 827896681 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 827896681 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 25149 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 25149 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 25149 # number of overall misses +system.cpu.dcache.overall_misses::total 25149 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 164690000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 164690000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 831954164 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 831954164 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 115000 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 115000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 992185181 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 992185181 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 992185181 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 992185181 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 90008687 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 90008687 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 82052660 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 82052660 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 13567 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 13567 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 13257 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 13257 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 172061347 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 172061347 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 172061347 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 172061347 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000045 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000045 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000259 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000259 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000147 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000147 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_latency::cpu.data 996644164 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 996644164 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 996644164 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 996644164 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 88819275 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 88819275 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 82052665 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 82052665 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 13477 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 13477 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 13225 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 13225 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 170871940 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 170871940 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 170871940 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 170871940 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000046 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000046 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000257 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000257 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000148 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000148 # miss rate for LoadLockedReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.000147 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.000147 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000147 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000147 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 40455.183452 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 40455.183452 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39020.440260 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 39020.440260 # average WriteReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 40704.399407 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 40704.399407 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39423.502061 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 39423.502061 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 57500 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 57500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 39250.936823 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 39250.936823 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 39250.936823 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 39250.936823 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 13009 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 844 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 400 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 16 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 32.522500 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 52.750000 # average number of cycles each access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 39629.574297 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 39629.574297 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 39629.574297 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 39629.574297 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 13562 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 751 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 431 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 12 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 31.466357 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 62.583333 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1035 # number of writebacks -system.cpu.dcache.writebacks::total 1035 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2253 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 2253 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 18405 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 18405 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 1040 # number of writebacks +system.cpu.dcache.writebacks::total 1040 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2234 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 2234 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 18291 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 18291 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 20658 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 20658 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 20658 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 20658 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1808 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1808 # number of ReadReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 20525 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 20525 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 20525 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 20525 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1812 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1812 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2812 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 2812 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 4620 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 4620 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 4620 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 4620 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 79609500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 79609500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 131989000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 131989000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 211598500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 211598500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 211598500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 211598500 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 4624 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 4624 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 4624 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 4624 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 79757000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 79757000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 131966500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 131966500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 211723500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 211723500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 211723500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 211723500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000020 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000020 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000034 # mshr miss rate for WriteReq accesses @@ -699,159 +844,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 44031.803097 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 44031.803097 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 46937.766714 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 46937.766714 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45800.541126 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 45800.541126 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45800.541126 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 45800.541126 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 44016.004415 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 44016.004415 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 46929.765292 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 46929.765292 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45787.954152 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 45787.954152 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45787.954152 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 45787.954152 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 3986.038510 # Cycle average of tags in use -system.cpu.l2cache.total_refs 13248 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 5422 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 2.443379 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 370.679666 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 2797.931598 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 817.427246 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.011312 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.085386 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.024946 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.121644 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 12839 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 301 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 13140 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 1035 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 1035 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 17 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 17 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 12839 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 318 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 13157 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 12839 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 318 # number of overall hits -system.cpu.l2cache.overall_hits::total 13157 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 3057 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 1506 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 4563 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 2796 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 2796 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 3057 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 4302 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 7359 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 3057 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 4302 # number of overall misses -system.cpu.l2cache.overall_misses::total 7359 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 151027000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 74633000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 225660000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 128994500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 128994500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 151027000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 203627500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 354654500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 151027000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 203627500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 354654500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 15896 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1807 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 17703 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 1035 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 1035 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 2813 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 2813 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 15896 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 4620 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 20516 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 15896 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 4620 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 20516 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.192313 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.833426 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.257753 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.993957 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.993957 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.192313 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.931169 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.358696 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.192313 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.931169 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.358696 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 49403.663723 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 49557.104914 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 49454.306377 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 46135.371960 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 46135.371960 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 49403.663723 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 47333.217108 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 48193.300720 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 49403.663723 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 47333.217108 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 48193.300720 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 11 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 39 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 50 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 11 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 39 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 50 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 11 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 39 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 50 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3046 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1467 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 4513 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 2796 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 2796 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3046 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 4263 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 7309 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3046 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 4263 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 7309 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 111924644 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 54839196 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 166763840 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 94353475 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 94353475 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 111924644 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 149192671 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 261117315 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 111924644 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 149192671 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 261117315 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.191621 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.811843 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.254929 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.993957 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.993957 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.191621 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.922727 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.356259 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.191621 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.922727 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.356259 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 36744.794485 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 37381.865031 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 36951.881232 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 33745.878040 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 33745.878040 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 36744.794485 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 34997.107905 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 35725.450130 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 36744.794485 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 34997.107905 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 35725.450130 # average overall mshr miss latency -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini index 0ba1f17a2..219e926d0 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini @@ -10,6 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a +clock=1000 init_param=0 kernel= load_addr_mask=1099511627775 @@ -29,7 +30,7 @@ system_port=system.membus.slave[0] [system.cpu] type=DerivO3CPU -children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload +children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -77,6 +78,7 @@ iewToFetchDelay=1 iewToRenameDelay=1 instShiftAmt=2 interrupts=system.cpu.interrupts +isa=system.cpu.isa issueToExecuteDelay=1 issueWidth=8 itb=system.cpu.itb @@ -95,7 +97,6 @@ numPhysIntRegs=256 numROBEntries=192 numRobs=1 numThreads=1 -phase=0 predType=tournament profile=0 progress_interval=0 @@ -129,16 +130,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=2 is_top_level=true -latency=1000 max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=2 size=262144 subblock_size=0 system=system @@ -421,16 +424,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=2 is_top_level=true -latency=1000 max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=2 size=131072 subblock_size=0 system=system @@ -444,6 +449,9 @@ mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=AlphaInterrupts +[system.cpu.isa] +type=AlphaISA + [system.cpu.itb] type=AlphaTLB size=48 @@ -451,22 +459,24 @@ size=48 [system.cpu.l2cache] type=BaseCache addr_ranges=0:18446744073709551615 -assoc=2 +assoc=8 block_size=64 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=20 is_top_level=false -latency=1000 max_miss_count=0 -mshrs=10 +mshrs=20 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=20 size=2097152 subblock_size=0 system=system -tgts_per_mshr=5 +tgts_per_mshr=12 trace_addr=0 two_queue=false write_buffers=8 @@ -476,10 +486,10 @@ mem_side=system.membus.slave[1] [system.cpu.toL2Bus] type=CoherentBus block_size=64 -clock=1000 +clock=500 header_cycles=1 use_default_range=false -width=8 +width=32 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side @@ -489,12 +499,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=perlbmk -I. -I lib lgred.makerand.pl -cwd=build/ALPHA/tests/fast/long/se/40.perlbmk/alpha/tru64/o3-timing +cwd=build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/o3-timing egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk +executable=/projects/pd/randd/dist/cpu2000/binaries/alpha/tru64/perlbmk gid=100 input=cin max_stack_size=67108864 @@ -512,18 +522,32 @@ clock=1000 header_cycles=1 use_default_range=false width=8 -master=system.physmem.port[0] +master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] -type=SimpleMemory +type=SimpleDRAM +addr_mapping=openmap +banks_per_rank=8 +clock=1000 conf_table_reported=false -file= in_addr_map=true -latency=30000 -latency_var=0 +lines_per_rowbuffer=64 +mem_sched_policy=fcfs null=false +page_policy=open range=0:134217727 +ranks_per_channel=2 +read_buffer_size=32 +tBURST=4000 +tCL=14000 +tRCD=14000 +tREFI=7800000 +tRFC=300000 +tRP=14000 +tWTR=1000 +write_buffer_size=32 +write_thresh_perc=70 zero=false port=system.membus.master[0] diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simout b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simout index b26c5402f..319c358f1 100755 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 2 2012 08:30:56 -gem5 started Jul 2 2012 09:41:27 -gem5 executing on zizzer -command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/40.perlbmk/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/fast/long/se/40.perlbmk/alpha/tru64/o3-timing +gem5 compiled Oct 30 2012 11:02:14 +gem5 started Oct 30 2012 12:07:24 +gem5 executing on u200540-lin +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. @@ -1385,4 +1385,4 @@ info: Increasing stack size by one page. 2000: 760651391 1000: 4031656975 0: 2206428413 -Exiting @ tick 646278131000 because target called exit() +Exiting @ tick 626365181000 because target called exit() diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt index ca0137184..cc561b02c 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt @@ -1,64 +1,64 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.643360 # Number of seconds simulated -sim_ticks 643359514000 # Number of ticks simulated -final_tick 643359514000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.626365 # Number of seconds simulated +sim_ticks 626365181000 # Number of ticks simulated +final_tick 626365181000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 181804 # Simulator instruction rate (inst/s) -host_op_rate 181804 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 64159253 # Simulator tick rate (ticks/s) -host_mem_usage 240484 # Number of bytes of host memory used -host_seconds 10027.54 # Real time elapsed on the host +host_inst_rate 141169 # Simulator instruction rate (inst/s) +host_op_rate 141169 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 48503245 # Simulator tick rate (ticks/s) +host_mem_usage 240100 # Number of bytes of host memory used +host_seconds 12913.88 # Real time elapsed on the host sim_insts 1823043370 # Number of instructions simulated sim_ops 1823043370 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 179328 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 30296192 # Number of bytes read from this memory -system.physmem.bytes_read::total 30475520 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 179328 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 179328 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu.inst 176064 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 30294656 # Number of bytes read from this memory +system.physmem.bytes_read::total 30470720 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 176064 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 176064 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 4282112 # Number of bytes written to this memory system.physmem.bytes_written::total 4282112 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2802 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 473378 # Number of read requests responded to by this memory -system.physmem.num_reads::total 476180 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 2751 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 473354 # Number of read requests responded to by this memory +system.physmem.num_reads::total 476105 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 66908 # Number of write requests responded to by this memory system.physmem.num_writes::total 66908 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 278737 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 47090610 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 47369347 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 278737 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 278737 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 6655862 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 6655862 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 6655862 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 278737 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 47090610 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 54025209 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 476180 # Total number of read requests seen +system.physmem.bw_read::cpu.inst 281088 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 48365805 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 48646893 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 281088 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 281088 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 6836446 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 6836446 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 6836446 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 281088 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 48365805 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 55483340 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 476105 # Total number of read requests seen system.physmem.writeReqs 66908 # Total number of write requests seen -system.physmem.cpureqs 543088 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 30475520 # Total number of bytes read from memory +system.physmem.cpureqs 543013 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 30470720 # Total number of bytes read from memory system.physmem.bytesWritten 4282112 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 30475520 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 30470720 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 4282112 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 78 # Number of read reqs serviced by write Q +system.physmem.servicedByWrQ 93 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 29588 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 29640 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 29713 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 29989 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 29577 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 29636 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 29701 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 29984 # Track reads on a per bank basis system.physmem.perBankRdReqs::4 29897 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 29812 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 29833 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 29883 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 29824 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 29670 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 29716 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 29651 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 29711 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 29806 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 29835 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 29877 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 29819 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 29663 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 29709 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 29641 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 29707 # Track reads on a per bank basis system.physmem.perBankRdReqs::13 29667 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 29710 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 29798 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 29702 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 29791 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 4187 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 4171 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 4154 # Track writes on a per bank basis @@ -77,14 +77,14 @@ system.physmem.perBankWrReqs::14 4170 # Tr system.physmem.perBankWrReqs::15 4213 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 643359452500 # Total gap between requests +system.physmem.totGap 626365119500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 476180 # Categorize read packet sizes +system.physmem.readPktSize::6 476105 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -105,12 +105,12 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 406668 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 67034 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 2226 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 147 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 406602 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 67013 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 2214 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 157 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 23 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -171,47 +171,47 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 1657778750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 15956610750 # Sum of mem lat for all requests -system.physmem.totBusLat 1904408000 # Total cycles spent in databus access -system.physmem.totBankLat 12394424000 # Total cycles spent in bank access -system.physmem.avgQLat 3481.98 # Average queueing delay per request -system.physmem.avgBankLat 26033.13 # Average bank access latency per request +system.physmem.totQLat 2248288249 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 16547544249 # Sum of mem lat for all requests +system.physmem.totBusLat 1904048000 # Total cycles spent in databus access +system.physmem.totBankLat 12395208000 # Total cycles spent in bank access +system.physmem.avgQLat 4723.18 # Average queueing delay per request +system.physmem.avgBankLat 26039.70 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 33515.11 # Average memory access latency -system.physmem.avgRdBW 47.37 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 6.66 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 47.37 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 6.66 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 34762.87 # Average memory access latency +system.physmem.avgRdBW 48.65 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 6.84 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 48.65 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 6.84 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 0.34 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.02 # Average read queue length over time -system.physmem.avgWrQLen 10.97 # Average write queue length over time -system.physmem.readRowHits 265466 # Number of row buffer hits during reads -system.physmem.writeRowHits 48780 # Number of row buffer hits during writes -system.physmem.readRowHitRate 55.76 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 72.91 # Row buffer hit rate for writes -system.physmem.avgGap 1184632.05 # Average gap between requests +system.physmem.busUtil 0.35 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.03 # Average read queue length over time +system.physmem.avgWrQLen 11.00 # Average write queue length over time +system.physmem.readRowHits 265467 # Number of row buffer hits during reads +system.physmem.writeRowHits 48790 # Number of row buffer hits during writes +system.physmem.readRowHitRate 55.77 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 72.92 # Row buffer hit rate for writes +system.physmem.avgGap 1153499.31 # Average gap between requests system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 526069225 # DTB read hits -system.cpu.dtb.read_misses 579156 # DTB read misses +system.cpu.dtb.read_hits 522560373 # DTB read hits +system.cpu.dtb.read_misses 588728 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 526648381 # DTB read accesses -system.cpu.dtb.write_hits 297161949 # DTB write hits -system.cpu.dtb.write_misses 50214 # DTB write misses +system.cpu.dtb.read_accesses 523149101 # DTB read accesses +system.cpu.dtb.write_hits 283071161 # DTB write hits +system.cpu.dtb.write_misses 50270 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 297212163 # DTB write accesses -system.cpu.dtb.data_hits 823231174 # DTB hits -system.cpu.dtb.data_misses 629370 # DTB misses +system.cpu.dtb.write_accesses 283121431 # DTB write accesses +system.cpu.dtb.data_hits 805631534 # DTB hits +system.cpu.dtb.data_misses 638998 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 823860544 # DTB accesses -system.cpu.itb.fetch_hits 405407805 # ITB hits -system.cpu.itb.fetch_misses 819 # ITB misses +system.cpu.dtb.data_accesses 806270532 # DTB accesses +system.cpu.itb.fetch_hits 395323042 # ITB hits +system.cpu.itb.fetch_misses 713 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 405408624 # ITB accesses +system.cpu.itb.fetch_accesses 395323755 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -225,246 +225,246 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 39 # Number of system calls -system.cpu.numCycles 1286719029 # number of cpu cycles simulated +system.cpu.numCycles 1252730363 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 402098178 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 264077360 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 27592144 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 331664988 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 265014495 # Number of BTB hits +system.cpu.BPredUnit.lookups 388924238 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 255857711 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 25855826 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 319270007 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 258448229 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 57783698 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 7200 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 424132228 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 3367367633 # Number of instructions fetch has processed -system.cpu.fetch.Branches 402098178 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 322798193 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 646196241 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 166511643 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 68824339 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 161 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 9321 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 70 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 405407805 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 9489583 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1277592072 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.635714 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.156498 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 57345473 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 6929 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 410516643 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 3276851782 # Number of instructions fetch has processed +system.cpu.fetch.Branches 388924238 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 315793702 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 630639053 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 158095234 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 69542401 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 142 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 6974 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 40 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 395323042 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 11287657 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1242455631 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.637399 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.141502 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 631395831 49.42% 49.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 61908546 4.85% 54.27% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 44955490 3.52% 57.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 72442913 5.67% 63.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 127234893 9.96% 73.41% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 45699485 3.58% 76.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 41229418 3.23% 80.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 8398105 0.66% 80.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 244327391 19.12% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 611816578 49.24% 49.24% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 57562553 4.63% 53.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 43380535 3.49% 57.37% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 71885087 5.79% 63.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 129158557 10.40% 73.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 46353903 3.73% 77.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 41221359 3.32% 80.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 7475471 0.60% 81.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 233601588 18.80% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1277592072 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.312499 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.617019 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 452657714 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 55753482 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 621910588 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 8852787 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 138417501 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 35688961 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 12608 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 3272292546 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 46854 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 138417501 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 480561611 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 21495863 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 27669 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 602513400 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 34576028 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 3180651525 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 116 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 14808 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 29849843 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 2112719200 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3696606448 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3567977970 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 128628478 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 1242455631 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.310461 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.615768 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 438637304 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 56111569 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 606899212 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 9069214 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 131738332 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 31728331 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 12429 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 3195294876 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 46495 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 131738332 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 467849375 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 21501203 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 26667 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 586406570 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 34933484 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 3096787172 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 107 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 15151 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 28695106 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 2055570524 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3581032022 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3460282692 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 120749330 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1384969070 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 727750130 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 4257 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 122 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 112675652 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 746614838 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 365012896 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 68733869 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 9300063 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2678263841 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 113 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2207816608 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 17947963 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 855152506 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 736519407 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 74 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1277592072 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.728108 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.823912 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 670601454 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 4229 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 95 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 109203185 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 744330520 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 351486216 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 69160897 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 8862018 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2624452005 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 84 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2160789811 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 17925786 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 801345385 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 726874664 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 45 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1242455631 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.739128 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.803652 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 463406335 36.27% 36.27% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 208221001 16.30% 52.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 253020667 19.80% 72.37% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 119517466 9.35% 81.73% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 107963864 8.45% 90.18% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 79412827 6.22% 96.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 22155797 1.73% 98.13% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 18005418 1.41% 99.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 5888697 0.46% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 445618907 35.87% 35.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 197093468 15.86% 51.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 251212495 20.22% 71.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 120765174 9.72% 81.67% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 104645405 8.42% 90.09% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 79514591 6.40% 96.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 24185782 1.95% 98.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 17651908 1.42% 99.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1767901 0.14% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1277592072 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1242455631 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 1146338 3.02% 3.02% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 3.02% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 3.02% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.02% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.02% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.02% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 3.02% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.02% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 3.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 3.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.02% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 26001591 68.56% 71.58% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 10776371 28.42% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 1146234 3.12% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 25650345 69.73% 72.85% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 9987945 27.15% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2752 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1263752223 57.24% 57.24% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 17092 0.00% 57.24% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 57.24% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 29225332 1.32% 58.56% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 8254699 0.37% 58.94% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 7204653 0.33% 59.26% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 4 0.00% 59.26% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.26% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.26% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 590734000 26.76% 86.02% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 308625853 13.98% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1234634682 57.14% 57.14% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 17092 0.00% 57.14% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 57.14% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 27851271 1.29% 58.43% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 8254694 0.38% 58.81% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 7204651 0.33% 59.14% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 4 0.00% 59.14% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.14% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.14% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 589669482 27.29% 86.43% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 293155183 13.57% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2207816608 # Type of FU issued -system.cpu.iq.rate 1.715850 # Inst issue rate -system.cpu.iq.fu_busy_cnt 37924300 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.017177 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 5591649635 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 3435076999 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 2032506919 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 157447916 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 98414178 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 76358311 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2164690748 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 81047408 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 59332604 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2160789811 # Type of FU issued +system.cpu.iq.rate 1.724864 # Inst issue rate +system.cpu.iq.fu_busy_cnt 36784524 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.017024 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 5467643878 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 3337715121 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1990557348 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 151101685 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 88155822 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 73610149 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2120121697 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 77449886 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 62086371 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 235544812 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 11687 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 77448 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 154218000 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 233260494 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 21308 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 76027 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 140691320 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 4399 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 2001 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 4419 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 2184 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 138417501 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 7967616 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 401073 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 3039337687 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 731219 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 746614838 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 365012896 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 113 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 191088 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 1450 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 77448 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 27584304 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 31589 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 27615893 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 2113102879 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 526648496 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 94713729 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 131738332 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 7963688 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 401158 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2987881141 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 737486 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 744330520 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 351486216 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 84 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 191221 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 1459 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 76027 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 25850018 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 29386 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 25879404 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 2066687986 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 523149239 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 94101825 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 361073733 # number of nop insts executed -system.cpu.iew.exec_refs 823861177 # number of memory reference insts executed -system.cpu.iew.exec_branches 283370996 # Number of branches executed -system.cpu.iew.exec_stores 297212681 # Number of stores executed -system.cpu.iew.exec_rate 1.642241 # Inst execution rate -system.cpu.iew.wb_sent 2111610495 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 2108865230 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1193923515 # num instructions producing a value -system.cpu.iew.wb_consumers 1771725000 # num instructions consuming a value +system.cpu.iew.exec_nop 363429052 # number of nop insts executed +system.cpu.iew.exec_refs 806271170 # number of memory reference insts executed +system.cpu.iew.exec_branches 277685226 # Number of branches executed +system.cpu.iew.exec_stores 283121931 # Number of stores executed +system.cpu.iew.exec_rate 1.649747 # Inst execution rate +system.cpu.iew.wb_sent 2066566988 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 2064167497 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1181646251 # num instructions producing a value +system.cpu.iew.wb_consumers 1754266128 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.638948 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.673876 # average fanout of values written-back +system.cpu.iew.wb_rate 1.647735 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.673584 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 1013373341 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 961921272 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 39 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 27579934 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1139174571 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.763547 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.475615 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 25843781 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1110717299 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.808730 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.509348 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 512941432 45.03% 45.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 233024401 20.46% 65.48% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 122205483 10.73% 76.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 58495999 5.13% 81.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 54572847 4.79% 86.14% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 24070176 2.11% 88.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 18202956 1.60% 89.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 17085980 1.50% 91.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 98575297 8.65% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 491335332 44.24% 44.24% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 228930715 20.61% 64.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 119800633 10.79% 75.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 58838434 5.30% 80.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 50772069 4.57% 85.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 24138536 2.17% 87.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 19157540 1.72% 89.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 16738195 1.51% 90.91% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 101005845 9.09% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1139174571 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1110717299 # Number of insts commited each cycle system.cpu.commit.committedInsts 2008987604 # Number of instructions committed system.cpu.commit.committedOps 2008987604 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -475,320 +475,192 @@ system.cpu.commit.branches 266706457 # Nu system.cpu.commit.fp_insts 71824891 # Number of committed floating point instructions. system.cpu.commit.int_insts 1778941351 # Number of committed integer instructions. system.cpu.commit.function_calls 39955347 # Number of function calls committed. -system.cpu.commit.bw_lim_events 98575297 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 101005845 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 4057323809 # The number of ROB reads -system.cpu.rob.rob_writes 6183141843 # The number of ROB writes -system.cpu.timesIdled 212566 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 9126957 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 3974983920 # The number of ROB reads +system.cpu.rob.rob_writes 6073558017 # The number of ROB writes +system.cpu.timesIdled 212495 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 10274732 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1823043370 # Number of Instructions Simulated system.cpu.committedOps 1823043370 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 1823043370 # Number of Instructions Simulated -system.cpu.cpi 0.705808 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.705808 # CPI: Total CPI of All Threads -system.cpu.ipc 1.416815 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.416815 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 2692001611 # number of integer regfile reads -system.cpu.int_regfile_writes 1522401675 # number of integer regfile writes -system.cpu.fp_regfile_reads 82933521 # number of floating regfile reads -system.cpu.fp_regfile_writes 54035244 # number of floating regfile writes +system.cpu.cpi 0.687164 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.687164 # CPI: Total CPI of All Threads +system.cpu.ipc 1.455256 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.455256 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 2628560765 # number of integer regfile reads +system.cpu.int_regfile_writes 1497106363 # number of integer regfile writes +system.cpu.fp_regfile_reads 78811457 # number of floating regfile reads +system.cpu.fp_regfile_writes 52660996 # number of floating regfile writes system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.icache.replacements 8405 # number of replacements -system.cpu.icache.tagsinuse 1669.043453 # Cycle average of tags in use -system.cpu.icache.total_refs 405395000 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 10125 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 40039.012346 # Average number of references to valid blocks. +system.cpu.icache.replacements 8336 # number of replacements +system.cpu.icache.tagsinuse 1656.236510 # Cycle average of tags in use +system.cpu.icache.total_refs 395310182 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 10048 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 39342.175756 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1669.043453 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.814963 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.814963 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 405395000 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 405395000 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 405395000 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 405395000 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 405395000 # number of overall hits -system.cpu.icache.overall_hits::total 405395000 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 12805 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 12805 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 12805 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 12805 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 12805 # number of overall misses -system.cpu.icache.overall_misses::total 12805 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 310013999 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 310013999 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 310013999 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 310013999 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 310013999 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 310013999 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 405407805 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 405407805 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 405407805 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 405407805 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 405407805 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 405407805 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000032 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000032 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000032 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000032 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000032 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000032 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 24210.386490 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 24210.386490 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 24210.386490 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 24210.386490 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 24210.386490 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 24210.386490 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 1240 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 1656.236510 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.808709 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.808709 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 395310182 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 395310182 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 395310182 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 395310182 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 395310182 # number of overall hits +system.cpu.icache.overall_hits::total 395310182 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 12860 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 12860 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 12860 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 12860 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 12860 # number of overall misses +system.cpu.icache.overall_misses::total 12860 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 302484999 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 302484999 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 302484999 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 302484999 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 302484999 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 302484999 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 395323042 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 395323042 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 395323042 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 395323042 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 395323042 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 395323042 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000033 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000033 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000033 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000033 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000033 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000033 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23521.384059 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 23521.384059 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 23521.384059 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 23521.384059 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 23521.384059 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 23521.384059 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 562 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 17 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 15 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 72.941176 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 37.466667 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2679 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 2679 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 2679 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 2679 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 2679 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 2679 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 10126 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 10126 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 10126 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 10126 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 10126 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 10126 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 232973499 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 232973499 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 232973499 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 232973499 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 232973499 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 232973499 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2811 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 2811 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 2811 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 2811 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 2811 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 2811 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 10049 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 10049 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 10049 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 10049 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 10049 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 10049 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 227447999 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 227447999 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 227447999 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 227447999 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 227447999 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 227447999 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000025 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000025 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000025 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000025 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 23007.455955 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 23007.455955 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 23007.455955 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 23007.455955 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 23007.455955 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 23007.455955 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22633.893820 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 22633.893820 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22633.893820 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 22633.893820 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22633.893820 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 22633.893820 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1528133 # number of replacements -system.cpu.dcache.tagsinuse 4094.874938 # Cycle average of tags in use -system.cpu.dcache.total_refs 674537761 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1532229 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 440.232995 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 312771000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4094.874938 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999725 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999725 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 464804507 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 464804507 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 209733210 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 209733210 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 44 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 44 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 674537717 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 674537717 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 674537717 # number of overall hits -system.cpu.dcache.overall_hits::total 674537717 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1925854 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1925854 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1061686 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1061686 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 2987540 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2987540 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2987540 # number of overall misses -system.cpu.dcache.overall_misses::total 2987540 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 59226868000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 59226868000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 33628175859 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 33628175859 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 51000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 51000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 92855043859 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 92855043859 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 92855043859 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 92855043859 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 466730361 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 466730361 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 210794896 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 210794896 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 45 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 45 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 677525257 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 677525257 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 677525257 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 677525257 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004126 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.004126 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005037 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.005037 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.022222 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.022222 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.004409 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.004409 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.004409 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.004409 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 30753.560758 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 30753.560758 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31674.314118 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 31674.314118 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 51000 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 51000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 31080.770085 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 31080.770085 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 31080.770085 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 31080.770085 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 12002 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 95 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 360 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 33.338889 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 95 # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 95938 # number of writebacks -system.cpu.dcache.writebacks::total 95938 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 465267 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 465267 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 990045 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 990045 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1455312 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1455312 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1455312 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1455312 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1460587 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1460587 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 71641 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 71641 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1532228 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1532228 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1532228 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1532228 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 35449802000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 35449802000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3677102500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3677102500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 49000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 49000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 39126904500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 39126904500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 39126904500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 39126904500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003129 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003129 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000340 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000340 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.022222 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.022222 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002262 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.002262 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002262 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.002262 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24270.928058 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24270.928058 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51326.789129 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51326.789129 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 49000 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 49000 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25535.954505 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 25535.954505 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25535.954505 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 25535.954505 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 443402 # number of replacements -system.cpu.l2cache.tagsinuse 32704.051187 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1090376 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 476137 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 2.290047 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 443327 # number of replacements +system.cpu.l2cache.tagsinuse 32703.368896 # Cycle average of tags in use +system.cpu.l2cache.total_refs 1090075 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 476063 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 2.289770 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 1293.286803 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 35.630813 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 31375.133571 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.039468 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.001087 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.957493 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.998048 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 7323 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 1054063 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1061386 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 95938 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 95938 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 4788 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 4788 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 7323 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1058851 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1066174 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 7323 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1058851 # number of overall hits -system.cpu.l2cache.overall_hits::total 1066174 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 2803 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 406525 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 409328 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 66853 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 66853 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 2803 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 473378 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 476181 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 2803 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 473378 # number of overall misses -system.cpu.l2cache.overall_misses::total 476181 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 149606000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 23448047500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 23597653500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3556964500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 3556964500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 149606000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 27005012000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 27154618000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 149606000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 27005012000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 27154618000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 10126 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1460588 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 1470714 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 95938 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 95938 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 71641 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 71641 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 10126 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1532229 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 1542355 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 10126 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1532229 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 1542355 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.276812 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.278330 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.278319 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.933167 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.933167 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.276812 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.308947 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.308736 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.276812 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.308947 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.308736 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53373.528362 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 57679.226370 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 57649.741772 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 53205.757408 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 53205.757408 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53373.528362 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 57047.458902 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 57025.832614 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53373.528362 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 57047.458902 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 57025.832614 # average overall miss latency +system.cpu.l2cache.occ_blocks::writebacks 1301.685858 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 33.962586 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 31367.720451 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.039724 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.001036 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.957267 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.998028 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 7297 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 1053741 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1061038 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 95985 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 95985 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 4786 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 4786 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 7297 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 1058527 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 1065824 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 7297 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 1058527 # number of overall hits +system.cpu.l2cache.overall_hits::total 1065824 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 2752 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 406502 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 409254 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 66852 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 66852 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 2752 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 473354 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 476106 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 2752 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 473354 # number of overall misses +system.cpu.l2cache.overall_misses::total 476106 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 144416000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 23987597000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 24132013000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3556756000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 3556756000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 144416000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 27544353000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 27688769000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 144416000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 27544353000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 27688769000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 10049 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 1460243 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 1470292 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 95985 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 95985 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 71638 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 71638 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 10049 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1531881 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 1541930 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 10049 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1531881 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 1541930 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.273858 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.278380 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.278349 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.933192 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.933192 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.273858 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.309002 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.308773 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.273858 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.309002 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.308773 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52476.744186 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 59009.788390 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 58965.857389 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 53203.434452 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 53203.434452 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52476.744186 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 58189.754391 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 58156.731904 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52476.744186 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 58189.754391 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 58156.731904 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -799,50 +671,162 @@ system.cpu.l2cache.fast_writes 0 # nu system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks::writebacks 66908 # number of writebacks system.cpu.l2cache.writebacks::total 66908 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2803 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 406525 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 409328 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66853 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 66853 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 2803 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 473378 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 476181 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 2803 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 473378 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 476181 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 114329941 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 18253645467 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 18367975408 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2750960138 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2750960138 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 114329941 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 21004605605 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 21118935546 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 114329941 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 21004605605 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 21118935546 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.276812 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.278330 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.278319 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.933167 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.933167 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.276812 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.308947 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.308736 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.276812 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.308947 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.308736 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40788.419907 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 44901.655414 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 44873.488762 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 41149.389526 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 41149.389526 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40788.419907 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 44371.740142 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 44350.647224 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40788.419907 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 44371.740142 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 44350.647224 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2752 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 406502 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 409254 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66852 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 66852 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2752 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 473354 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 476106 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2752 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 473354 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 476106 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 109781392 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 18848561489 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 18958342881 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2750782112 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2750782112 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 109781392 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 21599343601 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 21709124993 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 109781392 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 21599343601 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 21709124993 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.273858 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.278380 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.278349 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.933192 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.933192 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.273858 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.309002 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.308773 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.273858 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.309002 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.308773 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39891.494186 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 46367.696811 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 46324.148038 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 41147.342069 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 41147.342069 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39891.494186 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 45630.423744 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 45597.251438 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39891.494186 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 45630.423744 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 45597.251438 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.replacements 1527785 # number of replacements +system.cpu.dcache.tagsinuse 4094.883301 # Cycle average of tags in use +system.cpu.dcache.total_refs 668274960 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1531881 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 436.244695 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 304908000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4094.883301 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999727 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999727 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 458541726 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 458541726 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 209733214 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 209733214 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 20 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 20 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 668274940 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 668274940 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 668274940 # number of overall hits +system.cpu.dcache.overall_hits::total 668274940 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1925848 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1925848 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1061682 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1061682 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2987530 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2987530 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2987530 # number of overall misses +system.cpu.dcache.overall_misses::total 2987530 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 59762661000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 59762661000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 33641566357 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 33641566357 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 93404227357 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 93404227357 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 93404227357 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 93404227357 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 460467574 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 460467574 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 210794896 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 210794896 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 20 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 20 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 671262470 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 671262470 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 671262470 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 671262470 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004182 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.004182 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005037 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.005037 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.004451 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.004451 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.004451 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.004451 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 31031.868039 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 31031.868039 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31687.045986 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 31687.045986 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 31264.699386 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 31264.699386 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 31264.699386 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 31264.699386 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 11600 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 137 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 365 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 31.780822 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 137 # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 95985 # number of writebacks +system.cpu.dcache.writebacks::total 95985 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 465605 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 465605 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 990044 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 990044 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1455649 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1455649 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1455649 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1455649 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1460243 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1460243 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 71638 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 71638 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1531881 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1531881 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1531881 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1531881 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 35985859000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 35985859000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3676864000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3676864000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 39662723000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 39662723000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 39662723000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 39662723000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003171 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003171 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000340 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000340 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002282 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.002282 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002282 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.002282 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24643.746965 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24643.746965 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51325.609313 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51325.609313 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25891.517030 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 25891.517030 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25891.517030 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 25891.517030 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini index 39878e8d2..c3641e537 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini @@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a -clock=1 +clock=1000 init_param=0 kernel= load_addr_mask=1099511627775 @@ -30,7 +30,7 @@ system_port=system.membus.slave[0] [system.cpu] type=DerivO3CPU -children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload +children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -78,6 +78,7 @@ iewToFetchDelay=1 iewToRenameDelay=1 instShiftAmt=2 interrupts=system.cpu.interrupts +isa=system.cpu.isa issueToExecuteDelay=1 issueWidth=8 itb=system.cpu.itb @@ -129,18 +130,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=262144 subblock_size=0 system=system @@ -159,7 +160,7 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=ArmTableWalker -clock=1 +clock=500 num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[3] @@ -432,18 +433,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=131072 subblock_size=0 system=system @@ -457,6 +458,23 @@ mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=ArmInterrupts +[system.cpu.isa] +type=ArmISA +fpsid=1090793632 +id_isar0=34607377 +id_isar1=34677009 +id_isar2=555950401 +id_isar3=17899825 +id_isar4=268501314 +id_isar5=0 +id_mmfr0=3 +id_mmfr1=0 +id_mmfr2=19070976 +id_mmfr3=4027589137 +id_pfr0=49 +id_pfr1=1 +midr=890224640 + [system.cpu.itb] type=ArmTLB children=walker @@ -465,7 +483,7 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=ArmTableWalker -clock=1 +clock=500 num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[2] @@ -473,24 +491,24 @@ port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] type=BaseCache addr_ranges=0:18446744073709551615 -assoc=2 +assoc=8 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=20 is_top_level=false max_miss_count=0 -mshrs=10 +mshrs=20 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=20 size=2097152 subblock_size=0 system=system -tgts_per_mshr=5 +tgts_per_mshr=12 trace_addr=0 two_queue=false write_buffers=8 @@ -500,10 +518,10 @@ mem_side=system.membus.slave[1] [system.cpu.toL2Bus] type=CoherentBus block_size=64 -clock=1000 +clock=500 header_cycles=1 use_default_range=false -width=8 +width=32 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port @@ -540,15 +558,28 @@ master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] -type=SimpleMemory -bandwidth=73.000000 -clock=1 +type=SimpleDRAM +addr_mapping=openmap +banks_per_rank=8 +clock=1000 conf_table_reported=false in_addr_map=true -latency=30000 -latency_var=0 +lines_per_rowbuffer=64 +mem_sched_policy=fcfs null=false +page_policy=open range=0:134217727 +ranks_per_channel=2 +read_buffer_size=32 +tBURST=4000 +tCL=14000 +tRCD=14000 +tREFI=7800000 +tRFC=300000 +tRP=14000 +tWTR=1000 +write_buffer_size=32 +write_thresh_perc=70 zero=false port=system.membus.master[0] diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout index 278fe40f3..220b82b27 100755 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout @@ -1,8 +1,8 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 21 2012 11:19:00 -gem5 started Sep 21 2012 12:46:31 +gem5 compiled Oct 30 2012 11:20:14 +gem5 started Oct 30 2012 20:00:53 gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second @@ -1385,4 +1385,4 @@ info: Increasing stack size by one page. 2000: 760651391 1000: 4031656975 0: 2206428413 -Exiting @ tick 653190727500 because target called exit() +Exiting @ tick 624867585500 because target called exit() diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt index ac8776e10..65535d511 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt @@ -1,64 +1,64 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.635788 # Number of seconds simulated -sim_ticks 635788224000 # Number of ticks simulated -final_tick 635788224000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.624868 # Number of seconds simulated +sim_ticks 624867585500 # Number of ticks simulated +final_tick 624867585500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 107590 # Simulator instruction rate (inst/s) -host_op_rate 146523 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 49411882 # Simulator tick rate (ticks/s) -host_mem_usage 254872 # Number of bytes of host memory used -host_seconds 12867.11 # Real time elapsed on the host -sim_insts 1384378595 # Number of instructions simulated -sim_ops 1885333347 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 160512 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 30246144 # Number of bytes read from this memory -system.physmem.bytes_read::total 30406656 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 160512 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 160512 # Number of instructions bytes read from this memory +host_inst_rate 92987 # Simulator instruction rate (inst/s) +host_op_rate 126636 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 41971725 # Simulator tick rate (ticks/s) +host_mem_usage 253512 # Number of bytes of host memory used +host_seconds 14887.82 # Real time elapsed on the host +sim_insts 1384379060 # Number of instructions simulated +sim_ops 1885333812 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 155584 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 30242752 # Number of bytes read from this memory +system.physmem.bytes_read::total 30398336 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 155584 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 155584 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 4230272 # Number of bytes written to this memory system.physmem.bytes_written::total 4230272 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2508 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 472596 # Number of read requests responded to by this memory -system.physmem.num_reads::total 475104 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 2431 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 472543 # Number of read requests responded to by this memory +system.physmem.num_reads::total 474974 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 66098 # Number of write requests responded to by this memory system.physmem.num_writes::total 66098 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 252461 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 47572671 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 47825132 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 252461 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 252461 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 6653587 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 6653587 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 6653587 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 252461 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 47572671 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 54478719 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 475105 # Total number of read requests seen +system.physmem.bw_read::cpu.inst 248987 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 48398657 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 48647644 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 248987 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 248987 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 6769869 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 6769869 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 6769869 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 248987 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 48398657 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 55417514 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 474974 # Total number of read requests seen system.physmem.writeReqs 66098 # Total number of write requests seen -system.physmem.cpureqs 545524 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 30406656 # Total number of bytes read from memory +system.physmem.cpureqs 545402 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 30398336 # Total number of bytes read from memory system.physmem.bytesWritten 4230272 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 30406656 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 30398336 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 4230272 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 162 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 4321 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 29681 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 29709 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 29623 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 29546 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 29672 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 29640 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 29628 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 29737 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 29753 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 29773 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 29801 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 29855 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 29675 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 29602 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 29637 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 29611 # Track reads on a per bank basis +system.physmem.servicedByWrQ 146 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 4330 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 29668 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 29687 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 29628 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 29545 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 29653 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 29623 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 29618 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 29734 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 29744 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 29769 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 29790 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 29857 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 29669 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 29606 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 29627 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 29610 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 4129 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 4141 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 4096 # Track writes on a per bank basis @@ -77,14 +77,14 @@ system.physmem.perBankWrReqs::14 4108 # Tr system.physmem.perBankWrReqs::15 4128 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 635788203500 # Total gap between requests +system.physmem.totGap 624867513500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 475105 # Categorize read packet sizes +system.physmem.readPktSize::6 474974 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -102,16 +102,16 @@ system.physmem.neitherpktsize::2 0 # ca system.physmem.neitherpktsize::3 0 # categorize neither packet sizes system.physmem.neitherpktsize::4 0 # categorize neither packet sizes system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 4321 # categorize neither packet sizes +system.physmem.neitherpktsize::6 4330 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 407840 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 66686 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 312 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 82 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 17 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 407769 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 66657 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 297 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 83 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 18 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see @@ -171,27 +171,27 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 2296699471 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 17086173471 # Sum of mem lat for all requests -system.physmem.totBusLat 1899772000 # Total cycles spent in databus access -system.physmem.totBankLat 12889702000 # Total cycles spent in bank access -system.physmem.avgQLat 4835.74 # Average queueing delay per request -system.physmem.avgBankLat 27139.47 # Average bank access latency per request +system.physmem.totQLat 3316258619 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 18090208619 # Sum of mem lat for all requests +system.physmem.totBusLat 1899312000 # Total cycles spent in databus access +system.physmem.totBankLat 12874638000 # Total cycles spent in bank access +system.physmem.avgQLat 6984.13 # Average queueing delay per request +system.physmem.avgBankLat 27114.32 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 35975.21 # Average memory access latency -system.physmem.avgRdBW 47.83 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 6.65 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 47.83 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 6.65 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 38098.45 # Average memory access latency +system.physmem.avgRdBW 48.65 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 6.77 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 48.65 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 6.77 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 0.34 # Data bus utilization in percentage +system.physmem.busUtil 0.35 # Data bus utilization in percentage system.physmem.avgRdQLen 0.03 # Average read queue length over time -system.physmem.avgWrQLen 17.42 # Average write queue length over time -system.physmem.readRowHits 249227 # Number of row buffer hits during reads -system.physmem.writeRowHits 48069 # Number of row buffer hits during writes +system.physmem.avgWrQLen 17.43 # Average write queue length over time +system.physmem.readRowHits 249202 # Number of row buffer hits during reads +system.physmem.writeRowHits 48033 # Number of row buffer hits during writes system.physmem.readRowHitRate 52.48 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 72.72 # Row buffer hit rate for writes -system.physmem.avgGap 1174768.44 # Average gap between requests +system.physmem.writeRowHitRate 72.67 # Row buffer hit rate for writes +system.physmem.avgGap 1154869.43 # Average gap between requests system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -235,577 +235,450 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1411 # Number of system calls -system.cpu.numCycles 1271576449 # number of cpu cycles simulated +system.cpu.numCycles 1249735172 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 450228409 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 355532784 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 33221025 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 286250905 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 237054856 # Number of BTB hits +system.cpu.BPredUnit.lookups 439117025 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 350578524 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 30630316 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 248764319 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 227490785 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 53630453 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 2814194 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 368782120 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 2317566621 # Number of instructions fetch has processed -system.cpu.fetch.Branches 450228409 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 290685309 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 618187609 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 167802769 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 122950545 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 2044 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 34033 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 120 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 346967374 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 10833079 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1244485983 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.575716 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.174798 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 52186990 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 2806187 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 354123352 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 2285928065 # Number of instructions fetch has processed +system.cpu.fetch.Branches 439117025 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 279677775 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 600707462 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 157912293 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 133000859 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 565 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 11147 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 82 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 333825475 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 10767149 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1215073364 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.587868 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.187266 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 626344117 50.33% 50.33% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 45317842 3.64% 53.97% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 101227769 8.13% 62.11% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 59470859 4.78% 66.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 73017121 5.87% 72.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 44727211 3.59% 76.35% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 30024154 2.41% 78.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 31448495 2.53% 81.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 232908415 18.72% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 614410423 50.57% 50.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 42578199 3.50% 54.07% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 95045800 7.82% 61.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 56224969 4.63% 66.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 72457573 5.96% 72.48% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 42599927 3.51% 75.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 31039765 2.55% 78.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 31697654 2.61% 81.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 229019054 18.85% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1244485983 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.354071 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.822593 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 419135073 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 95311788 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 577111124 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 18421558 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 134506440 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 50263790 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 26327 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 3103411757 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 60284 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 134506440 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 455352486 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 27182944 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 495803 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 558181591 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 68766719 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 3020461835 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 80 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1786182 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 58542729 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 3 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 2987223490 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 14381793689 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 13781741718 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 600051971 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 1993152898 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 994070592 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 26249 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 23484 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 177920569 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 971527729 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 505697139 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 29364054 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 38323451 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2844663565 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 34202 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2471693501 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 7154025 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 946732451 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 2394075214 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 11217 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1244485983 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.986116 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.887022 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 1215073364 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.351368 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.829130 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 403820359 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 105461627 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 561742218 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 16831582 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 127217578 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 44615078 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 13114 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 3041090435 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 27022 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 127217578 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 439577665 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 35450988 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 444214 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 540789818 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 71593101 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2966286071 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 77 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 4807554 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 56267627 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 2940514356 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 14121260893 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 13550785312 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 570475581 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 1993153642 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 947360714 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 22542 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 20019 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 191397273 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 972715984 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 490205592 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 36288460 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 40771047 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2804297042 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 31006 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2436370950 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 13311855 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 906440094 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 2354573703 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 7928 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1215073364 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.005123 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.874281 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 394145382 31.67% 31.67% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 193214413 15.53% 47.20% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 204405304 16.42% 63.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 171173190 13.75% 77.38% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 129740055 10.43% 87.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 97310600 7.82% 95.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 36398713 2.92% 98.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 12543196 1.01% 99.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 5555130 0.45% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 379121475 31.20% 31.20% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 183370974 15.09% 46.29% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 203148367 16.72% 63.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 169783138 13.97% 76.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 132635579 10.92% 87.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 93723777 7.71% 95.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 37883178 3.12% 98.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 12361449 1.02% 99.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 3045427 0.25% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1244485983 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1215073364 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 746380 0.82% 0.82% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 24393 0.03% 0.85% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 0.85% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.85% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.85% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.85% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 0.85% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.85% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 0.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 0.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.85% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 55867065 61.34% 62.19% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 34441237 37.81% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 714606 0.82% 0.82% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 24380 0.03% 0.84% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 0.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 0.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 0.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 0.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.84% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 55143304 62.90% 63.75% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 31782308 36.25% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1129092447 45.68% 45.68% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 11228574 0.45% 46.14% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 46.14% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 46.14% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 46.14% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 46.14% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 46.14% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 46.14% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 46.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 46.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 46.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 46.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 46.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 46.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 46.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 46.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 46.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 46.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 46.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 46.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 1375289 0.06% 46.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 46.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 6876479 0.28% 46.47% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 5501982 0.22% 46.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 46.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 23586280 0.95% 47.65% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.65% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.65% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.65% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 837187213 33.87% 81.52% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 456845236 18.48% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1107294192 45.45% 45.45% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 11224034 0.46% 45.91% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 45.91% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 45.91% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 45.91% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 45.91% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 45.91% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 45.91% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 45.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 45.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 45.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 45.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 45.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 45.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 45.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 45.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 45.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 45.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 45.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 45.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 1375289 0.06% 45.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 45.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 6876476 0.28% 46.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 5502357 0.23% 46.47% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 46.47% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 23404551 0.96% 47.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.43% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 838357967 34.41% 81.84% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 442336083 18.16% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2471693501 # Type of FU issued -system.cpu.iq.rate 1.943803 # Inst issue rate -system.cpu.iq.fu_busy_cnt 91079075 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.036849 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 6158633993 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 3704145010 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 2281572785 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 127472092 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 87353789 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 58523777 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2496546302 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 66226274 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 80772254 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2436370950 # Type of FU issued +system.cpu.iq.rate 1.949510 # Inst issue rate +system.cpu.iq.fu_busy_cnt 87664598 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.035982 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 6066277406 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 3628118286 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 2252998417 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 122514311 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 82717236 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 56437909 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2460715459 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 63320089 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 84361835 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 340138947 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 4271 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 411099 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 228700241 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 341327109 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 8250 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 1428808 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 213208601 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 3 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 284 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 6 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 221 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 134506440 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 8643138 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 547079 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2844711818 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 10610498 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 971527729 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 505697139 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 23185 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 540297 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 2527 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 411099 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 34712988 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1840552 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 36553540 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 2395281486 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 793221583 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 76412015 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 127217578 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 13751124 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1562188 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2804340477 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 1409393 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 972715984 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 490205592 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 19935 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1558593 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 2526 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 1428808 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 32521161 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1512713 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 34033874 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 2362219907 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 792646926 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 74151043 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 14051 # number of nop insts executed -system.cpu.iew.exec_refs 1229345389 # number of memory reference insts executed -system.cpu.iew.exec_branches 327128098 # Number of branches executed -system.cpu.iew.exec_stores 436123806 # Number of stores executed -system.cpu.iew.exec_rate 1.883710 # Inst execution rate -system.cpu.iew.wb_sent 2368179118 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 2340096562 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1354502475 # num instructions producing a value -system.cpu.iew.wb_consumers 2541864992 # num instructions consuming a value +system.cpu.iew.exec_nop 12429 # number of nop insts executed +system.cpu.iew.exec_refs 1216288233 # number of memory reference insts executed +system.cpu.iew.exec_branches 322226431 # Number of branches executed +system.cpu.iew.exec_stores 423641307 # Number of stores executed +system.cpu.iew.exec_rate 1.890176 # Inst execution rate +system.cpu.iew.wb_sent 2335115057 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 2309436326 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1347701281 # num instructions producing a value +system.cpu.iew.wb_consumers 2523709653 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.840311 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.532877 # average fanout of values written-back +system.cpu.iew.wb_rate 1.847941 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.534016 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 959367728 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 22985 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 33197953 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1109979545 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.698540 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.378671 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 918995782 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 23078 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 30617997 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1087855788 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.733083 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.398277 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 463287159 41.74% 41.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 297974077 26.85% 68.58% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 91457957 8.24% 76.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 72253905 6.51% 83.33% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 45208298 4.07% 87.41% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 23225084 2.09% 89.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 15854658 1.43% 90.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 10141159 0.91% 91.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 90577248 8.16% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 447553397 41.14% 41.14% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 288592120 26.53% 67.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 95115403 8.74% 76.41% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 70228058 6.46% 82.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 46464545 4.27% 87.14% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 22184894 2.04% 89.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 15849617 1.46% 90.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 10984656 1.01% 91.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 90883098 8.35% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1109979545 # Number of insts commited each cycle -system.cpu.commit.committedInsts 1384389611 # Number of instructions committed -system.cpu.commit.committedOps 1885344363 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 1087855788 # Number of insts commited each cycle +system.cpu.commit.committedInsts 1384390076 # Number of instructions committed +system.cpu.commit.committedOps 1885344828 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 908385680 # Number of memory references committed -system.cpu.commit.loads 631388782 # Number of loads committed +system.cpu.commit.refs 908385866 # Number of memory references committed +system.cpu.commit.loads 631388875 # Number of loads committed system.cpu.commit.membars 9986 # Number of memory barriers committed -system.cpu.commit.branches 299635996 # Number of branches committed +system.cpu.commit.branches 299636089 # Number of branches committed system.cpu.commit.fp_insts 52289415 # Number of committed floating point instructions. -system.cpu.commit.int_insts 1653705271 # Number of committed integer instructions. +system.cpu.commit.int_insts 1653705643 # Number of committed integer instructions. system.cpu.commit.function_calls 41577833 # Number of function calls committed. -system.cpu.commit.bw_lim_events 90577248 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 90883098 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3864096043 # The number of ROB reads -system.cpu.rob.rob_writes 5823945497 # The number of ROB writes -system.cpu.timesIdled 351641 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 27090466 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 1384378595 # Number of Instructions Simulated -system.cpu.committedOps 1885333347 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 1384378595 # Number of Instructions Simulated -system.cpu.cpi 0.918518 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.918518 # CPI: Total CPI of All Threads -system.cpu.ipc 1.088710 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.088710 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 11907054979 # number of integer regfile reads -system.cpu.int_regfile_writes 2251695031 # number of integer regfile writes -system.cpu.fp_regfile_reads 70501707 # number of floating regfile reads -system.cpu.fp_regfile_writes 50326111 # number of floating regfile writes -system.cpu.misc_regfile_reads 3707678526 # number of misc regfile reads -system.cpu.misc_regfile_writes 13776104 # number of misc regfile writes -system.cpu.icache.replacements 23916 # number of replacements -system.cpu.icache.tagsinuse 1661.487549 # Cycle average of tags in use -system.cpu.icache.total_refs 346930644 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 25614 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 13544.571094 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 3801294955 # The number of ROB reads +system.cpu.rob.rob_writes 5735909866 # The number of ROB writes +system.cpu.timesIdled 353133 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 34661808 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 1384379060 # Number of Instructions Simulated +system.cpu.committedOps 1885333812 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 1384379060 # Number of Instructions Simulated +system.cpu.cpi 0.902741 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.902741 # CPI: Total CPI of All Threads +system.cpu.ipc 1.107738 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.107738 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 11770471325 # number of integer regfile reads +system.cpu.int_regfile_writes 2224868034 # number of integer regfile writes +system.cpu.fp_regfile_reads 68796296 # number of floating regfile reads +system.cpu.fp_regfile_writes 49549961 # number of floating regfile writes +system.cpu.misc_regfile_reads 3658188004 # number of misc regfile reads +system.cpu.misc_regfile_writes 13776290 # number of misc regfile writes +system.cpu.icache.replacements 22546 # number of replacements +system.cpu.icache.tagsinuse 1642.542137 # Cycle average of tags in use +system.cpu.icache.total_refs 333790581 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 24232 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 13774.784624 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1661.487549 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.811273 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.811273 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 346934721 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 346934721 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 346934721 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 346934721 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 346934721 # number of overall hits -system.cpu.icache.overall_hits::total 346934721 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 32652 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 32652 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 32652 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 32652 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 32652 # number of overall misses -system.cpu.icache.overall_misses::total 32652 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 492196499 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 492196499 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 492196499 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 492196499 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 492196499 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 492196499 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 346967373 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 346967373 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 346967373 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 346967373 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 346967373 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 346967373 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000094 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000094 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000094 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000094 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000094 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000094 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15074.007687 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 15074.007687 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 15074.007687 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 15074.007687 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 15074.007687 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 15074.007687 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 1459 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 1642.542137 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.802023 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.802023 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 333794637 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 333794637 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 333794637 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 333794637 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 333794637 # number of overall hits +system.cpu.icache.overall_hits::total 333794637 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 30836 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 30836 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 30836 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 30836 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 30836 # number of overall misses +system.cpu.icache.overall_misses::total 30836 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 469688998 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 469688998 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 469688998 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 469688998 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 469688998 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 469688998 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 333825473 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 333825473 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 333825473 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 333825473 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 333825473 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 333825473 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000092 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000092 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000092 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000092 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000092 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000092 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15231.839344 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 15231.839344 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 15231.839344 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 15231.839344 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 15231.839344 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 15231.839344 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 1009 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 35 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 29 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 41.685714 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 34.793103 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2714 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 2714 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 2714 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 2714 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 2714 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 2714 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 29938 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 29938 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 29938 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 29938 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 29938 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 29938 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 396628999 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 396628999 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 396628999 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 396628999 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 396628999 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 396628999 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2272 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 2272 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 2272 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 2272 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 2272 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 2272 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 28564 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 28564 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 28564 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 28564 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 28564 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 28564 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 379117998 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 379117998 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 379117998 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 379117998 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 379117998 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 379117998 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000086 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000086 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000086 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000086 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000086 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000086 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13248.346550 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13248.346550 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13248.346550 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 13248.346550 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13248.346550 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 13248.346550 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13272.580801 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13272.580801 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13272.580801 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 13272.580801 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13272.580801 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 13272.580801 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1533079 # number of replacements -system.cpu.dcache.tagsinuse 4094.602102 # Cycle average of tags in use -system.cpu.dcache.total_refs 974126836 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1537175 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 633.712385 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 342496000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4094.602102 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999659 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999659 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 697989238 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 697989238 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 276101323 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 276101323 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 12267 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 12267 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 11586 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 11586 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 974090561 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 974090561 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 974090561 # number of overall hits -system.cpu.dcache.overall_hits::total 974090561 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2001936 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2001936 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 834355 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 834355 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 2836291 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2836291 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2836291 # number of overall misses -system.cpu.dcache.overall_misses::total 2836291 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 68815075500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 68815075500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 39938491970 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 39938491970 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 99000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 99000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 108753567470 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 108753567470 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 108753567470 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 108753567470 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 699991174 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 699991174 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 276935678 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 276935678 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 12269 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 12269 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 11586 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 11586 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 976926852 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 976926852 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 976926852 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 976926852 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002860 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.002860 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003013 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.003013 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000163 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000163 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.002903 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.002903 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.002903 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.002903 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34374.263463 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 34374.263463 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47867.504803 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 47867.504803 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 49500 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 49500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 38343.585856 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 38343.585856 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 38343.585856 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 38343.585856 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 1801 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 752 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 60 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 85 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 30.016667 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 8.847059 # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 96247 # number of writebacks -system.cpu.dcache.writebacks::total 96247 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 537314 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 537314 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 757477 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 757477 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1294791 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1294791 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1294791 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1294791 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1464622 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1464622 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 76878 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 76878 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1541500 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1541500 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1541500 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1541500 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 36879858500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 36879858500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3477356000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3477356000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 40357214500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 40357214500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 40357214500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 40357214500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002092 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002092 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000278 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000278 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001578 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.001578 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001578 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.001578 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25180.461921 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25180.461921 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 45232.134031 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 45232.134031 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26180.482971 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 26180.482971 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26180.482971 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 26180.482971 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 442324 # number of replacements -system.cpu.l2cache.tagsinuse 32688.980204 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1110893 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 475069 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 2.338382 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 442193 # number of replacements +system.cpu.l2cache.tagsinuse 32688.524201 # Cycle average of tags in use +system.cpu.l2cache.total_refs 1109720 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 474940 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 2.336548 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 1305.388172 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 55.371770 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 31328.220262 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.039837 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.001690 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.956061 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.997589 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 23103 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 1058082 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1081185 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 96247 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 96247 # number of Writeback hits +system.cpu.l2cache.occ_blocks::writebacks 1294.928331 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 48.758922 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 31344.836948 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.039518 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.001488 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.956569 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.997575 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 21799 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 1058077 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1079876 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 96322 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 96322 # number of Writeback hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 3 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 3 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 6476 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 6476 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 23103 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1064558 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1087661 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 23103 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1064558 # number of overall hits -system.cpu.l2cache.overall_hits::total 1087661 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 2512 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 406540 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 409052 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 4321 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 4321 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 66078 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 66078 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 2512 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 472618 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 475130 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 2512 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 472618 # number of overall misses -system.cpu.l2cache.overall_misses::total 475130 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 131130500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 24833789000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 24964919500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3241668500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 3241668500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 131130500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 28075457500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 28206588000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 131130500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 28075457500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 28206588000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 25615 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1464622 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 1490237 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 96247 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 96247 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 4324 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 4324 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 72554 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 72554 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 25615 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1537176 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 1562791 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 25615 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1537176 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 1562791 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.098068 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.277573 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.274488 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.999306 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.999306 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.910742 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.910742 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.098068 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.307459 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.304027 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.098068 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.307459 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.304027 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52201.632166 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 61085.720962 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 61031.163520 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 49058.211508 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 49058.211508 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52201.632166 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59404.122357 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 59366.042978 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52201.632166 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59404.122357 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 59366.042978 # average overall miss latency +system.cpu.l2cache.ReadExReq_hits::cpu.data 6441 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 6441 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 21799 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 1064518 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 1086317 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 21799 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 1064518 # number of overall hits +system.cpu.l2cache.overall_hits::total 1086317 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 2433 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 406491 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 408924 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 4330 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 4330 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 66074 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 66074 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 2433 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 472565 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 474998 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 2433 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 472565 # number of overall misses +system.cpu.l2cache.overall_misses::total 474998 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 128014500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 25837930500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 25965945000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3242870000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 3242870000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 128014500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 29080800500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 29208815000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 128014500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 29080800500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 29208815000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 24232 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 1464568 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 1488800 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 96322 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 96322 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 4333 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 4333 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 72515 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 72515 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 24232 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1537083 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 1561315 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 24232 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1537083 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 1561315 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.100404 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.277550 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.274667 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.999308 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.999308 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.911177 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.911177 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.100404 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.307443 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.304229 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.100404 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.307443 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.304229 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52615.906289 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 63563.351956 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 63498.217273 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 49079.365560 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 49079.365560 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52615.906289 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 61538.202152 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 61492.501021 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52615.906289 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 61538.202152 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 61492.501021 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -816,67 +689,193 @@ system.cpu.l2cache.fast_writes 0 # nu system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks::writebacks 66098 # number of writebacks system.cpu.l2cache.writebacks::total 66098 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 3 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 22 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 25 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 3 # number of demand (read+write) MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 24 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.data 22 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 25 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 3 # number of overall MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 24 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 22 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 25 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2509 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 406518 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 409027 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 4321 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 4321 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66078 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 66078 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 2509 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 472596 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 475105 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 2509 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 472596 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 475105 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 99443391 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 19690336164 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 19789779555 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 43223820 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 43223820 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2389121519 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2389121519 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 99443391 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 22079457683 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 22178901074 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 99443391 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 22079457683 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 22178901074 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.097950 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.277558 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.274471 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.999306 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.999306 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.910742 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.910742 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.097950 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.307444 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.304011 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.097950 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.307444 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.304011 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39634.671582 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 48436.566558 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 48382.575123 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10003.198334 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10003.198334 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36156.080980 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36156.080980 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39634.671582 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 46719.518750 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 46682.104112 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39634.671582 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 46719.518750 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 46682.104112 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_hits::total 24 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2431 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 406469 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 408900 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 4330 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 4330 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66074 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 66074 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2431 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 472543 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 474974 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2431 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 472543 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 474974 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 97294812 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 20693796850 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20791091662 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 43304330 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 43304330 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2390499504 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2390499504 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 97294812 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 23084296354 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 23181591166 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 97294812 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 23084296354 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 23181591166 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.100322 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.277535 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.274651 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.999308 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.999308 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.911177 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.911177 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.100322 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.307428 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.304214 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.100322 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.307428 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.304214 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40022.547100 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 50911.131845 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 50846.396826 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36179.124981 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36179.124981 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40022.547100 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 48851.207941 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 48806.021311 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40022.547100 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 48851.207941 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 48806.021311 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.replacements 1532987 # number of replacements +system.cpu.dcache.tagsinuse 4094.606879 # Cycle average of tags in use +system.cpu.dcache.total_refs 970022641 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1537083 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 631.080196 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 335185000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4094.606879 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999660 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999660 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 693885026 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 693885026 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 276101075 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 276101075 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 11981 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 11981 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 11679 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 11679 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 969986101 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 969986101 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 969986101 # number of overall hits +system.cpu.dcache.overall_hits::total 969986101 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1953380 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1953380 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 834603 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 834603 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 2787983 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2787983 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2787983 # number of overall misses +system.cpu.dcache.overall_misses::total 2787983 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 67369161000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 67369161000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 39954942470 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 39954942470 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 199000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 199000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 107324103470 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 107324103470 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 107324103470 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 107324103470 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 695838406 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 695838406 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 276935678 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 276935678 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11984 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 11984 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 11679 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 11679 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 972774084 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 972774084 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 972774084 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 972774084 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002807 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.002807 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003014 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.003014 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000250 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000250 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.002866 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.002866 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.002866 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.002866 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34488.507612 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 34488.507612 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47872.991674 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 47872.991674 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 66333.333333 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 66333.333333 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 38495.250319 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 38495.250319 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 38495.250319 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 38495.250319 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 1740 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 681 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 55 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 87 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 31.636364 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 7.827586 # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 96322 # number of writebacks +system.cpu.dcache.writebacks::total 96322 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 488810 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 488810 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 757757 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 757757 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1246567 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1246567 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1246567 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1246567 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1464570 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1464570 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 76846 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 76846 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1541416 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1541416 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1541416 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1541416 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 37884239500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 37884239500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3478488500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3478488500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 41362728000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 41362728000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 41362728000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 41362728000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002105 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002105 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000277 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000277 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001585 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.001585 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001585 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.001585 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25867.141550 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25867.141550 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 45265.706738 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 45265.706738 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26834.240724 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 26834.240724 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26834.240724 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 26834.240724 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/config.ini index fc9577d62..00b189ec1 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/config.ini +++ b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/config.ini @@ -10,6 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a +clock=1000 init_param=0 kernel= load_addr_mask=1099511627775 @@ -29,7 +30,7 @@ system_port=system.membus.slave[0] [system.cpu] type=InOrderCPU -children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload +children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 RASSize=16 @@ -54,8 +55,6 @@ do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb fetchBuffSize=4 -functionTrace=false -functionTraceStart=0 function_trace=false function_trace_start=0 globalCtrBits=2 @@ -63,6 +62,7 @@ globalHistoryBits=13 globalPredictorSize=8192 instShiftAmt=2 interrupts=system.cpu.interrupts +isa=system.cpu.isa itb=system.cpu.itb localCtrBits=2 localHistoryBits=11 @@ -76,7 +76,6 @@ memBlockSize=64 multLatency=1 multRepeatRate=1 numThreads=1 -phase=0 predType=tournament profile=0 progress_interval=0 @@ -94,20 +93,22 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=2 is_top_level=true -latency=1000 max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=2 size=262144 subblock_size=0 system=system -tgts_per_mshr=5 +tgts_per_mshr=20 trace_addr=0 two_queue=false write_buffers=8 @@ -123,20 +124,22 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=2 is_top_level=true -latency=1000 max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=2 size=131072 subblock_size=0 system=system -tgts_per_mshr=5 +tgts_per_mshr=20 trace_addr=0 two_queue=false write_buffers=8 @@ -146,6 +149,9 @@ mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=AlphaInterrupts +[system.cpu.isa] +type=AlphaISA + [system.cpu.itb] type=AlphaTLB size=48 @@ -153,22 +159,24 @@ size=48 [system.cpu.l2cache] type=BaseCache addr_ranges=0:18446744073709551615 -assoc=2 +assoc=8 block_size=64 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=20 is_top_level=false -latency=10000 max_miss_count=0 -mshrs=10 +mshrs=20 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=20 size=2097152 subblock_size=0 system=system -tgts_per_mshr=5 +tgts_per_mshr=12 trace_addr=0 two_queue=false write_buffers=8 @@ -178,10 +186,10 @@ mem_side=system.membus.slave[1] [system.cpu.toL2Bus] type=CoherentBus block_size=64 -clock=1000 +clock=500 header_cycles=1 use_default_range=false -width=8 +width=32 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side @@ -191,12 +199,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=vortex lendian.raw -cwd=build/ALPHA/tests/fast/long/se/50.vortex/alpha/tru64/inorder-timing +cwd=build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/inorder-timing egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex +executable=/projects/pd/randd/dist/cpu2000/binaries/alpha/tru64/vortex gid=100 input=cin max_stack_size=67108864 @@ -214,18 +222,32 @@ clock=1000 header_cycles=1 use_default_range=false width=8 -master=system.physmem.port[0] +master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] -type=SimpleMemory +type=SimpleDRAM +addr_mapping=openmap +banks_per_rank=8 +clock=1000 conf_table_reported=false -file= in_addr_map=true -latency=30000 -latency_var=0 +lines_per_rowbuffer=64 +mem_sched_policy=fcfs null=false +page_policy=open range=0:134217727 +ranks_per_channel=2 +read_buffer_size=32 +tBURST=4000 +tCL=14000 +tRCD=14000 +tREFI=7800000 +tRFC=300000 +tRP=14000 +tWTR=1000 +write_buffer_size=32 +write_thresh_perc=70 zero=false port=system.membus.master[0] diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/simout b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/simout index e501186a7..2318eb90a 100755 --- a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/simout +++ b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/simout @@ -1,11 +1,11 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 2 2012 08:30:56 -gem5 started Jul 2 2012 09:54:39 -gem5 executing on zizzer -command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/50.vortex/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/fast/long/se/50.vortex/alpha/tru64/inorder-timing +gem5 compiled Oct 30 2012 11:02:14 +gem5 started Oct 30 2012 12:19:26 +gem5 executing on u200540-lin +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. -Exiting @ tick 47910283500 because target called exit() +Exiting @ tick 43266024500 because target called exit() diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt index e532ddba3..130fea357 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,64 +1,64 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.043596 # Number of seconds simulated -sim_ticks 43595903500 # Number of ticks simulated -final_tick 43595903500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.043266 # Number of seconds simulated +sim_ticks 43266024500 # Number of ticks simulated +final_tick 43266024500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 146921 # Simulator instruction rate (inst/s) -host_op_rate 146921 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 72505010 # Simulator tick rate (ticks/s) -host_mem_usage 252940 # Number of bytes of host memory used -host_seconds 601.28 # Real time elapsed on the host +host_inst_rate 113775 # Simulator instruction rate (inst/s) +host_op_rate 113775 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 55722813 # Simulator tick rate (ticks/s) +host_mem_usage 252752 # Number of bytes of host memory used +host_seconds 776.45 # Real time elapsed on the host sim_insts 88340673 # Number of instructions simulated sim_ops 88340673 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 454912 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10138304 # Number of bytes read from this memory -system.physmem.bytes_read::total 10593216 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 454912 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 454912 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu.inst 454720 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10138368 # Number of bytes read from this memory +system.physmem.bytes_read::total 10593088 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 454720 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 454720 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 7295808 # Number of bytes written to this memory system.physmem.bytes_written::total 7295808 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 7108 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 158411 # Number of read requests responded to by this memory -system.physmem.num_reads::total 165519 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 7105 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 158412 # Number of read requests responded to by this memory +system.physmem.num_reads::total 165517 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 113997 # Number of write requests responded to by this memory system.physmem.num_writes::total 113997 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 10434742 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 232551758 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 242986500 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 10434742 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 10434742 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 167350770 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 167350770 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 167350770 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 10434742 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 232551758 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 410337269 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 165519 # Total number of read requests seen +system.physmem.bw_read::cpu.inst 10509863 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 234326313 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 244836176 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 10509863 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 10509863 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 168626725 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 168626725 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 168626725 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 10509863 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 234326313 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 413462901 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 165517 # Total number of read requests seen system.physmem.writeReqs 113997 # Total number of write requests seen -system.physmem.cpureqs 279516 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 10593216 # Total number of bytes read from memory +system.physmem.cpureqs 279514 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 10593088 # Total number of bytes read from memory system.physmem.bytesWritten 7295808 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 10593216 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 10593088 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 7295808 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 2 # Number of read reqs serviced by write Q +system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 10672 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 10220 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 10695 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 10332 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 10519 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 10219 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 10232 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 10665 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 10222 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 10694 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 10333 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 10520 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 10218 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 10233 # Track reads on a per bank basis system.physmem.perBankRdReqs::7 9969 # Track reads on a per bank basis system.physmem.perBankRdReqs::8 10371 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 10218 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 10217 # Track reads on a per bank basis system.physmem.perBankRdReqs::10 10609 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 10332 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 10334 # Track reads on a per bank basis system.physmem.perBankRdReqs::12 10345 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 9920 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 10624 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 10240 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 9919 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 10626 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 10242 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 7408 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 6899 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 7248 # Track writes on a per bank basis @@ -77,14 +77,14 @@ system.physmem.perBankWrReqs::14 7374 # Tr system.physmem.perBankWrReqs::15 7193 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 43595883500 # Total gap between requests +system.physmem.totGap 43266004500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 165519 # Categorize read packet sizes +system.physmem.readPktSize::6 165517 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -105,10 +105,10 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 71904 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 70293 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 17020 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 6297 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 71923 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 70247 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 17074 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 6270 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -138,13 +138,13 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 3115 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 4887 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4930 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 3114 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 4875 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4923 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 4950 # What write queue length does an incoming req see system.physmem.wrQLenPdf::4 4954 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 4955 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 4956 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 4956 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 4957 # What write queue length does an incoming req see system.physmem.wrQLenPdf::7 4957 # What write queue length does an incoming req see system.physmem.wrQLenPdf::8 4957 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 4956 # What write queue length does an incoming req see @@ -161,57 +161,57 @@ system.physmem.wrQLenPdf::19 4956 # Wh system.physmem.wrQLenPdf::20 4956 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 4956 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 4956 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 1842 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 70 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 27 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 1843 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 82 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 34 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 7 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 9323896604 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 11720942604 # Sum of mem lat for all requests +system.physmem.totQLat 9309879146 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 11706015146 # Sum of mem lat for all requests system.physmem.totBusLat 662068000 # Total cycles spent in databus access -system.physmem.totBankLat 1734978000 # Total cycles spent in bank access -system.physmem.avgQLat 56331.96 # Average queueing delay per request -system.physmem.avgBankLat 10482.17 # Average bank access latency per request +system.physmem.totBankLat 1734068000 # Total cycles spent in bank access +system.physmem.avgQLat 56247.27 # Average queueing delay per request +system.physmem.avgBankLat 10476.68 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 70814.13 # Average memory access latency -system.physmem.avgRdBW 242.99 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 167.35 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 242.99 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 167.35 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 70723.94 # Average memory access latency +system.physmem.avgRdBW 244.84 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 168.63 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 244.84 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 168.63 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 2.56 # Data bus utilization in percentage +system.physmem.busUtil 2.58 # Data bus utilization in percentage system.physmem.avgRdQLen 0.27 # Average read queue length over time -system.physmem.avgWrQLen 10.36 # Average write queue length over time -system.physmem.readRowHits 151893 # Number of row buffer hits during reads -system.physmem.writeRowHits 41557 # Number of row buffer hits during writes -system.physmem.readRowHitRate 91.77 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 36.45 # Row buffer hit rate for writes -system.physmem.avgGap 155969.19 # Average gap between requests +system.physmem.avgWrQLen 10.35 # Average write queue length over time +system.physmem.readRowHits 151965 # Number of row buffer hits during reads +system.physmem.writeRowHits 41713 # Number of row buffer hits during writes +system.physmem.readRowHitRate 91.81 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 36.59 # Row buffer hit rate for writes +system.physmem.avgGap 154790.12 # Average gap between requests system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 20277538 # DTB read hits +system.cpu.dtb.read_hits 20277550 # DTB read hits system.cpu.dtb.read_misses 90148 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 20367686 # DTB read accesses -system.cpu.dtb.write_hits 14728672 # DTB write hits +system.cpu.dtb.read_accesses 20367698 # DTB read accesses +system.cpu.dtb.write_hits 14728696 # DTB write hits system.cpu.dtb.write_misses 7252 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 14735924 # DTB write accesses -system.cpu.dtb.data_hits 35006210 # DTB hits +system.cpu.dtb.write_accesses 14735948 # DTB write accesses +system.cpu.dtb.data_hits 35006246 # DTB hits system.cpu.dtb.data_misses 97400 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 35103610 # DTB accesses -system.cpu.itb.fetch_hits 12476759 # ITB hits -system.cpu.itb.fetch_misses 12943 # ITB misses +system.cpu.dtb.data_accesses 35103646 # DTB accesses +system.cpu.itb.fetch_hits 12367278 # ITB hits +system.cpu.itb.fetch_misses 11044 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 12489702 # ITB accesses +system.cpu.itb.fetch_accesses 12378322 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -225,42 +225,42 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4583 # Number of system calls -system.cpu.numCycles 87191808 # number of cpu cycles simulated +system.cpu.numCycles 86532050 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.branch_predictor.lookups 18827150 # Number of BP lookups -system.cpu.branch_predictor.condPredicted 12439421 # Number of conditional branches predicted -system.cpu.branch_predictor.condIncorrect 5024981 # Number of conditional branches incorrect -system.cpu.branch_predictor.BTBLookups 16201522 # Number of BTB lookups -system.cpu.branch_predictor.BTBHits 5047120 # Number of BTB hits -system.cpu.branch_predictor.usedRAS 1660945 # Number of times the RAS was used to get a target. +system.cpu.branch_predictor.lookups 18742312 # Number of BP lookups +system.cpu.branch_predictor.condPredicted 12317439 # Number of conditional branches predicted +system.cpu.branch_predictor.condIncorrect 4774431 # Number of conditional branches incorrect +system.cpu.branch_predictor.BTBLookups 15498318 # Number of BTB lookups +system.cpu.branch_predictor.BTBHits 4661486 # Number of BTB hits +system.cpu.branch_predictor.usedRAS 1660962 # Number of times the RAS was used to get a target. system.cpu.branch_predictor.RASInCorrect 1030 # Number of incorrect RAS predictions. -system.cpu.branch_predictor.BTBHitPct 31.152135 # BTB Hit Percentage -system.cpu.branch_predictor.predictedTaken 8476186 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 10350964 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 74333119 # Number of Reads from Int. Register File +system.cpu.branch_predictor.BTBHitPct 30.077367 # BTB Hit Percentage +system.cpu.branch_predictor.predictedTaken 8071751 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 10670561 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 74169472 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 52319250 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 126652369 # Total Accesses (Read+Write) to the Int. Register File -system.cpu.regfile_manager.floatRegFileReads 65259 # Number of Reads from FP Register File +system.cpu.regfile_manager.intRegFileAccesses 126488722 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.floatRegFileReads 66053 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 227630 # Number of Writes to FP Register File -system.cpu.regfile_manager.floatRegFileAccesses 292889 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 14121677 # Number of Registers Read Through Forwarding Logic -system.cpu.agen_unit.agens 35064639 # Number of Address Generations -system.cpu.execution_unit.predictedTakenIncorrect 4680318 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.execution_unit.predictedNotTakenIncorrect 234163 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.execution_unit.mispredicted 4914481 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.predicted 8857790 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.mispredictPct 35.683882 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.executions 44776328 # Number of Instructions Executed. +system.cpu.regfile_manager.floatRegFileAccesses 293683 # Total Accesses (Read+Write) to the FP Register File +system.cpu.regfile_manager.regForwards 14165611 # Number of Registers Read Through Forwarding Logic +system.cpu.agen_unit.agens 35060577 # Number of Address Generations +system.cpu.execution_unit.predictedTakenIncorrect 4447125 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.execution_unit.predictedNotTakenIncorrect 216806 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.execution_unit.mispredicted 4663931 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.predicted 9108659 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.mispredictPct 33.863863 # Percentage of Incorrect Branches Predicts +system.cpu.execution_unit.executions 44777842 # Number of Instructions Executed. system.cpu.mult_div_unit.multiplies 41107 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 77836216 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 77186042 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 230753 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 16919077 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 70272731 # Number of cycles cpu stages are processed. -system.cpu.activity 80.595566 # Percentage of cycles cpu is active +system.cpu.timesIdled 230961 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 16958681 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 69573369 # Number of cycles cpu stages are processed. +system.cpu.activity 80.401850 # Percentage of cycles cpu is active system.cpu.comLoads 20276638 # Number of Load instructions committed system.cpu.comStores 14613377 # Number of Store instructions committed system.cpu.comBranches 13754477 # Number of Branches instructions committed @@ -272,302 +272,194 @@ system.cpu.committedInsts 88340673 # Nu system.cpu.committedOps 88340673 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 88340673 # Number of Instructions committed (Total) -system.cpu.cpi 0.986995 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 0.979527 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 0.986995 # CPI: Total CPI of All Threads -system.cpu.ipc 1.013176 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 0.979527 # CPI: Total CPI of All Threads +system.cpu.ipc 1.020901 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 1.013176 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 33768817 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 53422991 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 61.270654 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 44539685 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 42652123 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 48.917581 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 44072021 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 43119787 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 49.453943 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 65076368 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 22115440 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 25.364126 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 41085926 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 46105882 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 52.878686 # Percentage of cycles stage was utilized (processing insts). -system.cpu.icache.replacements 85196 # number of replacements -system.cpu.icache.tagsinuse 1908.917223 # Cycle average of tags in use -system.cpu.icache.total_refs 12358549 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 87242 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 141.658249 # Average number of references to valid blocks. +system.cpu.ipc_total 1.020901 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 33881250 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 52650800 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 60.845432 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 44079875 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 42452175 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 49.059481 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 43502532 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 43029518 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 49.726683 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 64419596 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 22112454 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 25.554062 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 40482959 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 46049091 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 53.216226 # Percentage of cycles stage was utilized (processing insts). +system.cpu.icache.replacements 84282 # number of replacements +system.cpu.icache.tagsinuse 1908.908494 # Cycle average of tags in use +system.cpu.icache.total_refs 12250113 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 86328 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 141.901967 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1908.917223 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.932088 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.932088 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 12358549 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 12358549 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 12358549 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 12358549 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 12358549 # number of overall hits -system.cpu.icache.overall_hits::total 12358549 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 118203 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 118203 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 118203 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 118203 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 118203 # number of overall misses -system.cpu.icache.overall_misses::total 118203 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 1846898500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 1846898500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 1846898500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 1846898500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 1846898500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 1846898500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 12476752 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 12476752 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 12476752 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 12476752 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 12476752 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 12476752 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.009474 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.009474 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.009474 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.009474 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.009474 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.009474 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15624.802247 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 15624.802247 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 15624.802247 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 15624.802247 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 15624.802247 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 15624.802247 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 306 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 1908.908494 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.932084 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.932084 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 12250113 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 12250113 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 12250113 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 12250113 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 12250113 # number of overall hits +system.cpu.icache.overall_hits::total 12250113 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 117156 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 117156 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 117156 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 117156 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 117156 # number of overall misses +system.cpu.icache.overall_misses::total 117156 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 1822166500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 1822166500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 1822166500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 1822166500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 1822166500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 1822166500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 12367269 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 12367269 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 12367269 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 12367269 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 12367269 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 12367269 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.009473 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.009473 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.009473 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.009473 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.009473 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.009473 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15553.334870 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 15553.334870 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 15553.334870 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 15553.334870 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 15553.334870 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 15553.334870 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 309 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 26 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 24 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 19 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 4 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 12.750000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 16.263158 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets 6.500000 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 30961 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 30961 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 30961 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 30961 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 30961 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 30961 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 87242 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 87242 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 87242 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 87242 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 87242 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 87242 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1292347500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 1292347500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1292347500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 1292347500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1292347500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 1292347500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006992 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006992 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006992 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.006992 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006992 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.006992 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14813.363976 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14813.363976 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14813.363976 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 14813.363976 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14813.363976 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 14813.363976 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 30828 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 30828 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 30828 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 30828 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 30828 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 30828 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 86328 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 86328 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 86328 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 86328 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 86328 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 86328 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1279244500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 1279244500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1279244500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 1279244500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1279244500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 1279244500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006980 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006980 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006980 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.006980 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006980 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.006980 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14818.419285 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14818.419285 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14818.419285 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 14818.419285 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14818.419285 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 14818.419285 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 200251 # number of replacements -system.cpu.dcache.tagsinuse 4078.664341 # Cycle average of tags in use -system.cpu.dcache.total_refs 33754987 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 204347 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 165.184647 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 249990000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4078.664341 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.995768 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.995768 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 20180268 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 20180268 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 13574719 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 13574719 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 33754987 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 33754987 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 33754987 # number of overall hits -system.cpu.dcache.overall_hits::total 33754987 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 96370 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 96370 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1038658 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1038658 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 1135028 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1135028 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1135028 # number of overall misses -system.cpu.dcache.overall_misses::total 1135028 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 3954988500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 3954988500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 91520281000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 91520281000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 95475269500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 95475269500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 95475269500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 95475269500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 20276638 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 20276638 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 34890015 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 34890015 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 34890015 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 34890015 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004753 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.004753 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.071076 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.071076 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.032532 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.032532 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.032532 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.032532 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 41039.623327 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 41039.623327 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 88113.971105 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 88113.971105 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 84117.105041 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 84117.105041 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 84117.105041 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 84117.105041 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 6175044 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 397 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 116295 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 53.098104 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 397 # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 168353 # number of writebacks -system.cpu.dcache.writebacks::total 168353 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 35603 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 35603 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 895078 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 895078 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 930681 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 930681 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 930681 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 930681 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 60767 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 60767 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143580 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 143580 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 204347 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 204347 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 204347 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 204347 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1939972500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 1939972500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 14546837500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 14546837500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16486810000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 16486810000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16486810000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 16486810000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002997 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002997 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009825 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009825 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005857 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.005857 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005857 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.005857 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 31924.770023 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 31924.770023 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 101315.207550 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 101315.207550 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 80680.460198 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 80680.460198 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 80680.460198 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 80680.460198 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 131596 # number of replacements -system.cpu.l2cache.tagsinuse 30981.821005 # Cycle average of tags in use -system.cpu.l2cache.total_refs 152256 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 163654 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.930353 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 131593 # number of replacements +system.cpu.l2cache.tagsinuse 30981.522130 # Cycle average of tags in use +system.cpu.l2cache.total_refs 151339 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 163652 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.924761 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 27273.690706 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 2026.855781 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 1681.274518 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.832327 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.061855 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.051308 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.945490 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 80134 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 33057 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 113191 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 168353 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 168353 # number of Writeback hits +system.cpu.l2cache.occ_blocks::writebacks 27280.254395 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 2018.521657 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 1682.746078 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.832527 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.061600 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.051353 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.945481 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 79223 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 33054 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 112277 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 168350 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 168350 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits::cpu.data 12879 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 12879 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 80134 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 45936 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 126070 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 80134 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 45936 # number of overall hits -system.cpu.l2cache.overall_hits::total 126070 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 7108 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 27520 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 34628 # number of ReadReq misses +system.cpu.l2cache.demand_hits::cpu.inst 79223 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 45933 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 125156 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 79223 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 45933 # number of overall hits +system.cpu.l2cache.overall_hits::total 125156 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 7105 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 27521 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 34626 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 130891 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 130891 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 7108 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 158411 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 165519 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 7108 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 158411 # number of overall misses -system.cpu.l2cache.overall_misses::total 165519 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 400938500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1545176500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 1946115000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 14274056000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 14274056000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 400938500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 15819232500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 16220171000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 400938500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 15819232500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 16220171000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 87242 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 60577 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 147819 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 168353 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 168353 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.demand_misses::cpu.inst 7105 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 158412 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 165517 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 7105 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 158412 # number of overall misses +system.cpu.l2cache.overall_misses::total 165517 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 397918500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1540033500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 1937952000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 14268456500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 14268456500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 397918500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 15808490000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 16206408500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 397918500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 15808490000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 16206408500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 86328 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 60575 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 146903 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 168350 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 168350 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 143770 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 143770 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 87242 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 204347 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 291589 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 87242 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 204347 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 291589 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.081475 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.454298 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.234259 # miss rate for ReadReq accesses +system.cpu.l2cache.demand_accesses::cpu.inst 86328 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 204345 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 290673 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 86328 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 204345 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 290673 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.082302 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.454329 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.235707 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.910419 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.910419 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.081475 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.775206 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.567645 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.081475 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.775206 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.567645 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 56406.654474 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 56147.401890 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 56200.617997 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 109052.998296 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 109052.998296 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 56406.654474 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 99861.957187 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 97995.825253 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 56406.654474 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 99861.957187 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 97995.825253 # average overall miss latency +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.082302 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.775218 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.569427 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.082302 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.775218 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.569427 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 56005.418719 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 55958.486247 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 55968.116444 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 109010.218426 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 109010.218426 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 56005.418719 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 99793.513118 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 97913.860812 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 56005.418719 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 99793.513118 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 97913.860812 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -578,50 +470,158 @@ system.cpu.l2cache.fast_writes 0 # nu system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks::writebacks 113997 # number of writebacks system.cpu.l2cache.writebacks::total 113997 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 7108 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 27520 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 34628 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 7105 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 27521 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 34626 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 130891 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 130891 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 7108 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 158411 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 165519 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 7108 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 158411 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 165519 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 310665087 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1192490455 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1503155542 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 12652907225 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 12652907225 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 310665087 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 13845397680 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 14156062767 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 310665087 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 13845397680 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 14156062767 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.081475 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.454298 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.234259 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 7105 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 158412 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 165517 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 7105 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 158412 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 165517 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 307703601 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1187367459 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1495071060 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 12647339647 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 12647339647 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 307703601 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 13834707106 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 14142410707 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 307703601 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 13834707106 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 14142410707 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.082302 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.454329 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.235707 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.910419 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.910419 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.081475 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.775206 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.567645 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.081475 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.775206 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.567645 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 43706.399409 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 43331.775254 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 43408.673386 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 96667.511326 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 96667.511326 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 43706.399409 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 87401.744071 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 85525.303844 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 43706.399409 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 87401.744071 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 85525.303844 # average overall mshr miss latency +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.082302 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.775218 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.569427 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.082302 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.775218 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.569427 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 43308.036735 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 43144.052142 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 43177.700572 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 96624.975338 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 96624.975338 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 43308.036735 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 87333.706449 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 85443.855960 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 43308.036735 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 87333.706449 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 85443.855960 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.replacements 200249 # number of replacements +system.cpu.dcache.tagsinuse 4078.683111 # Cycle average of tags in use +system.cpu.dcache.total_refs 33755002 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 204345 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 165.186337 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 248488000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4078.683111 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.995772 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.995772 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 20180271 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 20180271 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 13574731 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 13574731 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 33755002 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 33755002 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 33755002 # number of overall hits +system.cpu.dcache.overall_hits::total 33755002 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 96367 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 96367 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1038646 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1038646 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 1135013 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1135013 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1135013 # number of overall misses +system.cpu.dcache.overall_misses::total 1135013 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 3942448000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 3942448000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 91414151500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 91414151500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 95356599500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 95356599500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 95356599500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 95356599500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 20276638 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 20276638 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 14613377 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 34890015 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 34890015 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 34890015 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 34890015 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004753 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.004753 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.071075 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.071075 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.032531 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.032531 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.032531 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.032531 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 40910.768209 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 40910.768209 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 88012.808503 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 88012.808503 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 84013.662839 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 84013.662839 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 84013.662839 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 84013.662839 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 6187652 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 65 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 116324 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 53.193253 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 65 # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 168350 # number of writebacks +system.cpu.dcache.writebacks::total 168350 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 35602 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 35602 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 895066 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 895066 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 930668 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 930668 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 930668 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 930668 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 60765 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 60765 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143580 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 143580 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 204345 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 204345 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 204345 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 204345 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1934793000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 1934793000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 14541156500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 14541156500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16475949500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 16475949500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16475949500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 16475949500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002997 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002997 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009825 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009825 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005857 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.005857 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005857 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.005857 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 31840.582572 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 31840.582572 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 101275.640758 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 101275.640758 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 80628.101984 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 80628.101984 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 80628.101984 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 80628.101984 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini index 0698ab8df..06d858804 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini @@ -10,6 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a +clock=1000 init_param=0 kernel= load_addr_mask=1099511627775 @@ -29,7 +30,7 @@ system_port=system.membus.slave[0] [system.cpu] type=DerivO3CPU -children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload +children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -77,6 +78,7 @@ iewToFetchDelay=1 iewToRenameDelay=1 instShiftAmt=2 interrupts=system.cpu.interrupts +isa=system.cpu.isa issueToExecuteDelay=1 issueWidth=8 itb=system.cpu.itb @@ -95,7 +97,6 @@ numPhysIntRegs=256 numROBEntries=192 numRobs=1 numThreads=1 -phase=0 predType=tournament profile=0 progress_interval=0 @@ -129,16 +130,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=2 is_top_level=true -latency=1000 max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=2 size=262144 subblock_size=0 system=system @@ -421,16 +424,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=2 is_top_level=true -latency=1000 max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=2 size=131072 subblock_size=0 system=system @@ -444,6 +449,9 @@ mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=AlphaInterrupts +[system.cpu.isa] +type=AlphaISA + [system.cpu.itb] type=AlphaTLB size=48 @@ -451,22 +459,24 @@ size=48 [system.cpu.l2cache] type=BaseCache addr_ranges=0:18446744073709551615 -assoc=2 +assoc=8 block_size=64 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=20 is_top_level=false -latency=1000 max_miss_count=0 -mshrs=10 +mshrs=20 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=20 size=2097152 subblock_size=0 system=system -tgts_per_mshr=5 +tgts_per_mshr=12 trace_addr=0 two_queue=false write_buffers=8 @@ -476,10 +486,10 @@ mem_side=system.membus.slave[1] [system.cpu.toL2Bus] type=CoherentBus block_size=64 -clock=1000 +clock=500 header_cycles=1 use_default_range=false -width=8 +width=32 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side @@ -489,12 +499,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=vortex lendian.raw -cwd=build/ALPHA/tests/fast/long/se/50.vortex/alpha/tru64/o3-timing +cwd=build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/o3-timing egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex +executable=/projects/pd/randd/dist/cpu2000/binaries/alpha/tru64/vortex gid=100 input=cin max_stack_size=67108864 @@ -512,18 +522,32 @@ clock=1000 header_cycles=1 use_default_range=false width=8 -master=system.physmem.port[0] +master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] -type=SimpleMemory +type=SimpleDRAM +addr_mapping=openmap +banks_per_rank=8 +clock=1000 conf_table_reported=false -file= in_addr_map=true -latency=30000 -latency_var=0 +lines_per_rowbuffer=64 +mem_sched_policy=fcfs null=false +page_policy=open range=0:134217727 +ranks_per_channel=2 +read_buffer_size=32 +tBURST=4000 +tCL=14000 +tRCD=14000 +tREFI=7800000 +tRFC=300000 +tRP=14000 +tWTR=1000 +write_buffer_size=32 +write_thresh_perc=70 zero=false port=system.membus.master[0] diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simout b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simout index 3d5324180..8fd1a4d9e 100755 --- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simout @@ -1,11 +1,11 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 2 2012 08:30:56 -gem5 started Jul 2 2012 10:05:33 -gem5 executing on zizzer -command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/50.vortex/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/fast/long/se/50.vortex/alpha/tru64/o3-timing +gem5 compiled Oct 30 2012 11:02:14 +gem5 started Oct 30 2012 12:32:34 +gem5 executing on u200540-lin +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. -Exiting @ tick 21619648000 because target called exit() +Exiting @ tick 24414646000 because target called exit() diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt index 04dfac9bb..c5e407e29 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt @@ -1,90 +1,90 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.024767 # Number of seconds simulated -sim_ticks 24766869000 # Number of ticks simulated -final_tick 24766869000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.024415 # Number of seconds simulated +sim_ticks 24414646000 # Number of ticks simulated +final_tick 24414646000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 162319 # Simulator instruction rate (inst/s) -host_op_rate 162319 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 50509376 # Simulator tick rate (ticks/s) -host_mem_usage 253968 # Number of bytes of host memory used -host_seconds 490.34 # Real time elapsed on the host +host_inst_rate 171645 # Simulator instruction rate (inst/s) +host_op_rate 171645 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 52651835 # Simulator tick rate (ticks/s) +host_mem_usage 254848 # Number of bytes of host memory used +host_seconds 463.70 # Real time elapsed on the host sim_insts 79591756 # Number of instructions simulated sim_ops 79591756 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 491520 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10154752 # Number of bytes read from this memory -system.physmem.bytes_read::total 10646272 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 491520 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 491520 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu.inst 490368 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10153920 # Number of bytes read from this memory +system.physmem.bytes_read::total 10644288 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 490368 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 490368 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 7296960 # Number of bytes written to this memory system.physmem.bytes_written::total 7296960 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 7680 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 158668 # Number of read requests responded to by this memory -system.physmem.num_reads::total 166348 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 7662 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 158655 # Number of read requests responded to by this memory +system.physmem.num_reads::total 166317 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 114015 # Number of write requests responded to by this memory system.physmem.num_writes::total 114015 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 19845867 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 410013555 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 429859422 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 19845867 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 19845867 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 294625857 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 294625857 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 294625857 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 19845867 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 410013555 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 724485279 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 166348 # Total number of read requests seen +system.physmem.bw_read::cpu.inst 20084993 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 415894623 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 435979616 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 20084993 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 20084993 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 298876338 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 298876338 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 298876338 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 20084993 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 415894623 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 734855955 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 166317 # Total number of read requests seen system.physmem.writeReqs 114015 # Total number of write requests seen -system.physmem.cpureqs 280363 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 10646272 # Total number of bytes read from memory +system.physmem.cpureqs 280332 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 10644288 # Total number of bytes read from memory system.physmem.bytesWritten 7296960 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 10646272 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 10644288 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 7296960 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 2 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 10739 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 10314 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 10735 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 10372 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 10586 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 10283 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 10737 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 10315 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 10736 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 10379 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 10583 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 10274 # Track reads on a per bank basis system.physmem.perBankRdReqs::6 10277 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 10016 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 10446 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 10273 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 10645 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 10379 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 10383 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 9952 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 10691 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 10255 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 7408 # Track writes on a per bank basis +system.physmem.perBankRdReqs::7 10017 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 10445 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 10266 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 10643 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 10374 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 10376 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 9953 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 10688 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 10252 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 7409 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 6902 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 7249 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 6952 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 7298 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 7042 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 7150 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 6839 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 7207 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 6885 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 7248 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 6953 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 7299 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 7041 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 7149 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 6837 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 7208 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 6884 # Track writes on a per bank basis system.physmem.perBankWrReqs::10 7381 # Track writes on a per bank basis system.physmem.perBankWrReqs::11 7081 # Track writes on a per bank basis system.physmem.perBankWrReqs::12 7120 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 6935 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 7375 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 6936 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 7376 # Track writes on a per bank basis system.physmem.perBankWrReqs::15 7191 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 24766835500 # Total gap between requests +system.physmem.totGap 24414612500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 166348 # Categorize read packet sizes +system.physmem.readPktSize::6 166317 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -105,11 +105,11 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 70675 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 64436 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 24903 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 6313 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 18 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 70693 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 64431 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 24801 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 6372 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 17 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -138,14 +138,14 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 3959 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 4862 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4939 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 3897 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 4853 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4936 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 4949 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 4954 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 4955 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 4956 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 4956 # What write queue length does an incoming req see system.physmem.wrQLenPdf::6 4956 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 4957 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 4956 # What write queue length does an incoming req see system.physmem.wrQLenPdf::8 4957 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 4957 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 4957 # What write queue length does an incoming req see @@ -161,57 +161,57 @@ system.physmem.wrQLenPdf::19 4957 # Wh system.physmem.wrQLenPdf::20 4957 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 4957 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 4957 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 999 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 96 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 1061 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 22 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 9402171924 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 11754135924 # Sum of mem lat for all requests -system.physmem.totBusLat 665384000 # Total cycles spent in databus access -system.physmem.totBankLat 1686580000 # Total cycles spent in bank access -system.physmem.avgQLat 56521.78 # Average queueing delay per request -system.physmem.avgBankLat 10138.99 # Average bank access latency per request +system.physmem.totQLat 9394568799 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 11745778799 # Sum of mem lat for all requests +system.physmem.totBusLat 665260000 # Total cycles spent in databus access +system.physmem.totBankLat 1685950000 # Total cycles spent in bank access +system.physmem.avgQLat 56486.60 # Average queueing delay per request +system.physmem.avgBankLat 10137.09 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 70660.77 # Average memory access latency -system.physmem.avgRdBW 429.86 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 294.63 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 429.86 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 294.63 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 70623.69 # Average memory access latency +system.physmem.avgRdBW 435.98 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 298.88 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 435.98 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 298.88 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 4.53 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.47 # Average read queue length over time -system.physmem.avgWrQLen 9.66 # Average write queue length over time -system.physmem.readRowHits 152267 # Number of row buffer hits during reads -system.physmem.writeRowHits 40679 # Number of row buffer hits during writes -system.physmem.readRowHitRate 91.54 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 35.68 # Row buffer hit rate for writes -system.physmem.avgGap 88338.46 # Average gap between requests +system.physmem.busUtil 4.59 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.48 # Average read queue length over time +system.physmem.avgWrQLen 10.01 # Average write queue length over time +system.physmem.readRowHits 152275 # Number of row buffer hits during reads +system.physmem.writeRowHits 40821 # Number of row buffer hits during writes +system.physmem.readRowHitRate 91.56 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 35.80 # Row buffer hit rate for writes +system.physmem.avgGap 87091.78 # Average gap between requests system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 22524754 # DTB read hits -system.cpu.dtb.read_misses 221109 # DTB read misses -system.cpu.dtb.read_acv 49 # DTB read access violations -system.cpu.dtb.read_accesses 22745863 # DTB read accesses -system.cpu.dtb.write_hits 15800982 # DTB write hits -system.cpu.dtb.write_misses 41722 # DTB write misses -system.cpu.dtb.write_acv 1 # DTB write access violations -system.cpu.dtb.write_accesses 15842704 # DTB write accesses -system.cpu.dtb.data_hits 38325736 # DTB hits -system.cpu.dtb.data_misses 262831 # DTB misses -system.cpu.dtb.data_acv 50 # DTB access violations -system.cpu.dtb.data_accesses 38588567 # DTB accesses -system.cpu.itb.fetch_hits 14187534 # ITB hits -system.cpu.itb.fetch_misses 37797 # ITB misses +system.cpu.dtb.read_hits 22403664 # DTB read hits +system.cpu.dtb.read_misses 220373 # DTB read misses +system.cpu.dtb.read_acv 50 # DTB read access violations +system.cpu.dtb.read_accesses 22624037 # DTB read accesses +system.cpu.dtb.write_hits 15711393 # DTB write hits +system.cpu.dtb.write_misses 41143 # DTB write misses +system.cpu.dtb.write_acv 4 # DTB write access violations +system.cpu.dtb.write_accesses 15752536 # DTB write accesses +system.cpu.dtb.data_hits 38115057 # DTB hits +system.cpu.dtb.data_misses 261516 # DTB misses +system.cpu.dtb.data_acv 54 # DTB access violations +system.cpu.dtb.data_accesses 38376573 # DTB accesses +system.cpu.itb.fetch_hits 13911095 # ITB hits +system.cpu.itb.fetch_misses 34570 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 14225331 # ITB accesses +system.cpu.itb.fetch_accesses 13945665 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -225,246 +225,246 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4583 # Number of system calls -system.cpu.numCycles 49533742 # number of cpu cycles simulated +system.cpu.numCycles 48829295 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 16746521 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 10800034 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 477053 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 12193904 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 7496910 # Number of BTB hits +system.cpu.BPredUnit.lookups 16536427 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 10675204 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 418905 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 11705282 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 7341882 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 2006546 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 45028 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 16102899 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 106919359 # Number of instructions fetch has processed -system.cpu.fetch.Branches 16746521 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9503456 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 19851092 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2196928 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 6491501 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 8361 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 314458 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 32 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 14187534 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 227935 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 44359313 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.410302 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.133631 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1987114 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 42052 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 15791672 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 105370615 # Number of instructions fetch has processed +system.cpu.fetch.Branches 16536427 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9328996 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 19544366 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2001802 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 6569447 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 7667 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 313140 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 52 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 13911095 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 206120 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 43680847 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.412284 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.135635 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 24508221 55.25% 55.25% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1552927 3.50% 58.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1407762 3.17% 61.92% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1534147 3.46% 65.38% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 4200830 9.47% 74.85% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1874236 4.23% 79.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 688640 1.55% 80.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1098273 2.48% 83.11% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 7494277 16.89% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 24136481 55.26% 55.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1528556 3.50% 58.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1370450 3.14% 61.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1506920 3.45% 65.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 4142263 9.48% 74.83% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1846581 4.23% 79.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 675220 1.55% 80.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1067886 2.44% 83.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 7406490 16.96% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 44359313 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.338083 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.158516 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 17202144 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 6044851 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 18844952 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 783382 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1483984 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3808507 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 109388 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 105012446 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 304839 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1483984 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 17687031 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 3815602 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 84566 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 19093119 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 2195011 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 103566225 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 486 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2675 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 2071816 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 62457346 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 124882897 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 124424416 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 458481 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 43680847 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.338658 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.157938 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 16869436 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 6110909 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 18556945 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 793975 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1349582 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3748874 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 107098 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 103640564 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 305578 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1349582 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 17328003 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 3849727 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 84405 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 18840913 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 2228217 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 102377631 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 426 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2729 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 2099672 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 61646345 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 123373260 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 122920505 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 452755 # Number of floating rename lookups system.cpu.rename.CommittedMaps 52546881 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 9910465 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 5561 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 5559 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 4548155 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 23430190 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 16410014 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1178549 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 390985 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 91582200 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 5227 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 89129103 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 121099 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 11405338 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 5024468 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 644 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 44359313 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.009253 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.109781 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 9099464 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 5536 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 5534 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 4609870 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 23237420 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 16278692 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1191956 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 452268 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 90762555 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 5288 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 88451556 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 99102 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 10723978 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 4670719 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 705 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 43680847 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.024951 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.111086 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 15871640 35.78% 35.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 6995929 15.77% 51.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 5623158 12.68% 64.23% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 4788485 10.79% 75.02% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4723434 10.65% 85.67% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2673880 6.03% 91.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1944632 4.38% 96.08% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1314765 2.96% 99.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 423390 0.95% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 15440168 35.35% 35.35% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 6886071 15.76% 51.11% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 5612203 12.85% 63.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 4740584 10.85% 74.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4695591 10.75% 85.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2649897 6.07% 91.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1923598 4.40% 96.03% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1315990 3.01% 99.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 416745 0.95% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 44359313 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 43680847 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 127127 6.74% 6.74% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 6.74% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 6.74% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.74% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.74% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.74% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 6.74% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.74% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 6.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 6.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.74% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 794266 42.09% 48.82% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 965741 51.18% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 126167 6.80% 6.80% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 6.80% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 6.80% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.80% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.80% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.80% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 6.80% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.80% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 6.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 6.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.80% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 781555 42.12% 48.92% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 947649 51.08% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 49762830 55.83% 55.83% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 43850 0.05% 55.88% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 55.88% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 121597 0.14% 56.02% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 88 0.00% 56.02% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 121881 0.14% 56.15% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 60 0.00% 56.15% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 38947 0.04% 56.20% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.20% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 23025644 25.83% 82.03% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 16014206 17.97% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 49366923 55.81% 55.81% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 43857 0.05% 55.86% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 55.86% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 121501 0.14% 56.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 87 0.00% 56.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 121281 0.14% 56.14% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 51 0.00% 56.14% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 38946 0.04% 56.18% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.18% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 22854121 25.84% 82.02% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 15904789 17.98% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 89129103 # Type of FU issued -system.cpu.iq.rate 1.799361 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1887134 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.021173 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 224014583 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 102585406 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 87044839 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 611169 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 425269 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 296604 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 90710574 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 305663 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1465776 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 88451556 # Type of FU issued +system.cpu.iq.rate 1.811444 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1855371 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.020976 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 221933846 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 101092156 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 86564383 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 604586 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 417604 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 294342 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 90004545 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 302382 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1470214 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 3153552 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 5566 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 18132 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1796637 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 2960782 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 4826 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 18180 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1665315 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2518 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 82425 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 2876 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 81924 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1483984 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 2836184 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 76819 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 101124099 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 260669 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 23430190 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 16410014 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 5227 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 60088 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 531 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 18132 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 252052 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 171036 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 423088 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 88146777 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 22749364 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 982326 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1349582 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 2855245 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 77128 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 100251958 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 208716 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 23237420 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 16278692 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 5288 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 60129 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 488 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 18180 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 198098 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 161281 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 359379 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 87608240 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 22627118 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 843316 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 9536672 # number of nop insts executed -system.cpu.iew.exec_refs 38592395 # number of memory reference insts executed -system.cpu.iew.exec_branches 15153499 # Number of branches executed -system.cpu.iew.exec_stores 15843031 # Number of stores executed -system.cpu.iew.exec_rate 1.779530 # Inst execution rate -system.cpu.iew.wb_sent 87753741 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 87341443 # cumulative count of insts written-back -system.cpu.iew.wb_producers 33435183 # num instructions producing a value -system.cpu.iew.wb_consumers 43872218 # num instructions consuming a value +system.cpu.iew.exec_nop 9484115 # number of nop insts executed +system.cpu.iew.exec_refs 38379967 # number of memory reference insts executed +system.cpu.iew.exec_branches 15086881 # Number of branches executed +system.cpu.iew.exec_stores 15752849 # Number of stores executed +system.cpu.iew.exec_rate 1.794174 # Inst execution rate +system.cpu.iew.wb_sent 87251382 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 86858725 # cumulative count of insts written-back +system.cpu.iew.wb_producers 33364118 # num instructions producing a value +system.cpu.iew.wb_consumers 43780682 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.763272 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.762104 # average fanout of values written-back +system.cpu.iew.wb_rate 1.778824 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.762074 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 9751269 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 8914358 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 4583 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 370067 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 42875329 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.060408 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.788298 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 313984 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 42331265 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.086889 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.804714 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 19913451 46.45% 46.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 7068985 16.49% 62.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3438952 8.02% 70.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2090019 4.87% 75.83% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 2085052 4.86% 80.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1168150 2.72% 83.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1107868 2.58% 86.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 727256 1.70% 87.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5275596 12.30% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 19478152 46.01% 46.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 7019307 16.58% 62.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3402930 8.04% 70.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2062880 4.87% 75.51% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2059752 4.87% 80.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1161194 2.74% 83.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1088223 2.57% 85.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 718067 1.70% 87.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5340760 12.62% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 42875329 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 42331265 # Number of insts commited each cycle system.cpu.commit.committedInsts 88340672 # Number of instructions committed system.cpu.commit.committedOps 88340672 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -475,304 +475,192 @@ system.cpu.commit.branches 13754477 # Nu system.cpu.commit.fp_insts 267754 # Number of committed floating point instructions. system.cpu.commit.int_insts 77942044 # Number of committed integer instructions. system.cpu.commit.function_calls 1661057 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5275596 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5340760 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 134374332 # The number of ROB reads -system.cpu.rob.rob_writes 197671452 # The number of ROB writes -system.cpu.timesIdled 69954 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 5174429 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 132928193 # The number of ROB reads +system.cpu.rob.rob_writes 195862433 # The number of ROB writes +system.cpu.timesIdled 69428 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 5148448 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 79591756 # Number of Instructions Simulated system.cpu.committedOps 79591756 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 79591756 # Number of Instructions Simulated -system.cpu.cpi 0.622348 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.622348 # CPI: Total CPI of All Threads -system.cpu.ipc 1.606819 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.606819 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 116696990 # number of integer regfile reads -system.cpu.int_regfile_writes 57893587 # number of integer regfile writes -system.cpu.fp_regfile_reads 251486 # number of floating regfile reads -system.cpu.fp_regfile_writes 240711 # number of floating regfile writes -system.cpu.misc_regfile_reads 38028 # number of misc regfile reads +system.cpu.cpi 0.613497 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.613497 # CPI: Total CPI of All Threads +system.cpu.ipc 1.630000 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.630000 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 115949669 # number of integer regfile reads +system.cpu.int_regfile_writes 57525330 # number of integer regfile writes +system.cpu.fp_regfile_reads 249508 # number of floating regfile reads +system.cpu.fp_regfile_writes 240213 # number of floating regfile writes +system.cpu.misc_regfile_reads 38023 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.icache.replacements 92300 # number of replacements -system.cpu.icache.tagsinuse 1931.186939 # Cycle average of tags in use -system.cpu.icache.total_refs 14080520 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 94348 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 149.240259 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 20259707000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1931.186939 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.942962 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.942962 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 14080520 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 14080520 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 14080520 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 14080520 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 14080520 # number of overall hits -system.cpu.icache.overall_hits::total 14080520 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 107014 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 107014 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 107014 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 107014 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 107014 # number of overall misses -system.cpu.icache.overall_misses::total 107014 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 1801616999 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 1801616999 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 1801616999 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 1801616999 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 1801616999 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 1801616999 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 14187534 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 14187534 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 14187534 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 14187534 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 14187534 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 14187534 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.007543 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.007543 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.007543 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.007543 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.007543 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.007543 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16835.339292 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 16835.339292 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 16835.339292 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 16835.339292 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 16835.339292 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 16835.339292 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 434 # number of cycles access was blocked +system.cpu.icache.replacements 91621 # number of replacements +system.cpu.icache.tagsinuse 1930.572235 # Cycle average of tags in use +system.cpu.icache.total_refs 13805106 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 93669 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 147.381802 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 19945764000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 1930.572235 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.942662 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.942662 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 13805106 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 13805106 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 13805106 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 13805106 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 13805106 # number of overall hits +system.cpu.icache.overall_hits::total 13805106 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 105989 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 105989 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 105989 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 105989 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 105989 # number of overall misses +system.cpu.icache.overall_misses::total 105989 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 1780097998 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 1780097998 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 1780097998 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 1780097998 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 1780097998 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 1780097998 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 13911095 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 13911095 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 13911095 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 13911095 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 13911095 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 13911095 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.007619 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.007619 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.007619 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.007619 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.007619 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.007619 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16795.120229 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 16795.120229 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 16795.120229 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 16795.120229 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 16795.120229 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 16795.120229 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 364 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 9 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 14 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 48.222222 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 26 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 12665 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 12665 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 12665 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 12665 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 12665 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 12665 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 94349 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 94349 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 94349 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 94349 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 94349 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 94349 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1400064000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 1400064000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1400064000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 1400064000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1400064000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 1400064000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006650 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006650 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006650 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.006650 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006650 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.006650 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14839.203383 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14839.203383 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14839.203383 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 14839.203383 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14839.203383 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 14839.203383 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 12319 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 12319 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 12319 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 12319 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 12319 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 12319 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 93670 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 93670 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 93670 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 93670 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 93670 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 93670 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1391219000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 1391219000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1391219000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 1391219000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1391219000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 1391219000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006733 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006733 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006733 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.006733 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006733 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.006733 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14852.343333 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14852.343333 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14852.343333 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 14852.343333 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14852.343333 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 14852.343333 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 201586 # number of replacements -system.cpu.dcache.tagsinuse 4077.128651 # Cycle average of tags in use -system.cpu.dcache.total_refs 34331018 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 205682 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 166.913089 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 177489000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4077.128651 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.995393 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.995393 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 20756846 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 20756846 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 13574115 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 13574115 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 57 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 57 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 34330961 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 34330961 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 34330961 # number of overall hits -system.cpu.dcache.overall_hits::total 34330961 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 266792 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 266792 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1039262 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1039262 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 1306054 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1306054 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1306054 # number of overall misses -system.cpu.dcache.overall_misses::total 1306054 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 12393965000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 12393965000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 93492268598 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 93492268598 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 105886233598 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 105886233598 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 105886233598 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 105886233598 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 21023638 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 21023638 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 57 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 57 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 35637015 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 35637015 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 35637015 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 35637015 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012690 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.012690 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.071117 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.071117 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.036649 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.036649 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.036649 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.036649 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 46455.534649 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 46455.534649 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 89960.249290 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 89960.249290 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 81073.396351 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 81073.396351 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 81073.396351 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 81073.396351 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 5474703 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 114 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 112304 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 48.748958 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 114 # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 169009 # number of writebacks -system.cpu.dcache.writebacks::total 169009 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 204529 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 204529 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 895843 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 895843 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1100372 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1100372 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1100372 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1100372 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 62263 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 62263 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143419 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 143419 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 205682 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 205682 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 205682 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 205682 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2025118000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2025118000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 14654502991 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 14654502991 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16679620991 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 16679620991 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16679620991 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 16679620991 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002962 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002962 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009814 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009814 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005772 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.005772 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005772 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.005772 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 32525.223648 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 32525.223648 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 102179.648380 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 102179.648380 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 81094.218215 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 81094.218215 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 81094.218215 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 81094.218215 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 132442 # number of replacements -system.cpu.l2cache.tagsinuse 30854.003971 # Cycle average of tags in use -system.cpu.l2cache.total_refs 160847 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 164507 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.977752 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 132407 # number of replacements +system.cpu.l2cache.tagsinuse 30853.775951 # Cycle average of tags in use +system.cpu.l2cache.total_refs 160055 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 164479 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.973103 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 26667.895606 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 2125.543689 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 2060.564676 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.813840 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.064866 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.062883 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.941589 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 86668 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 34393 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 121061 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 169009 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 169009 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 12621 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 12621 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 86668 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 47014 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 133682 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 86668 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 47014 # number of overall hits -system.cpu.l2cache.overall_hits::total 133682 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 7681 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 27866 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 35547 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 130802 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 130802 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 7681 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 158668 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 166349 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 7681 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 158668 # number of overall misses -system.cpu.l2cache.overall_misses::total 166349 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 438125500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1616867500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 2054993000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 14383174000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 14383174000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 438125500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 16000041500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 16438167000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 438125500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 16000041500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 16438167000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 94349 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 62259 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 156608 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 169009 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 169009 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 143423 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 143423 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 94349 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 205682 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 300031 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 94349 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 205682 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 300031 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.081411 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.447582 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.226981 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.912002 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.912002 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.081411 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.771424 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.554439 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.081411 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.771424 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.554439 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 57040.164041 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 58022.949114 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 57810.588798 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 109961.422608 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 109961.422608 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 57040.164041 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 100839.750296 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 98817.347865 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 57040.164041 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 100839.750296 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 98817.347865 # average overall miss latency +system.cpu.l2cache.occ_blocks::writebacks 26652.913522 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 2131.265496 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 2069.596933 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.813382 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.065041 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.063159 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.941583 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 86007 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 34313 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 120320 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 168957 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 168957 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 12635 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 12635 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 86007 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 46948 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 132955 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 86007 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 46948 # number of overall hits +system.cpu.l2cache.overall_hits::total 132955 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 7663 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 27857 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 35520 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 130798 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 130798 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 7663 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 158655 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 166318 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 7663 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 158655 # number of overall misses +system.cpu.l2cache.overall_misses::total 166318 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 436539000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1622577000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 2059116000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 14368905500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 14368905500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 436539000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 15991482500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 16428021500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 436539000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 15991482500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 16428021500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 93670 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 62170 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 155840 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 168957 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 168957 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 143433 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 143433 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 93670 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 205603 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 299273 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 93670 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 205603 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 299273 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.081808 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.448078 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.227926 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.911910 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.911910 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.081808 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.771657 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.555740 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.081808 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.771657 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.555740 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 56967.114707 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 58246.652547 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 57970.608108 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 109855.697335 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 109855.697335 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 56967.114707 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 100794.065740 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 98774.765810 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 56967.114707 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 100794.065740 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 98774.765810 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -783,50 +671,162 @@ system.cpu.l2cache.fast_writes 0 # nu system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks::writebacks 114015 # number of writebacks system.cpu.l2cache.writebacks::total 114015 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 7681 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 27866 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 35547 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 130802 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 130802 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 7681 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 158668 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 166349 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 7681 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 158668 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 166349 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 340900477 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1256603152 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1597503629 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 12762940575 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 12762940575 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 340900477 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 14019543727 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 14360444204 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 340900477 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 14019543727 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 14360444204 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.081411 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.447582 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.226981 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.912002 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.912002 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.081411 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.771424 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.554439 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.081411 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.771424 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.554439 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 44382.303997 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 45094.493361 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 44940.603398 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 97574.506315 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 97574.506315 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 44382.303997 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 88357.726366 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 86327.204876 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 44382.303997 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 88357.726366 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 86327.204876 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 7663 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 27857 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 35520 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 130798 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 130798 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 7663 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 158655 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 166318 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 7663 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 158655 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 166318 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 339509017 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1262432105 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1601941122 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 12748622275 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 12748622275 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 339509017 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 14011054380 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 14350563397 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 339509017 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 14011054380 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 14350563397 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.081808 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.448078 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.227926 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.911910 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.911910 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.081808 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.771657 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.555740 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.081808 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.771657 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.555740 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 44304.974162 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 45318.307966 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 45099.693750 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 97468.021491 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 97468.021491 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 44304.974162 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 88311.458069 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 86283.886272 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 44304.974162 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 88311.458069 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 86283.886272 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.replacements 201507 # number of replacements +system.cpu.dcache.tagsinuse 4077.368240 # Cycle average of tags in use +system.cpu.dcache.total_refs 34205521 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 205603 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 166.366838 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 173993000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4077.368240 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.995451 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.995451 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 20631452 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 20631452 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 13574012 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 13574012 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 57 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 57 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 34205464 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 34205464 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 34205464 # number of overall hits +system.cpu.dcache.overall_hits::total 34205464 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 267045 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 267045 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1039365 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1039365 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 1306410 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1306410 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1306410 # number of overall misses +system.cpu.dcache.overall_misses::total 1306410 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 12450634000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 12450634000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 93436551833 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 93436551833 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 105887185833 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 105887185833 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 105887185833 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 105887185833 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 20898497 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 20898497 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 14613377 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 57 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 57 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 35511874 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 35511874 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 35511874 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 35511874 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012778 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.012778 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.071124 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.071124 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.036788 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.036788 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.036788 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.036788 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 46623.730083 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 46623.730083 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 89897.727779 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 89897.727779 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 81052.032542 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 81052.032542 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 81052.032542 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 81052.032542 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 5486905 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 119 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 112436 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 48.800251 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 119 # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 168957 # number of writebacks +system.cpu.dcache.writebacks::total 168957 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 204872 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 204872 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 895935 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 895935 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1100807 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1100807 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1100807 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1100807 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 62173 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 62173 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143430 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 143430 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 205603 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 205603 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 205603 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 205603 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2029919500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2029919500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 14640535990 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 14640535990 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16670455490 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 16670455490 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16670455490 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 16670455490 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002975 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002975 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009815 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009815 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005790 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.005790 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005790 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.005790 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 32649.534364 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 32649.534364 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 102074.433452 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 102074.433452 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 81080.798870 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 81080.798870 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 81080.798870 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 81080.798870 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini index b2095b317..889e8b1f0 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini @@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a -clock=1 +clock=1000 init_param=0 kernel= load_addr_mask=1099511627775 @@ -30,7 +30,7 @@ system_port=system.membus.slave[0] [system.cpu] type=DerivO3CPU -children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload +children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -78,6 +78,7 @@ iewToFetchDelay=1 iewToRenameDelay=1 instShiftAmt=2 interrupts=system.cpu.interrupts +isa=system.cpu.isa issueToExecuteDelay=1 issueWidth=8 itb=system.cpu.itb @@ -129,18 +130,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=262144 subblock_size=0 system=system @@ -159,7 +160,7 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=ArmTableWalker -clock=1 +clock=500 num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[3] @@ -432,18 +433,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=131072 subblock_size=0 system=system @@ -457,6 +458,23 @@ mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=ArmInterrupts +[system.cpu.isa] +type=ArmISA +fpsid=1090793632 +id_isar0=34607377 +id_isar1=34677009 +id_isar2=555950401 +id_isar3=17899825 +id_isar4=268501314 +id_isar5=0 +id_mmfr0=3 +id_mmfr1=0 +id_mmfr2=19070976 +id_mmfr3=4027589137 +id_pfr0=49 +id_pfr1=1 +midr=890224640 + [system.cpu.itb] type=ArmTLB children=walker @@ -465,7 +483,7 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=ArmTableWalker -clock=1 +clock=500 num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[2] @@ -473,24 +491,24 @@ port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] type=BaseCache addr_ranges=0:18446744073709551615 -assoc=2 +assoc=8 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=20 is_top_level=false max_miss_count=0 -mshrs=10 +mshrs=20 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=20 size=2097152 subblock_size=0 system=system -tgts_per_mshr=5 +tgts_per_mshr=12 trace_addr=0 two_queue=false write_buffers=8 @@ -500,10 +518,10 @@ mem_side=system.membus.slave[1] [system.cpu.toL2Bus] type=CoherentBus block_size=64 -clock=1000 +clock=500 header_cycles=1 use_default_range=false -width=8 +width=32 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port @@ -540,15 +558,28 @@ master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] -type=SimpleMemory -bandwidth=73.000000 -clock=1 +type=SimpleDRAM +addr_mapping=openmap +banks_per_rank=8 +clock=1000 conf_table_reported=false in_addr_map=true -latency=30000 -latency_var=0 +lines_per_rowbuffer=64 +mem_sched_policy=fcfs null=false +page_policy=open range=0:134217727 +ranks_per_channel=2 +read_buffer_size=32 +tBURST=4000 +tCL=14000 +tRCD=14000 +tREFI=7800000 +tRFC=300000 +tRP=14000 +tWTR=1000 +write_buffer_size=32 +write_thresh_perc=70 zero=false port=system.membus.master[0] diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout index 726190563..dc0676551 100755 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout @@ -1,11 +1,11 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 21 2012 11:19:00 -gem5 started Sep 21 2012 11:57:39 +gem5 compiled Oct 30 2012 11:20:14 +gem5 started Oct 30 2012 20:20:38 gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. -Exiting @ tick 24260940500 because target called exit() +Exiting @ tick 26292466000 because target called exit() diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt index bbe40238a..69c62381b 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt @@ -1,90 +1,90 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.026781 # Number of seconds simulated -sim_ticks 26780535000 # Number of ticks simulated -final_tick 26780535000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.026292 # Number of seconds simulated +sim_ticks 26292466000 # Number of ticks simulated +final_tick 26292466000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 149394 # Simulator instruction rate (inst/s) -host_op_rate 211994 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 56410244 # Simulator tick rate (ticks/s) -host_mem_usage 261852 # Number of bytes of host memory used -host_seconds 474.75 # Real time elapsed on the host -sim_insts 70924159 # Number of instructions simulated -sim_ops 100643406 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 300160 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 7944448 # Number of bytes read from this memory -system.physmem.bytes_read::total 8244608 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 300160 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 300160 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 5372672 # Number of bytes written to this memory -system.physmem.bytes_written::total 5372672 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 4690 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 124132 # Number of read requests responded to by this memory -system.physmem.num_reads::total 128822 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 83948 # Number of write requests responded to by this memory -system.physmem.num_writes::total 83948 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 11208141 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 296650086 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 307858226 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 11208141 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 11208141 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 200618546 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 200618546 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 200618546 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 11208141 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 296650086 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 508476772 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 128823 # Total number of read requests seen -system.physmem.writeReqs 83948 # Total number of write requests seen -system.physmem.cpureqs 213079 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 8244608 # Total number of bytes read from memory -system.physmem.bytesWritten 5372672 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 8244608 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 5372672 # bytesWritten derated as per pkt->getSize() +host_inst_rate 115195 # Simulator instruction rate (inst/s) +host_op_rate 163465 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 42703788 # Simulator tick rate (ticks/s) +host_mem_usage 260928 # Number of bytes of host memory used +host_seconds 615.69 # Real time elapsed on the host +sim_insts 70925094 # Number of instructions simulated +sim_ops 100644341 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 298432 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 7943232 # Number of bytes read from this memory +system.physmem.bytes_read::total 8241664 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 298432 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 298432 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 5372352 # Number of bytes written to this memory +system.physmem.bytes_written::total 5372352 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 4663 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 124113 # Number of read requests responded to by this memory +system.physmem.num_reads::total 128776 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 83943 # Number of write requests responded to by this memory +system.physmem.num_writes::total 83943 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 11350476 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 302110574 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 313461050 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 11350476 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 11350476 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 204330472 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 204330472 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 204330472 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 11350476 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 302110574 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 517791522 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 128777 # Total number of read requests seen +system.physmem.writeReqs 83943 # Total number of write requests seen +system.physmem.cpureqs 213018 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 8241664 # Total number of bytes read from memory +system.physmem.bytesWritten 5372352 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 8241664 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 5372352 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 3 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 308 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 8176 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 8046 # Track reads on a per bank basis +system.physmem.neitherReadNorWrite 298 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 8167 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 8037 # Track reads on a per bank basis system.physmem.perBankRdReqs::2 8102 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 7891 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 7930 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 7896 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 7927 # Track reads on a per bank basis system.physmem.perBankRdReqs::5 8109 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 8032 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 7950 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 7992 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 8193 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 8188 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 8163 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 8063 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 8009 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 8024 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 7958 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 7983 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 8195 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 8177 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 8153 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 8060 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 8008 # Track reads on a per bank basis system.physmem.perBankRdReqs::14 7995 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 7981 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 5174 # Track writes on a per bank basis +system.physmem.perBankRdReqs::15 7983 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 5171 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 5038 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 5232 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 5233 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 5165 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 5231 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 5234 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 5166 # Track writes on a per bank basis system.physmem.perBankWrReqs::5 5377 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 5168 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 5164 # Track writes on a per bank basis system.physmem.perBankWrReqs::7 5136 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 5231 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 5232 # Track writes on a per bank basis system.physmem.perBankWrReqs::9 5377 # Track writes on a per bank basis system.physmem.perBankWrReqs::10 5465 # Track writes on a per bank basis system.physmem.perBankWrReqs::11 5417 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 5374 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 5287 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 5126 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 5148 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 5372 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 5285 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 5127 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 5151 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 26780515500 # Total gap between requests +system.physmem.totGap 26292446500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 128823 # Categorize read packet sizes +system.physmem.readPktSize::6 128777 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -93,7 +93,7 @@ system.physmem.writePktSize::2 0 # ca system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 83948 # categorize write packet sizes +system.physmem.writePktSize::6 83943 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -102,14 +102,14 @@ system.physmem.neitherpktsize::2 0 # ca system.physmem.neitherpktsize::3 0 # categorize neither packet sizes system.physmem.neitherpktsize::4 0 # categorize neither packet sizes system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 308 # categorize neither packet sizes +system.physmem.neitherpktsize::6 298 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 71083 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 55295 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 2364 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 64 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 14 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 71059 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 55263 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 2369 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 71 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 12 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -138,11 +138,11 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 3587 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 3649 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 3650 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 3650 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 3650 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 3590 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 3644 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 3649 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 3649 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 3649 # What write queue length does an incoming req see system.physmem.wrQLenPdf::5 3650 # What write queue length does an incoming req see system.physmem.wrQLenPdf::6 3650 # What write queue length does an incoming req see system.physmem.wrQLenPdf::7 3650 # What write queue length does an incoming req see @@ -154,44 +154,44 @@ system.physmem.wrQLenPdf::12 3650 # Wh system.physmem.wrQLenPdf::13 3650 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 3650 # What write queue length does an incoming req see system.physmem.wrQLenPdf::15 3650 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3650 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 3650 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 3650 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 3650 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 3650 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3649 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 3649 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 3649 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 3649 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 3649 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 3649 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 3649 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 63 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 60 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 4847041699 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 6735959699 # Sum of mem lat for all requests -system.physmem.totBusLat 515280000 # Total cycles spent in databus access -system.physmem.totBankLat 1373638000 # Total cycles spent in bank access -system.physmem.avgQLat 37626.47 # Average queueing delay per request -system.physmem.avgBankLat 10663.24 # Average bank access latency per request +system.physmem.totQLat 4868161034 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 6756433034 # Sum of mem lat for all requests +system.physmem.totBusLat 515096000 # Total cycles spent in databus access +system.physmem.totBankLat 1373176000 # Total cycles spent in bank access +system.physmem.avgQLat 37803.91 # Average queueing delay per request +system.physmem.avgBankLat 10663.46 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 52289.70 # Average memory access latency -system.physmem.avgRdBW 307.86 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 200.62 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 307.86 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 200.62 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 52467.37 # Average memory access latency +system.physmem.avgRdBW 313.46 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 204.33 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 313.46 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 204.33 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 3.18 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.25 # Average read queue length over time -system.physmem.avgWrQLen 9.64 # Average write queue length over time -system.physmem.readRowHits 118946 # Number of row buffer hits during reads -system.physmem.writeRowHits 27105 # Number of row buffer hits during writes -system.physmem.readRowHitRate 92.34 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 32.29 # Row buffer hit rate for writes -system.physmem.avgGap 125865.44 # Average gap between requests +system.physmem.busUtil 3.24 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.26 # Average read queue length over time +system.physmem.avgWrQLen 9.45 # Average write queue length over time +system.physmem.readRowHits 118938 # Number of row buffer hits during reads +system.physmem.writeRowHits 27082 # Number of row buffer hits during writes +system.physmem.readRowHitRate 92.36 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 32.26 # Row buffer hit rate for writes +system.physmem.avgGap 123601.20 # Average gap between requests system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -235,581 +235,455 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 53561071 # number of cpu cycles simulated +system.cpu.numCycles 52584933 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 16989438 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 12991194 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 680202 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 11755292 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 8009849 # Number of BTB hits +system.cpu.BPredUnit.lookups 16605622 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 12744819 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 601134 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 10608037 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 7769778 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1851785 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 114363 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 12914479 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 87008149 # Number of instructions fetch has processed -system.cpu.fetch.Branches 16989438 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9861634 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 21655288 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2666634 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 10515039 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 139 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 571 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 35 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 11971869 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 198806 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 47045662 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.589318 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.332778 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1827213 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 113597 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 12549160 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 85090933 # Number of instructions fetch has processed +system.cpu.fetch.Branches 16605622 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9596991 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 21171852 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2347507 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 10606958 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 61 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 522 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 68 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 11672224 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 180779 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 46048900 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.587178 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.333418 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 25412140 54.02% 54.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2169507 4.61% 58.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2024864 4.30% 62.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2094897 4.45% 67.38% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1497374 3.18% 70.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1417625 3.01% 73.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 986770 2.10% 75.68% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1225872 2.61% 78.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 10216613 21.72% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 24897026 54.07% 54.07% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2135353 4.64% 58.70% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1967483 4.27% 62.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2044942 4.44% 67.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1463280 3.18% 70.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1379331 3.00% 73.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 959670 2.08% 75.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1190775 2.59% 78.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 10011040 21.74% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 47045662 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.317198 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.624466 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 15025286 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 8880734 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 19918391 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1367786 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1853465 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3434521 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 108932 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 119105730 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 372945 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1853465 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 16780714 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 2530019 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 932679 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 19483180 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 5465605 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 116933277 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 184 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 14375 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4623545 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 215 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 117254635 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 538431443 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 538426294 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 5149 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 99159120 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 18095515 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 25625 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 25611 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12984960 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 29963650 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 22702028 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 3806099 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 4346835 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 113028204 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 41641 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 108286515 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 316116 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 12256138 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 28707838 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 4549 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 47045662 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.301732 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.993875 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 46048900 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.315787 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.618162 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 14627644 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 8956467 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 19461806 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1385483 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1617500 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3326611 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 104659 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 116720432 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 360894 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1617500 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 16338587 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 2555401 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 926852 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 19086495 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 5524065 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 114852318 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 168 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 16183 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4665174 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 343 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 115176508 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 529186359 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 529181674 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 4685 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 99160616 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 16015892 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 24809 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 24798 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13045945 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 29582757 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 22430841 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 3912004 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 4391398 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 111440700 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 41006 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 107204361 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 269260 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 10685136 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 25571717 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 3727 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 46048900 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.328055 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.987613 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 11469393 24.38% 24.38% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 8159881 17.34% 41.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7486298 15.91% 57.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 7193710 15.29% 72.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 5478307 11.64% 84.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 3936871 8.37% 92.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1856294 3.95% 96.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 881703 1.87% 98.76% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 583205 1.24% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 10795987 23.44% 23.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 8084539 17.56% 41.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7444488 16.17% 57.17% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 7134852 15.49% 72.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 5412181 11.75% 84.41% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 3900032 8.47% 92.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1833850 3.98% 96.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 869462 1.89% 98.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 573509 1.25% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 47045662 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 46048900 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 112009 4.47% 4.47% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 4.47% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 4.47% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 2 0.00% 4.47% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.47% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.47% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 4.47% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.47% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 4.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 4.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.47% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1372514 54.80% 59.28% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 1019865 40.72% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 110622 4.49% 4.49% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 4.49% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 4.49% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.49% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.49% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.49% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 4.49% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.49% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 4.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 4.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.49% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1351687 54.87% 59.36% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 1001007 40.64% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 57275495 52.89% 52.89% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 91732 0.08% 52.98% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.98% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 181 0.00% 52.98% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.98% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 52.98% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 52.98% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 52.98% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 52.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 52.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 52.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 52.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 52.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 52.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 52.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 52.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 52.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 52.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 52.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 52.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 52.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 52.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 52.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.98% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 29138143 26.91% 79.89% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 21780957 20.11% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 56616683 52.81% 52.81% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 91709 0.09% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 161 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 28875176 26.93% 79.83% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 21620625 20.17% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 108286515 # Type of FU issued -system.cpu.iq.rate 2.021739 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2504390 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.023127 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 266438684 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 125354112 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 106381358 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 514 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 754 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 156 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 110790645 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 260 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 2168801 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 107204361 # Type of FU issued +system.cpu.iq.rate 2.038690 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2463316 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.022978 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 263189734 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 122194582 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 105533921 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 464 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 696 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 152 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 109667441 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 236 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 2181528 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 2653236 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 7465 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 30261 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2142984 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 2272156 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 6578 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 29396 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1871610 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 29 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 473 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 28 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 493 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1853465 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1042007 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 44975 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 113079657 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 348290 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 29963650 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 22702028 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 25073 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 6129 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 5511 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 30261 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 453510 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 204690 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 658200 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 107104018 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 28789803 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1182497 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1617500 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1047454 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 46131 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 111491510 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 290951 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 29582757 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 22430841 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 24336 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 6480 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 5483 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 29396 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 390184 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 182395 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 572579 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 106179962 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 28578383 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1024399 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 9812 # number of nop insts executed -system.cpu.iew.exec_refs 50259028 # number of memory reference insts executed -system.cpu.iew.exec_branches 14733119 # Number of branches executed -system.cpu.iew.exec_stores 21469225 # Number of stores executed -system.cpu.iew.exec_rate 1.999662 # Inst execution rate -system.cpu.iew.wb_sent 106622925 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 106381514 # cumulative count of insts written-back -system.cpu.iew.wb_producers 53628948 # num instructions producing a value -system.cpu.iew.wb_consumers 104196549 # num instructions consuming a value +system.cpu.iew.exec_nop 9804 # number of nop insts executed +system.cpu.iew.exec_refs 49916161 # number of memory reference insts executed +system.cpu.iew.exec_branches 14598129 # Number of branches executed +system.cpu.iew.exec_stores 21337778 # Number of stores executed +system.cpu.iew.exec_rate 2.019209 # Inst execution rate +system.cpu.iew.wb_sent 105751543 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 105534073 # cumulative count of insts written-back +system.cpu.iew.wb_producers 53248858 # num instructions producing a value +system.cpu.iew.wb_consumers 103476528 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.986172 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.514690 # average fanout of values written-back +system.cpu.iew.wb_rate 2.006926 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.514598 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 12431579 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 37092 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 573556 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 45192198 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.227131 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.747743 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 10842444 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 37279 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 498355 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 44431401 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.265287 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.763630 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 15976760 35.35% 35.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 11724717 25.94% 61.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3516948 7.78% 69.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2892652 6.40% 75.48% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1888504 4.18% 79.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1974510 4.37% 84.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 692586 1.53% 85.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 573861 1.27% 86.83% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5951660 13.17% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 15343377 34.53% 34.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 11655601 26.23% 60.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3462235 7.79% 68.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2874946 6.47% 75.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1877627 4.23% 79.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1953879 4.40% 83.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 688656 1.55% 85.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 567495 1.28% 86.48% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 6007585 13.52% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 45192198 # Number of insts commited each cycle -system.cpu.commit.committedInsts 70929711 # Number of instructions committed -system.cpu.commit.committedOps 100648958 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 44431401 # Number of insts commited each cycle +system.cpu.commit.committedInsts 70930646 # Number of instructions committed +system.cpu.commit.committedOps 100649893 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 47869458 # Number of memory references committed -system.cpu.commit.loads 27310414 # Number of loads committed +system.cpu.commit.refs 47869832 # Number of memory references committed +system.cpu.commit.loads 27310601 # Number of loads committed system.cpu.commit.membars 15920 # Number of memory barriers committed -system.cpu.commit.branches 13744811 # Number of branches committed +system.cpu.commit.branches 13744998 # Number of branches committed system.cpu.commit.fp_insts 56 # Number of committed floating point instructions. -system.cpu.commit.int_insts 91486003 # Number of committed integer instructions. +system.cpu.commit.int_insts 91486751 # Number of committed integer instructions. system.cpu.commit.function_calls 1679850 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5951660 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 6007585 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 152295776 # The number of ROB reads -system.cpu.rob.rob_writes 228025366 # The number of ROB writes -system.cpu.timesIdled 74466 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 6515409 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 70924159 # Number of Instructions Simulated -system.cpu.committedOps 100643406 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 70924159 # Number of Instructions Simulated -system.cpu.cpi 0.755188 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.755188 # CPI: Total CPI of All Threads -system.cpu.ipc 1.324174 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.324174 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 515451838 # number of integer regfile reads -system.cpu.int_regfile_writes 104231541 # number of integer regfile writes -system.cpu.fp_regfile_reads 698 # number of floating regfile reads -system.cpu.fp_regfile_writes 610 # number of floating regfile writes -system.cpu.misc_regfile_reads 145512549 # number of misc regfile reads -system.cpu.misc_regfile_writes 38452 # number of misc regfile writes -system.cpu.icache.replacements 31300 # number of replacements -system.cpu.icache.tagsinuse 1822.220766 # Cycle average of tags in use -system.cpu.icache.total_refs 11934433 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 33335 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 358.015089 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 149890854 # The number of ROB reads +system.cpu.rob.rob_writes 224611140 # The number of ROB writes +system.cpu.timesIdled 74350 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 6536033 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 70925094 # Number of Instructions Simulated +system.cpu.committedOps 100644341 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 70925094 # Number of Instructions Simulated +system.cpu.cpi 0.741415 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.741415 # CPI: Total CPI of All Threads +system.cpu.ipc 1.348772 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.348772 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 511431338 # number of integer regfile reads +system.cpu.int_regfile_writes 103318196 # number of integer regfile writes +system.cpu.fp_regfile_reads 686 # number of floating regfile reads +system.cpu.fp_regfile_writes 582 # number of floating regfile writes +system.cpu.misc_regfile_reads 143076838 # number of misc regfile reads +system.cpu.misc_regfile_writes 38826 # number of misc regfile writes +system.cpu.icache.replacements 30543 # number of replacements +system.cpu.icache.tagsinuse 1820.333452 # Cycle average of tags in use +system.cpu.icache.total_refs 11635566 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 32580 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 357.138306 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1822.220766 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.889756 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.889756 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 11934443 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 11934443 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 11934443 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 11934443 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 11934443 # number of overall hits -system.cpu.icache.overall_hits::total 11934443 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 37425 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 37425 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 37425 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 37425 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 37425 # number of overall misses -system.cpu.icache.overall_misses::total 37425 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 718344999 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 718344999 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 718344999 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 718344999 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 718344999 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 718344999 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 11971868 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 11971868 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 11971868 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 11971868 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 11971868 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 11971868 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.003126 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.003126 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.003126 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.003126 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.003126 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.003126 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19194.255150 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 19194.255150 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 19194.255150 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 19194.255150 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 19194.255150 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 19194.255150 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 1048 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 1820.333452 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.888835 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.888835 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 11635567 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 11635567 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 11635567 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 11635567 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 11635567 # number of overall hits +system.cpu.icache.overall_hits::total 11635567 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 36657 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 36657 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 36657 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 36657 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 36657 # number of overall misses +system.cpu.icache.overall_misses::total 36657 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 709011999 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 709011999 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 709011999 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 709011999 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 709011999 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 709011999 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 11672224 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 11672224 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 11672224 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 11672224 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 11672224 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 11672224 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.003141 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.003141 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.003141 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.003141 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.003141 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.003141 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19341.790081 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 19341.790081 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 19341.790081 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 19341.790081 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 19341.790081 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 19341.790081 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 1000 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 19 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 22 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 55.157895 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 45.454545 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3774 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 3774 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 3774 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 3774 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 3774 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 3774 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 33651 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 33651 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 33651 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 33651 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 33651 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 33651 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 589350499 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 589350499 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 589350499 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 589350499 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 589350499 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 589350499 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.002811 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.002811 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.002811 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.002811 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.002811 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.002811 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 17513.610264 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 17513.610264 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17513.610264 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 17513.610264 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17513.610264 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 17513.610264 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3773 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 3773 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 3773 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 3773 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 3773 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 3773 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 32884 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 32884 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 32884 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 32884 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 32884 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 32884 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 580604499 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 580604499 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 580604499 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 580604499 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 580604499 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 580604499 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.002817 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.002817 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.002817 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.002817 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.002817 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.002817 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 17656.139734 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 17656.139734 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17656.139734 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 17656.139734 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17656.139734 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 17656.139734 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 158507 # number of replacements -system.cpu.dcache.tagsinuse 4072.917720 # Cycle average of tags in use -system.cpu.dcache.total_refs 44563863 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 162603 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 274.065442 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 285154000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4072.917720 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.994365 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.994365 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 26258448 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 26258448 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 18265067 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 18265067 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 20455 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 20455 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 19225 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 19225 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 44523515 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 44523515 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 44523515 # number of overall hits -system.cpu.dcache.overall_hits::total 44523515 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 125393 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 125393 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1584834 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1584834 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 44 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 44 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1710227 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1710227 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1710227 # number of overall misses -system.cpu.dcache.overall_misses::total 1710227 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 4597179000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 4597179000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 120104513482 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 120104513482 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 949000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 949000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 124701692482 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 124701692482 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 124701692482 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 124701692482 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 26383841 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 26383841 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 20499 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 20499 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 19225 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 19225 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 46233742 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 46233742 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 46233742 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 46233742 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004753 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.004753 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.079841 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.079841 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.002146 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.002146 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.036991 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.036991 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.036991 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.036991 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 36662.166150 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 36662.166150 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 75783.655248 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 75783.655248 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 21568.181818 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 21568.181818 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 72915.286966 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 72915.286966 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 72915.286966 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 72915.286966 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 2506 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 608 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 117 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 16 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 21.418803 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 38 # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 129149 # number of writebacks -system.cpu.dcache.writebacks::total 129149 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 69778 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 69778 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1477521 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1477521 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 44 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 44 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1547299 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1547299 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1547299 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1547299 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55615 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 55615 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107313 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 107313 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 162928 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 162928 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 162928 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 162928 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2039094000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2039094000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8257233993 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8257233993 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10296327993 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10296327993 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10296327993 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10296327993 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002108 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002108 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005406 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005406 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003524 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.003524 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003524 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.003524 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 36664.461027 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 36664.461027 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76945.328087 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76945.328087 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 63195.571007 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 63195.571007 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 63195.571007 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 63195.571007 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 95689 # number of replacements -system.cpu.l2cache.tagsinuse 30139.737825 # Cycle average of tags in use -system.cpu.l2cache.total_refs 90978 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 126809 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.717441 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 95650 # number of replacements +system.cpu.l2cache.tagsinuse 30136.955692 # Cycle average of tags in use +system.cpu.l2cache.total_refs 89930 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 126757 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.709468 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 26886.974949 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 1383.020531 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 1869.742346 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.820525 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.042206 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.057060 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.919792 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 28461 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 33637 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 62098 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 129149 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 129149 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 17 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 17 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 4769 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 4769 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 28461 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 38406 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 66867 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 28461 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 38406 # number of overall hits -system.cpu.l2cache.overall_hits::total 66867 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 4707 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 21944 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 26651 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 308 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 308 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 102253 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 102253 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 4707 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 124197 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 128904 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 4707 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 124197 # number of overall misses -system.cpu.l2cache.overall_misses::total 128904 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 270210000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1641574500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 1911784500 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 45500 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 45500 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8095497000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 8095497000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 270210000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 9737071500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 10007281500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 270210000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 9737071500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 10007281500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 33168 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 55581 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 88749 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 129149 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 129149 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 325 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 325 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 107022 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 107022 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 33168 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 162603 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 195771 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 33168 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 162603 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 195771 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.141914 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.394811 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.300296 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.947692 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.947692 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.955439 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.955439 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.141914 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.763805 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.658443 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.141914 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.763805 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.658443 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 57405.991077 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 74807.441670 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 71734.062512 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 147.727273 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 147.727273 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79171.241920 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79171.241920 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 57405.991077 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78400.214981 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 77633.599423 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 57405.991077 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78400.214981 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 77633.599423 # average overall miss latency +system.cpu.l2cache.occ_blocks::writebacks 26880.895911 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 1379.489976 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 1876.569805 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.820340 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.042099 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.057268 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.919707 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 27693 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 33453 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 61146 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 129052 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 129052 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 19 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 19 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 4778 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 4778 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 27693 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 38231 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 65924 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 27693 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 38231 # number of overall hits +system.cpu.l2cache.overall_hits::total 65924 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 4680 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 21915 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 26595 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 298 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 298 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 102256 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 102256 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 4680 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 124171 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 128851 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 4680 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 124171 # number of overall misses +system.cpu.l2cache.overall_misses::total 128851 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 269870000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1664898500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 1934768500 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 23000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 23000 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8091962000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 8091962000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 269870000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 9756860500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 10026730500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 269870000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 9756860500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 10026730500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 32373 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 55368 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 87741 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 129052 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 129052 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 317 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 317 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 107034 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 107034 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 32373 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 162402 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 194775 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 32373 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 162402 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 194775 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.144565 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.395806 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.303108 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.940063 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.940063 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.955360 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.955360 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.144565 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.764590 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.661538 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.144565 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.764590 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.661538 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 57664.529915 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75970.727812 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 72749.332581 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 77.181208 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 77.181208 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79134.349085 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79134.349085 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 57664.529915 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78576.000032 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 77816.474067 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 57664.529915 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78576.000032 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 77816.474067 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -818,69 +692,195 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 83948 # number of writebacks -system.cpu.l2cache.writebacks::total 83948 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 83943 # number of writebacks +system.cpu.l2cache.writebacks::total 83943 # number of writebacks system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 16 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 65 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 81 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 58 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 74 # number of ReadReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.inst 16 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 65 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 81 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 58 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 74 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.inst 16 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 65 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 81 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 4691 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 21879 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 26570 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 308 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 308 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102253 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 102253 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 4691 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 124132 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 128823 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 4691 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 124132 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 128823 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 210199490 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1366008240 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1576207730 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 3082308 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 3082308 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6824605081 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6824605081 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 210199490 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8190613321 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 8400812811 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 210199490 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8190613321 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 8400812811 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.141432 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.393642 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.299384 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.947692 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.947692 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955439 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955439 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.141432 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.763405 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.658029 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.141432 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.763405 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.658029 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 44809.100405 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62434.674345 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59322.835152 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10007.493506 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10007.493506 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66742.345760 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66742.345760 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 44809.100405 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65983.093167 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65212.056939 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 44809.100405 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65983.093167 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65212.056939 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_hits::cpu.data 58 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 74 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 4664 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 21857 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 26521 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 298 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 298 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102256 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 102256 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 4664 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 124113 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 128777 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 4664 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 124113 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 128777 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 210181444 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1389842080 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1600023524 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 2980298 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 2980298 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6821241683 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6821241683 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 210181444 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8211083763 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 8421265207 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 210181444 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8211083763 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 8421265207 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.144071 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.394759 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.302265 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.940063 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.940063 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955360 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955360 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.144071 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.764233 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.661158 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.144071 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.764233 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.661158 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 45064.632075 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63587.961751 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60330.437163 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66707.495726 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66707.495726 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 45064.632075 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66158.128182 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65394.171374 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 45064.632075 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66158.128182 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65394.171374 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.replacements 158306 # number of replacements +system.cpu.dcache.tagsinuse 4072.986675 # Cycle average of tags in use +system.cpu.dcache.total_refs 44343623 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 162402 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 273.048503 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 280868000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4072.986675 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.994382 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.994382 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 26038019 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 26038019 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 18265169 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 18265169 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 20453 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 20453 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 19412 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 19412 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 44303188 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 44303188 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 44303188 # number of overall hits +system.cpu.dcache.overall_hits::total 44303188 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 124631 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 124631 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1584732 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1584732 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 40 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 40 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1709363 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1709363 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1709363 # number of overall misses +system.cpu.dcache.overall_misses::total 1709363 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 4670085000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 4670085000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 120039172981 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 120039172981 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 743000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 743000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 124709257981 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 124709257981 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 124709257981 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 124709257981 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 26162650 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 26162650 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 20493 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 20493 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 19412 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 19412 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 46012551 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 46012551 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 46012551 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 46012551 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004764 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.004764 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.079836 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.079836 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001952 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.001952 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.037150 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.037150 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.037150 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.037150 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 37471.295264 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 37471.295264 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 75747.301740 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 75747.301740 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 18575 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 18575 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 72956.568020 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 72956.568020 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 72956.568020 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 72956.568020 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 4330 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 648 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 137 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 15 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 31.605839 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 43.200000 # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 129052 # number of writebacks +system.cpu.dcache.writebacks::total 129052 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 69229 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 69229 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1477415 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1477415 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 40 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 40 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1546644 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1546644 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1546644 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1546644 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55402 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 55402 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107317 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 107317 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 162719 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 162719 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 162719 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 162719 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2060277500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2060277500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8253592492 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8253592492 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10313869992 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10313869992 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10313869992 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10313869992 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002118 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002118 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005406 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005406 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003536 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.003536 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003536 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.003536 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 37187.782030 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 37187.782030 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76908.527931 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76908.527931 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 63384.546316 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 63384.546316 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 63384.546316 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 63384.546316 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/config.ini index 38e3365ee..8009459e0 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/config.ini +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/config.ini @@ -10,6 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a +clock=1000 init_param=0 kernel= load_addr_mask=1099511627775 @@ -29,7 +30,7 @@ system_port=system.membus.slave[0] [system.cpu] type=InOrderCPU -children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload +children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 RASSize=16 @@ -54,8 +55,6 @@ do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb fetchBuffSize=4 -functionTrace=false -functionTraceStart=0 function_trace=false function_trace_start=0 globalCtrBits=2 @@ -63,6 +62,7 @@ globalHistoryBits=13 globalPredictorSize=8192 instShiftAmt=2 interrupts=system.cpu.interrupts +isa=system.cpu.isa itb=system.cpu.itb localCtrBits=2 localHistoryBits=11 @@ -76,7 +76,6 @@ memBlockSize=64 multLatency=1 multRepeatRate=1 numThreads=1 -phase=0 predType=tournament profile=0 progress_interval=0 @@ -94,20 +93,22 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=2 is_top_level=true -latency=1000 max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=2 size=262144 subblock_size=0 system=system -tgts_per_mshr=5 +tgts_per_mshr=20 trace_addr=0 two_queue=false write_buffers=8 @@ -123,20 +124,22 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=2 is_top_level=true -latency=1000 max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=2 size=131072 subblock_size=0 system=system -tgts_per_mshr=5 +tgts_per_mshr=20 trace_addr=0 two_queue=false write_buffers=8 @@ -146,6 +149,9 @@ mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=AlphaInterrupts +[system.cpu.isa] +type=AlphaISA + [system.cpu.itb] type=AlphaTLB size=48 @@ -153,22 +159,24 @@ size=48 [system.cpu.l2cache] type=BaseCache addr_ranges=0:18446744073709551615 -assoc=2 +assoc=8 block_size=64 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=20 is_top_level=false -latency=10000 max_miss_count=0 -mshrs=10 +mshrs=20 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=20 size=2097152 subblock_size=0 system=system -tgts_per_mshr=5 +tgts_per_mshr=12 trace_addr=0 two_queue=false write_buffers=8 @@ -178,10 +186,10 @@ mem_side=system.membus.slave[1] [system.cpu.toL2Bus] type=CoherentBus block_size=64 -clock=1000 +clock=500 header_cycles=1 use_default_range=false -width=8 +width=32 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side @@ -191,12 +199,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=bzip2 input.source 1 -cwd=build/ALPHA/tests/fast/long/se/60.bzip2/alpha/tru64/inorder-timing +cwd=build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/inorder-timing egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/alpha/tru64/bzip2 +executable=/projects/pd/randd/dist/cpu2000/binaries/alpha/tru64/bzip2 gid=100 input=cin max_stack_size=67108864 @@ -214,18 +222,32 @@ clock=1000 header_cycles=1 use_default_range=false width=8 -master=system.physmem.port[0] +master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] -type=SimpleMemory +type=SimpleDRAM +addr_mapping=openmap +banks_per_rank=8 +clock=1000 conf_table_reported=false -file= in_addr_map=true -latency=30000 -latency_var=0 +lines_per_rowbuffer=64 +mem_sched_policy=fcfs null=false +page_policy=open range=0:134217727 +ranks_per_channel=2 +read_buffer_size=32 +tBURST=4000 +tCL=14000 +tRCD=14000 +tREFI=7800000 +tRFC=300000 +tRP=14000 +tWTR=1000 +write_buffer_size=32 +write_thresh_perc=70 zero=false port=system.membus.master[0] diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/simout b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/simout index 1e72565e9..43339a0ee 100755 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/simout +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 2 2012 08:30:56 -gem5 started Jul 2 2012 10:10:01 -gem5 executing on zizzer -command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/60.bzip2/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/fast/long/se/60.bzip2/alpha/tru64/inorder-timing +gem5 compiled Oct 30 2012 11:02:14 +gem5 started Oct 30 2012 12:40:49 +gem5 executing on u200540-lin +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. @@ -23,4 +23,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 996061088500 because target called exit() +Exiting @ tick 985089830500 because target called exit() diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt index 9335161f5..7470c11aa 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,66 +1,66 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.987579 # Number of seconds simulated -sim_ticks 987579062500 # Number of ticks simulated -final_tick 987579062500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.985090 # Number of seconds simulated +sim_ticks 985089830500 # Number of ticks simulated +final_tick 985089830500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 79028 # Simulator instruction rate (inst/s) -host_op_rate 79028 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 42888030 # Simulator tick rate (ticks/s) -host_mem_usage 458304 # Number of bytes of host memory used -host_seconds 23026.92 # Real time elapsed on the host +host_inst_rate 109003 # Simulator instruction rate (inst/s) +host_op_rate 109003 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 59005665 # Simulator tick rate (ticks/s) +host_mem_usage 485696 # Number of bytes of host memory used +host_seconds 16694.83 # Real time elapsed on the host sim_insts 1819780127 # Number of instructions simulated sim_ops 1819780127 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 54976 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 125364928 # Number of bytes read from this memory -system.physmem.bytes_read::total 125419904 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 125364992 # Number of bytes read from this memory +system.physmem.bytes_read::total 125419968 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 54976 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 54976 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 65155520 # Number of bytes written to this memory system.physmem.bytes_written::total 65155520 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 859 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1958827 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1959686 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1958828 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1959687 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 1018055 # Number of write requests responded to by this memory system.physmem.num_writes::total 1018055 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 55667 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 126941662 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 126997330 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 55667 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 55667 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 65974991 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 65974991 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 65974991 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 55667 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 126941662 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 192972321 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1959686 # Total number of read requests seen +system.physmem.bw_read::cpu.inst 55808 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 127262497 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 127318306 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 55808 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 55808 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 66141704 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 66141704 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 66141704 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 55808 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 127262497 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 193460010 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1959687 # Total number of read requests seen system.physmem.writeReqs 1018055 # Total number of write requests seen -system.physmem.cpureqs 2977741 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 125419904 # Total number of bytes read from memory +system.physmem.cpureqs 2977742 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 125419968 # Total number of bytes read from memory system.physmem.bytesWritten 65155520 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 125419904 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 125419968 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 65155520 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 577 # Number of read reqs serviced by write Q +system.physmem.servicedByWrQ 582 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 122432 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 123238 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 122431 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 123239 # Track reads on a per bank basis system.physmem.perBankRdReqs::2 122861 # Track reads on a per bank basis system.physmem.perBankRdReqs::3 121276 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 122601 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 122224 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 122602 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 122222 # Track reads on a per bank basis system.physmem.perBankRdReqs::6 124477 # Track reads on a per bank basis system.physmem.perBankRdReqs::7 123481 # Track reads on a per bank basis system.physmem.perBankRdReqs::8 121547 # Track reads on a per bank basis system.physmem.perBankRdReqs::9 122168 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 122611 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 120103 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 122610 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 120102 # Track reads on a per bank basis system.physmem.perBankRdReqs::12 120483 # Track reads on a per bank basis system.physmem.perBankRdReqs::13 121941 # Track reads on a per bank basis system.physmem.perBankRdReqs::14 124488 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 123178 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 123177 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 63120 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 63437 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 63438 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 63830 # Track writes on a per bank basis system.physmem.perBankWrReqs::3 63407 # Track writes on a per bank basis system.physmem.perBankWrReqs::4 63139 # Track writes on a per bank basis @@ -69,7 +69,7 @@ system.physmem.perBankWrReqs::6 63395 # Tr system.physmem.perBankWrReqs::7 63432 # Track writes on a per bank basis system.physmem.perBankWrReqs::8 62525 # Track writes on a per bank basis system.physmem.perBankWrReqs::9 63278 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 63961 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 63960 # Track writes on a per bank basis system.physmem.perBankWrReqs::11 63327 # Track writes on a per bank basis system.physmem.perBankWrReqs::12 63976 # Track writes on a per bank basis system.physmem.perBankWrReqs::13 64713 # Track writes on a per bank basis @@ -77,14 +77,14 @@ system.physmem.perBankWrReqs::14 65307 # Tr system.physmem.perBankWrReqs::15 64492 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 987579010500 # Total gap between requests +system.physmem.totGap 985089778500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 1959686 # Categorize read packet sizes +system.physmem.readPktSize::6 1959687 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -105,10 +105,10 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 1651837 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 192315 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 82006 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 32950 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 1651728 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 192414 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 82029 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 32933 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -138,9 +138,9 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 42531 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 44116 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 44251 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 42510 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 44115 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 44249 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 44263 # What write queue length does an incoming req see system.physmem.wrQLenPdf::4 44264 # What write queue length does an incoming req see system.physmem.wrQLenPdf::5 44264 # What write queue length does an incoming req see @@ -161,9 +161,9 @@ system.physmem.wrQLenPdf::19 44263 # Wh system.physmem.wrQLenPdf::20 44263 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 44263 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 44263 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 1733 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 148 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 13 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 1754 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 149 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 15 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see @@ -171,47 +171,47 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 19599583947 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 85189869947 # Sum of mem lat for all requests -system.physmem.totBusLat 7836436000 # Total cycles spent in databus access -system.physmem.totBankLat 57753850000 # Total cycles spent in bank access -system.physmem.avgQLat 10004.34 # Average queueing delay per request -system.physmem.avgBankLat 29479.65 # Average bank access latency per request +system.physmem.totQLat 19640844571 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 85229742571 # Sum of mem lat for all requests +system.physmem.totBusLat 7836420000 # Total cycles spent in databus access +system.physmem.totBankLat 57752478000 # Total cycles spent in bank access +system.physmem.avgQLat 10025.42 # Average queueing delay per request +system.physmem.avgBankLat 29479.01 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 43483.99 # Average memory access latency -system.physmem.avgRdBW 127.00 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 65.97 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 127.00 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 65.97 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 43504.43 # Average memory access latency +system.physmem.avgRdBW 127.32 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 66.14 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 127.32 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 66.14 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 1.21 # Data bus utilization in percentage system.physmem.avgRdQLen 0.09 # Average read queue length over time system.physmem.avgWrQLen 10.28 # Average write queue length over time -system.physmem.readRowHits 834542 # Number of row buffer hits during reads -system.physmem.writeRowHits 194109 # Number of row buffer hits during writes +system.physmem.readRowHits 834572 # Number of row buffer hits during reads +system.physmem.writeRowHits 194113 # Number of row buffer hits during writes system.physmem.readRowHitRate 42.60 # Row buffer hit rate for reads system.physmem.writeRowHitRate 19.07 # Row buffer hit rate for writes -system.physmem.avgGap 331653.76 # Average gap between requests +system.physmem.avgGap 330817.71 # Average gap between requests system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 444784364 # DTB read hits +system.cpu.dtb.read_hits 444784566 # DTB read hits system.cpu.dtb.read_misses 4897078 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 449681442 # DTB read accesses -system.cpu.dtb.write_hits 160833165 # DTB write hits +system.cpu.dtb.read_accesses 449681644 # DTB read accesses +system.cpu.dtb.write_hits 160833172 # DTB write hits system.cpu.dtb.write_misses 1701304 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 162534469 # DTB write accesses -system.cpu.dtb.data_hits 605617529 # DTB hits +system.cpu.dtb.write_accesses 162534476 # DTB write accesses +system.cpu.dtb.data_hits 605617738 # DTB hits system.cpu.dtb.data_misses 6598382 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 612215911 # DTB accesses -system.cpu.itb.fetch_hits 232120860 # ITB hits +system.cpu.dtb.data_accesses 612216120 # DTB accesses +system.cpu.itb.fetch_hits 231916745 # ITB hits system.cpu.itb.fetch_misses 22 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 232120882 # ITB accesses +system.cpu.itb.fetch_accesses 231916767 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -225,42 +225,42 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 29 # Number of system calls -system.cpu.numCycles 1975158126 # number of cpu cycles simulated +system.cpu.numCycles 1970179662 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.branch_predictor.lookups 328916009 # Number of BP lookups -system.cpu.branch_predictor.condPredicted 253846257 # Number of conditional branches predicted -system.cpu.branch_predictor.condIncorrect 140045817 # Number of conditional branches incorrect -system.cpu.branch_predictor.BTBLookups 232481413 # Number of BTB lookups -system.cpu.branch_predictor.BTBHits 138136467 # Number of BTB hits +system.cpu.branch_predictor.lookups 326556831 # Number of BP lookups +system.cpu.branch_predictor.condPredicted 252596788 # Number of conditional branches predicted +system.cpu.branch_predictor.condIncorrect 138232865 # Number of conditional branches incorrect +system.cpu.branch_predictor.BTBLookups 218937552 # Number of BTB lookups +system.cpu.branch_predictor.BTBHits 135479530 # Number of BTB hits system.cpu.branch_predictor.usedRAS 16767439 # Number of times the RAS was used to get a target. system.cpu.branch_predictor.RASInCorrect 6 # Number of incorrect RAS predictions. -system.cpu.branch_predictor.BTBHitPct 59.418284 # BTB Hit Percentage -system.cpu.branch_predictor.predictedTaken 175138589 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 153777420 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 1669811898 # Number of Reads from Int. Register File +system.cpu.branch_predictor.BTBHitPct 61.880444 # BTB Hit Percentage +system.cpu.branch_predictor.predictedTaken 172296521 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 154260310 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 1667620352 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 1376202617 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 3046014515 # Total Accesses (Read+Write) to the Int. Register File -system.cpu.regfile_manager.floatRegFileReads 237 # Number of Reads from FP Register File +system.cpu.regfile_manager.intRegFileAccesses 3043822969 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.floatRegFileReads 232 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 345 # Number of Writes to FP Register File -system.cpu.regfile_manager.floatRegFileAccesses 582 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 650984890 # Number of Registers Read Through Forwarding Logic -system.cpu.agen_unit.agens 617988746 # Number of Address Generations -system.cpu.execution_unit.predictedTakenIncorrect 121313944 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.execution_unit.predictedNotTakenIncorrect 12133415 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.execution_unit.mispredicted 133447359 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.predicted 81752917 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.mispredictPct 62.010775 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.executions 1139622793 # Number of Instructions Executed. +system.cpu.regfile_manager.floatRegFileAccesses 577 # Total Accesses (Read+Write) to the FP Register File +system.cpu.regfile_manager.regForwards 651716748 # Number of Registers Read Through Forwarding Logic +system.cpu.agen_unit.agens 617888959 # Number of Address Generations +system.cpu.execution_unit.predictedTakenIncorrect 120522099 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.execution_unit.predictedNotTakenIncorrect 11112308 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.execution_unit.mispredicted 131634407 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.predicted 83565858 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.mispredictPct 61.168329 # Percentage of Incorrect Branches Predicts +system.cpu.execution_unit.executions 1139351244 # Number of Instructions Executed. system.cpu.mult_div_unit.multiplies 75 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 1746581569 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 1741570972 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 7474420 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 398305853 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 1576852273 # Number of cycles cpu stages are processed. -system.cpu.activity 79.834230 # Percentage of cycles cpu is active +system.cpu.timesIdled 7474606 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 398498363 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 1571681299 # Number of cycles cpu stages are processed. +system.cpu.activity 79.773501 # Percentage of cycles cpu is active system.cpu.comLoads 444595663 # Number of Load instructions committed system.cpu.comStores 160728502 # Number of Store instructions committed system.cpu.comBranches 214632552 # Number of Branches instructions committed @@ -272,72 +272,72 @@ system.cpu.committedInsts 1819780127 # Nu system.cpu.committedOps 1819780127 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 1819780127 # Number of Instructions committed (Total) -system.cpu.cpi 1.085383 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 1.082647 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 1.085383 # CPI: Total CPI of All Threads -system.cpu.ipc 0.921334 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 1.082647 # CPI: Total CPI of All Threads +system.cpu.ipc 0.923662 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 0.921334 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 784384186 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 1190773940 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 60.287525 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 1042820423 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 932337703 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 47.203193 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 1001198544 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 973959582 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 49.310461 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 1565492748 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 409665378 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 20.740890 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 952315389 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 1022842737 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 51.785360 # Percentage of cycles stage was utilized (processing insts). +system.cpu.ipc_total 0.923662 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 783567133 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 1186612529 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 60.228646 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 1036391021 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 933788641 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 47.396116 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 997796043 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 972383619 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 49.355073 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 1560555740 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 409623922 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 20.791196 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 948846788 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 1021332874 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 51.839581 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 1 # number of replacements -system.cpu.icache.tagsinuse 667.497042 # Cycle average of tags in use -system.cpu.icache.total_refs 232119756 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 667.601881 # Cycle average of tags in use +system.cpu.icache.total_refs 231915637 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 859 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 270220.903376 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 269983.279395 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 667.497042 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.325926 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.325926 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 232119756 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 232119756 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 232119756 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 232119756 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 232119756 # number of overall hits -system.cpu.icache.overall_hits::total 232119756 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1104 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1104 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1104 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1104 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1104 # number of overall misses -system.cpu.icache.overall_misses::total 1104 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 58767000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 58767000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 58767000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 58767000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 58767000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 58767000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 232120860 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 232120860 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 232120860 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 232120860 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 232120860 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 232120860 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 667.601881 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.325977 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.325977 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 231915637 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 231915637 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 231915637 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 231915637 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 231915637 # number of overall hits +system.cpu.icache.overall_hits::total 231915637 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1108 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1108 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1108 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1108 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1108 # number of overall misses +system.cpu.icache.overall_misses::total 1108 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 59929000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 59929000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 59929000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 59929000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 59929000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 59929000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 231916745 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 231916745 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 231916745 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 231916745 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 231916745 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 231916745 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000005 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000005 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000005 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000005 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000005 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000005 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53230.978261 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 53230.978261 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 53230.978261 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 53230.978261 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 53230.978261 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 53230.978261 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54087.545126 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 54087.545126 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 54087.545126 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 54087.545126 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 54087.545126 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 54087.545126 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 63 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked @@ -346,203 +346,95 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 63 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 245 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 245 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 245 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 245 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 245 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 245 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 249 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 249 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 249 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 249 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 249 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 249 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 859 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 859 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 859 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 859 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 859 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 859 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 46993000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 46993000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 46993000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 46993000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 46993000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 46993000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 47313000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 47313000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 47313000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 47313000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 47313000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 47313000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000004 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000004 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000004 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54706.635623 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54706.635623 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54706.635623 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 54706.635623 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54706.635623 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 54706.635623 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 55079.161816 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 55079.161816 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 55079.161816 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 55079.161816 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 55079.161816 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 55079.161816 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 9107377 # number of replacements -system.cpu.dcache.tagsinuse 4082.124534 # Cycle average of tags in use -system.cpu.dcache.total_refs 593539067 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 9111473 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 65.141944 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 12681076000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4082.124534 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.996612 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.996612 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 437268755 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 437268755 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 156270312 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 156270312 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 593539067 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 593539067 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 593539067 # number of overall hits -system.cpu.dcache.overall_hits::total 593539067 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 7326908 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 7326908 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 4458190 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 4458190 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 11785098 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 11785098 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 11785098 # number of overall misses -system.cpu.dcache.overall_misses::total 11785098 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 160313092500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 160313092500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 195290221000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 195290221000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 355603313500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 355603313500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 355603313500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 355603313500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 444595663 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 444595663 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 160728502 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 605324165 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 605324165 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 605324165 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 605324165 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.016480 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.016480 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.027737 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.027737 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.019469 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.019469 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.019469 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.019469 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21880.047149 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 21880.047149 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 43804.822361 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 43804.822361 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 30173.980182 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 30173.980182 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 30173.980182 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 30173.980182 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 9234267 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 4818811 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 358092 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 65601 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 25.787415 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 73.456365 # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3693297 # number of writebacks -system.cpu.dcache.writebacks::total 3693297 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 104632 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 104632 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2568993 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2568993 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2673625 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2673625 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2673625 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2673625 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7222276 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7222276 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889197 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1889197 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9111473 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9111473 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9111473 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9111473 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 144007395000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 144007395000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 67943434500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 67943434500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 211950829500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 211950829500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 211950829500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 211950829500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.016245 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.016245 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011754 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.011754 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.015052 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.015052 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.015052 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.015052 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19939.336990 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19939.336990 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35964.187165 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35964.187165 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23261.971967 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 23261.971967 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23261.971967 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 23261.971967 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 1926955 # number of replacements -system.cpu.l2cache.tagsinuse 30885.794112 # Cycle average of tags in use +system.cpu.l2cache.replacements 1926956 # number of replacements +system.cpu.l2cache.tagsinuse 30892.708902 # Cycle average of tags in use system.cpu.l2cache.total_refs 8958711 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 1956748 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 4.578367 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 67633900002 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 15038.473814 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 35.309498 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 15812.010801 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.458938 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.001078 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.482544 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.942560 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.data 6044303 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 6044303 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 3693297 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 3693297 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1108343 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1108343 # number of ReadExReq hits +system.cpu.l2cache.sampled_refs 1956749 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 4.578365 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 67095700002 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::writebacks 15036.085957 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 35.170225 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 15821.452721 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.458865 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.001073 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.482832 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.942771 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.data 6044304 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 6044304 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 3693296 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 3693296 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 1108342 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 1108342 # number of ReadExReq hits system.cpu.l2cache.demand_hits::cpu.data 7152646 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::total 7152646 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.data 7152646 # number of overall hits system.cpu.l2cache.overall_hits::total 7152646 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.inst 859 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 1177531 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 1178390 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 1177532 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 1178391 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 781296 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 781296 # number of ReadExReq misses system.cpu.l2cache.demand_misses::cpu.inst 859 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 1958827 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 1959686 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 1958828 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 1959687 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 859 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 1958827 # number of overall misses -system.cpu.l2cache.overall_misses::total 1959686 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 46130000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 76211329000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 76257459000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 54802656500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 54802656500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 46130000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 131013985500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 131060115500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 46130000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 131013985500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 131060115500 # number of overall miss cycles +system.cpu.l2cache.overall_misses::cpu.data 1958828 # number of overall misses +system.cpu.l2cache.overall_misses::total 1959687 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 46450000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 76219681500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 76266131500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 54834553000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 54834553000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 46450000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 131054234500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 131100684500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 46450000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 131054234500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 131100684500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 859 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 7221834 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 7222693 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 3693297 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 3693297 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 1889639 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 1889639 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 7221836 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 7222695 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 3693296 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 3693296 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 1889638 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 1889638 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 859 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 9111473 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 9112332 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 9111474 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 9112333 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 859 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 9111473 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 9112332 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 9111474 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 9112333 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.163052 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::total 0.163151 # miss rate for ReadReq accesses @@ -554,17 +446,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.215059 # system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.214985 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.215059 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53701.979045 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 64721.293112 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 64713.260466 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70143.270284 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70143.270284 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53701.979045 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 66883.898119 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 66878.120015 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53701.979045 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 66883.898119 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 66878.120015 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 54074.505239 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 64728.331374 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 64720.565160 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70184.095400 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70184.095400 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 54074.505239 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 66904.411464 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 66898.787664 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 54074.505239 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 66904.411464 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 66898.787664 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -576,27 +468,27 @@ system.cpu.l2cache.cache_copies 0 # nu system.cpu.l2cache.writebacks::writebacks 1018055 # number of writebacks system.cpu.l2cache.writebacks::total 1018055 # number of writebacks system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 859 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1177531 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 1178390 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1177532 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1178391 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 781296 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 781296 # number of ReadExReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 859 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 1958827 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 1959686 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1958828 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 1959687 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 859 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 1958827 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 1959686 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 35264420 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 61190782598 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 61226047018 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 44920930070 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 44920930070 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 35264420 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 106111712668 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 106146977088 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 35264420 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 106111712668 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 106146977088 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::cpu.data 1958828 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 1959687 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 35585421 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 61199276421 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 61234861842 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 44953209175 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 44953209175 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 35585421 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 106152485596 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 106188071017 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 35585421 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 106152485596 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 106188071017 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.163052 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.163151 # mshr miss rate for ReadReq accesses @@ -608,17 +500,125 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.215059 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214985 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.215059 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41052.875437 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 51965.326261 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 51957.371514 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57495.405160 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57495.405160 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41052.875437 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 54171.048627 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54165.298465 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41052.875437 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 54171.048627 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54165.298465 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41426.566938 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 51972.495373 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 51964.807812 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57536.719982 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57536.719982 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41426.566938 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 54191.835933 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54186.240464 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41426.566938 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 54191.835933 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54186.240464 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.replacements 9107378 # number of replacements +system.cpu.dcache.tagsinuse 4082.173275 # Cycle average of tags in use +system.cpu.dcache.total_refs 593539212 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 9111474 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 65.141953 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 12614691000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4082.173275 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.996624 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.996624 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 437268752 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 437268752 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 156270460 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 156270460 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 593539212 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 593539212 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 593539212 # number of overall hits +system.cpu.dcache.overall_hits::total 593539212 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 7326911 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 7326911 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 4458042 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 4458042 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 11784953 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 11784953 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 11784953 # number of overall misses +system.cpu.dcache.overall_misses::total 11784953 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 160323624500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 160323624500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 195351556000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 195351556000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 355675180500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 355675180500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 355675180500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 355675180500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 444595663 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 444595663 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 160728502 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 605324165 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 605324165 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 605324165 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 605324165 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.016480 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.016480 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.027736 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.027736 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.019469 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.019469 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.019469 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.019469 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21881.475631 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 21881.475631 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 43820.034894 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 43820.034894 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 30180.449638 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 30180.449638 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 30180.449638 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 30180.449638 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 9247830 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 4818517 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 358256 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 65602 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 25.813469 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 73.450764 # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 3693296 # number of writebacks +system.cpu.dcache.writebacks::total 3693296 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 104633 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 104633 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2568846 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2568846 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2673479 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2673479 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2673479 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2673479 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7222278 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7222278 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889196 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1889196 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 9111474 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9111474 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9111474 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9111474 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 144015924000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 144015924000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 67975303000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 67975303000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 211991227000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 211991227000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 211991227000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 211991227000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.016245 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.016245 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011754 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.011754 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.015052 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.015052 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.015052 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.015052 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19940.512398 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19940.512398 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35981.075018 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35981.075018 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23266.403109 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 23266.403109 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23266.403109 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 23266.403109 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini index 2f4837fe9..fb395fc71 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini @@ -10,6 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a +clock=1000 init_param=0 kernel= load_addr_mask=1099511627775 @@ -29,7 +30,7 @@ system_port=system.membus.slave[0] [system.cpu] type=DerivO3CPU -children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload +children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -77,6 +78,7 @@ iewToFetchDelay=1 iewToRenameDelay=1 instShiftAmt=2 interrupts=system.cpu.interrupts +isa=system.cpu.isa issueToExecuteDelay=1 issueWidth=8 itb=system.cpu.itb @@ -95,7 +97,6 @@ numPhysIntRegs=256 numROBEntries=192 numRobs=1 numThreads=1 -phase=0 predType=tournament profile=0 progress_interval=0 @@ -129,16 +130,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=2 is_top_level=true -latency=1000 max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=2 size=262144 subblock_size=0 system=system @@ -421,16 +424,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=2 is_top_level=true -latency=1000 max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=2 size=131072 subblock_size=0 system=system @@ -444,6 +449,9 @@ mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=AlphaInterrupts +[system.cpu.isa] +type=AlphaISA + [system.cpu.itb] type=AlphaTLB size=48 @@ -451,22 +459,24 @@ size=48 [system.cpu.l2cache] type=BaseCache addr_ranges=0:18446744073709551615 -assoc=2 +assoc=8 block_size=64 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=20 is_top_level=false -latency=1000 max_miss_count=0 -mshrs=10 +mshrs=20 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=20 size=2097152 subblock_size=0 system=system -tgts_per_mshr=5 +tgts_per_mshr=12 trace_addr=0 two_queue=false write_buffers=8 @@ -476,10 +486,10 @@ mem_side=system.membus.slave[1] [system.cpu.toL2Bus] type=CoherentBus block_size=64 -clock=1000 +clock=500 header_cycles=1 use_default_range=false -width=8 +width=32 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side @@ -489,12 +499,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=bzip2 input.source 1 -cwd=build/ALPHA/tests/fast/long/se/60.bzip2/alpha/tru64/o3-timing +cwd=build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/o3-timing egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/alpha/tru64/bzip2 +executable=/projects/pd/randd/dist/cpu2000/binaries/alpha/tru64/bzip2 gid=100 input=cin max_stack_size=67108864 @@ -512,18 +522,32 @@ clock=1000 header_cycles=1 use_default_range=false width=8 -master=system.physmem.port[0] +master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] -type=SimpleMemory +type=SimpleDRAM +addr_mapping=openmap +banks_per_rank=8 +clock=1000 conf_table_reported=false -file= in_addr_map=true -latency=30000 -latency_var=0 +lines_per_rowbuffer=64 +mem_sched_policy=fcfs null=false +page_policy=open range=0:134217727 +ranks_per_channel=2 +read_buffer_size=32 +tBURST=4000 +tCL=14000 +tRCD=14000 +tREFI=7800000 +tRFC=300000 +tRP=14000 +tWTR=1000 +write_buffer_size=32 +write_thresh_perc=70 zero=false port=system.membus.master[0] diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout index 3e5b31249..78436c89b 100755 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 2 2012 08:30:56 -gem5 started Jul 2 2012 10:10:10 -gem5 executing on zizzer -command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/60.bzip2/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/fast/long/se/60.bzip2/alpha/tru64/o3-timing +gem5 compiled Oct 30 2012 11:02:14 +gem5 started Oct 30 2012 12:41:35 +gem5 executing on u200540-lin +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. @@ -23,4 +23,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 621254733000 because target called exit() +Exiting @ tick 655919824500 because target called exit() diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt index 4dfb5e529..c867780d0 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt @@ -1,90 +1,90 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.676099 # Number of seconds simulated -sim_ticks 676099363500 # Number of ticks simulated -final_tick 676099363500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.655920 # Number of seconds simulated +sim_ticks 655919824500 # Number of ticks simulated +final_tick 655919824500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 178127 # Simulator instruction rate (inst/s) -host_op_rate 178127 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 69371375 # Simulator tick rate (ticks/s) -host_mem_usage 459324 # Number of bytes of host memory used -host_seconds 9746.09 # Real time elapsed on the host +host_inst_rate 137989 # Simulator instruction rate (inst/s) +host_op_rate 137989 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 52135439 # Simulator tick rate (ticks/s) +host_mem_usage 496344 # Number of bytes of host memory used +host_seconds 12581.07 # Real time elapsed on the host sim_insts 1736043781 # Number of instructions simulated sim_ops 1736043781 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 61568 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 125805120 # Number of bytes read from this memory -system.physmem.bytes_read::total 125866688 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 61568 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 61568 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 65265216 # Number of bytes written to this memory -system.physmem.bytes_written::total 65265216 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 962 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1965705 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1966667 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1019769 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1019769 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 91064 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 186074898 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 186165961 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 91064 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 91064 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 96531989 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 96531989 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 96531989 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 91064 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 186074898 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 282697950 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1966667 # Total number of read requests seen -system.physmem.writeReqs 1019769 # Total number of write requests seen -system.physmem.cpureqs 2986436 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 125866688 # Total number of bytes read from memory -system.physmem.bytesWritten 65265216 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 125866688 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 65265216 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 625 # Number of read reqs serviced by write Q +system.physmem.bytes_read::cpu.inst 61504 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 125796416 # Number of bytes read from this memory +system.physmem.bytes_read::total 125857920 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 61504 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 61504 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 65262592 # Number of bytes written to this memory +system.physmem.bytes_written::total 65262592 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 961 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1965569 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1966530 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1019728 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1019728 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 93768 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 191786269 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 191880037 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 93768 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 93768 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 99497819 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 99497819 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 99497819 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 93768 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 191786269 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 291377856 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1966530 # Total number of read requests seen +system.physmem.writeReqs 1019728 # Total number of write requests seen +system.physmem.cpureqs 2986258 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 125857920 # Total number of bytes read from memory +system.physmem.bytesWritten 65262592 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 125857920 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 65262592 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 571 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 123034 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 123551 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 123227 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 121682 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 123042 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 122572 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 124906 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 123907 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 121965 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 122878 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 123012 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 120476 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 120832 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 122358 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 124956 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 123644 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 63285 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 63494 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 63931 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 63515 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 63255 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 62796 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 63501 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 63537 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 62612 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 63480 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 64069 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 63419 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 64057 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 64815 # Track writes on a per bank basis +system.physmem.perBankRdReqs::0 123004 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 123537 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 123239 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 121669 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 123045 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 122605 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 124908 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 123890 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 121960 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 122835 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 123027 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 120429 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 120849 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 122324 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 124974 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 123664 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 63268 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 63478 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 63945 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 63503 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 63256 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 62809 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 63505 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 63532 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 62611 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 63461 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 64078 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 63409 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 64056 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 64812 # Track writes on a per bank basis system.physmem.perBankWrReqs::14 65441 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 64562 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 64564 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 676099295000 # Total gap between requests +system.physmem.totGap 655919756000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 1966667 # Categorize read packet sizes +system.physmem.readPktSize::6 1966530 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -93,7 +93,7 @@ system.physmem.writePktSize::2 0 # ca system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 1019769 # categorize write packet sizes +system.physmem.writePktSize::6 1019728 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -105,13 +105,13 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 1634338 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 235140 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 70255 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 26277 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 26 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 5 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 1634092 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 234966 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 70615 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 26268 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 18 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see @@ -138,80 +138,80 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 43276 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 44165 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 44311 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 43349 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 44157 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 44312 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 44332 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 44338 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 44338 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 44338 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 44338 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 44338 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 44338 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 44338 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 44338 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 44338 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 44338 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 44338 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 44338 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 44338 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 44338 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 44337 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 44337 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 44337 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 44337 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 44337 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 1062 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 173 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 27 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 44335 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 44336 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 44336 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 44336 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 44336 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 44336 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 44336 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 44336 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 44336 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 44336 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 44336 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 44336 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 44336 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 44336 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 44336 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 44336 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 44336 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 44336 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 44336 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 987 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 179 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 24 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 20663639504 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 85829737504 # Sum of mem lat for all requests -system.physmem.totBusLat 7864168000 # Total cycles spent in databus access -system.physmem.totBankLat 57301930000 # Total cycles spent in bank access -system.physmem.avgQLat 10510.27 # Average queueing delay per request -system.physmem.avgBankLat 29145.83 # Average bank access latency per request +system.physmem.totQLat 20705208242 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 85868216242 # Sum of mem lat for all requests +system.physmem.totBusLat 7863836000 # Total cycles spent in databus access +system.physmem.totBankLat 57299172000 # Total cycles spent in bank access +system.physmem.avgQLat 10531.86 # Average queueing delay per request +system.physmem.avgBankLat 29145.66 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 43656.11 # Average memory access latency -system.physmem.avgRdBW 186.17 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 96.53 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 186.17 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 96.53 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 43677.52 # Average memory access latency +system.physmem.avgRdBW 191.88 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 99.50 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 191.88 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 99.50 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 1.77 # Data bus utilization in percentage +system.physmem.busUtil 1.82 # Data bus utilization in percentage system.physmem.avgRdQLen 0.13 # Average read queue length over time -system.physmem.avgWrQLen 11.69 # Average write queue length over time -system.physmem.readRowHits 840809 # Number of row buffer hits during reads -system.physmem.writeRowHits 193935 # Number of row buffer hits during writes +system.physmem.avgWrQLen 10.55 # Average write queue length over time +system.physmem.readRowHits 840760 # Number of row buffer hits during reads +system.physmem.writeRowHits 193886 # Number of row buffer hits during writes system.physmem.readRowHitRate 42.77 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 19.02 # Row buffer hit rate for writes -system.physmem.avgGap 226390.02 # Average gap between requests +system.physmem.writeRowHitRate 19.01 # Row buffer hit rate for writes +system.physmem.avgGap 219646.04 # Average gap between requests system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 623300287 # DTB read hits -system.cpu.dtb.read_misses 11248161 # DTB read misses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 634548448 # DTB read accesses -system.cpu.dtb.write_hits 212126260 # DTB write hits -system.cpu.dtb.write_misses 7156273 # DTB write misses +system.cpu.dtb.read_hits 613741491 # DTB read hits +system.cpu.dtb.read_misses 11247891 # DTB read misses +system.cpu.dtb.read_acv 2 # DTB read access violations +system.cpu.dtb.read_accesses 624989382 # DTB read accesses +system.cpu.dtb.write_hits 212247245 # DTB write hits +system.cpu.dtb.write_misses 7144332 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 219282533 # DTB write accesses -system.cpu.dtb.data_hits 835426547 # DTB hits -system.cpu.dtb.data_misses 18404434 # DTB misses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 853830981 # DTB accesses -system.cpu.itb.fetch_hits 409165317 # ITB hits -system.cpu.itb.fetch_misses 53 # ITB misses +system.cpu.dtb.write_accesses 219391577 # DTB write accesses +system.cpu.dtb.data_hits 825988736 # DTB hits +system.cpu.dtb.data_misses 18392223 # DTB misses +system.cpu.dtb.data_acv 2 # DTB access violations +system.cpu.dtb.data_accesses 844380959 # DTB accesses +system.cpu.itb.fetch_hits 390708850 # ITB hits +system.cpu.itb.fetch_misses 38 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 409165370 # ITB accesses +system.cpu.itb.fetch_accesses 390708888 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -225,246 +225,246 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 29 # Number of system calls -system.cpu.numCycles 1352198728 # number of cpu cycles simulated +system.cpu.numCycles 1311839650 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 392126599 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 302845458 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 19199722 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 274650283 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 270818962 # Number of BTB hits +system.cpu.BPredUnit.lookups 381024003 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 296029232 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 16079219 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 261934224 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 259237388 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 25776268 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 6145 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 421462775 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 3238747115 # Number of instructions fetch has processed -system.cpu.fetch.Branches 392126599 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 296595230 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 591261083 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 148936596 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 163448952 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 730 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1316 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 23 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 409165317 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 10196267 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1298229870 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.494741 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.143526 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 24703724 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 3041 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 402148068 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 3157560086 # Number of instructions fetch has processed +system.cpu.fetch.Branches 381024003 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 283941112 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 573880213 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 140086808 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 165153102 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 27 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1285 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 13 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 390708850 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 8061624 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1257505437 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.510971 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.156516 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 706968787 54.46% 54.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 44358932 3.42% 57.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 22743833 1.75% 59.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 41944085 3.23% 62.86% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 132056857 10.17% 73.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 64435006 4.96% 77.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 41239075 3.18% 81.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 30635006 2.36% 83.53% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 213848289 16.47% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 683625224 54.36% 54.36% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 42619367 3.39% 57.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 21744894 1.73% 59.48% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 39684878 3.16% 62.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 129121337 10.27% 72.91% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 61516601 4.89% 77.80% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 38545793 3.07% 80.86% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 28125558 2.24% 83.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 212521785 16.90% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1298229870 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.289992 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.395171 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 455239490 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 145264666 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 557656082 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 18015537 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 122054095 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 61382914 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 1012 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 3154733525 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 2110 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 122054095 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 478678718 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 92924622 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 7988 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 549590922 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 54973525 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 3070816575 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 560752 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1743859 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 49056518 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 2295520192 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3973370931 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3971968228 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1402703 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 1257505437 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.290450 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.406971 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 433733980 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 146719588 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 542274905 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 18455051 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 116321913 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 58305735 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 954 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 3085307728 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 2035 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 116321913 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 456557347 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 93252503 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 5104 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 535232007 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 56136563 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 3003562340 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 560555 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1735251 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 50037437 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 2245657329 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3895152131 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3893909248 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1242883 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1376202963 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 919317229 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 211 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 209 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 118384405 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 691487195 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 258255800 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 68719353 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 37210437 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2756294295 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 187 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2536632821 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 3950694 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 1007358741 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 432150244 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 158 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1298229870 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.953917 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.961710 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 869454366 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 190 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 189 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 120669951 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 679225578 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 255273844 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 68130212 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 37368209 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2722510883 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 144 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2508555980 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 3078936 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 977267031 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 413974741 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 115 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1257505437 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.994867 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.973352 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 442263739 34.07% 34.07% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 208903385 16.09% 50.16% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 191557841 14.76% 64.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 152463661 11.74% 76.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 137672348 10.60% 87.26% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 81203098 6.25% 93.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 63863451 4.92% 98.44% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 15081593 1.16% 99.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 5220754 0.40% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 417762073 33.22% 33.22% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 201459942 16.02% 49.24% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 185268981 14.73% 63.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 153261704 12.19% 76.16% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 133079768 10.58% 86.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 81048988 6.45% 93.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 65262511 5.19% 98.38% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 15257874 1.21% 99.59% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 5103596 0.41% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1298229870 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1257505437 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 2156518 11.37% 11.37% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 11.37% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 11.37% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.37% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.37% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.37% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 11.37% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.37% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 11.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 11.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.37% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 12254343 64.62% 76.00% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 4551680 24.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 2150864 11.67% 11.67% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 11.67% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 11.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 11.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 11.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 11.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.67% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 11870466 64.42% 76.09% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 4405017 23.91% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1658475044 65.38% 65.38% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 107 0.00% 65.38% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.38% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 273 0.00% 65.38% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 15 0.00% 65.38% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 163 0.00% 65.38% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 34 0.00% 65.38% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 24 0.00% 65.38% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.38% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 652209568 25.71% 91.09% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 225947593 8.91% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1643219876 65.50% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 107 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 253 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 15 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 157 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 26 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 24 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 641326950 25.57% 91.07% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 224008572 8.93% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2536632821 # Type of FU issued -system.cpu.iq.rate 1.875932 # Inst issue rate -system.cpu.iq.fu_busy_cnt 18962541 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.007475 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 6392425036 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 3762406457 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 2431792022 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 1983711 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1351957 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 870252 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2554620629 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 974733 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 62690136 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2508555980 # Type of FU issued +system.cpu.iq.rate 1.912243 # Inst issue rate +system.cpu.iq.fu_busy_cnt 18426347 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.007345 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 6294223850 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 3698666551 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 2412312770 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 1898830 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 1217307 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 851008 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2526043830 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 938497 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 62613731 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 246891532 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 263108 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 106999 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 97527298 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 234629915 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 264851 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 107543 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 94545342 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 177 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1449625 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 100 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1452143 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 122054095 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 42236040 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1169448 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2901607263 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 18449890 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 691487195 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 258255800 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 187 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 295034 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 19978 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 106999 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 13433299 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 8961049 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 22394348 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 2485079596 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 634549945 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 51553225 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 116321913 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 41870148 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1143259 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2864507060 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 8845706 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 679225578 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 255273844 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 144 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 295805 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 17199 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 107543 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 10354551 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 8556122 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 18910673 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 2461271813 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 624989902 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 47284167 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 145312781 # number of nop insts executed -system.cpu.iew.exec_refs 853832523 # number of memory reference insts executed -system.cpu.iew.exec_branches 304694140 # Number of branches executed -system.cpu.iew.exec_stores 219282578 # Number of stores executed -system.cpu.iew.exec_rate 1.837806 # Inst execution rate -system.cpu.iew.wb_sent 2461943508 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 2432662274 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1394848463 # num instructions producing a value -system.cpu.iew.wb_consumers 1766930878 # num instructions consuming a value +system.cpu.iew.exec_nop 141996033 # number of nop insts executed +system.cpu.iew.exec_refs 844381512 # number of memory reference insts executed +system.cpu.iew.exec_branches 300766985 # Number of branches executed +system.cpu.iew.exec_stores 219391610 # Number of stores executed +system.cpu.iew.exec_rate 1.876199 # Inst execution rate +system.cpu.iew.wb_sent 2441119325 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 2413163778 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1388569148 # num instructions producing a value +system.cpu.iew.wb_consumers 1764314853 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.799042 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.789419 # average fanout of values written-back +system.cpu.iew.wb_rate 1.839526 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.787030 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 860868467 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 823556826 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 29 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 19198826 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1176175775 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.547201 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.484504 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 16078403 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1141183524 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.594643 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.519930 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 658247718 55.97% 55.97% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 175915600 14.96% 70.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 90578875 7.70% 78.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 53177308 4.52% 83.14% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 35329719 3.00% 86.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 23851430 2.03% 88.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 23326017 1.98% 90.16% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 23350140 1.99% 92.14% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 92398968 7.86% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 628040121 55.03% 55.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 174132211 15.26% 70.29% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 86354537 7.57% 77.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 53988637 4.73% 82.59% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 34269513 3.00% 85.59% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 24750272 2.17% 87.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 22050678 1.93% 89.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 22940990 2.01% 91.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 94656565 8.29% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1176175775 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1141183524 # Number of insts commited each cycle system.cpu.commit.committedInsts 1819780126 # Number of instructions committed system.cpu.commit.committedOps 1819780126 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -475,317 +475,189 @@ system.cpu.commit.branches 214632552 # Nu system.cpu.commit.fp_insts 805525 # Number of committed floating point instructions. system.cpu.commit.int_insts 1718967519 # Number of committed integer instructions. system.cpu.commit.function_calls 16767440 # Number of function calls committed. -system.cpu.commit.bw_lim_events 92398968 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 94656565 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3678646200 # The number of ROB reads -system.cpu.rob.rob_writes 5483460601 # The number of ROB writes -system.cpu.timesIdled 829567 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 53968858 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 3604084711 # The number of ROB reads +system.cpu.rob.rob_writes 5403096067 # The number of ROB writes +system.cpu.timesIdled 804666 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 54334213 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1736043781 # Number of Instructions Simulated system.cpu.committedOps 1736043781 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 1736043781 # Number of Instructions Simulated -system.cpu.cpi 0.778897 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.778897 # CPI: Total CPI of All Threads -system.cpu.ipc 1.283867 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.283867 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3341460388 # number of integer regfile reads -system.cpu.int_regfile_writes 1950187380 # number of integer regfile writes -system.cpu.fp_regfile_reads 51936 # number of floating regfile reads -system.cpu.fp_regfile_writes 538 # number of floating regfile writes +system.cpu.cpi 0.755649 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.755649 # CPI: Total CPI of All Threads +system.cpu.ipc 1.323366 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.323366 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3316903206 # number of integer regfile reads +system.cpu.int_regfile_writes 1931453212 # number of integer regfile writes +system.cpu.fp_regfile_reads 30791 # number of floating regfile reads +system.cpu.fp_regfile_writes 509 # number of floating regfile writes system.cpu.misc_regfile_reads 25 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.icache.replacements 1 # number of replacements -system.cpu.icache.tagsinuse 771.801258 # Cycle average of tags in use -system.cpu.icache.total_refs 409163812 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 962 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 425326.207900 # Average number of references to valid blocks. +system.cpu.icache.tagsinuse 768.875728 # Cycle average of tags in use +system.cpu.icache.total_refs 390707378 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 961 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 406563.348595 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 771.801258 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.376856 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.376856 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 409163812 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 409163812 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 409163812 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 409163812 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 409163812 # number of overall hits -system.cpu.icache.overall_hits::total 409163812 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1504 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1504 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1504 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1504 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1504 # number of overall misses -system.cpu.icache.overall_misses::total 1504 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 80548999 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 80548999 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 80548999 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 80548999 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 80548999 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 80548999 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 409165316 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 409165316 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 409165316 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 409165316 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 409165316 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 409165316 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 768.875728 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.375428 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.375428 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 390707378 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 390707378 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 390707378 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 390707378 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 390707378 # number of overall hits +system.cpu.icache.overall_hits::total 390707378 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1472 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1472 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1472 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1472 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1472 # number of overall misses +system.cpu.icache.overall_misses::total 1472 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 78332000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 78332000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 78332000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 78332000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 78332000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 78332000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 390708850 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 390708850 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 390708850 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 390708850 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 390708850 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 390708850 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53556.515293 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 53556.515293 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 53556.515293 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 53556.515293 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 53556.515293 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 53556.515293 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 1029 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53214.673913 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 53214.673913 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 53214.673913 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 53214.673913 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 53214.673913 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 53214.673913 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 187 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 7 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 3 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 147 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 62.333333 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 542 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 542 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 542 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 542 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 542 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 542 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 962 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 962 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 962 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 962 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 962 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 962 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 57069999 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 57069999 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 57069999 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 57069999 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 57069999 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 57069999 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 511 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 511 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 511 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 511 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 511 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 511 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 961 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 961 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 961 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 961 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 961 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 961 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 56098500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 56098500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 56098500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 56098500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 56098500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 56098500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 59324.323285 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 59324.323285 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 59324.323285 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 59324.323285 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 59324.323285 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 59324.323285 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 58375.130073 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 58375.130073 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 58375.130073 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 58375.130073 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 58375.130073 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 58375.130073 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 9177397 # number of replacements -system.cpu.dcache.tagsinuse 4086.580271 # Cycle average of tags in use -system.cpu.dcache.total_refs 703801568 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 9181493 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 76.654371 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 5761373000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4086.580271 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.997700 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.997700 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 548148518 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 548148518 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 155653046 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 155653046 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 4 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 4 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 703801564 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 703801564 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 703801564 # number of overall hits -system.cpu.dcache.overall_hits::total 703801564 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 11295128 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 11295128 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 5075456 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 5075456 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 16370584 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 16370584 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 16370584 # number of overall misses -system.cpu.dcache.overall_misses::total 16370584 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 280321207500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 280321207500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 216815235389 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 216815235389 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 51500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 51500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 497136442889 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 497136442889 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 497136442889 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 497136442889 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 559443646 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 559443646 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 160728502 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 5 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 720172148 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 720172148 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 720172148 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 720172148 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.020190 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.020190 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.031578 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.031578 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.200000 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.200000 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.022731 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.022731 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.022731 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.022731 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24817.886747 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 24817.886747 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42718.375529 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 42718.375529 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 51500 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 51500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 30367.666962 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 30367.666962 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 30367.666962 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 30367.666962 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 10443209 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 5645556 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 732857 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 65131 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 14.249996 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 86.680014 # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3725010 # number of writebacks -system.cpu.dcache.writebacks::total 3725010 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3997316 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 3997316 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3191776 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 3191776 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 7189092 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 7189092 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 7189092 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 7189092 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7297812 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7297812 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1883680 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1883680 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9181492 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9181492 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9181492 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9181492 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 149509028500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 149509028500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 65361082800 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 65361082800 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 49500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 49500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 214870111300 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 214870111300 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 214870111300 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 214870111300 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.013045 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.013045 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011720 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.011720 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.200000 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.200000 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.012749 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.012749 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.012749 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.012749 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 20486.829272 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 20486.829272 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34698.612716 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34698.612716 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 49500 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 49500 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23402.526659 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 23402.526659 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23402.526659 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 23402.526659 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 1933961 # number of replacements -system.cpu.l2cache.tagsinuse 31328.043846 # Cycle average of tags in use -system.cpu.l2cache.total_refs 9059502 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 1963742 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 4.613387 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 30942494502 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 14698.563987 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 28.777983 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 16600.701877 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.448565 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.000878 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.506613 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.956056 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.data 6107231 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 6107231 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 3725010 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 3725010 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1108557 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1108557 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.data 7215788 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 7215788 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.data 7215788 # number of overall hits -system.cpu.l2cache.overall_hits::total 7215788 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 962 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 1190572 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 1191534 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 775133 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 775133 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 962 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 1965705 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 1966667 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 962 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 1965705 # number of overall misses -system.cpu.l2cache.overall_misses::total 1966667 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 56098500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 80363331500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 80419430000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 51942474500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 51942474500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 56098500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 132305806000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 132361904500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 56098500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 132305806000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 132361904500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 962 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 7297803 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 7298765 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 3725010 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 3725010 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 1883690 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 1883690 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 962 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 9181493 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 9182455 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 962 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 9181493 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 9182455 # number of overall (read+write) accesses +system.cpu.l2cache.replacements 1933820 # number of replacements +system.cpu.l2cache.tagsinuse 31412.329215 # Cycle average of tags in use +system.cpu.l2cache.total_refs 9058347 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 1963602 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 4.613128 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 27341900502 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::writebacks 14673.243602 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 26.610693 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 16712.474920 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.447792 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.000812 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.510024 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.958628 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.data 6106187 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 6106187 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 3724933 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 3724933 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 1108387 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 1108387 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.data 7214574 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 7214574 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.data 7214574 # number of overall hits +system.cpu.l2cache.overall_hits::total 7214574 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 961 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 1190397 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 1191358 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 775172 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 775172 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 961 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 1965569 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 1966530 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 961 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 1965569 # number of overall misses +system.cpu.l2cache.overall_misses::total 1966530 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 55130500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 80411180500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 80466311000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 51933315000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 51933315000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 55130500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 132344495500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 132399626000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 55130500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 132344495500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 132399626000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 961 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 7296584 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 7297545 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 3724933 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 3724933 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 1883559 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 1883559 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 961 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 9180143 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 9181104 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 961 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 9180143 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 9181104 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.163141 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.163251 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.411497 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.411497 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.163144 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.163255 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.411546 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.411546 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.214094 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.214177 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.214111 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.214193 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.214094 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.214177 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 58314.449064 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 67499.766079 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 67492.350197 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 67011.047781 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 67011.047781 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 58314.449064 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 67307.050651 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 67302.651898 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 58314.449064 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 67307.050651 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 67302.651898 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::cpu.data 0.214111 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.214193 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 57367.845994 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 67549.885038 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 67541.671773 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 66995.860274 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 66995.860274 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 57367.845994 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 67331.391317 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 67326.522352 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 57367.845994 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 67331.391317 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 67326.522352 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -794,52 +666,180 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 1019769 # number of writebacks -system.cpu.l2cache.writebacks::total 1019769 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 962 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1190572 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 1191534 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 775133 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 775133 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 962 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 1965705 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 1966667 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 962 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 1965705 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 1966667 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 43990994 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 65246294234 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 65290285228 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 42161089674 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 42161089674 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 43990994 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 107407383908 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 107451374902 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 43990994 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 107407383908 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 107451374902 # number of overall MSHR miss cycles +system.cpu.l2cache.writebacks::writebacks 1019728 # number of writebacks +system.cpu.l2cache.writebacks::total 1019728 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 961 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1190397 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1191358 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 775172 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 775172 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 961 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1965569 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 1966530 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 961 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 1965569 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 1966530 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 43023532 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 65297790926 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 65340814458 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 42150717127 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 42150717127 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 43023532 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 107448508053 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 107491531585 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 43023532 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 107448508053 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 107491531585 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.163141 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.163251 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.411497 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.411497 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.163144 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.163255 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.411546 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.411546 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.214094 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.214177 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.214111 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.214193 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214094 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.214177 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 45728.683992 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 54802.476653 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 54795.150812 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 54392.071650 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54392.071650 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 45728.683992 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 54640.642369 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54636.283063 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 45728.683992 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 54640.642369 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54636.283063 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214111 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.214193 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 44769.544225 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 54853.793252 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 54845.658868 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 54375.954146 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54375.954146 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 44769.544225 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 54665.345278 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54660.509418 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 44769.544225 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 54665.345278 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54660.509418 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.replacements 9176047 # number of replacements +system.cpu.dcache.tagsinuse 4087.418525 # Cycle average of tags in use +system.cpu.dcache.total_refs 694335392 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 9180143 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 75.634485 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 5062814000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4087.418525 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.997905 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.997905 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 538685115 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 538685115 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 155650275 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 155650275 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 2 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 2 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 694335390 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 694335390 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 694335390 # number of overall hits +system.cpu.dcache.overall_hits::total 694335390 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 11273608 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 11273608 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 5078227 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 5078227 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 16351835 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 16351835 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 16351835 # number of overall misses +system.cpu.dcache.overall_misses::total 16351835 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 280031703000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 280031703000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 217034506033 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 217034506033 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 48500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 48500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 497066209033 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 497066209033 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 497066209033 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 497066209033 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 549958723 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 549958723 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 160728502 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 3 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 710687225 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 710687225 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 710687225 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 710687225 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.020499 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.020499 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.031595 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.031595 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.333333 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.333333 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.023008 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.023008 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.023008 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.023008 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24839.581348 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 24839.581348 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42738.244280 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 42738.244280 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 48500 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 48500 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 30398.191337 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 30398.191337 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 30398.191337 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 30398.191337 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 10428893 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 5642690 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 733632 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 65134 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 14.215428 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 86.632020 # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 3724933 # number of writebacks +system.cpu.dcache.writebacks::total 3724933 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3977017 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 3977017 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3194676 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3194676 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 7171693 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 7171693 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 7171693 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 7171693 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7296591 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7296591 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1883551 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1883551 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 9180142 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9180142 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9180142 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9180142 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 149546401000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 149546401000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 65349746897 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 65349746897 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 46500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 46500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 214896147897 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 214896147897 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 214896147897 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 214896147897 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.013268 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.013268 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011719 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.011719 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.333333 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.333333 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.012917 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.012917 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.012917 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.012917 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 20495.379418 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 20495.379418 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34694.970774 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34694.970774 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 46500 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 46500 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23408.804341 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 23408.804341 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23408.804341 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 23408.804341 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini index 725d1f37b..34e401024 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini @@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a -clock=1 +clock=1000 init_param=0 kernel= load_addr_mask=1099511627775 @@ -30,7 +30,7 @@ system_port=system.membus.slave[0] [system.cpu] type=DerivO3CPU -children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload +children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -78,6 +78,7 @@ iewToFetchDelay=1 iewToRenameDelay=1 instShiftAmt=2 interrupts=system.cpu.interrupts +isa=system.cpu.isa issueToExecuteDelay=1 issueWidth=8 itb=system.cpu.itb @@ -129,18 +130,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=262144 subblock_size=0 system=system @@ -159,7 +160,7 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=ArmTableWalker -clock=1 +clock=500 num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[3] @@ -432,18 +433,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=131072 subblock_size=0 system=system @@ -457,6 +458,23 @@ mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=ArmInterrupts +[system.cpu.isa] +type=ArmISA +fpsid=1090793632 +id_isar0=34607377 +id_isar1=34677009 +id_isar2=555950401 +id_isar3=17899825 +id_isar4=268501314 +id_isar5=0 +id_mmfr0=3 +id_mmfr1=0 +id_mmfr2=19070976 +id_mmfr3=4027589137 +id_pfr0=49 +id_pfr1=1 +midr=890224640 + [system.cpu.itb] type=ArmTLB children=walker @@ -465,7 +483,7 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=ArmTableWalker -clock=1 +clock=500 num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[2] @@ -473,24 +491,24 @@ port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] type=BaseCache addr_ranges=0:18446744073709551615 -assoc=2 +assoc=8 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=20 is_top_level=false max_miss_count=0 -mshrs=10 +mshrs=20 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=20 size=2097152 subblock_size=0 system=system -tgts_per_mshr=5 +tgts_per_mshr=12 trace_addr=0 two_queue=false write_buffers=8 @@ -500,10 +518,10 @@ mem_side=system.membus.slave[1] [system.cpu.toL2Bus] type=CoherentBus block_size=64 -clock=1000 +clock=500 header_cycles=1 use_default_range=false -width=8 +width=32 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port @@ -540,15 +558,28 @@ master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] -type=SimpleMemory -bandwidth=73.000000 -clock=1 +type=SimpleDRAM +addr_mapping=openmap +banks_per_rank=8 +clock=1000 conf_table_reported=false in_addr_map=true -latency=30000 -latency_var=0 +lines_per_rowbuffer=64 +mem_sched_policy=fcfs null=false +page_policy=open range=0:134217727 +ranks_per_channel=2 +read_buffer_size=32 +tBURST=4000 +tCL=14000 +tRCD=14000 +tREFI=7800000 +tRFC=300000 +tRP=14000 +tWTR=1000 +write_buffer_size=32 +write_thresh_perc=70 zero=false port=system.membus.master[0] diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout index 434faed57..e7a9dda21 100755 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout @@ -1,8 +1,8 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 21 2012 11:19:00 -gem5 started Sep 21 2012 12:45:19 +gem5 compiled Oct 30 2012 11:20:14 +gem5 started Oct 30 2012 20:33:15 gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second @@ -24,4 +24,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 479173106500 because target called exit() +Exiting @ tick 506342716000 because target called exit() diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt index 21ff71fb2..2a9784b55 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt @@ -1,90 +1,90 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.515058 # Number of seconds simulated -sim_ticks 515058060000 # Number of ticks simulated -final_tick 515058060000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.506343 # Number of seconds simulated +sim_ticks 506342716000 # Number of ticks simulated +final_tick 506342716000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 166099 # Simulator instruction rate (inst/s) -host_op_rate 185296 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 55388247 # Simulator tick rate (ticks/s) -host_mem_usage 494292 # Number of bytes of host memory used -host_seconds 9299.05 # Real time elapsed on the host -sim_insts 1544563078 # Number of instructions simulated -sim_ops 1723073890 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 48320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 144392128 # Number of bytes read from this memory -system.physmem.bytes_read::total 144440448 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 48320 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 48320 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 70617600 # Number of bytes written to this memory -system.physmem.bytes_written::total 70617600 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 755 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2256127 # Number of read requests responded to by this memory -system.physmem.num_reads::total 2256882 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1103400 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1103400 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 93815 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 280341459 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 280435274 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 93815 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 93815 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 137106096 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 137106096 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 137106096 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 93815 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 280341459 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 417541370 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 2256882 # Total number of read requests seen -system.physmem.writeReqs 1103400 # Total number of write requests seen -system.physmem.cpureqs 3360282 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 144440448 # Total number of bytes read from memory -system.physmem.bytesWritten 70617600 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 144440448 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 70617600 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 637 # Number of read reqs serviced by write Q +host_inst_rate 134396 # Simulator instruction rate (inst/s) +host_op_rate 149928 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 44057957 # Simulator tick rate (ticks/s) +host_mem_usage 522896 # Number of bytes of host memory used +host_seconds 11492.65 # Real time elapsed on the host +sim_insts 1544563043 # Number of instructions simulated +sim_ops 1723073855 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 47744 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 143751360 # Number of bytes read from this memory +system.physmem.bytes_read::total 143799104 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 47744 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 47744 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 70435456 # Number of bytes written to this memory +system.physmem.bytes_written::total 70435456 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 746 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 2246115 # Number of read requests responded to by this memory +system.physmem.num_reads::total 2246861 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1100554 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1100554 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 94292 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 283901309 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 283995601 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 94292 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 94292 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 139106289 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 139106289 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 139106289 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 94292 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 283901309 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 423101890 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 2246861 # Total number of read requests seen +system.physmem.writeReqs 1100554 # Total number of write requests seen +system.physmem.cpureqs 3347415 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 143799104 # Total number of bytes read from memory +system.physmem.bytesWritten 70435456 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 143799104 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 70435456 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 613 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 140407 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 144367 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 142491 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 141453 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 138510 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 140931 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 142120 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 141749 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 141832 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 140373 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 140948 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 141413 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 137790 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 141680 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 139536 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 140645 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 69366 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 70506 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 69820 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 68968 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 67927 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 68673 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 68853 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 68680 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 68439 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 68530 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 68800 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 68663 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 67351 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 70531 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 69216 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 69077 # Track writes on a per bank basis +system.physmem.perBankRdReqs::0 139880 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 143856 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 141905 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 140877 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 137960 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 140233 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 141491 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 140982 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 141233 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 139496 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 140455 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 140890 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 137116 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 141034 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 138952 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 139888 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 69217 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 70379 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 69592 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 68832 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 67727 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 68464 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 68713 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 68501 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 68243 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 68230 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 68643 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 68550 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 67188 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 70321 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 69053 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 68901 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 515058007000 # Total gap between requests +system.physmem.totGap 506342647500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 2256882 # Categorize read packet sizes +system.physmem.readPktSize::6 2246861 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -93,7 +93,7 @@ system.physmem.writePktSize::2 0 # ca system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 1103400 # categorize write packet sizes +system.physmem.writePktSize::6 1100554 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -105,11 +105,11 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 1580398 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 450395 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 158442 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 66982 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 24 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 1577627 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 446326 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 156341 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 65934 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 16 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -138,60 +138,60 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 45630 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 47618 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 47927 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 47968 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 47973 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 47974 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 47974 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 47974 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 47974 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 47974 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 47974 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 47974 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 47974 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 47974 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 47974 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 47974 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 47974 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 47974 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 47974 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 47974 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 47974 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 47973 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 47973 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 2344 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 356 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 47 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 45498 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 47479 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 47800 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 47843 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 47850 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 47850 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 47850 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 47850 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 47850 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 47850 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 47850 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 47850 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 47850 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 47850 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 47850 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 47850 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 47850 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 47850 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 47850 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 47850 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 47850 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 47850 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 47850 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 2353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 372 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 51 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 27231628654 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 103251704654 # Sum of mem lat for all requests -system.physmem.totBusLat 9024980000 # Total cycles spent in databus access -system.physmem.totBankLat 66995096000 # Total cycles spent in bank access -system.physmem.avgQLat 12069.45 # Average queueing delay per request -system.physmem.avgBankLat 29693.18 # Average bank access latency per request +system.physmem.totQLat 27053022176 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 102785772176 # Sum of mem lat for all requests +system.physmem.totBusLat 8984992000 # Total cycles spent in databus access +system.physmem.totBankLat 66747758000 # Total cycles spent in bank access +system.physmem.avgQLat 12043.65 # Average queueing delay per request +system.physmem.avgBankLat 29715.22 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 45762.63 # Average memory access latency -system.physmem.avgRdBW 280.44 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 137.11 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 280.44 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 137.11 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 45758.87 # Average memory access latency +system.physmem.avgRdBW 284.00 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 139.11 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 284.00 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 139.11 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 2.61 # Data bus utilization in percentage +system.physmem.busUtil 2.64 # Data bus utilization in percentage system.physmem.avgRdQLen 0.20 # Average read queue length over time -system.physmem.avgWrQLen 11.32 # Average write queue length over time -system.physmem.readRowHits 919391 # Number of row buffer hits during reads -system.physmem.writeRowHits 189315 # Number of row buffer hits during writes -system.physmem.readRowHitRate 40.75 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 17.16 # Row buffer hit rate for writes -system.physmem.avgGap 153278.21 # Average gap between requests +system.physmem.avgWrQLen 10.20 # Average write queue length over time +system.physmem.readRowHits 914443 # Number of row buffer hits during reads +system.physmem.writeRowHits 189193 # Number of row buffer hits during writes +system.physmem.readRowHitRate 40.71 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 17.19 # Row buffer hit rate for writes +system.physmem.avgGap 151263.78 # Average gap between requests system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -235,569 +235,442 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.numCycles 1030116121 # number of cpu cycles simulated +system.cpu.numCycles 1012685433 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 307748972 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 253170818 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 16168830 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 178836343 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 162524431 # Number of BTB hits +system.cpu.BPredUnit.lookups 301954621 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 248216809 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 15201913 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 174080905 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 160275912 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 18394581 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 234 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 302711500 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 2208582342 # Number of instructions fetch has processed -system.cpu.fetch.Branches 307748972 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 180919012 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 439713036 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 91477277 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 153604124 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 69 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 9 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 292882660 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 6106896 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 969047070 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.529561 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.216174 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 17543051 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 217 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 296171329 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 2177000343 # Number of instructions fetch has processed +system.cpu.fetch.Branches 301954621 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 177818963 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 433079666 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 86445035 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 152984584 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 67 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 286733341 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 5527590 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 951199831 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.533171 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.216208 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 529334144 54.62% 54.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 25043926 2.58% 57.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 39264186 4.05% 61.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 48337631 4.99% 66.25% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 43062270 4.44% 70.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 47882627 4.94% 75.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 39313310 4.06% 79.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 19335068 2.00% 81.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 177473908 18.31% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 518120232 54.47% 54.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 25036737 2.63% 57.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 39011944 4.10% 61.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 48247673 5.07% 66.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 42552998 4.47% 70.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 46316076 4.87% 75.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 38402395 4.04% 79.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 18552878 1.95% 81.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 174958898 18.39% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 969047070 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.298752 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.144013 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 334775915 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 131820236 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 409429631 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 20003640 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 73017648 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 46459880 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 721 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 2395467722 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 2521 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 73017648 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 358478616 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 61310545 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 17059 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 404218624 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 72004578 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2331266224 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 128849 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 5208113 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 58805545 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 5 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 2308002536 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 10761064902 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 10761060796 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 4106 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 1706320018 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 601682518 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1074 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1071 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 160130696 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 634128265 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 221560674 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 87711423 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 69100091 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2223438682 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1093 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2032725138 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 5162970 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 495697928 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1172411676 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 912 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 969047070 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.097654 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.906175 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 951199831 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.298172 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.149730 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 327457175 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 131287653 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 403449648 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 20041830 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 68963525 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 46005772 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 694 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 2358153457 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 2386 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 68963525 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 350605393 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 61238175 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 13721 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 398828619 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 71550398 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2297300888 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 126992 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 5036459 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 58395724 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 6 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 2272291937 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 10608987199 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 10608983762 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 3437 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 1706319962 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 565971975 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 462 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 459 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 158423553 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 623142693 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 220479196 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 86005454 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 70775057 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2196663707 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 506 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2016028881 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 3978647 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 469035072 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1108322137 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 332 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 951199831 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.119459 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.906333 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 282916763 29.20% 29.20% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 152378116 15.72% 44.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 162831122 16.80% 61.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 119917560 12.37% 74.10% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 126106053 13.01% 87.11% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 74105592 7.65% 94.76% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 38169342 3.94% 98.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 10016302 1.03% 99.73% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 2606220 0.27% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 271401880 28.53% 28.53% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 150954811 15.87% 44.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 160752249 16.90% 61.30% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 119324059 12.54% 73.85% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 124037458 13.04% 86.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 73914082 7.77% 94.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 38408733 4.04% 98.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 9827717 1.03% 99.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 2578842 0.27% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 969047070 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 951199831 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 856823 3.47% 3.47% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 4485 0.02% 3.49% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 3.49% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.49% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.49% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.49% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 3.49% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.49% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 3.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 3.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.49% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 18914760 76.65% 80.14% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 4900553 19.86% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 872713 3.66% 3.66% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 5800 0.02% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 18252533 76.46% 80.14% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 4741041 19.86% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1244244744 61.21% 61.21% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 933049 0.05% 61.26% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.26% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.00% 61.26% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.26% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.26% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.26% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.26% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 77 0.00% 61.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 3 0.00% 61.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 31 0.00% 61.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 15 0.00% 61.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.26% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 593617066 29.20% 90.46% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 193930151 9.54% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1235530867 61.29% 61.29% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 926678 0.05% 61.33% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.33% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.00% 61.33% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.33% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.33% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.33% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.33% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 58 0.00% 61.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 61.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 25 0.00% 61.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 11 0.00% 61.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.33% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 586539458 29.09% 90.43% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 193031781 9.57% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2032725138 # Type of FU issued -system.cpu.iq.rate 1.973297 # Inst issue rate -system.cpu.iq.fu_busy_cnt 24676621 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.012140 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 5064336479 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2719325477 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1969225475 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 458 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 784 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 183 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2057401528 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 231 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 63678179 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2016028881 # Type of FU issued +system.cpu.iq.rate 1.990775 # Inst issue rate +system.cpu.iq.fu_busy_cnt 23872087 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.011841 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 5011107955 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2665888919 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1956633156 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 372 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 668 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 148 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2039900782 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 186 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 64729425 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 148201485 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 301622 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 191452 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 46713618 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 137215920 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 273705 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 192829 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 45632147 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 3827005 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 3 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 3804190 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 73017648 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 27244100 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1491546 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2223439933 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 6134188 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 634128265 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 221560674 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1025 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 470403 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 82153 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 191452 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 8679785 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 10261943 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 18941728 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 2001081478 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 578449212 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 31643660 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 68963525 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 27139108 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1495868 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2196664320 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 6096220 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 623142693 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 220479196 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 440 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 474677 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 89373 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 192829 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 8139641 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 9611816 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 17751457 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1986428018 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 573006458 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 29600863 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 158 # number of nop insts executed -system.cpu.iew.exec_refs 769422153 # number of memory reference insts executed -system.cpu.iew.exec_branches 239265351 # Number of branches executed -system.cpu.iew.exec_stores 190972941 # Number of stores executed -system.cpu.iew.exec_rate 1.942579 # Inst execution rate -system.cpu.iew.wb_sent 1978131551 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1969225658 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1302526017 # num instructions producing a value -system.cpu.iew.wb_consumers 2074719324 # num instructions consuming a value +system.cpu.iew.exec_nop 107 # number of nop insts executed +system.cpu.iew.exec_refs 763162577 # number of memory reference insts executed +system.cpu.iew.exec_branches 238305506 # Number of branches executed +system.cpu.iew.exec_stores 190156119 # Number of stores executed +system.cpu.iew.exec_rate 1.961545 # Inst execution rate +system.cpu.iew.wb_sent 1965069993 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1956633304 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1295741844 # num instructions producing a value +system.cpu.iew.wb_consumers 2060291868 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.911654 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.627808 # average fanout of values written-back +system.cpu.iew.wb_rate 1.932123 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.628912 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 500462812 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 181 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 16168149 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 896029423 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.923010 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.718948 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 473688675 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 174 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 15201254 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 882236307 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.953075 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.733441 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 406862083 45.41% 45.41% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 193059933 21.55% 66.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 73977423 8.26% 75.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 35390708 3.95% 79.16% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 18895903 2.11% 81.27% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 30453376 3.40% 84.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 19841212 2.21% 86.88% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 11401039 1.27% 88.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 106147746 11.85% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 395033936 44.78% 44.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 192005187 21.76% 66.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 72432268 8.21% 74.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 35243986 3.99% 78.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 18949129 2.15% 80.89% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 30789454 3.49% 84.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 20064460 2.27% 86.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 11401450 1.29% 87.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 106316437 12.05% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 896029423 # Number of insts commited each cycle -system.cpu.commit.committedInsts 1544563096 # Number of instructions committed -system.cpu.commit.committedOps 1723073908 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 882236307 # Number of insts commited each cycle +system.cpu.commit.committedInsts 1544563061 # Number of instructions committed +system.cpu.commit.committedOps 1723073873 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 660773836 # Number of memory references committed -system.cpu.commit.loads 485926780 # Number of loads committed +system.cpu.commit.refs 660773822 # Number of memory references committed +system.cpu.commit.loads 485926773 # Number of loads committed system.cpu.commit.membars 62 # Number of memory barriers committed -system.cpu.commit.branches 213462437 # Number of branches committed +system.cpu.commit.branches 213462430 # Number of branches committed system.cpu.commit.fp_insts 36 # Number of committed floating point instructions. -system.cpu.commit.int_insts 1536941885 # Number of committed integer instructions. +system.cpu.commit.int_insts 1536941857 # Number of committed integer instructions. system.cpu.commit.function_calls 13665177 # Number of function calls committed. -system.cpu.commit.bw_lim_events 106147746 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 106316437 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3013417798 # The number of ROB reads -system.cpu.rob.rob_writes 4520246386 # The number of ROB writes -system.cpu.timesIdled 1016810 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 61069051 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 1544563078 # Number of Instructions Simulated -system.cpu.committedOps 1723073890 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 1544563078 # Number of Instructions Simulated -system.cpu.cpi 0.666930 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.666930 # CPI: Total CPI of All Threads -system.cpu.ipc 1.499407 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.499407 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 10019536016 # number of integer regfile reads -system.cpu.int_regfile_writes 1949927429 # number of integer regfile writes -system.cpu.fp_regfile_reads 198 # number of floating regfile reads -system.cpu.fp_regfile_writes 204 # number of floating regfile writes -system.cpu.misc_regfile_reads 2950890294 # number of misc regfile reads -system.cpu.misc_regfile_writes 146 # number of misc regfile writes -system.cpu.icache.replacements 21 # number of replacements -system.cpu.icache.tagsinuse 635.874030 # Cycle average of tags in use -system.cpu.icache.total_refs 292881421 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 787 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 372149.200762 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 2972681819 # The number of ROB reads +system.cpu.rob.rob_writes 4462636284 # The number of ROB writes +system.cpu.timesIdled 1007749 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 61485602 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 1544563043 # Number of Instructions Simulated +system.cpu.committedOps 1723073855 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 1544563043 # Number of Instructions Simulated +system.cpu.cpi 0.655645 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.655645 # CPI: Total CPI of All Threads +system.cpu.ipc 1.525215 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.525215 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 9949187154 # number of integer regfile reads +system.cpu.int_regfile_writes 1936551418 # number of integer regfile writes +system.cpu.fp_regfile_reads 155 # number of floating regfile reads +system.cpu.fp_regfile_writes 154 # number of floating regfile writes +system.cpu.misc_regfile_reads 2914618242 # number of misc regfile reads +system.cpu.misc_regfile_writes 132 # number of misc regfile writes +system.cpu.icache.replacements 22 # number of replacements +system.cpu.icache.tagsinuse 625.107966 # Cycle average of tags in use +system.cpu.icache.total_refs 286732187 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 775 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 369977.015484 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 635.874030 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.310485 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.310485 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 292881421 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 292881421 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 292881421 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 292881421 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 292881421 # number of overall hits -system.cpu.icache.overall_hits::total 292881421 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1239 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1239 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1239 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1239 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1239 # number of overall misses -system.cpu.icache.overall_misses::total 1239 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 62929999 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 62929999 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 62929999 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 62929999 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 62929999 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 62929999 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 292882660 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 292882660 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 292882660 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 292882660 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 292882660 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 292882660 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 625.107966 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.305228 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.305228 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 286732187 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 286732187 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 286732187 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 286732187 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 286732187 # number of overall hits +system.cpu.icache.overall_hits::total 286732187 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1154 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1154 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1154 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1154 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1154 # number of overall misses +system.cpu.icache.overall_misses::total 1154 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 59543000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 59543000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 59543000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 59543000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 59543000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 59543000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 286733341 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 286733341 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 286733341 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 286733341 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 286733341 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 286733341 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 50790.959645 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 50790.959645 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 50790.959645 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 50790.959645 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 50790.959645 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 50790.959645 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 213 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 51597.053726 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 51597.053726 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 51597.053726 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 51597.053726 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 51597.053726 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 51597.053726 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 207 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 3 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 71 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 69 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 452 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 452 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 452 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 452 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 452 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 452 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 787 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 787 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 787 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 787 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 787 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 787 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 42672499 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 42672499 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 42672499 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 42672499 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 42672499 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 42672499 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 379 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 379 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 379 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 379 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 379 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 379 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 775 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 775 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 775 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 775 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 775 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 775 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 41824000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 41824000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 41824000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 41824000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 41824000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 41824000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000003 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000003 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000003 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54221.726811 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54221.726811 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54221.726811 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 54221.726811 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54221.726811 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 54221.726811 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53966.451613 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53966.451613 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53966.451613 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 53966.451613 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53966.451613 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 53966.451613 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 9616996 # number of replacements -system.cpu.dcache.tagsinuse 4088.070177 # Cycle average of tags in use -system.cpu.dcache.total_refs 662383558 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 9621092 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 68.847025 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 3431633000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4088.070177 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.998064 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.998064 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 495328808 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 495328808 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 167054576 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 167054576 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 102 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 102 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 72 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 72 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 662383384 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 662383384 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 662383384 # number of overall hits -system.cpu.dcache.overall_hits::total 662383384 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 11493898 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 11493898 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 5531471 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 5531471 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 17025369 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 17025369 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 17025369 # number of overall misses -system.cpu.dcache.overall_misses::total 17025369 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 300469698500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 300469698500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 217116494201 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 217116494201 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 190500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 190500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 517586192701 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 517586192701 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 517586192701 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 517586192701 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 506822706 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 506822706 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 105 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 105 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 72 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 72 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 679408753 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 679408753 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 679408753 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 679408753 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.022678 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.022678 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032051 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.032051 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.028571 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.028571 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.025059 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.025059 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.025059 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.025059 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26141.670867 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 26141.670867 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39251.131245 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 39251.131245 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 63500 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 63500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 30400.879576 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 30400.879576 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 30400.879576 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 30400.879576 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 19937535 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 989836 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1174592 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 64547 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 16.974009 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 15.335120 # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3785750 # number of writebacks -system.cpu.dcache.writebacks::total 3785750 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3766794 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 3766794 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3637483 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 3637483 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 7404277 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 7404277 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 7404277 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 7404277 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7727104 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7727104 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1893988 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1893988 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9621092 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9621092 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9621092 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9621092 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 171327843500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 171327843500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 71936813831 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 71936813831 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 243264657331 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 243264657331 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 243264657331 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 243264657331 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015246 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015246 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010974 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010974 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014161 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.014161 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014161 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.014161 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22172.322710 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22172.322710 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37981.662941 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37981.662941 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25284.516283 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 25284.516283 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25284.516283 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 25284.516283 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 2224194 # number of replacements -system.cpu.l2cache.tagsinuse 31538.307180 # Cycle average of tags in use -system.cpu.l2cache.total_refs 9258938 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 2253968 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 4.107839 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 20485728502 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 14439.228019 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 20.648477 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 17078.430684 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.440650 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.000630 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.521192 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.962473 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 30 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 6299217 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 6299247 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 3785750 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 3785750 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1065742 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1065742 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 30 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 7364959 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 7364989 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 30 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 7364959 # number of overall hits -system.cpu.l2cache.overall_hits::total 7364989 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 757 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 1427887 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 1428644 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 828246 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 828246 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 757 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 2256133 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 2256890 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 757 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 2256133 # number of overall misses -system.cpu.l2cache.overall_misses::total 2256890 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 41571500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 98780136000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 98821707500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 58846759000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 58846759000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 41571500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 157626895000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 157668466500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 41571500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 157626895000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 157668466500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 787 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 7727104 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 7727891 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 3785750 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 3785750 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 1893988 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 1893988 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 787 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 9621092 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 9621879 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 787 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 9621092 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 9621879 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.961881 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.184789 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.184869 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.437303 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.437303 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.961881 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.234499 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.234558 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.961881 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.234499 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.234558 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 54916.116248 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 69179.238973 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 69171.681329 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71049.855961 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71049.855961 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 54916.116248 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69865.958700 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 69860.944264 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 54916.116248 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69865.958700 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 69860.944264 # average overall miss latency +system.cpu.l2cache.replacements 2214170 # number of replacements +system.cpu.l2cache.tagsinuse 31523.647608 # Cycle average of tags in use +system.cpu.l2cache.total_refs 9246689 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 2243948 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 4.120723 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 20415148502 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::writebacks 14433.962078 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 20.520835 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 17069.164694 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.440490 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.000626 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.520910 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.962025 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 28 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 6288951 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 6288979 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 3781955 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 3781955 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 1067075 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 1067075 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 28 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 7356026 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 7356054 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 28 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 7356026 # number of overall hits +system.cpu.l2cache.overall_hits::total 7356054 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 747 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 1419691 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 1420438 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 826431 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 826431 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 747 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 2246122 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 2246869 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 747 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 2246122 # number of overall misses +system.cpu.l2cache.overall_misses::total 2246869 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 40761000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 98155765500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 98196526500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 58740659000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 58740659000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 40761000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 156896424500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 156937185500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 40761000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 156896424500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 156937185500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 775 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 7708642 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 7709417 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 3781955 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 3781955 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 1893506 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 1893506 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 775 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 9602148 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 9602923 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 775 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 9602148 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 9602923 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.963871 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.184169 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.184247 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.436455 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.436455 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.963871 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.233919 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.233978 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.963871 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.233919 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.233978 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 54566.265060 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 69138.823519 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 69131.159896 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71077.511613 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71077.511613 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 54566.265060 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69852.138263 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 69847.056281 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 54566.265060 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69852.138263 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 69847.056281 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -806,61 +679,187 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 1103400 # number of writebacks -system.cpu.l2cache.writebacks::total 1103400 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 6 # number of ReadReq MSHR hits +system.cpu.l2cache.writebacks::writebacks 1100554 # number of writebacks +system.cpu.l2cache.writebacks::total 1100554 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 7 # number of ReadReq MSHR hits system.cpu.l2cache.ReadReq_mshr_hits::total 8 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 6 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 7 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::total 8 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 6 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 7 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 8 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 755 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1427881 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 1428636 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 828246 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 828246 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 755 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 2256127 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 2256882 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 755 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 2256127 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 2256882 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 31971694 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 80731453067 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 80763424761 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 48402066091 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 48402066091 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 31971694 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 129133519158 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 129165490852 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 31971694 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 129133519158 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 129165490852 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.959339 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.184789 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.184868 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.437303 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.437303 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.959339 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.234498 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.234557 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.959339 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.234498 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.234557 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 42346.614570 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 56539.342611 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56531.842093 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58439.239177 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58439.239177 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42346.614570 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57236.812980 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57231.831727 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42346.614570 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57236.812980 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57231.831727 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 746 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1419684 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1420430 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 826431 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 826431 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 746 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 2246115 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 2246861 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 746 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 2246115 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 2246861 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 31288684 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 80209878843 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 80241167527 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 48317396987 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 48317396987 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 31288684 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 128527275830 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 128558564514 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 31288684 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 128527275830 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 128558564514 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.962581 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.184168 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.184246 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.436455 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.436455 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.962581 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.233918 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.233977 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.962581 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.233918 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.233977 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41941.935657 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 56498.403055 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56490.758099 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58465.131375 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58465.131375 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41941.935657 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57222.037086 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57216.963806 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41941.935657 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57222.037086 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57216.963806 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.replacements 9598051 # number of replacements +system.cpu.dcache.tagsinuse 4087.935978 # Cycle average of tags in use +system.cpu.dcache.total_refs 655966956 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 9602147 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 68.314613 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 3423729000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4087.935978 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.998031 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.998031 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 488912900 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 488912900 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 167053904 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 167053904 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 87 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 87 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 65 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 65 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 655966804 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 655966804 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 655966804 # number of overall hits +system.cpu.dcache.overall_hits::total 655966804 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 11479195 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 11479195 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 5532143 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 5532143 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 17011338 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 17011338 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 17011338 # number of overall misses +system.cpu.dcache.overall_misses::total 17011338 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 299504228000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 299504228000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 217114926916 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 217114926916 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 187000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 187000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 516619154916 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 516619154916 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 516619154916 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 516619154916 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 500392095 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 500392095 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 90 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 90 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 65 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 65 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 672978142 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 672978142 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 672978142 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 672978142 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.022940 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.022940 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032054 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.032054 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.033333 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.033333 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.025278 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.025278 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.025278 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.025278 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26091.048022 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 26091.048022 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39246.080030 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 39246.080030 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 62333.333333 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 62333.333333 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 30369.107646 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 30369.107646 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 30369.107646 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 30369.107646 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 19754018 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 992148 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1171998 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 64543 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 16.854993 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 15.371892 # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 3781955 # number of writebacks +system.cpu.dcache.writebacks::total 3781955 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3770552 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 3770552 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3638638 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3638638 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 7409190 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 7409190 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 7409190 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 7409190 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7708643 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7708643 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1893505 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1893505 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 9602148 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9602148 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9602148 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9602148 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 170578712500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 170578712500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 71843645589 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 71843645589 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 242422358089 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 242422358089 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 242422358089 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 242422358089 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015405 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015405 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010971 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010971 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014268 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.014268 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014268 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.014268 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22128.241313 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22128.241313 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37942.147282 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37942.147282 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25246.680023 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 25246.680023 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25246.680023 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 25246.680023 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/config.ini index db2911eab..402c5cbcd 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/config.ini +++ b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/config.ini @@ -10,6 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a +clock=1000 init_param=0 kernel= load_addr_mask=1099511627775 @@ -29,7 +30,7 @@ system_port=system.membus.slave[0] [system.cpu] type=InOrderCPU -children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload +children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 RASSize=16 @@ -54,8 +55,6 @@ do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb fetchBuffSize=4 -functionTrace=false -functionTraceStart=0 function_trace=false function_trace_start=0 globalCtrBits=2 @@ -63,6 +62,7 @@ globalHistoryBits=13 globalPredictorSize=8192 instShiftAmt=2 interrupts=system.cpu.interrupts +isa=system.cpu.isa itb=system.cpu.itb localCtrBits=2 localHistoryBits=11 @@ -76,7 +76,6 @@ memBlockSize=64 multLatency=1 multRepeatRate=1 numThreads=1 -phase=0 predType=tournament profile=0 progress_interval=0 @@ -94,20 +93,22 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=2 is_top_level=true -latency=1000 max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=2 size=262144 subblock_size=0 system=system -tgts_per_mshr=5 +tgts_per_mshr=20 trace_addr=0 two_queue=false write_buffers=8 @@ -123,20 +124,22 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=2 is_top_level=true -latency=1000 max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=2 size=131072 subblock_size=0 system=system -tgts_per_mshr=5 +tgts_per_mshr=20 trace_addr=0 two_queue=false write_buffers=8 @@ -146,6 +149,9 @@ mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=AlphaInterrupts +[system.cpu.isa] +type=AlphaISA + [system.cpu.itb] type=AlphaTLB size=48 @@ -153,22 +159,24 @@ size=48 [system.cpu.l2cache] type=BaseCache addr_ranges=0:18446744073709551615 -assoc=2 +assoc=8 block_size=64 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=20 is_top_level=false -latency=10000 max_miss_count=0 -mshrs=10 +mshrs=20 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=20 size=2097152 subblock_size=0 system=system -tgts_per_mshr=5 +tgts_per_mshr=12 trace_addr=0 two_queue=false write_buffers=8 @@ -178,10 +186,10 @@ mem_side=system.membus.slave[1] [system.cpu.toL2Bus] type=CoherentBus block_size=64 -clock=1000 +clock=500 header_cycles=1 use_default_range=false -width=8 +width=32 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side @@ -191,12 +199,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=twolf smred -cwd=build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/inorder-timing +cwd=build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/inorder-timing egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/alpha/tru64/twolf +executable=/projects/pd/randd/dist/cpu2000/binaries/alpha/tru64/twolf gid=100 input=cin max_stack_size=67108864 @@ -214,18 +222,32 @@ clock=1000 header_cycles=1 use_default_range=false width=8 -master=system.physmem.port[0] +master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] -type=SimpleMemory +type=SimpleDRAM +addr_mapping=openmap +banks_per_rank=8 +clock=1000 conf_table_reported=false -file= in_addr_map=true -latency=30000 -latency_var=0 +lines_per_rowbuffer=64 +mem_sched_policy=fcfs null=false +page_policy=open range=0:134217727 +ranks_per_channel=2 +read_buffer_size=32 +tBURST=4000 +tCL=14000 +tRCD=14000 +tREFI=7800000 +tRFC=300000 +tRP=14000 +tWTR=1000 +write_buffer_size=32 +write_thresh_perc=70 zero=false port=system.membus.master[0] diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/simout b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/simout index b50317767..483ce54bf 100755 --- a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/simout +++ b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/simout @@ -1,12 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 2 2012 08:30:56 -gem5 started Jul 2 2012 10:35:16 -gem5 executing on zizzer -command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/inorder-timing -Couldn't unlink build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/inorder-timing/smred.sav -Couldn't unlink build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/inorder-timing/smred.sv2 +gem5 compiled Oct 30 2012 11:02:14 +gem5 started Oct 30 2012 13:10:16 +gem5 executing on u200540-lin +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. @@ -23,4 +21,4 @@ Authors: Carl Sechen, Bill Swartz 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 42012413000 because target called exit() +122 123 124 Exiting @ tick 41615049000 because target called exit() diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt index ba13ea976..7f70f56b6 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.041949 # Number of seconds simulated -sim_ticks 41948719000 # Number of ticks simulated -final_tick 41948719000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.041615 # Number of seconds simulated +sim_ticks 41615049000 # Number of ticks simulated +final_tick 41615049000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 82495 # Simulator instruction rate (inst/s) -host_op_rate 82495 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 37654494 # Simulator tick rate (ticks/s) -host_mem_usage 221732 # Number of bytes of host memory used -host_seconds 1114.04 # Real time elapsed on the host +host_inst_rate 117678 # Simulator instruction rate (inst/s) +host_op_rate 117678 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 53286406 # Simulator tick rate (ticks/s) +host_mem_usage 217828 # Number of bytes of host memory used +host_seconds 780.97 # Real time elapsed on the host sim_insts 91903056 # Number of instructions simulated sim_ops 91903056 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 178816 # Number of bytes read from this memory @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 178816 # Nu system.physmem.num_reads::cpu.inst 2794 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 2144 # Number of read requests responded to by this memory system.physmem.num_reads::total 4938 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 4262728 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3271041 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 7533770 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 4262728 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 4262728 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 4262728 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3271041 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7533770 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 4296907 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3297269 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 7594176 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 4296907 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 4296907 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 4296907 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3297269 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 7594176 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 4938 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen system.physmem.cpureqs 4938 # Reqs generatd by CPU via cache - shady @@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 41948681000 # Total gap between requests +system.physmem.totGap 41614997000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -99,8 +99,8 @@ system.physmem.neitherpktsize::6 0 # ca system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes system.physmem.rdQLenPdf::0 3467 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 991 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 438 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1008 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 421 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 36 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -164,47 +164,47 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 18563928 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 107349928 # Sum of mem lat for all requests +system.physmem.totQLat 17845427 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 106827427 # Sum of mem lat for all requests system.physmem.totBusLat 19752000 # Total cycles spent in databus access -system.physmem.totBankLat 69034000 # Total cycles spent in bank access -system.physmem.avgQLat 3759.40 # Average queueing delay per request -system.physmem.avgBankLat 13980.15 # Average bank access latency per request +system.physmem.totBankLat 69230000 # Total cycles spent in bank access +system.physmem.avgQLat 3613.90 # Average queueing delay per request +system.physmem.avgBankLat 14019.85 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 21739.56 # Average memory access latency -system.physmem.avgRdBW 7.53 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 21633.74 # Average memory access latency +system.physmem.avgRdBW 7.59 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 7.53 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 7.59 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.05 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 4458 # Number of row buffer hits during reads +system.physmem.readRowHits 4457 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 90.28 # Row buffer hit rate for reads +system.physmem.readRowHitRate 90.26 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 8495075.13 # Average gap between requests +system.physmem.avgGap 8427500.41 # Average gap between requests system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 19996251 # DTB read hits +system.cpu.dtb.read_hits 19996253 # DTB read hits system.cpu.dtb.read_misses 10 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 19996261 # DTB read accesses +system.cpu.dtb.read_accesses 19996263 # DTB read accesses system.cpu.dtb.write_hits 6501863 # DTB write hits system.cpu.dtb.write_misses 23 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations system.cpu.dtb.write_accesses 6501886 # DTB write accesses -system.cpu.dtb.data_hits 26498114 # DTB hits +system.cpu.dtb.data_hits 26498116 # DTB hits system.cpu.dtb.data_misses 33 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 26498147 # DTB accesses -system.cpu.itb.fetch_hits 10035746 # ITB hits +system.cpu.dtb.data_accesses 26498149 # DTB accesses +system.cpu.itb.fetch_hits 9956935 # ITB hits system.cpu.itb.fetch_misses 49 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 10035795 # ITB accesses +system.cpu.itb.fetch_accesses 9956984 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -218,42 +218,42 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 389 # Number of system calls -system.cpu.numCycles 83897439 # number of cpu cycles simulated +system.cpu.numCycles 83230099 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.branch_predictor.lookups 13564910 # Number of BP lookups -system.cpu.branch_predictor.condPredicted 9782241 # Number of conditional branches predicted -system.cpu.branch_predictor.condIncorrect 4497823 # Number of conditional branches incorrect -system.cpu.branch_predictor.BTBLookups 7992573 # Number of BTB lookups -system.cpu.branch_predictor.BTBHits 3850501 # Number of BTB hits +system.cpu.branch_predictor.lookups 13412629 # Number of BP lookups +system.cpu.branch_predictor.condPredicted 9650146 # Number of conditional branches predicted +system.cpu.branch_predictor.condIncorrect 4269214 # Number of conditional branches incorrect +system.cpu.branch_predictor.BTBLookups 7424481 # Number of BTB lookups +system.cpu.branch_predictor.BTBHits 3768497 # Number of BTB hits system.cpu.branch_predictor.usedRAS 1029619 # Number of times the RAS was used to get a target. -system.cpu.branch_predictor.RASInCorrect 122 # Number of incorrect RAS predictions. -system.cpu.branch_predictor.BTBHitPct 48.175988 # BTB Hit Percentage -system.cpu.branch_predictor.predictedTaken 5999726 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 7565184 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 73745307 # Number of Reads from Int. Register File +system.cpu.branch_predictor.RASInCorrect 126 # Number of incorrect RAS predictions. +system.cpu.branch_predictor.BTBHitPct 50.757716 # BTB Hit Percentage +system.cpu.branch_predictor.predictedTaken 5905664 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 7506965 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 73570547 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 62575472 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 136320779 # Total Accesses (Read+Write) to the Int. Register File -system.cpu.regfile_manager.floatRegFileReads 2206802 # Number of Reads from FP Register File +system.cpu.regfile_manager.intRegFileAccesses 136146019 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.floatRegFileReads 2206128 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 5851888 # Number of Writes to FP Register File -system.cpu.regfile_manager.floatRegFileAccesses 8058690 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 38528710 # Number of Registers Read Through Forwarding Logic -system.cpu.agen_unit.agens 26769089 # Number of Address Generations -system.cpu.execution_unit.predictedTakenIncorrect 3520477 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.execution_unit.predictedNotTakenIncorrect 976488 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.execution_unit.mispredicted 4496965 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.predicted 5743737 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.mispredictPct 43.912663 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.executions 57470360 # Number of Instructions Executed. -system.cpu.mult_div_unit.multiplies 458258 # Number of Multipy Operations Executed +system.cpu.regfile_manager.floatRegFileAccesses 8058016 # Total Accesses (Read+Write) to the FP Register File +system.cpu.regfile_manager.regForwards 38521872 # Number of Registers Read Through Forwarding Logic +system.cpu.agen_unit.agens 26722393 # Number of Address Generations +system.cpu.execution_unit.predictedTakenIncorrect 3469296 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.execution_unit.predictedNotTakenIncorrect 799060 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.execution_unit.mispredicted 4268356 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.predicted 5972346 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.mispredictPct 41.680307 # Percentage of Incorrect Branches Predicts +system.cpu.execution_unit.executions 57404029 # Number of Instructions Executed. +system.cpu.mult_div_unit.multiplies 458253 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 83635742 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 82970257 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 10897 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 7614848 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 76282591 # Number of cycles cpu stages are processed. -system.cpu.activity 90.923623 # Percentage of cycles cpu is active +system.cpu.timesIdled 10685 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 7622365 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 75607734 # Number of cycles cpu stages are processed. +system.cpu.activity 90.841817 # Percentage of cycles cpu is active system.cpu.comLoads 19996198 # Number of Load instructions committed system.cpu.comStores 6501103 # Number of Store instructions committed system.cpu.comBranches 10240685 # Number of Branches instructions committed @@ -265,72 +265,72 @@ system.cpu.committedInsts 91903056 # Nu system.cpu.committedOps 91903056 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 91903056 # Number of Instructions committed (Total) -system.cpu.cpi 0.912891 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 0.905629 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 0.912891 # CPI: Total CPI of All Threads -system.cpu.ipc 1.095421 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 0.905629 # CPI: Total CPI of All Threads +system.cpu.ipc 1.104205 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 1.095421 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 27675918 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 56221521 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 67.012202 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 34449958 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 49447481 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 58.938010 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 33919397 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 49978042 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 59.570402 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 65867839 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 18029600 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 21.490048 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 29953374 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 53944065 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 64.297630 # Percentage of cycles stage was utilized (processing insts). -system.cpu.icache.replacements 8127 # number of replacements -system.cpu.icache.tagsinuse 1492.667941 # Cycle average of tags in use -system.cpu.icache.total_refs 10023995 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 10012 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 1001.198062 # Average number of references to valid blocks. +system.cpu.ipc_total 1.104205 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 27549736 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 55680363 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 66.899311 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 33978401 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 49251698 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 59.175345 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 33378776 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 49851323 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 59.895787 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 65203595 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 18026504 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 21.658636 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 29370403 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 53859696 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 64.711801 # Percentage of cycles stage was utilized (processing insts). +system.cpu.icache.replacements 7635 # number of replacements +system.cpu.icache.tagsinuse 1492.730683 # Cycle average of tags in use +system.cpu.icache.total_refs 9945572 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 9520 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 1044.702941 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1492.667941 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.728842 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.728842 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 10023995 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 10023995 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 10023995 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 10023995 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 10023995 # number of overall hits -system.cpu.icache.overall_hits::total 10023995 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 11751 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 11751 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 11751 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 11751 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 11751 # number of overall misses -system.cpu.icache.overall_misses::total 11751 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 259062500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 259062500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 259062500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 259062500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 259062500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 259062500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 10035746 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 10035746 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 10035746 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 10035746 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 10035746 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 10035746 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001171 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.001171 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.001171 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.001171 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.001171 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.001171 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22045.996085 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 22045.996085 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 22045.996085 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 22045.996085 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 22045.996085 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 22045.996085 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1492.730683 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.728872 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.728872 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 9945572 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 9945572 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 9945572 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 9945572 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 9945572 # number of overall hits +system.cpu.icache.overall_hits::total 9945572 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 11363 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 11363 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 11363 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 11363 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 11363 # number of overall misses +system.cpu.icache.overall_misses::total 11363 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 253418000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 253418000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 253418000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 253418000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 253418000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 253418000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 9956935 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 9956935 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 9956935 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 9956935 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 9956935 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 9956935 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001141 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.001141 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.001141 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.001141 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.001141 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.001141 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22302.032914 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 22302.032914 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 22302.032914 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 22302.032914 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 22302.032914 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 22302.032914 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 7 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked @@ -339,171 +339,63 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 7 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1739 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1739 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1739 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1739 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1739 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1739 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 10012 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 10012 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 10012 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 10012 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 10012 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 10012 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 209799500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 209799500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 209799500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 209799500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 209799500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 209799500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000998 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000998 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000998 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000998 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000998 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000998 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20954.804235 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20954.804235 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20954.804235 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 20954.804235 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20954.804235 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 20954.804235 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1843 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1843 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1843 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1843 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1843 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1843 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 9520 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 9520 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 9520 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 9520 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 9520 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 9520 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 204186500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 204186500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 204186500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 204186500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 204186500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 204186500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000956 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000956 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000956 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000956 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000956 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000956 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21448.161765 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21448.161765 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21448.161765 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 21448.161765 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21448.161765 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 21448.161765 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 157 # number of replacements -system.cpu.dcache.tagsinuse 1441.862848 # Cycle average of tags in use -system.cpu.dcache.total_refs 26488630 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 2223 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 11915.713000 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 1441.862848 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.352017 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.352017 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 19995623 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 19995623 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 6493007 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 6493007 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 26488630 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 26488630 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 26488630 # number of overall hits -system.cpu.dcache.overall_hits::total 26488630 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 575 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 575 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 8096 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 8096 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 8671 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 8671 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 8671 # number of overall misses -system.cpu.dcache.overall_misses::total 8671 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 28479000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 28479000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 330607000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 330607000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 359086000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 359086000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 359086000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 359086000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 19996198 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 19996198 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6501103 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 26497301 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 26497301 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 26497301 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 26497301 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000029 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000029 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001245 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.001245 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000327 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000327 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000327 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000327 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 49528.695652 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 49528.695652 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 40835.844862 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 40835.844862 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 41412.293853 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 41412.293853 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 41412.293853 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 41412.293853 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 11966 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 828 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 14.451691 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 107 # number of writebacks -system.cpu.dcache.writebacks::total 107 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 100 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 100 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6348 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 6348 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 6448 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 6448 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 6448 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 6448 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 475 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 475 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1748 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1748 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2223 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2223 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2223 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2223 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 22783000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 22783000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 82274500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 82274500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 105057500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 105057500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 105057500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 105057500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000269 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000269 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.000084 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.000084 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 47964.210526 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 47964.210526 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 47067.791762 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 47067.791762 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 47259.334233 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 47259.334233 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 47259.334233 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 47259.334233 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 2190.279989 # Cycle average of tags in use -system.cpu.l2cache.total_refs 7285 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 2190.387059 # Cycle average of tags in use +system.cpu.l2cache.total_refs 6793 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 3282 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 2.219683 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 2.069775 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 17.844336 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 1821.341583 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 351.094069 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.000545 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.055583 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::writebacks 17.839462 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 1821.429033 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 351.118565 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.000544 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.055586 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.010715 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.066842 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 7218 # number of ReadReq hits +system.cpu.l2cache.occ_percent::total 0.066845 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 6726 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 53 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 7271 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 6779 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 107 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 107 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits::cpu.data 26 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 26 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 7218 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 6726 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.data 79 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 7297 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 7218 # number of overall hits +system.cpu.l2cache.demand_hits::total 6805 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 6726 # number of overall hits system.cpu.l2cache.overall_hits::cpu.data 79 # number of overall hits -system.cpu.l2cache.overall_hits::total 7297 # number of overall hits +system.cpu.l2cache.overall_hits::total 6805 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.inst 2794 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.data 422 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::total 3216 # number of ReadReq misses @@ -515,52 +407,52 @@ system.cpu.l2cache.demand_misses::total 4938 # nu system.cpu.l2cache.overall_misses::cpu.inst 2794 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 2144 # number of overall misses system.cpu.l2cache.overall_misses::total 4938 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 127295000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 21759500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 149054500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 80257000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 80257000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 127295000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 102016500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 229311500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 127295000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 102016500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 229311500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 10012 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 127130500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 21966500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 149097000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 79600500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 79600500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 127130500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 101567000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 228697500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 127130500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 101567000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 228697500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 9520 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 475 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 10487 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 9995 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 107 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 107 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 1748 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 1748 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 10012 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 9520 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 2223 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 12235 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 10012 # number of overall (read+write) accesses +system.cpu.l2cache.demand_accesses::total 11743 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 9520 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 2223 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 12235 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.279065 # miss rate for ReadReq accesses +system.cpu.l2cache.overall_accesses::total 11743 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.293487 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.888421 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.306665 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.321761 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.985126 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.985126 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.279065 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.293487 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.964462 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.403596 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.279065 # miss rate for overall accesses +system.cpu.l2cache.demand_miss_rate::total 0.420506 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.293487 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.964462 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.403596 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 45560.128848 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 51562.796209 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 46347.792289 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 46606.852497 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 46606.852497 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 45560.128848 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 47582.322761 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 46438.132847 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 45560.128848 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 47582.322761 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 46438.132847 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::total 0.420506 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 45501.252684 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52053.317536 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 46361.007463 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 46225.609756 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 46225.609756 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 45501.252684 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 47372.667910 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 46313.791009 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 45501.252684 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 47372.667910 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 46313.791009 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -580,39 +472,147 @@ system.cpu.l2cache.demand_mshr_misses::total 4938 system.cpu.l2cache.overall_mshr_misses::cpu.inst 2794 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 2144 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 4938 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 91926812 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 16443678 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 108370490 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 59040867 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 59040867 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 91926812 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 75484545 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 167411357 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 91926812 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 75484545 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 167411357 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.279065 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 91774816 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 16652177 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 108426993 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 58348895 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 58348895 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 91774816 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 75001072 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 166775888 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 91774816 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 75001072 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 166775888 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.293487 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.888421 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.306665 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.321761 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.985126 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.985126 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.279065 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.293487 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.964462 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.403596 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.279065 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.420506 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.293487 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964462 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.403596 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32901.507516 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 38966.061611 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 33697.291667 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 34286.217770 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 34286.217770 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32901.507516 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 35207.343750 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 33902.664439 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32901.507516 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 35207.343750 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 33902.664439 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.420506 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32847.106657 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 39460.135071 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 33714.861007 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 33884.375726 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 33884.375726 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32847.106657 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 34981.843284 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 33773.974889 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32847.106657 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 34981.843284 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 33773.974889 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.replacements 157 # number of replacements +system.cpu.dcache.tagsinuse 1441.892023 # Cycle average of tags in use +system.cpu.dcache.total_refs 26488629 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 2223 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 11915.712551 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 1441.892023 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.352024 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.352024 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 19995623 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 19995623 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 6493006 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 6493006 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 26488629 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 26488629 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 26488629 # number of overall hits +system.cpu.dcache.overall_hits::total 26488629 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 575 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 575 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 8097 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 8097 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 8672 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 8672 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 8672 # number of overall misses +system.cpu.dcache.overall_misses::total 8672 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 28721000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 28721000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 329862500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 329862500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 358583500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 358583500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 358583500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 358583500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 19996198 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 19996198 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6501103 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 26497301 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 26497301 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 26497301 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 26497301 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000029 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000029 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001245 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.001245 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000327 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000327 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000327 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000327 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 49949.565217 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 49949.565217 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 40738.853897 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 40738.853897 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 41349.573339 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 41349.573339 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 41349.573339 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 41349.573339 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 11994 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 830 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 14.450602 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 107 # number of writebacks +system.cpu.dcache.writebacks::total 107 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 100 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 100 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6349 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 6349 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 6449 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 6449 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 6449 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 6449 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 475 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 475 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1748 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1748 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2223 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2223 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2223 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2223 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 22990000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 22990000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 81618000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 81618000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 104608000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 104608000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 104608000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 104608000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000269 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000269 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.000084 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.000084 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 48400 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 48400 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 46692.219680 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 46692.219680 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 47057.130004 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 47057.130004 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 47057.130004 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 47057.130004 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini index 064828e12..231709206 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini @@ -10,6 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a +clock=1000 init_param=0 kernel= load_addr_mask=1099511627775 @@ -29,7 +30,7 @@ system_port=system.membus.slave[0] [system.cpu] type=DerivO3CPU -children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload +children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -77,6 +78,7 @@ iewToFetchDelay=1 iewToRenameDelay=1 instShiftAmt=2 interrupts=system.cpu.interrupts +isa=system.cpu.isa issueToExecuteDelay=1 issueWidth=8 itb=system.cpu.itb @@ -95,7 +97,6 @@ numPhysIntRegs=256 numROBEntries=192 numRobs=1 numThreads=1 -phase=0 predType=tournament profile=0 progress_interval=0 @@ -129,16 +130,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=2 is_top_level=true -latency=1000 max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=2 size=262144 subblock_size=0 system=system @@ -421,16 +424,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=2 is_top_level=true -latency=1000 max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=2 size=131072 subblock_size=0 system=system @@ -444,6 +449,9 @@ mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=AlphaInterrupts +[system.cpu.isa] +type=AlphaISA + [system.cpu.itb] type=AlphaTLB size=48 @@ -451,22 +459,24 @@ size=48 [system.cpu.l2cache] type=BaseCache addr_ranges=0:18446744073709551615 -assoc=2 +assoc=8 block_size=64 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=20 is_top_level=false -latency=1000 max_miss_count=0 -mshrs=10 +mshrs=20 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=20 size=2097152 subblock_size=0 system=system -tgts_per_mshr=5 +tgts_per_mshr=12 trace_addr=0 two_queue=false write_buffers=8 @@ -476,10 +486,10 @@ mem_side=system.membus.slave[1] [system.cpu.toL2Bus] type=CoherentBus block_size=64 -clock=1000 +clock=500 header_cycles=1 use_default_range=false -width=8 +width=32 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side @@ -489,12 +499,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=twolf smred -cwd=build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/o3-timing +cwd=build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/alpha/tru64/twolf +executable=/projects/pd/randd/dist/cpu2000/binaries/alpha/tru64/twolf gid=100 input=cin max_stack_size=67108864 @@ -512,18 +522,32 @@ clock=1000 header_cycles=1 use_default_range=false width=8 -master=system.physmem.port[0] +master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] -type=SimpleMemory +type=SimpleDRAM +addr_mapping=openmap +banks_per_rank=8 +clock=1000 conf_table_reported=false -file= in_addr_map=true -latency=30000 -latency_var=0 +lines_per_rowbuffer=64 +mem_sched_policy=fcfs null=false +page_policy=open range=0:134217727 +ranks_per_channel=2 +read_buffer_size=32 +tBURST=4000 +tCL=14000 +tRCD=14000 +tREFI=7800000 +tRFC=300000 +tRP=14000 +tWTR=1000 +write_buffer_size=32 +write_thresh_perc=70 zero=false port=system.membus.master[0] diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout index bbfeb5540..4f948ec38 100755 --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout @@ -1,12 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 2 2012 08:30:56 -gem5 started Jul 2 2012 10:49:45 -gem5 executing on zizzer -command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/o3-timing -Couldn't unlink build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/o3-timing/smred.sav -Couldn't unlink build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/o3-timing/smred.sv2 +gem5 compiled Oct 30 2012 11:02:14 +gem5 started Oct 30 2012 13:23:29 +gem5 executing on u200540-lin +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. @@ -23,4 +21,4 @@ Authors: Carl Sechen, Bill Swartz 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 23661066000 because target called exit() +122 123 124 Exiting @ tick 23378067000 because target called exit() diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt index ef2eb2fe7..91f902e42 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt @@ -1,57 +1,57 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.023714 # Number of seconds simulated -sim_ticks 23713623000 # Number of ticks simulated -final_tick 23713623000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.023378 # Number of seconds simulated +sim_ticks 23378067000 # Number of ticks simulated +final_tick 23378067000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 202255 # Simulator instruction rate (inst/s) -host_op_rate 202255 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 56975613 # Simulator tick rate (ticks/s) -host_mem_usage 222752 # Number of bytes of host memory used -host_seconds 416.21 # Real time elapsed on the host +host_inst_rate 166789 # Simulator instruction rate (inst/s) +host_op_rate 166789 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 46320112 # Simulator tick rate (ticks/s) +host_mem_usage 219224 # Number of bytes of host memory used +host_seconds 504.71 # Real time elapsed on the host sim_insts 84179709 # Number of instructions simulated sim_ops 84179709 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 196928 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 138560 # Number of bytes read from this memory -system.physmem.bytes_read::total 335488 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 196928 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 196928 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3077 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2165 # Number of read requests responded to by this memory -system.physmem.num_reads::total 5242 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 8304425 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 5843055 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 14147480 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 8304425 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 8304425 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 8304425 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 5843055 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 14147480 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 5242 # Total number of read requests seen +system.physmem.bytes_read::cpu.inst 196096 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 138496 # Number of bytes read from this memory +system.physmem.bytes_read::total 334592 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 196096 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 196096 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3064 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 2164 # Number of read requests responded to by this memory +system.physmem.num_reads::total 5228 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 8388033 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 5924185 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 14312218 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 8388033 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 8388033 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 8388033 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 5924185 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 14312218 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 5228 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 5242 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 335488 # Total number of bytes read from memory +system.physmem.cpureqs 5228 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 334592 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 335488 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 334592 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 370 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 367 # Track reads on a per bank basis system.physmem.perBankRdReqs::1 340 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 254 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 319 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 254 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 253 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 316 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 255 # Track reads on a per bank basis system.physmem.perBankRdReqs::5 295 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 376 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 404 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 323 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 298 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 277 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 373 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 401 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 320 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 300 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 275 # Track reads on a per bank basis system.physmem.perBankRdReqs::11 288 # Track reads on a per bank basis system.physmem.perBankRdReqs::12 326 # Track reads on a per bank basis system.physmem.perBankRdReqs::13 385 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 380 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 353 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 382 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 352 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis @@ -70,14 +70,14 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 23713517000 # Total gap between requests +system.physmem.totGap 23377961000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 5242 # Categorize read packet sizes +system.physmem.readPktSize::6 5228 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -98,12 +98,12 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 3227 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1550 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 352 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 3190 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1567 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 365 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 92 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 19 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 13 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -164,47 +164,47 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 21552231 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 116524231 # Sum of mem lat for all requests -system.physmem.totBusLat 20968000 # Total cycles spent in databus access -system.physmem.totBankLat 74004000 # Total cycles spent in bank access -system.physmem.avgQLat 4111.45 # Average queueing delay per request -system.physmem.avgBankLat 14117.51 # Average bank access latency per request +system.physmem.totQLat 21787213 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 116311213 # Sum of mem lat for all requests +system.physmem.totBusLat 20912000 # Total cycles spent in databus access +system.physmem.totBankLat 73612000 # Total cycles spent in bank access +system.physmem.avgQLat 4167.41 # Average queueing delay per request +system.physmem.avgBankLat 14080.34 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 22228.96 # Average memory access latency -system.physmem.avgRdBW 14.15 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 22247.75 # Average memory access latency +system.physmem.avgRdBW 14.31 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 14.15 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 14.31 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.09 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 4692 # Number of row buffer hits during reads +system.physmem.readRowHits 4677 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 89.51 # Row buffer hit rate for reads +system.physmem.readRowHitRate 89.46 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 4523753.72 # Average gap between requests +system.physmem.avgGap 4471683.44 # Average gap between requests system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 23220961 # DTB read hits -system.cpu.dtb.read_misses 199829 # DTB read misses +system.cpu.dtb.read_hits 23102664 # DTB read hits +system.cpu.dtb.read_misses 192481 # DTB read misses system.cpu.dtb.read_acv 2 # DTB read access violations -system.cpu.dtb.read_accesses 23420790 # DTB read accesses -system.cpu.dtb.write_hits 7077526 # DTB write hits -system.cpu.dtb.write_misses 1364 # DTB write misses -system.cpu.dtb.write_acv 6 # DTB write access violations -system.cpu.dtb.write_accesses 7078890 # DTB write accesses -system.cpu.dtb.data_hits 30298487 # DTB hits -system.cpu.dtb.data_misses 201193 # DTB misses -system.cpu.dtb.data_acv 8 # DTB access violations -system.cpu.dtb.data_accesses 30499680 # DTB accesses -system.cpu.itb.fetch_hits 14949647 # ITB hits -system.cpu.itb.fetch_misses 105 # ITB misses +system.cpu.dtb.read_accesses 23295145 # DTB read accesses +system.cpu.dtb.write_hits 7068005 # DTB write hits +system.cpu.dtb.write_misses 1092 # DTB write misses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_accesses 7069097 # DTB write accesses +system.cpu.dtb.data_hits 30170669 # DTB hits +system.cpu.dtb.data_misses 193573 # DTB misses +system.cpu.dtb.data_acv 2 # DTB access violations +system.cpu.dtb.data_accesses 30364242 # DTB accesses +system.cpu.itb.fetch_hits 14708082 # ITB hits +system.cpu.itb.fetch_misses 96 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 14949752 # ITB accesses +system.cpu.itb.fetch_accesses 14708178 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -218,246 +218,245 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 389 # Number of system calls -system.cpu.numCycles 47427247 # number of cpu cycles simulated +system.cpu.numCycles 46756135 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 15025642 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 10894363 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 964786 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 8694430 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 7072700 # Number of BTB hits +system.cpu.BPredUnit.lookups 14833517 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 10762267 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 917019 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 8075874 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 6944735 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1485982 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 3318 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 15702309 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 128217574 # Number of instructions fetch has processed -system.cpu.fetch.Branches 15025642 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 8558682 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 22383156 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 4634796 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 5563262 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 84 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 2124 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 19 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 14949647 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 339712 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 47286808 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.711487 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.371391 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1466052 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 3147 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 15430530 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 126815242 # Number of instructions fetch has processed +system.cpu.fetch.Branches 14833517 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 8410787 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 22106787 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 4454905 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 5569972 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 51 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 2009 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 14708082 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 322729 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 46612836 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.720608 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.376239 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 24903652 52.67% 52.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2390695 5.06% 57.72% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1208579 2.56% 60.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1776118 3.76% 64.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2803213 5.93% 69.96% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1173314 2.48% 72.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1230561 2.60% 75.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 786829 1.66% 76.71% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 11013847 23.29% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 24506049 52.57% 52.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2362426 5.07% 57.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1191299 2.56% 60.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1739407 3.73% 63.93% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2752944 5.91% 69.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1147923 2.46% 72.30% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1216668 2.61% 74.91% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 768362 1.65% 76.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 10927758 23.44% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 47286808 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.316815 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.703458 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 17546675 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 4261865 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 20763738 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1090514 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3624016 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 2545492 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 12249 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 125138336 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 32050 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3624016 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 18714540 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 973231 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 8290 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 20663986 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 3302745 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 122153228 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 68 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 400521 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 2428440 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 89689212 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 158636809 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 148888433 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 9748376 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 46612836 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.317253 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.712270 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 17256308 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 4263506 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 20503237 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1097959 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3491826 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 2511850 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 12028 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 123858190 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 32546 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3491826 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 18399179 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 964925 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 7287 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 20435541 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 3314078 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 121046582 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 48 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 399182 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 2434828 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 88894409 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 157311905 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 147648223 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 9663682 # Number of floating rename lookups system.cpu.rename.CommittedMaps 68427361 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 21261851 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 999 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1008 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 8748966 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 25553670 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 8298282 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 2624329 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 917691 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 106148372 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2425 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 96973982 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 186832 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 21507239 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 16151719 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 2036 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 47286808 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.050762 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.875057 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 20467048 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 739 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 732 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 8795383 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 25343096 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 8237940 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 2594464 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 920924 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 105370947 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1446 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 96530679 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 178191 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 20721356 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 15565520 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1057 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 46612836 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.070903 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.875751 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 12523872 26.48% 26.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 9450826 19.99% 46.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 8468072 17.91% 64.38% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 6321623 13.37% 77.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4941695 10.45% 88.20% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2845109 6.02% 94.21% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1728871 3.66% 97.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 797328 1.69% 99.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 209412 0.44% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 12074665 25.90% 25.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 9351108 20.06% 45.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 8402793 18.03% 63.99% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 6288710 13.49% 77.48% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4905546 10.52% 88.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2859533 6.13% 94.14% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1729691 3.71% 97.85% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 796460 1.71% 99.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 204330 0.44% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 47286808 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 46612836 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 189731 12.08% 12.08% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 12.08% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 12.08% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 196 0.01% 12.09% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 12.09% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 7230 0.46% 12.55% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 5874 0.37% 12.92% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 843349 53.68% 66.60% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 66.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 66.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 66.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 66.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 66.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 66.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 66.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 66.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 66.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 66.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 66.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 66.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 66.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 66.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 66.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 66.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 66.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 66.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 66.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 66.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 66.60% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 445490 28.35% 94.95% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 79325 5.05% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 190047 12.12% 12.12% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 12.12% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 12.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 203 0.01% 12.13% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 12.13% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 7055 0.45% 12.58% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 5882 0.38% 12.95% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 842974 53.75% 66.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 66.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 66.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 66.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 66.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 66.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 66.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 66.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 66.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 66.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 66.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 66.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 66.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 66.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 66.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 66.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 66.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 66.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 66.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 66.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 66.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 66.70% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 444058 28.31% 95.01% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 78249 4.99% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 7 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 58981330 60.82% 60.82% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 480636 0.50% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 58717725 60.83% 60.83% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 479593 0.50% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2802326 2.89% 64.21% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 115452 0.12% 64.33% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 2386635 2.46% 66.79% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 311394 0.32% 67.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 759833 0.78% 67.89% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 319 0.00% 67.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.89% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 23966232 24.71% 92.61% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 7169818 7.39% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2796739 2.90% 64.22% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 115257 0.12% 64.34% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 2386885 2.47% 66.81% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 311006 0.32% 67.14% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 760000 0.79% 67.92% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 319 0.00% 67.92% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.92% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.92% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.92% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.92% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.92% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.92% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.92% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.92% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.92% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.92% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.92% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.92% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.92% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.92% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.92% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.92% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.92% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.92% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.92% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.92% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 23812199 24.67% 92.59% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 7150949 7.41% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 96973982 # Type of FU issued -system.cpu.iq.rate 2.044689 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1571195 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.016202 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 227861218 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 118862045 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 87356059 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 15131581 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 8830751 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 7068549 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 90549768 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 7995402 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1518620 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 96530679 # Type of FU issued +system.cpu.iq.rate 2.064556 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1568468 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.016248 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 226318050 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 117401953 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 87051166 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 15102803 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 8726703 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 7059295 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 90117667 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 7981473 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1519109 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 5557472 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 19450 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 34891 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1797179 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 5346898 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 18469 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 35032 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1736837 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 10488 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1489 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 10557 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1512 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3624016 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 135468 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 17609 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 116444859 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 396288 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 25553670 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 8298282 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 2425 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 3185 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 28 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 34891 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 568741 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 508698 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1077439 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 95679677 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 23421457 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1294305 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3491826 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 132020 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 18316 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 115597875 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 364987 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 25343096 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 8237940 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1446 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 3142 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 30 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 35032 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 529110 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 494336 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1023446 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 95309066 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 23295605 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1221613 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 10294062 # number of nop insts executed -system.cpu.iew.exec_refs 30500537 # number of memory reference insts executed -system.cpu.iew.exec_branches 12076025 # Number of branches executed -system.cpu.iew.exec_stores 7079080 # Number of stores executed -system.cpu.iew.exec_rate 2.017399 # Inst execution rate -system.cpu.iew.wb_sent 94965900 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 94424608 # cumulative count of insts written-back -system.cpu.iew.wb_producers 64613443 # num instructions producing a value -system.cpu.iew.wb_consumers 89987902 # num instructions consuming a value +system.cpu.iew.exec_nop 10225482 # number of nop insts executed +system.cpu.iew.exec_refs 30364899 # number of memory reference insts executed +system.cpu.iew.exec_branches 12021435 # Number of branches executed +system.cpu.iew.exec_stores 7069294 # Number of stores executed +system.cpu.iew.exec_rate 2.038429 # Inst execution rate +system.cpu.iew.wb_sent 94627849 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 94110461 # cumulative count of insts written-back +system.cpu.iew.wb_producers 64468484 # num instructions producing a value +system.cpu.iew.wb_consumers 89853069 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.990936 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.718024 # average fanout of values written-back +system.cpu.iew.wb_rate 2.012794 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.717488 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 24543105 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 23695922 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 389 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 952948 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 43662792 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.104837 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.733240 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 905358 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 43121010 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.131283 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.747044 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 17112386 39.19% 39.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 9977533 22.85% 62.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4511330 10.33% 72.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2294197 5.25% 77.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1617378 3.70% 81.33% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1129034 2.59% 83.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 721116 1.65% 85.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 819651 1.88% 87.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5480167 12.55% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 16684738 38.69% 38.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 9903892 22.97% 61.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4485087 10.40% 72.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2259914 5.24% 77.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1605498 3.72% 81.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1123100 2.60% 83.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 719913 1.67% 85.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 818667 1.90% 87.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5520201 12.80% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 43662792 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 43121010 # Number of insts commited each cycle system.cpu.commit.committedInsts 91903055 # Number of instructions committed system.cpu.commit.committedOps 91903055 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -468,372 +467,372 @@ system.cpu.commit.branches 10240685 # Nu system.cpu.commit.fp_insts 6862061 # Number of committed floating point instructions. system.cpu.commit.int_insts 79581076 # Number of committed integer instructions. system.cpu.commit.function_calls 1029620 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5480167 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5520201 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 154627745 # The number of ROB reads -system.cpu.rob.rob_writes 236540658 # The number of ROB writes -system.cpu.timesIdled 5097 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 140439 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 153198746 # The number of ROB reads +system.cpu.rob.rob_writes 234713539 # The number of ROB writes +system.cpu.timesIdled 5103 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 143299 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 84179709 # Number of Instructions Simulated system.cpu.committedOps 84179709 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 84179709 # Number of Instructions Simulated -system.cpu.cpi 0.563405 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.563405 # CPI: Total CPI of All Threads -system.cpu.ipc 1.774923 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.774923 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 129451321 # number of integer regfile reads -system.cpu.int_regfile_writes 70766811 # number of integer regfile writes -system.cpu.fp_regfile_reads 6191777 # number of floating regfile reads -system.cpu.fp_regfile_writes 6050030 # number of floating regfile writes -system.cpu.misc_regfile_reads 714415 # number of misc regfile reads +system.cpu.cpi 0.555432 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.555432 # CPI: Total CPI of All Threads +system.cpu.ipc 1.800399 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.800399 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 129015669 # number of integer regfile reads +system.cpu.int_regfile_writes 70499119 # number of integer regfile writes +system.cpu.fp_regfile_reads 6185969 # number of floating regfile reads +system.cpu.fp_regfile_writes 6040722 # number of floating regfile writes +system.cpu.misc_regfile_reads 714490 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.icache.replacements 10208 # number of replacements -system.cpu.icache.tagsinuse 1605.593166 # Cycle average of tags in use -system.cpu.icache.total_refs 14934718 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 12146 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 1229.599704 # Average number of references to valid blocks. +system.cpu.icache.replacements 9535 # number of replacements +system.cpu.icache.tagsinuse 1597.711655 # Cycle average of tags in use +system.cpu.icache.total_refs 14694095 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 11468 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 1281.312783 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1605.593166 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.783981 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.783981 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 14934718 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 14934718 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 14934718 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 14934718 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 14934718 # number of overall hits -system.cpu.icache.overall_hits::total 14934718 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 14928 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 14928 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 14928 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 14928 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 14928 # number of overall misses -system.cpu.icache.overall_misses::total 14928 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 320401000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 320401000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 320401000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 320401000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 320401000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 320401000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 14949646 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 14949646 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 14949646 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 14949646 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 14949646 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 14949646 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000999 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000999 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000999 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000999 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000999 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000999 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21463.089496 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 21463.089496 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 21463.089496 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 21463.089496 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 21463.089496 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 21463.089496 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 207 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 1597.711655 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.780133 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.780133 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 14694095 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 14694095 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 14694095 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 14694095 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 14694095 # number of overall hits +system.cpu.icache.overall_hits::total 14694095 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 13987 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 13987 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 13987 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 13987 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 13987 # number of overall misses +system.cpu.icache.overall_misses::total 13987 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 308160500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 308160500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 308160500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 308160500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 308160500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 308160500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 14708082 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 14708082 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 14708082 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 14708082 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 14708082 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 14708082 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000951 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000951 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000951 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000951 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000951 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000951 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22031.922499 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 22031.922499 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 22031.922499 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 22031.922499 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 22031.922499 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 22031.922499 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 97 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 41.400000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 19.400000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2782 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 2782 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 2782 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 2782 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 2782 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 2782 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 12146 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 12146 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 12146 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 12146 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 12146 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 12146 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 242268500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 242268500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 242268500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 242268500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 242268500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 242268500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000812 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000812 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000812 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000812 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000812 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000812 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19946.360942 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19946.360942 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19946.360942 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 19946.360942 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19946.360942 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 19946.360942 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2519 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 2519 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 2519 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 2519 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 2519 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 2519 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 11468 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 11468 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 11468 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 11468 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 11468 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 11468 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 234957500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 234957500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 234957500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 234957500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 234957500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 234957500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000780 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000780 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000780 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000780 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000780 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000780 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20488.097314 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20488.097314 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20488.097314 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 20488.097314 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20488.097314 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 20488.097314 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 158 # number of replacements -system.cpu.dcache.tagsinuse 1458.435251 # Cycle average of tags in use -system.cpu.dcache.total_refs 28182735 # Total number of references to valid blocks. +system.cpu.l2cache.replacements 0 # number of replacements +system.cpu.l2cache.tagsinuse 2411.634709 # Cycle average of tags in use +system.cpu.l2cache.total_refs 8474 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 3589 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 2.361103 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::writebacks 17.671111 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 2014.246310 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 379.717288 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.000539 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.061470 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.011588 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.073597 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 8404 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 55 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 8459 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 109 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 109 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 26 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 26 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 8404 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 81 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 8485 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 8404 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 81 # number of overall hits +system.cpu.l2cache.overall_hits::total 8485 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 3064 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 458 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 3522 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 1706 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 1706 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 3064 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 2164 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 5228 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 3064 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 2164 # number of overall misses +system.cpu.l2cache.overall_misses::total 5228 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 139445500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 25445000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 164890500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 80526000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 80526000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 139445500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 105971000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 245416500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 139445500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 105971000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 245416500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 11468 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 513 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 11981 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 109 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 109 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 1732 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 1732 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 11468 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 2245 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 13713 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 11468 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 2245 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 13713 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.267178 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.892788 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.293965 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.984988 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.984988 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.267178 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.963920 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.381244 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.267178 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.963920 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.381244 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 45510.933420 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 55556.768559 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 46817.291312 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 47201.641266 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 47201.641266 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 45510.933420 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 48969.963031 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 46942.712318 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 45510.933420 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 48969.963031 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 46942.712318 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3064 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 458 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 3522 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1706 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 1706 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3064 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 2164 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 5228 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3064 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 2164 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 5228 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 100817136 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 19709120 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 120526256 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 59472062 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 59472062 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 100817136 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 79181182 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 179998318 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 100817136 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 79181182 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 179998318 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.267178 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.892788 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.293965 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.984988 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.984988 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.267178 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.963920 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.381244 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.267178 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.963920 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.381244 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32903.765013 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 43033.013100 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 34220.969903 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 34860.528722 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 34860.528722 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32903.765013 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 36590.195009 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 34429.670620 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32903.765013 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 36590.195009 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 34429.670620 # average overall mshr miss latency +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.replacements 159 # number of replacements +system.cpu.dcache.tagsinuse 1458.941648 # Cycle average of tags in use +system.cpu.dcache.total_refs 28063904 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 2245 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 12553.556793 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 12500.625390 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 1458.435251 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.356063 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.356063 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 21689327 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 21689327 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 6492999 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 6492999 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 409 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 409 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 28182326 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 28182326 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 28182326 # number of overall hits -system.cpu.dcache.overall_hits::total 28182326 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1019 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1019 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 8104 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 8104 # number of WriteReq misses +system.cpu.dcache.occ_blocks::cpu.data 1458.941648 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.356187 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.356187 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 21570663 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 21570663 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 6493007 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 6493007 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 234 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 234 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 28063670 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 28063670 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 28063670 # number of overall hits +system.cpu.dcache.overall_hits::total 28063670 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 977 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 977 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 8096 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 8096 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 9123 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9123 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9123 # number of overall misses -system.cpu.dcache.overall_misses::total 9123 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 44496500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 44496500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 347386146 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 347386146 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 9073 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9073 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9073 # number of overall misses +system.cpu.dcache.overall_misses::total 9073 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 44122000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 44122000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 343188654 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 343188654 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 72000 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 72000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 391882646 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 391882646 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 391882646 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 391882646 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 21690346 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 21690346 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 387310654 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 387310654 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 387310654 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 387310654 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 21571640 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 21571640 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 6501103 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 410 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 410 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 28191449 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 28191449 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 28191449 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 28191449 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000047 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000047 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001247 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.001247 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.002439 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.002439 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000324 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000324 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000324 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000324 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 43666.830226 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 43666.830226 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42866.010118 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 42866.010118 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 235 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 235 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 28072743 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 28072743 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 28072743 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 28072743 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000045 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000045 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001245 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.001245 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.004255 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.004255 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000323 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000323 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000323 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000323 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 45160.696008 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 45160.696008 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42389.902915 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 42389.902915 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 72000 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 72000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 42955.458292 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 42955.458292 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 42955.458292 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 42955.458292 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 11029 # number of cycles access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 42688.267828 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 42688.267828 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 42688.267828 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 42688.267828 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 10592 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 474 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 468 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 23.267932 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 22.632479 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 108 # number of writebacks -system.cpu.dcache.writebacks::total 108 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 508 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 508 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6371 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 6371 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 6879 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 6879 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 6879 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 6879 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 511 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 511 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1733 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1733 # number of WriteReq MSHR misses +system.cpu.dcache.writebacks::writebacks 109 # number of writebacks +system.cpu.dcache.writebacks::total 109 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 465 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 465 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6364 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 6364 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 6829 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 6829 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 6829 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 6829 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 512 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 512 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1732 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1732 # number of WriteReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses system.cpu.dcache.demand_mshr_misses::cpu.data 2244 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses::total 2244 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 2244 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 2244 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 26251500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 26251500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 83394995 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 83394995 # number of WriteReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 26453500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 26453500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 82660498 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 82660498 # number of WriteReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 70000 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 70000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 109646495 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 109646495 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 109646495 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 109646495 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 109113998 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 109113998 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 109113998 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 109113998 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000267 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000267 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.002439 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.002439 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000266 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000266 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.004255 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.004255 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000080 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.000080 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000080 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000080 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 51372.798434 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 51372.798434 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 48121.751298 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 48121.751298 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 51666.992188 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 51666.992188 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 47725.460739 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 47725.460739 # average WriteReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 70000 # average LoadLockedReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 70000 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 48862.074421 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 48862.074421 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 48862.074421 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 48862.074421 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 48624.776292 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 48624.776292 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 48624.776292 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 48624.776292 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 2419.268456 # Cycle average of tags in use -system.cpu.l2cache.total_refs 9138 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 3601 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 2.537628 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 17.697198 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 2024.332365 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 377.238893 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.000540 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.061778 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.011512 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.073830 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 9069 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 54 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 9123 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 108 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 108 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 26 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 26 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 9069 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 80 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 9149 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 9069 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 80 # number of overall hits -system.cpu.l2cache.overall_hits::total 9149 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 3077 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 458 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 3535 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 1707 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 1707 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 3077 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 2165 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 5242 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 3077 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 2165 # number of overall misses -system.cpu.l2cache.overall_misses::total 5242 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 139425500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 25252500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 164678000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 81258000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 81258000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 139425500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 106510500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 245936000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 139425500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 106510500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 245936000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 12146 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 512 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 12658 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 108 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 108 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 1733 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 1733 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 12146 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 2245 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 14391 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 12146 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 2245 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 14391 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.253334 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.894531 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.279270 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.984997 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.984997 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.253334 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.964365 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.364255 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.253334 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.964365 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.364255 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 45312.154696 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 55136.462882 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 46585.007072 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 47602.811951 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 47602.811951 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 45312.154696 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 49196.535797 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 46916.444105 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 45312.154696 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 49196.535797 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 46916.444105 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3077 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 458 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 3535 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1707 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 1707 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3077 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 2165 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 5242 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3077 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 2165 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 5242 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 100633163 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 19510628 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 120143791 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 60209566 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 60209566 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 100633163 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 79720194 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 180353357 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 100633163 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 79720194 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 180353357 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.253334 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.894531 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.279270 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.984997 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.984997 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.253334 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.964365 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.364255 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.253334 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964365 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.364255 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32704.960351 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42599.624454 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 33986.928147 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 35272.153486 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 35272.153486 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32704.960351 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 36822.260508 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 34405.447730 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32704.960351 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 36822.260508 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 34405.447730 # average overall mshr miss latency -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini index 6abd7ca4a..27e85dd46 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini @@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a -clock=1 +clock=1000 init_param=0 kernel= load_addr_mask=1099511627775 @@ -30,7 +30,7 @@ system_port=system.membus.slave[0] [system.cpu] type=DerivO3CPU -children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload +children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -78,6 +78,7 @@ iewToFetchDelay=1 iewToRenameDelay=1 instShiftAmt=2 interrupts=system.cpu.interrupts +isa=system.cpu.isa issueToExecuteDelay=1 issueWidth=8 itb=system.cpu.itb @@ -129,18 +130,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=262144 subblock_size=0 system=system @@ -159,7 +160,7 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=ArmTableWalker -clock=1 +clock=500 num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[3] @@ -432,18 +433,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=131072 subblock_size=0 system=system @@ -457,6 +458,23 @@ mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=ArmInterrupts +[system.cpu.isa] +type=ArmISA +fpsid=1090793632 +id_isar0=34607377 +id_isar1=34677009 +id_isar2=555950401 +id_isar3=17899825 +id_isar4=268501314 +id_isar5=0 +id_mmfr0=3 +id_mmfr1=0 +id_mmfr2=19070976 +id_mmfr3=4027589137 +id_pfr0=49 +id_pfr1=1 +midr=890224640 + [system.cpu.itb] type=ArmTLB children=walker @@ -465,7 +483,7 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=ArmTableWalker -clock=1 +clock=500 num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[2] @@ -473,24 +491,24 @@ port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] type=BaseCache addr_ranges=0:18446744073709551615 -assoc=2 +assoc=8 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=20 is_top_level=false max_miss_count=0 -mshrs=10 +mshrs=20 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=20 size=2097152 subblock_size=0 system=system -tgts_per_mshr=5 +tgts_per_mshr=12 trace_addr=0 two_queue=false write_buffers=8 @@ -500,10 +518,10 @@ mem_side=system.membus.slave[1] [system.cpu.toL2Bus] type=CoherentBus block_size=64 -clock=1000 +clock=500 header_cycles=1 use_default_range=false -width=8 +width=32 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port @@ -540,15 +558,28 @@ master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] -type=SimpleMemory -bandwidth=73.000000 -clock=1 +type=SimpleDRAM +addr_mapping=openmap +banks_per_rank=8 +clock=1000 conf_table_reported=false in_addr_map=true -latency=30000 -latency_var=0 +lines_per_rowbuffer=64 +mem_sched_policy=fcfs null=false +page_policy=open range=0:134217727 +ranks_per_channel=2 +read_buffer_size=32 +tBURST=4000 +tCL=14000 +tRCD=14000 +tREFI=7800000 +tRFC=300000 +tRP=14000 +tWTR=1000 +write_buffer_size=32 +write_thresh_perc=70 zero=false port=system.membus.master[0] diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout index b01ca9643..df8c6714b 100755 --- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout @@ -1,12 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 21 2012 11:19:00 -gem5 started Sep 21 2012 13:57:03 +gem5 compiled Oct 30 2012 11:20:14 +gem5 started Oct 30 2012 20:48:26 gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing -Couldn't unlink build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing/smred.sav -Couldn't unlink build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -23,4 +21,4 @@ info: Increasing stack size by one page. 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 76020082000 because target called exit() +122 123 124 Exiting @ tick 74245032000 because target called exit() diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt index 3d59bfc93..341764510 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt @@ -1,57 +1,57 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.075963 # Number of seconds simulated -sim_ticks 75962996000 # Number of ticks simulated -final_tick 75962996000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.074245 # Number of seconds simulated +sim_ticks 74245032000 # Number of ticks simulated +final_tick 74245032000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 82470 # Simulator instruction rate (inst/s) -host_op_rate 90296 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 36352186 # Simulator tick rate (ticks/s) -host_mem_usage 236740 # Number of bytes of host memory used -host_seconds 2089.64 # Real time elapsed on the host -sim_insts 172333241 # Number of instructions simulated -sim_ops 188686723 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 132736 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 112192 # Number of bytes read from this memory -system.physmem.bytes_read::total 244928 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 132736 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 132736 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 2074 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1753 # Number of read requests responded to by this memory -system.physmem.num_reads::total 3827 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1747377 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1476930 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3224307 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1747377 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1747377 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1747377 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1476930 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3224307 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 3828 # Total number of read requests seen +host_inst_rate 109443 # Simulator instruction rate (inst/s) +host_op_rate 119829 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 47150577 # Simulator tick rate (ticks/s) +host_mem_usage 234068 # Number of bytes of host memory used +host_seconds 1574.64 # Real time elapsed on the host +sim_insts 172333441 # Number of instructions simulated +sim_ops 188686923 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 131008 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 111680 # Number of bytes read from this memory +system.physmem.bytes_read::total 242688 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 131008 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 131008 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 2047 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1745 # Number of read requests responded to by this memory +system.physmem.num_reads::total 3792 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1764536 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1504208 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3268744 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1764536 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1764536 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1764536 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1504208 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3268744 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 3793 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 3829 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 244928 # Total number of bytes read from memory +system.physmem.cpureqs 3795 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 242688 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 244928 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 242688 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 1 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 320 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 234 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 192 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 240 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 228 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 194 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 224 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 284 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 247 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 249 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 248 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 263 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 249 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 236 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 182 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 238 # Track reads on a per bank basis +system.physmem.neitherReadNorWrite 2 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 319 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 231 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 191 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 236 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 227 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 193 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 221 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 282 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 242 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 247 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 247 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 259 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 248 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 234 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 179 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 237 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis @@ -70,14 +70,14 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 75962976500 # Total gap between requests +system.physmem.totGap 74245012500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 3828 # Categorize read packet sizes +system.physmem.readPktSize::6 3793 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -95,15 +95,15 @@ system.physmem.neitherpktsize::2 0 # ca system.physmem.neitherpktsize::3 0 # categorize neither packet sizes system.physmem.neitherpktsize::4 0 # categorize neither packet sizes system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 1 # categorize neither packet sizes +system.physmem.neitherpktsize::6 2 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 2829 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 799 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 151 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 40 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 2791 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 811 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 147 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 38 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -164,27 +164,27 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 15909310 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 90413310 # Sum of mem lat for all requests -system.physmem.totBusLat 15312000 # Total cycles spent in databus access -system.physmem.totBankLat 59192000 # Total cycles spent in bank access -system.physmem.avgQLat 4156.04 # Average queueing delay per request -system.physmem.avgBankLat 15462.90 # Average bank access latency per request +system.physmem.totQLat 12366785 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 86366785 # Sum of mem lat for all requests +system.physmem.totBusLat 15172000 # Total cycles spent in databus access +system.physmem.totBankLat 58828000 # Total cycles spent in bank access +system.physmem.avgQLat 3260.42 # Average queueing delay per request +system.physmem.avgBankLat 15509.62 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 23618.94 # Average memory access latency -system.physmem.avgRdBW 3.22 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 22770.05 # Average memory access latency +system.physmem.avgRdBW 3.27 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 3.22 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 3.27 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 3324 # Number of row buffer hits during reads +system.physmem.readRowHits 3295 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 86.83 # Row buffer hit rate for reads +system.physmem.readRowHitRate 86.87 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 19844037.75 # Average gap between requests +system.physmem.avgGap 19574218.96 # Average gap between requests system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -228,647 +228,645 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 151925993 # number of cpu cycles simulated +system.cpu.numCycles 148490065 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 96812188 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 76032236 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 6553809 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 46446152 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 44209779 # Number of BTB hits +system.cpu.BPredUnit.lookups 94824011 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 74811084 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 6283419 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 44691419 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 43068728 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 4476893 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 89558 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 40612935 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 388214882 # Number of instructions fetch has processed -system.cpu.fetch.Branches 96812188 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 48686672 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 82228989 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 28431080 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 7111966 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 46 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 9226 # Number of stall cycles due to pending traps +system.cpu.BPredUnit.usedRAS 4355687 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 88461 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 39671704 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 380334125 # Number of instructions fetch has processed +system.cpu.fetch.Branches 94824011 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 47424415 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 80393373 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 27296286 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 7321256 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 12 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 4918 # Number of stall cycles due to pending traps system.cpu.fetch.PendingQuiesceStallCycles 1 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 57 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 37654254 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 1887415 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 151824267 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.799061 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.153208 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.IcacheWaitRetryStallCycles 51 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 36859860 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 1828379 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 148388373 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.800016 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.152801 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 69765849 45.95% 45.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 5500538 3.62% 49.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 10700560 7.05% 56.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 10437997 6.88% 63.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 8786758 5.79% 69.29% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 6834684 4.50% 73.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 6296298 4.15% 77.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 8361211 5.51% 83.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 25140372 16.56% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 68164460 45.94% 45.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 5263921 3.55% 49.48% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 10532073 7.10% 56.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 10289171 6.93% 63.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 8658719 5.84% 69.35% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 6556174 4.42% 73.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 6250200 4.21% 77.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 8011886 5.40% 83.38% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 24661769 16.62% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 151824267 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.637233 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.555289 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 46639472 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 5819765 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 76543741 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1113557 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 21707732 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 14816289 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 162918 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 401266810 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 729123 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 21707732 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 52145776 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 716376 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 699385 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 72090483 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 4464515 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 378976726 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 19 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 316631 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 3575950 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 15 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 642441440 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1614452334 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1596874036 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 17578298 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 298092491 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 344348949 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 33473 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 33471 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12628265 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 43987484 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 16888261 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 5791013 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 3746055 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 334831031 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 55567 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 252811108 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 890392 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 144974552 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 373956822 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 4307 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 151824267 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.665156 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.759693 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 148388373 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.638588 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.561344 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 45525708 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 5988328 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 74834240 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1196373 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 20843724 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 14343881 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 164426 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 392938907 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 736414 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 20843724 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 50922630 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 727420 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 699991 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 70572280 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 4622328 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 371457492 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 22 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 340569 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 3661423 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 29 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 631852668 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1582346867 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1565037376 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 17309491 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 298092811 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 333759857 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 32532 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 32528 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13064863 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 43027461 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 16443523 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 5668310 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 3691413 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 329308816 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 54643 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 249531465 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 795533 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 139603170 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 362284552 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 3343 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 148388373 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.681611 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.761108 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 58367016 38.44% 38.44% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 23007793 15.15% 53.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 25146514 16.56% 70.16% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 20482198 13.49% 83.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12879503 8.48% 92.13% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 6581643 4.34% 96.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 4062886 2.68% 99.15% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1113562 0.73% 99.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 183152 0.12% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 56153945 37.84% 37.84% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 22688522 15.29% 53.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 24821947 16.73% 69.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 20330759 13.70% 83.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12554169 8.46% 92.02% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 6514357 4.39% 96.41% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 4035019 2.72% 99.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1109043 0.75% 99.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 180612 0.12% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 151824267 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 148388373 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 966665 37.55% 37.55% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 5596 0.22% 37.77% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 37.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 37.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 37.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 37.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 37.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 37.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 37.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 37.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 37.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 37.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 37.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 37.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 37.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 37.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 37.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 37.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 37.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 37.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 94 0.00% 37.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 37.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 37.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 37.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 37.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 27 0.00% 37.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 37.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 37.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 37.78% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1198357 46.55% 84.33% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 403391 15.67% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 962652 38.43% 38.43% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 5596 0.22% 38.65% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 38.65% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 38.65% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 38.65% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 38.65% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 38.65% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 38.65% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 38.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 38.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 38.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 38.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 38.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 38.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 38.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 38.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 38.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 38.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 38.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 38.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 100 0.00% 38.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 38.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 38.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 38.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 38.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 50 0.00% 38.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 38.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 38.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 38.66% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1162967 46.43% 85.09% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 373557 14.91% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 197328873 78.05% 78.05% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 995382 0.39% 78.45% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.45% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.45% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.45% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 78.45% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 78.45% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 78.45% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 78.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 78.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 78.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 78.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 78.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 78.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 78.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 78.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 33194 0.01% 78.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 163810 0.06% 78.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 255234 0.10% 78.63% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 76440 0.03% 78.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 467356 0.18% 78.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 206283 0.08% 78.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 71857 0.03% 78.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 320 0.00% 78.95% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 39021114 15.43% 94.39% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 14191245 5.61% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 194943196 78.12% 78.12% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 980225 0.39% 78.52% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 78.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 78.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 78.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 78.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 78.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 78.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 78.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 78.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 78.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 78.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 78.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 33090 0.01% 78.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 164479 0.07% 78.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 254525 0.10% 78.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 76418 0.03% 78.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 465710 0.19% 78.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 206458 0.08% 79.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 71854 0.03% 79.03% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 321 0.00% 79.03% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 38372441 15.38% 94.40% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 13962748 5.60% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 252811108 # Type of FU issued -system.cpu.iq.rate 1.664041 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2574130 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.010182 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 657138452 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 477635375 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 240576408 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 3772553 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 2244745 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 1851453 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 253490963 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 1894275 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 2028433 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 249531465 # Type of FU issued +system.cpu.iq.rate 1.680459 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2504922 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.010039 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 647013011 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 466795184 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 237947786 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 3738747 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 2189794 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 1841578 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 250160112 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 1876275 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 2013222 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 14131956 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 16953 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 19730 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 4237583 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 13171893 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 11381 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 18785 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 3792805 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 4 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 84 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 14 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 96 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 21707732 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 16237 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 835 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 334904365 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 834808 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 43987484 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 16888261 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 33011 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 182 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 269 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 19730 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 4101344 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 3925912 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 8027256 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 245818022 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 37400003 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 6993086 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 20843724 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 17321 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 891 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 329380427 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 786985 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 43027461 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 16443523 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 32104 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 209 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 288 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 18785 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 3890771 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 3762289 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 7653060 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 243027736 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 36864796 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 6503729 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 17767 # number of nop insts executed -system.cpu.iew.exec_refs 51208402 # number of memory reference insts executed -system.cpu.iew.exec_branches 54033495 # Number of branches executed -system.cpu.iew.exec_stores 13808399 # Number of stores executed -system.cpu.iew.exec_rate 1.618012 # Inst execution rate -system.cpu.iew.wb_sent 243559168 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 242427861 # cumulative count of insts written-back -system.cpu.iew.wb_producers 150062323 # num instructions producing a value -system.cpu.iew.wb_consumers 269174598 # num instructions consuming a value +system.cpu.iew.exec_nop 16968 # number of nop insts executed +system.cpu.iew.exec_refs 50523279 # number of memory reference insts executed +system.cpu.iew.exec_branches 53444477 # Number of branches executed +system.cpu.iew.exec_stores 13658483 # Number of stores executed +system.cpu.iew.exec_rate 1.636660 # Inst execution rate +system.cpu.iew.wb_sent 240848315 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 239789364 # cumulative count of insts written-back +system.cpu.iew.wb_producers 148488630 # num instructions producing a value +system.cpu.iew.wb_consumers 267300896 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.595697 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.557491 # average fanout of values written-back +system.cpu.iew.wb_rate 1.614851 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.555511 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 146203238 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 51260 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 6400494 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 130116536 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.450247 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.162155 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 140679091 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 51300 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 6130085 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 127544650 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.479492 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.184685 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 59888298 46.03% 46.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 32076129 24.65% 70.68% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 13982572 10.75% 81.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 7654340 5.88% 87.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 4412681 3.39% 90.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1335897 1.03% 91.73% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1741211 1.34% 93.06% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1283921 0.99% 94.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 7741487 5.95% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 57798190 45.32% 45.32% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 31737959 24.88% 70.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 13785979 10.81% 81.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 7635406 5.99% 87.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 4383857 3.44% 90.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1319533 1.03% 91.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1705049 1.34% 92.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1307627 1.03% 93.83% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 7871050 6.17% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 130116536 # Number of insts commited each cycle -system.cpu.commit.committedInsts 172347629 # Number of instructions committed -system.cpu.commit.committedOps 188701111 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 127544650 # Number of insts commited each cycle +system.cpu.commit.committedInsts 172347829 # Number of instructions committed +system.cpu.commit.committedOps 188701311 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 42506206 # Number of memory references committed -system.cpu.commit.loads 29855528 # Number of loads committed +system.cpu.commit.refs 42506286 # Number of memory references committed +system.cpu.commit.loads 29855568 # Number of loads committed system.cpu.commit.membars 22408 # Number of memory barriers committed -system.cpu.commit.branches 40306355 # Number of branches committed +system.cpu.commit.branches 40306395 # Number of branches committed system.cpu.commit.fp_insts 1752310 # Number of committed floating point instructions. -system.cpu.commit.int_insts 150130393 # Number of committed integer instructions. +system.cpu.commit.int_insts 150130553 # Number of committed integer instructions. system.cpu.commit.function_calls 1848934 # Number of function calls committed. -system.cpu.commit.bw_lim_events 7741487 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 7871050 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 457274197 # The number of ROB reads -system.cpu.rob.rob_writes 691635591 # The number of ROB writes -system.cpu.timesIdled 2582 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 101726 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 172333241 # Number of Instructions Simulated -system.cpu.committedOps 188686723 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 172333241 # Number of Instructions Simulated -system.cpu.cpi 0.881583 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.881583 # CPI: Total CPI of All Threads -system.cpu.ipc 1.134324 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.134324 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1091906245 # number of integer regfile reads -system.cpu.int_regfile_writes 388600616 # number of integer regfile writes -system.cpu.fp_regfile_reads 2911397 # number of floating regfile reads -system.cpu.fp_regfile_writes 2511024 # number of floating regfile writes -system.cpu.misc_regfile_reads 474438629 # number of misc regfile reads -system.cpu.misc_regfile_writes 832124 # number of misc regfile writes -system.cpu.icache.replacements 2644 # number of replacements -system.cpu.icache.tagsinuse 1367.286315 # Cycle average of tags in use -system.cpu.icache.total_refs 37648759 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 4386 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 8583.848381 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 449048801 # The number of ROB reads +system.cpu.rob.rob_writes 679713725 # The number of ROB writes +system.cpu.timesIdled 2572 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 101692 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 172333441 # Number of Instructions Simulated +system.cpu.committedOps 188686923 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 172333441 # Number of Instructions Simulated +system.cpu.cpi 0.861644 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.861644 # CPI: Total CPI of All Threads +system.cpu.ipc 1.160572 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.160572 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1079711901 # number of integer regfile reads +system.cpu.int_regfile_writes 384939818 # number of integer regfile writes +system.cpu.fp_regfile_reads 2913621 # number of floating regfile reads +system.cpu.fp_regfile_writes 2497505 # number of floating regfile writes +system.cpu.misc_regfile_reads 464692735 # number of misc regfile reads +system.cpu.misc_regfile_writes 832204 # number of misc regfile writes +system.cpu.icache.replacements 2508 # number of replacements +system.cpu.icache.tagsinuse 1347.136586 # Cycle average of tags in use +system.cpu.icache.total_refs 36854521 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 4234 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 8704.421587 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1367.286315 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.667620 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.667620 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 37648759 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 37648759 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 37648759 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 37648759 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 37648759 # number of overall hits -system.cpu.icache.overall_hits::total 37648759 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 5495 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 5495 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 5495 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 5495 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 5495 # number of overall misses -system.cpu.icache.overall_misses::total 5495 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 164010000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 164010000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 164010000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 164010000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 164010000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 164010000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 37654254 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 37654254 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 37654254 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 37654254 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 37654254 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 37654254 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000146 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000146 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000146 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000146 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000146 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000146 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 29847.133758 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 29847.133758 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 29847.133758 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 29847.133758 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 29847.133758 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 29847.133758 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 669 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 1347.136586 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.657782 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.657782 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 36854521 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 36854521 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 36854521 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 36854521 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 36854521 # number of overall hits +system.cpu.icache.overall_hits::total 36854521 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 5339 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 5339 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 5339 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 5339 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 5339 # number of overall misses +system.cpu.icache.overall_misses::total 5339 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 158626499 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 158626499 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 158626499 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 158626499 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 158626499 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 158626499 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 36859860 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 36859860 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 36859860 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 36859860 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 36859860 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 36859860 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000145 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000145 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000145 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000145 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000145 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000145 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 29710.900730 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 29710.900730 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 29710.900730 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 29710.900730 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 29710.900730 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 29710.900730 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 604 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 18 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 17 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 37.166667 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 35.529412 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1106 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1106 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1106 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1106 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1106 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1106 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4389 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 4389 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 4389 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 4389 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 4389 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 4389 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 126227500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 126227500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 126227500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 126227500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 126227500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 126227500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000117 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000117 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000117 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000117 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000117 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000117 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 28759.968102 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 28759.968102 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 28759.968102 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 28759.968102 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 28759.968102 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 28759.968102 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1102 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1102 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1102 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1102 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1102 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1102 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4237 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 4237 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 4237 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 4237 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 4237 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 4237 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 122742499 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 122742499 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 122742499 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 122742499 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 122742499 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 122742499 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000115 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000115 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000115 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000115 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000115 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000115 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 28969.199670 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 28969.199670 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 28969.199670 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 28969.199670 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 28969.199670 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 28969.199670 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.replacements 0 # number of replacements +system.cpu.l2cache.tagsinuse 1961.084973 # Cycle average of tags in use +system.cpu.l2cache.total_refs 2275 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 2727 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.834250 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::writebacks 4.022996 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 1424.044648 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 533.017329 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.000123 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.043458 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.016266 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.059848 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 2184 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 90 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 2274 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 18 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 18 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 8 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 8 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 2184 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 98 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2282 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 2184 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 98 # number of overall hits +system.cpu.l2cache.overall_hits::total 2282 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 2051 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 681 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 2732 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 2 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 2 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 1075 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 1075 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 2051 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 1756 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 3807 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 2051 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 1756 # number of overall misses +system.cpu.l2cache.overall_misses::total 3807 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 96653500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 35087500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 131741000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 46197000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 46197000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 96653500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 81284500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 177938000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 96653500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 81284500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 177938000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 4235 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 771 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 5006 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 18 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 18 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 2 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 1083 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 1083 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 4235 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1854 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 6089 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 4235 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1854 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 6089 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.484298 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.883268 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.545745 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.992613 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.992613 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.484298 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.947141 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.625226 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.484298 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.947141 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.625226 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 47125.060946 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 51523.494860 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 48221.449488 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 42973.953488 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 42973.953488 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 47125.060946 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 46289.578588 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 46739.690045 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 47125.060946 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 46289.578588 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 46739.690045 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 3 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 11 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 14 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 3 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 11 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 14 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 3 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 11 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 14 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2048 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 670 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 2718 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 2 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1075 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 1075 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2048 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1745 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 3793 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2048 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 1745 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 3793 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 70387399 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 26266459 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 96653858 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 20002 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 20002 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 32716158 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 32716158 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 70387399 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 58982617 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 129370016 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 70387399 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 58982617 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 129370016 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.483589 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.869001 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.542948 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.992613 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.992613 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.483589 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.941208 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.622927 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.483589 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.941208 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.622927 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 34368.847168 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 39203.670149 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 35560.654157 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 30433.635349 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 30433.635349 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 34368.847168 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 33800.926648 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 34107.570788 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 34368.847168 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 33800.926648 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 34107.570788 # average overall mshr miss latency +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 57 # number of replacements -system.cpu.dcache.tagsinuse 1416.459985 # Cycle average of tags in use -system.cpu.dcache.total_refs 47307506 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1862 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 25406.823845 # Average number of references to valid blocks. +system.cpu.dcache.tagsinuse 1406.445400 # Cycle average of tags in use +system.cpu.dcache.total_refs 46805125 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1854 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 25245.482740 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 1416.459985 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.345815 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.345815 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 34892236 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 34892236 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 12356557 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 12356557 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 30260 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 30260 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 28451 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 28451 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 47248793 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 47248793 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 47248793 # number of overall hits -system.cpu.dcache.overall_hits::total 47248793 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1972 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1972 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 7730 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 7730 # number of WriteReq misses +system.cpu.dcache.occ_blocks::cpu.data 1406.445400 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.343370 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.343370 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 34390274 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 34390274 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 12356568 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 12356568 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 29790 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 29790 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 28491 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 28491 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 46746842 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 46746842 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 46746842 # number of overall hits +system.cpu.dcache.overall_hits::total 46746842 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1833 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1833 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 7719 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 7719 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 9702 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9702 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9702 # number of overall misses -system.cpu.dcache.overall_misses::total 9702 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 89685500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 89685500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 298721497 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 298721497 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 9552 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9552 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9552 # number of overall misses +system.cpu.dcache.overall_misses::total 9552 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 82596000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 82596000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 292720496 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 292720496 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 102000 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 102000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 388406997 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 388406997 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 388406997 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 388406997 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 34894208 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 34894208 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 375316496 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 375316496 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 375316496 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 375316496 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 34392107 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 34392107 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 30262 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 30262 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 28451 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 28451 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 47258495 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 47258495 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 47258495 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 47258495 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000057 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000057 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000625 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000625 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000066 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000066 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000205 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000205 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000205 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000205 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 45479.462475 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 45479.462475 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38644.436869 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 38644.436869 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 29792 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 29792 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 28491 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 28491 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 46756394 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 46756394 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 46756394 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 46756394 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000053 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000053 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000624 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000624 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000067 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000067 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000204 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000204 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000204 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000204 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 45060.556465 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 45060.556465 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37922.074880 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 37922.074880 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 51000 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 51000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 40033.704082 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 40033.704082 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 40033.704082 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 40033.704082 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 433 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 45 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 11 # number of cycles access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 39291.927973 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 39291.927973 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 39291.927973 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 39291.927973 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 476 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 40 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 14 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 39.363636 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 22.500000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 34 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 20 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 18 # number of writebacks system.cpu.dcache.writebacks::total 18 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1197 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1197 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6641 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 6641 # number of WriteReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1062 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1062 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6634 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 6634 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 7838 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 7838 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 7838 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 7838 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 775 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 775 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1089 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1089 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1864 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1864 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1864 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1864 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 38083000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 38083000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 48635999 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 48635999 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 86718999 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 86718999 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 86718999 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 86718999 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_hits::cpu.data 7696 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 7696 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 7696 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 7696 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 771 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 771 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1085 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1085 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1856 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1856 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1856 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1856 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 36781000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 36781000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 47410498 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 47410498 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 84191498 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 84191498 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 84191498 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 84191498 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000022 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000022 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000088 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000088 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000039 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.000039 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000039 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.000039 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 49139.354839 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 49139.354839 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44661.156107 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44661.156107 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 46523.068133 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 46523.068133 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 46523.068133 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 46523.068133 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.000040 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.000040 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 47705.577173 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 47705.577173 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 43696.311521 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 43696.311521 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45361.798491 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 45361.798491 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45361.798491 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 45361.798491 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 1988.724621 # Cycle average of tags in use -system.cpu.l2cache.total_refs 2398 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 2755 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.870417 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 3.999610 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 1449.117125 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 535.607885 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.000122 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.044224 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.016345 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.060691 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 2308 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 88 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 2396 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 18 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 18 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 1 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 1 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 9 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 9 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 2308 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 97 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2405 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 2308 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 97 # number of overall hits -system.cpu.l2cache.overall_hits::total 2405 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 2079 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 685 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 2764 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 1 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 1 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 1080 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 1080 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 2079 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 1765 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 3844 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 2079 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 1765 # number of overall misses -system.cpu.l2cache.overall_misses::total 3844 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 98742500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 36322000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 135064500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 47502500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 47502500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 98742500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 83824500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 182567000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 98742500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 83824500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 182567000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 4387 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 773 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 5160 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 18 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 18 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 2 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 1089 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 1089 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 4387 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1862 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 6249 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 4387 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1862 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 6249 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.473900 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.886158 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.535659 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.500000 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.500000 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.991736 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.991736 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.473900 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.947905 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.615138 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.473900 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.947905 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.615138 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 47495.189995 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 53024.817518 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 48865.593343 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 43983.796296 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 43983.796296 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 47495.189995 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 47492.634561 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 47494.016649 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 47495.189995 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 47492.634561 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 47494.016649 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 4 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 12 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 16 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 4 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 12 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 16 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 4 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 12 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 16 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2075 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 673 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 2748 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 1 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1080 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 1080 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 2075 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 1753 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 3828 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 2075 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 1753 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 3828 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 72306456 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 27405972 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 99712428 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 10001 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 10001 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 33965187 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 33965187 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 72306456 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 61371159 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 133677615 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 72306456 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 61371159 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 133677615 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.472988 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.870634 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.532558 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.500000 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.991736 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.991736 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.472988 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.941461 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.612578 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.472988 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.941461 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.612578 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 34846.484819 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40722.098068 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 36285.454148 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31449.247222 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31449.247222 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 34846.484819 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 35009.217912 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 34921.007053 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 34846.484819 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 35009.217912 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 34921.007053 # average overall mshr miss latency -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini index c4bf026a2..153c74c08 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini +++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini @@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a -clock=1 +clock=1000 init_param=0 kernel= load_addr_mask=1099511627775 @@ -30,7 +30,7 @@ system_port=system.membus.slave[0] [system.cpu] type=DerivO3CPU -children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload +children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -78,6 +78,7 @@ iewToFetchDelay=1 iewToRenameDelay=1 instShiftAmt=2 interrupts=system.cpu.interrupts +isa=system.cpu.isa issueToExecuteDelay=1 issueWidth=8 itb=system.cpu.itb @@ -129,17 +130,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=2 is_top_level=true -latency=1000 max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=2 size=262144 subblock_size=0 system=system @@ -158,7 +160,7 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=X86PagetableWalker -clock=1 +clock=500 system=system port=system.cpu.toL2Bus.slave[3] @@ -430,17 +432,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=2 is_top_level=true -latency=1000 max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=2 size=131072 subblock_size=0 system=system @@ -453,7 +456,7 @@ mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=X86LocalApic -clock=1 +clock=500 int_latency=1000 pio_addr=2305843009213693952 pio_latency=100000 @@ -462,6 +465,9 @@ int_master=system.membus.slave[2] int_slave=system.membus.master[2] pio=system.membus.master[1] +[system.cpu.isa] +type=X86ISA + [system.cpu.itb] type=X86TLB children=walker @@ -470,30 +476,31 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=X86PagetableWalker -clock=1 +clock=500 system=system port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] type=BaseCache addr_ranges=0:18446744073709551615 -assoc=2 +assoc=8 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=20 is_top_level=false -latency=1000 max_miss_count=0 -mshrs=10 +mshrs=20 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=20 size=2097152 subblock_size=0 system=system -tgts_per_mshr=5 +tgts_per_mshr=12 trace_addr=0 two_queue=false write_buffers=8 @@ -503,10 +510,10 @@ mem_side=system.membus.slave[1] [system.cpu.toL2Bus] type=CoherentBus block_size=64 -clock=1000 +clock=500 header_cycles=1 use_default_range=false -width=8 +width=32 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port @@ -521,7 +528,7 @@ egid=100 env= errout=cerr euid=100 -executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/twolf +executable=/projects/pd/randd/dist/cpu2000/binaries/x86/linux/twolf gid=100 input=cin max_stack_size=67108864 @@ -543,15 +550,28 @@ master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_s slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master [system.physmem] -type=SimpleMemory -clock=1 +type=SimpleDRAM +addr_mapping=openmap +banks_per_rank=8 +clock=1000 conf_table_reported=false -file= in_addr_map=true -latency=30000 -latency_var=0 +lines_per_rowbuffer=64 +mem_sched_policy=fcfs null=false +page_policy=open range=0:134217727 +ranks_per_channel=2 +read_buffer_size=32 +tBURST=4000 +tCL=14000 +tRCD=14000 +tREFI=7800000 +tRFC=300000 +tRP=14000 +tWTR=1000 +write_buffer_size=32 +write_thresh_perc=70 zero=false port=system.membus.master[0] diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout index 37b3dd11b..b5276d904 100755 --- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout +++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout @@ -1,14 +1,10 @@ -Redirecting stdout to build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/simout -Redirecting stderr to build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 10 2012 22:29:00 -gem5 started Sep 10 2012 22:29:07 -gem5 executing on ribera.cs.wisc.edu +gem5 compiled Oct 30 2012 11:14:29 +gem5 started Oct 30 2012 17:50:59 +gem5 executing on u200540-lin command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing -Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/smred.sav -Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -26,4 +22,4 @@ info: Increasing stack size by one page. 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 84416735500 because target called exit() +122 123 124 Exiting @ tick 82887492500 because target called exit() diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt index e84462d08..664d70a56 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt @@ -1,57 +1,57 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.084675 # Number of seconds simulated -sim_ticks 84674525000 # Number of ticks simulated -final_tick 84674525000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.082887 # Number of seconds simulated +sim_ticks 82887492500 # Number of ticks simulated +final_tick 82887492500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 95140 # Simulator instruction rate (inst/s) -host_op_rate 159463 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 60996786 # Simulator tick rate (ticks/s) -host_mem_usage 238356 # Number of bytes of host memory used -host_seconds 1388.18 # Real time elapsed on the host +host_inst_rate 73575 # Simulator instruction rate (inst/s) +host_op_rate 123318 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 46175257 # Simulator tick rate (ticks/s) +host_mem_usage 235032 # Number of bytes of host memory used +host_seconds 1795.06 # Real time elapsed on the host sim_insts 132071192 # Number of instructions simulated sim_ops 221362960 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 219904 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 124736 # Number of bytes read from this memory -system.physmem.bytes_read::total 344640 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 219904 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 219904 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3436 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1949 # Number of read requests responded to by this memory -system.physmem.num_reads::total 5385 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 2597050 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1473123 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4070173 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2597050 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2597050 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2597050 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1473123 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4070173 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 5387 # Total number of read requests seen +system.physmem.bytes_read::cpu.inst 218112 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 124480 # Number of bytes read from this memory +system.physmem.bytes_read::total 342592 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 218112 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 218112 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3408 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1945 # Number of read requests responded to by this memory +system.physmem.num_reads::total 5353 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 2631422 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1501795 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4133217 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2631422 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2631422 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2631422 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1501795 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4133217 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 5355 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 5559 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 344640 # Total number of bytes read from memory +system.physmem.cpureqs 5520 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 342592 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 344640 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 342592 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 172 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 307 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 316 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 319 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 319 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 313 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 373 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 330 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 309 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 260 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 279 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 362 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 435 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 441 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 355 # Track reads on a per bank basis +system.physmem.neitherReadNorWrite 165 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 306 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 321 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 313 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 318 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 310 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 368 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 332 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 306 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 257 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 277 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 361 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 434 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 437 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 352 # Track reads on a per bank basis system.physmem.perBankRdReqs::14 370 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 299 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 293 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis @@ -70,14 +70,14 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 84674494000 # Total gap between requests +system.physmem.totGap 82887463000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 5387 # Categorize read packet sizes +system.physmem.readPktSize::6 5355 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -95,16 +95,16 @@ system.physmem.neitherpktsize::2 0 # ca system.physmem.neitherpktsize::3 0 # categorize neither packet sizes system.physmem.neitherpktsize::4 0 # categorize neither packet sizes system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 172 # categorize neither packet sizes +system.physmem.neitherpktsize::6 165 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 4201 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 951 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 194 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 35 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 4195 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 926 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 196 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 34 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see @@ -164,266 +164,266 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 14711866 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 121393866 # Sum of mem lat for all requests -system.physmem.totBusLat 21548000 # Total cycles spent in databus access -system.physmem.totBankLat 85134000 # Total cycles spent in bank access -system.physmem.avgQLat 2730.99 # Average queueing delay per request -system.physmem.avgBankLat 15803.60 # Average bank access latency per request +system.physmem.totQLat 16692334 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 122490334 # Sum of mem lat for all requests +system.physmem.totBusLat 21420000 # Total cycles spent in databus access +system.physmem.totBankLat 84378000 # Total cycles spent in bank access +system.physmem.avgQLat 3117.15 # Average queueing delay per request +system.physmem.avgBankLat 15756.86 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 22534.60 # Average memory access latency -system.physmem.avgRdBW 4.07 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 22874.01 # Average memory access latency +system.physmem.avgRdBW 4.13 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 4.07 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 4.13 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 4765 # Number of row buffer hits during reads +system.physmem.readRowHits 4747 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 88.45 # Row buffer hit rate for reads +system.physmem.readRowHitRate 88.65 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 15718302.21 # Average gap between requests +system.physmem.avgGap 15478517.83 # Average gap between requests system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 169349051 # number of cpu cycles simulated +system.cpu.numCycles 165774986 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 20696936 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 20696936 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 2256292 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 15133236 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 13734962 # Number of BTB hits +system.cpu.BPredUnit.lookups 19962549 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 19962549 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 2008101 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 13827383 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 13115978 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 27265023 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 227328092 # Number of instructions fetch has processed -system.cpu.fetch.Branches 20696936 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 13734962 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 59711428 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 19294366 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 65485440 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 310 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1823 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 77 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 25705537 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 473097 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 169231475 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.210885 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.333405 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 25874933 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 219082558 # Number of instructions fetch has processed +system.cpu.fetch.Branches 19962549 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 13115978 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 57603231 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 17636080 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 66812180 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 382 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1920 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 86 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 24490621 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 428850 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 165653450 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.184047 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.324284 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 111185486 65.70% 65.70% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 3235568 1.91% 67.61% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2477028 1.46% 69.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 3104255 1.83% 70.91% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 3512943 2.08% 72.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 3722385 2.20% 75.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 4581451 2.71% 77.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 2802404 1.66% 79.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 34609955 20.45% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 109646244 66.19% 66.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 3069160 1.85% 68.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2390407 1.44% 69.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2911043 1.76% 71.24% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 3444057 2.08% 73.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 3578858 2.16% 75.48% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 4315336 2.61% 78.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 2737464 1.65% 79.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 33560881 20.26% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 169231475 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.122215 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.342364 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 40175646 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 55730709 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 46717910 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 9839836 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 16767374 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 365014393 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 16767374 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 47729605 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 14672331 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 23050 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 48352284 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 41686831 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 355859336 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 104 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 17343697 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 22236120 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 51 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 410085130 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 987094969 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 977133981 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 9960988 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 165653450 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.120420 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.321566 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 38806807 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 56798437 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 44693921 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 9993567 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 15360718 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 353645742 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 15360718 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 46261084 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 15045259 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 23094 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 46566997 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 42396298 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 345315167 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 90 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 18136112 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 22140506 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 107 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 398865932 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 960470736 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 950586912 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 9883824 # Number of floating rename lookups system.cpu.rename.CommittedMaps 259428603 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 150656527 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1756 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1746 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 90004350 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 89661097 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 32850020 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 59013027 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 19193820 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 342911318 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 4601 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 271901324 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 302838 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 121030414 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 246288577 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 3355 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 169231475 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.606683 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.513723 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 139437329 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1690 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1680 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 90473578 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 86725107 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 31801013 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 58042243 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 18917665 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 333696674 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 3504 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 267486026 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 249957 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 111886449 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 230098096 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 2258 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 165653450 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.614733 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.503292 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 47472289 28.05% 28.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 47010231 27.78% 55.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 33048937 19.53% 75.36% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 20116720 11.89% 87.25% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 13476087 7.96% 95.21% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 4976431 2.94% 98.15% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 2409834 1.42% 99.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 570016 0.34% 99.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 150930 0.09% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 45188105 27.28% 27.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 46827780 28.27% 55.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 32851570 19.83% 75.38% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 19799355 11.95% 87.33% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 13199962 7.97% 95.30% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 4781234 2.89% 98.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 2328741 1.41% 99.59% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 535047 0.32% 99.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 141656 0.09% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 169231475 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 165653450 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 133953 5.05% 5.05% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 5.05% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 5.05% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.05% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.05% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.05% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 5.05% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.05% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 5.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 5.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.05% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 2250624 84.89% 89.94% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 266784 10.06% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 130850 4.93% 4.93% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 4.93% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 4.93% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.93% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.93% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.93% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 4.93% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.93% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 4.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 4.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.93% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2255745 85.02% 89.96% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 266492 10.04% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 1212972 0.45% 0.45% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 177077896 65.13% 65.57% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 65.57% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.57% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 1583975 0.58% 66.15% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.15% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.15% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.15% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.15% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.15% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 68517375 25.20% 91.35% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 23509106 8.65% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 1212176 0.45% 0.45% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 174220200 65.13% 65.59% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 65.59% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.59% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 1600871 0.60% 66.18% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.18% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.18% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.18% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.18% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.18% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 67180560 25.12% 91.30% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 23272219 8.70% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 271901324 # Type of FU issued -system.cpu.iq.rate 1.605567 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2651361 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.009751 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 710689981 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 459620232 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 264156330 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 5298341 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 4622160 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 2541189 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 270684077 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 2655636 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 19034495 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 267486026 # Type of FU issued +system.cpu.iq.rate 1.613549 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2653087 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.009919 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 698167044 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 441210039 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 260260402 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 5361502 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 4667533 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 2580716 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 266230560 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 2696377 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 18979902 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 33011511 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 33645 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 301635 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 12334304 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 30075521 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 29325 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 296266 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 11285297 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 49870 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 57 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 49068 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 13 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 16767374 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 579251 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 261764 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 342915919 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 264352 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 89661097 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 32850020 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1726 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 174105 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 29972 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 301635 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1337300 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1023491 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 2360791 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 268724619 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 67385634 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 3176705 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 15360718 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 583386 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 263755 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 333700178 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 187889 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 86725107 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 31801013 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1675 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 149208 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 31553 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 296266 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1173784 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 915890 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 2089674 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 264607897 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 66196383 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2878129 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 90490308 # number of memory reference insts executed -system.cpu.iew.exec_branches 14777839 # Number of branches executed -system.cpu.iew.exec_stores 23104674 # Number of stores executed -system.cpu.iew.exec_rate 1.586809 # Inst execution rate -system.cpu.iew.wb_sent 267641874 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 266697519 # cumulative count of insts written-back -system.cpu.iew.wb_producers 215269478 # num instructions producing a value -system.cpu.iew.wb_consumers 378445061 # num instructions consuming a value +system.cpu.iew.exec_refs 89076319 # number of memory reference insts executed +system.cpu.iew.exec_branches 14601653 # Number of branches executed +system.cpu.iew.exec_stores 22879936 # Number of stores executed +system.cpu.iew.exec_rate 1.596187 # Inst execution rate +system.cpu.iew.wb_sent 263672307 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 262841118 # cumulative count of insts written-back +system.cpu.iew.wb_producers 212055070 # num instructions producing a value +system.cpu.iew.wb_consumers 375144375 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.574839 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.568826 # average fanout of values written-back +system.cpu.iew.wb_rate 1.585529 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.565263 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 121635359 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 112374263 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 1246 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 2256476 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 152464101 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.451902 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.927405 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 2008288 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 150292732 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.472879 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.939566 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 52775060 34.61% 34.61% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 57579919 37.77% 72.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 14057130 9.22% 81.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 11929298 7.82% 89.43% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 4294184 2.82% 92.24% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 2937870 1.93% 94.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1056484 0.69% 94.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 997351 0.65% 95.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 6836805 4.48% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 50934932 33.89% 33.89% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 57339097 38.15% 72.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 13849183 9.21% 81.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 12078421 8.04% 89.29% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 4153000 2.76% 92.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 2960899 1.97% 94.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1067284 0.71% 94.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1009293 0.67% 95.41% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 6900623 4.59% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 152464101 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 150292732 # Number of insts commited each cycle system.cpu.commit.committedInsts 132071192 # Number of instructions committed system.cpu.commit.committedOps 221362960 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -434,366 +434,366 @@ system.cpu.commit.branches 12326938 # Nu system.cpu.commit.fp_insts 2162459 # Number of committed floating point instructions. system.cpu.commit.int_insts 220339549 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 6836805 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 6900623 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 488625615 # The number of ROB reads -system.cpu.rob.rob_writes 702805180 # The number of ROB writes -system.cpu.timesIdled 3014 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 117576 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 477129332 # The number of ROB reads +system.cpu.rob.rob_writes 682869787 # The number of ROB writes +system.cpu.timesIdled 2894 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 121536 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 132071192 # Number of Instructions Simulated system.cpu.committedOps 221362960 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 132071192 # Number of Instructions Simulated -system.cpu.cpi 1.282256 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.282256 # CPI: Total CPI of All Threads -system.cpu.ipc 0.779876 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.779876 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 567778401 # number of integer regfile reads -system.cpu.int_regfile_writes 302773713 # number of integer regfile writes -system.cpu.fp_regfile_reads 3495333 # number of floating regfile reads -system.cpu.fp_regfile_writes 2213146 # number of floating regfile writes -system.cpu.misc_regfile_reads 139456752 # number of misc regfile reads +system.cpu.cpi 1.255194 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.255194 # CPI: Total CPI of All Threads +system.cpu.ipc 0.796690 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.796690 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 562502955 # number of integer regfile reads +system.cpu.int_regfile_writes 298724994 # number of integer regfile writes +system.cpu.fp_regfile_reads 3533274 # number of floating regfile reads +system.cpu.fp_regfile_writes 2240391 # number of floating regfile writes +system.cpu.misc_regfile_reads 137022497 # number of misc regfile reads system.cpu.misc_regfile_writes 844 # number of misc regfile writes -system.cpu.icache.replacements 5349 # number of replacements -system.cpu.icache.tagsinuse 1642.940012 # Cycle average of tags in use -system.cpu.icache.total_refs 25695767 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 7318 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 3511.310057 # Average number of references to valid blocks. +system.cpu.icache.replacements 4672 # number of replacements +system.cpu.icache.tagsinuse 1624.482835 # Cycle average of tags in use +system.cpu.icache.total_refs 24481725 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 6641 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 3686.451589 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1642.940012 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.802217 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.802217 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 25695767 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 25695767 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 25695767 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 25695767 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 25695767 # number of overall hits -system.cpu.icache.overall_hits::total 25695767 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 9770 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 9770 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 9770 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 9770 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 9770 # number of overall misses -system.cpu.icache.overall_misses::total 9770 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 270457998 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 270457998 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 270457998 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 270457998 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 270457998 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 270457998 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 25705537 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 25705537 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 25705537 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 25705537 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 25705537 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 25705537 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000380 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000380 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000380 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000380 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000380 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000380 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 27682.497236 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 27682.497236 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 27682.497236 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 27682.497236 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 27682.497236 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 27682.497236 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 937 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 1624.482835 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.793205 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.793205 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 24481725 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 24481725 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 24481725 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 24481725 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 24481725 # number of overall hits +system.cpu.icache.overall_hits::total 24481725 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 8896 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 8896 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 8896 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 8896 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 8896 # number of overall misses +system.cpu.icache.overall_misses::total 8896 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 259036998 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 259036998 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 259036998 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 259036998 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 259036998 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 259036998 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 24490621 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 24490621 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 24490621 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 24490621 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 24490621 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 24490621 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000363 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000363 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000363 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000363 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000363 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000363 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 29118.367581 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 29118.367581 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 29118.367581 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 29118.367581 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 29118.367581 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 29118.367581 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 776 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 26 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 23 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 36.038462 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 33.739130 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2279 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 2279 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 2279 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 2279 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 2279 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 2279 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 7491 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 7491 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 7491 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 7491 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 7491 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 7491 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 205062498 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 205062498 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 205062498 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 205062498 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 205062498 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 205062498 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000291 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000291 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000291 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000291 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000291 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000291 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 27374.515819 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 27374.515819 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 27374.515819 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 27374.515819 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 27374.515819 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 27374.515819 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2090 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 2090 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 2090 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 2090 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 2090 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 2090 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 6806 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 6806 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 6806 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 6806 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 6806 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 6806 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 197845998 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 197845998 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 197845998 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 197845998 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 197845998 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 197845998 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000278 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000278 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000278 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000278 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000278 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000278 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 29069.350279 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 29069.350279 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 29069.350279 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 29069.350279 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 29069.350279 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 29069.350279 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 56 # number of replacements -system.cpu.dcache.tagsinuse 1425.106127 # Cycle average of tags in use -system.cpu.dcache.total_refs 68695607 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1989 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 34537.761187 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 0 # number of replacements +system.cpu.l2cache.tagsinuse 2515.121511 # Cycle average of tags in use +system.cpu.l2cache.total_refs 3268 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 3800 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.860000 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::writebacks 1.781670 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 2238.764869 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 274.574971 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.000054 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.068322 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.008379 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.076755 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 3233 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 32 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 3265 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 14 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 14 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 7 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 7 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 3233 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 39 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 3272 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 3233 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 39 # number of overall hits +system.cpu.l2cache.overall_hits::total 3272 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 3408 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 388 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 3796 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 165 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 165 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 1559 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 1559 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 3408 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 1947 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 5355 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 3408 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 1947 # number of overall misses +system.cpu.l2cache.overall_misses::total 5355 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 158546500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 21486000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 180032500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 68323000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 68323000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 158546500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 89809000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 248355500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 158546500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 89809000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 248355500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 6641 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 420 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 7061 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 14 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 14 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 165 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 165 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 1566 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 1566 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 6641 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1986 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 8627 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 6641 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1986 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 8627 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.513176 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.923810 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.537601 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.995530 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.995530 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.513176 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.980363 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.620726 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.513176 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.980363 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.620726 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 46521.860329 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 55376.288660 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 47426.896733 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 43824.887749 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 43824.887749 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 46521.860329 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 46126.861839 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 46378.244631 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 46521.860329 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 46126.861839 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 46378.244631 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3408 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 388 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 3796 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 165 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 165 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1559 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 1559 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3408 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1947 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 5355 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3408 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 1947 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 5355 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 115558515 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 16623105 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 132181620 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1650165 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1650165 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 48534991 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 48534991 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 115558515 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 65158096 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 180716611 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 115558515 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 65158096 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 180716611 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.513176 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.923810 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.537601 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.995530 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.995530 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.513176 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.980363 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.620726 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.513176 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.980363 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.620726 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 33908.014965 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42843.054124 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 34821.290832 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31132.130212 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31132.130212 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 33908.014965 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 33465.894196 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 33747.266293 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 33908.014965 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 33465.894196 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 33747.266293 # average overall mshr miss latency +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.replacements 58 # number of replacements +system.cpu.dcache.tagsinuse 1410.405109 # Cycle average of tags in use +system.cpu.dcache.total_refs 67572103 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1984 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 34058.519657 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 1425.106127 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.347926 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.347926 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 48181413 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 48181413 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 20513994 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 20513994 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 68695407 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 68695407 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 68695407 # number of overall hits -system.cpu.dcache.overall_hits::total 68695407 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 817 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 817 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1736 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1736 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2553 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2553 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2553 # number of overall misses -system.cpu.dcache.overall_misses::total 2553 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 37812500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 37812500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 76776000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 76776000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 114588500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 114588500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 114588500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 114588500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 48182230 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 48182230 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.occ_blocks::cpu.data 1410.405109 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.344337 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.344337 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 47057893 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 47057893 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 20513998 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 20513998 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 67571891 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 67571891 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 67571891 # number of overall hits +system.cpu.dcache.overall_hits::total 67571891 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 802 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 802 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1732 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1732 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2534 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2534 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2534 # number of overall misses +system.cpu.dcache.overall_misses::total 2534 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 36818000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 36818000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 77209500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 77209500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 114027500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 114027500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 114027500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 114027500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 47058695 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 47058695 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 20515730 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 20515730 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 68697960 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 68697960 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 68697960 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 68697960 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 67574425 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 67574425 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 67574425 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 67574425 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000017 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000017 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000085 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000085 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000084 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000084 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.000037 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.000037 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000037 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000037 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 46282.129743 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 46282.129743 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44225.806452 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 44225.806452 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 44883.862123 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 44883.862123 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 44883.862123 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 44883.862123 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 262 # number of cycles access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 45907.730673 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 45907.730673 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44578.233256 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 44578.233256 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 44999.013418 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 44999.013418 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 44999.013418 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 44999.013418 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 86 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 6 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 43.666667 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 43 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 13 # number of writebacks -system.cpu.dcache.writebacks::total 13 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 388 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 388 # number of ReadReq MSHR hits +system.cpu.dcache.writebacks::writebacks 14 # number of writebacks +system.cpu.dcache.writebacks::total 14 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 381 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 381 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 2 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 390 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 390 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 390 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 390 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 429 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 429 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1734 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1734 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2163 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2163 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2163 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2163 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 22702000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 22702000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 73194000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 73194000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 95896000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 95896000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 95896000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 95896000 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_hits::cpu.data 383 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 383 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 383 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 383 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 421 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 421 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1730 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1730 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2151 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2151 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2151 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2151 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 22306500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 22306500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 73636000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 73636000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 95942500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 95942500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 95942500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 95942500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000009 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000009 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000085 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000085 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000031 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.000031 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000031 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.000031 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 52918.414918 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 52918.414918 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42211.072664 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42211.072664 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 44334.720296 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 44334.720296 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44334.720296 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 44334.720296 # average overall mshr miss latency +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000084 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000032 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.000032 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000032 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.000032 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 52984.560570 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 52984.560570 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42564.161850 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42564.161850 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 44603.672710 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 44603.672710 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44603.672710 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 44603.672710 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 2574.474688 # Cycle average of tags in use -system.cpu.l2cache.total_refs 3918 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 3834 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 1.021909 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 1.998861 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 2280.064423 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 292.411404 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.000061 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.069582 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.008924 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.078567 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 3883 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 32 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 3915 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 13 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 13 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 8 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 8 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 3883 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 40 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 3923 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 3883 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 40 # number of overall hits -system.cpu.l2cache.overall_hits::total 3923 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 3436 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 396 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 3832 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 172 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 172 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 1555 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 1555 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 3436 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 1951 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 5387 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 3436 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 1951 # number of overall misses -system.cpu.l2cache.overall_misses::total 5387 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 158572500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 21872000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 180444500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 67710500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 67710500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 158572500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 89582500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 248155000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 158572500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 89582500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 248155000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 7319 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 428 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 7747 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 13 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 13 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 172 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 172 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 1563 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 1563 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 7319 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1991 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 9310 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 7319 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1991 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 9310 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.469463 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.925234 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.494643 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.994882 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.994882 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.469463 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.979910 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.578625 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.469463 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.979910 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.578625 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 46150.320140 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 55232.323232 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 47088.856994 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 43543.729904 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 43543.729904 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 46150.320140 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 45916.196822 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 46065.528123 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 46150.320140 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 45916.196822 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 46065.528123 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3436 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 396 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 3832 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 172 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 172 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1555 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 1555 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3436 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 1951 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 5387 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3436 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 1951 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 5387 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 115214557 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 16918595 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 132133152 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1720172 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1720172 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 47963988 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 47963988 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 115214557 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 64882583 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 180097140 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 115214557 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 64882583 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 180097140 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.469463 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.925234 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.494643 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994882 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994882 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.469463 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.979910 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.578625 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.469463 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.979910 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.578625 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 33531.594005 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42723.724747 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 34481.511482 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 30845.008360 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 30845.008360 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 33531.594005 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 33256.065095 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 33431.806200 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 33531.594005 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 33256.065095 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 33431.806200 # average overall mshr miss latency -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |