diff options
| author | Gabe Black <gblack@eecs.umich.edu> | 2011-08-09 03:37:45 -0700 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2011-08-09 03:37:45 -0700 |
| commit | 8586a800b704184289651c9f965ce78f4d09cf6d (patch) | |
| tree | c9e4e2ac8f290f3b464c4644d4bec2b3682e5951 /tests/long | |
| parent | 3989f41261b9d13f336a37cb6717f9fdb5a71bb1 (diff) | |
| download | gem5-8586a800b704184289651c9f965ce78f4d09cf6d.tar.xz | |
Stats: Update stats for the recent O3 interrupt change.
Diffstat (limited to 'tests/long')
8 files changed, 2197 insertions, 2204 deletions
diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini index 085ebcfb6..298e17d0f 100644 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini @@ -10,13 +10,13 @@ type=LinuxAlphaSystem children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 -console=/chips/pd/randd/dist/binaries/console +console=/dist/m5/system/binaries/console init_param=0 -kernel=/chips/pd/randd/dist/binaries/vmlinux +kernel=/dist/m5/system/binaries/vmlinux load_addr_mask=1099511627775 mem_mode=timing memories=system.physmem -pal=/chips/pd/randd/dist/binaries/ts_osfpal +pal=/dist/m5/system/binaries/ts_osfpal physmem=system.physmem readfile=tests/halt.sh symbolfile= @@ -931,7 +931,7 @@ table_size=65536 [system.disk0.image.child] type=RawDiskImage -image_file=/chips/pd/randd/dist/disks/linux-latest.img +image_file=/dist/m5/system/disks/linux-latest.img read_only=true [system.disk2] @@ -951,7 +951,7 @@ table_size=65536 [system.disk2.image.child] type=RawDiskImage -image_file=/chips/pd/randd/dist/disks/linux-bigswap2.img +image_file=/dist/m5/system/disks/linux-bigswap2.img read_only=true [system.intrctrl] @@ -1080,7 +1080,7 @@ system=system [system.simple_disk.disk] type=RawDiskImage -image_file=/chips/pd/randd/dist/disks/linux-latest.img +image_file=/dist/m5/system/disks/linux-latest.img read_only=true [system.terminal] diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout index 9c91bbd4a..b594e76f7 100755 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout @@ -1,13 +1,13 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 8 2011 15:02:59 -gem5 started Jul 8 2011 18:23:45 -gem5 executing on u200439-lin.austin.arm.com +gem5 compiled Aug 9 2011 03:11:31 +gem5 started Aug 9 2011 03:11:36 +gem5 executing on burrito command line: build/ALPHA_FS/gem5.opt -d build/ALPHA_FS/tests/opt/long/10.linux-boot/alpha/linux/tsunami-o3-dual -re tests/run.py build/ALPHA_FS/tests/opt/long/10.linux-boot/alpha/linux/tsunami-o3-dual Global frequency set at 1000000000000 ticks per second -info: kernel located at: /chips/pd/randd/dist/binaries/vmlinux +info: kernel located at: /dist/m5/system/binaries/vmlinux 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 info: Entering event queue @ 0. Starting simulation... info: Launching CPU 1 @ 107915000 -Exiting @ tick 1898652239500 because m5_exit instruction encountered +Exiting @ tick 1897528709500 because m5_exit instruction encountered diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt index 049977b68..669f31e44 100644 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt @@ -1,133 +1,133 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.898652 # Number of seconds simulated -sim_ticks 1898652239500 # Number of ticks simulated +sim_seconds 1.897529 # Number of seconds simulated +sim_ticks 1897528709500 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 56630 # Simulator instruction rate (inst/s) -host_tick_rate 1915374267 # Simulator tick rate (ticks/s) -host_mem_usage 336120 # Number of bytes of host memory used -host_seconds 991.27 # Real time elapsed on the host -sim_insts 56136028 # Number of instructions simulated -system.l2c.replacements 398212 # number of replacements -system.l2c.tagsinuse 35264.339871 # Cycle average of tags in use -system.l2c.total_refs 2531779 # Total number of references to valid blocks. -system.l2c.sampled_refs 433064 # Sample count of references to valid blocks. -system.l2c.avg_refs 5.846201 # Average number of references to valid blocks. +host_inst_rate 133002 # Simulator instruction rate (inst/s) +host_tick_rate 4420145385 # Simulator tick rate (ticks/s) +host_mem_usage 318652 # Number of bytes of host memory used +host_seconds 429.29 # Real time elapsed on the host +sim_insts 57096369 # Number of instructions simulated +system.l2c.replacements 396849 # number of replacements +system.l2c.tagsinuse 35842.640466 # Cycle average of tags in use +system.l2c.total_refs 2454377 # Total number of references to valid blocks. +system.l2c.sampled_refs 435040 # Sample count of references to valid blocks. +system.l2c.avg_refs 5.641727 # Average number of references to valid blocks. system.l2c.warmup_cycle 9253572000 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::0 10247.642027 # Average occupied blocks per context -system.l2c.occ_blocks::1 2471.458479 # Average occupied blocks per context -system.l2c.occ_blocks::2 22545.239365 # Average occupied blocks per context -system.l2c.occ_percent::0 0.156367 # Average percentage of cache occupancy -system.l2c.occ_percent::1 0.037711 # Average percentage of cache occupancy -system.l2c.occ_percent::2 0.344013 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::0 988451 # number of ReadReq hits -system.l2c.ReadReq_hits::1 903729 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1892180 # number of ReadReq hits -system.l2c.Writeback_hits::0 854494 # number of Writeback hits -system.l2c.Writeback_hits::total 854494 # number of Writeback hits -system.l2c.UpgradeReq_hits::0 118 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::1 98 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 216 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::0 35 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::1 33 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 68 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::0 107958 # number of ReadExReq hits -system.l2c.ReadExReq_hits::1 83389 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 191347 # number of ReadExReq hits -system.l2c.demand_hits::0 1096409 # number of demand (read+write) hits -system.l2c.demand_hits::1 987118 # number of demand (read+write) hits +system.l2c.occ_blocks::0 12439.136290 # Average occupied blocks per context +system.l2c.occ_blocks::1 328.499708 # Average occupied blocks per context +system.l2c.occ_blocks::2 23075.004468 # Average occupied blocks per context +system.l2c.occ_percent::0 0.189806 # Average percentage of cache occupancy +system.l2c.occ_percent::1 0.005013 # Average percentage of cache occupancy +system.l2c.occ_percent::2 0.352097 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::0 1462245 # number of ReadReq hits +system.l2c.ReadReq_hits::1 390216 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1852461 # number of ReadReq hits +system.l2c.Writeback_hits::0 805889 # number of Writeback hits +system.l2c.Writeback_hits::total 805889 # number of Writeback hits +system.l2c.UpgradeReq_hits::0 158 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::1 388 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 546 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::0 42 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::1 29 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 71 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::0 131406 # number of ReadExReq hits +system.l2c.ReadExReq_hits::1 39589 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 170995 # number of ReadExReq hits +system.l2c.demand_hits::0 1593651 # number of demand (read+write) hits +system.l2c.demand_hits::1 429805 # number of demand (read+write) hits system.l2c.demand_hits::2 0 # number of demand (read+write) hits -system.l2c.demand_hits::total 2083527 # number of demand (read+write) hits -system.l2c.overall_hits::0 1096409 # number of overall hits -system.l2c.overall_hits::1 987118 # number of overall hits +system.l2c.demand_hits::total 2023456 # number of demand (read+write) hits +system.l2c.overall_hits::0 1593651 # number of overall hits +system.l2c.overall_hits::1 429805 # number of overall hits system.l2c.overall_hits::2 0 # number of overall hits -system.l2c.overall_hits::total 2083527 # number of overall hits -system.l2c.ReadReq_misses::0 301714 # number of ReadReq misses -system.l2c.ReadReq_misses::1 8229 # number of ReadReq misses -system.l2c.ReadReq_misses::total 309943 # number of ReadReq misses -system.l2c.UpgradeReq_misses::0 2585 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::1 556 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 3141 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::0 58 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::1 106 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 164 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::0 104499 # number of ReadExReq misses -system.l2c.ReadExReq_misses::1 19805 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 124304 # number of ReadExReq misses -system.l2c.demand_misses::0 406213 # number of demand (read+write) misses -system.l2c.demand_misses::1 28034 # number of demand (read+write) misses +system.l2c.overall_hits::total 2023456 # number of overall hits +system.l2c.ReadReq_misses::0 304910 # number of ReadReq misses +system.l2c.ReadReq_misses::1 5378 # number of ReadReq misses +system.l2c.ReadReq_misses::total 310288 # number of ReadReq misses +system.l2c.UpgradeReq_misses::0 2801 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::1 1482 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 4283 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::0 670 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::1 687 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 1357 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::0 114075 # number of ReadExReq misses +system.l2c.ReadExReq_misses::1 11670 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 125745 # number of ReadExReq misses +system.l2c.demand_misses::0 418985 # number of demand (read+write) misses +system.l2c.demand_misses::1 17048 # number of demand (read+write) misses system.l2c.demand_misses::2 0 # number of demand (read+write) misses -system.l2c.demand_misses::total 434247 # number of demand (read+write) misses -system.l2c.overall_misses::0 406213 # number of overall misses -system.l2c.overall_misses::1 28034 # number of overall misses +system.l2c.demand_misses::total 436033 # number of demand (read+write) misses +system.l2c.overall_misses::0 418985 # number of overall misses +system.l2c.overall_misses::1 17048 # number of overall misses system.l2c.overall_misses::2 0 # number of overall misses -system.l2c.overall_misses::total 434247 # number of overall misses -system.l2c.ReadReq_miss_latency 16115869500 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency 5950500 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency 996000 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency 6519390500 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency 22635260000 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency 22635260000 # number of overall miss cycles -system.l2c.ReadReq_accesses::0 1290165 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::1 911958 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2202123 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::0 854494 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 854494 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::0 2703 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::1 654 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 3357 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::0 93 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::1 139 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 232 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::0 212457 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::1 103194 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 315651 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::0 1502622 # number of demand (read+write) accesses -system.l2c.demand_accesses::1 1015152 # number of demand (read+write) accesses +system.l2c.overall_misses::total 436033 # number of overall misses +system.l2c.ReadReq_miss_latency 16152594500 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency 19106500 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency 3089000 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency 6595991500 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency 22748586000 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency 22748586000 # number of overall miss cycles +system.l2c.ReadReq_accesses::0 1767155 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::1 395594 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2162749 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::0 805889 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 805889 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::0 2959 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::1 1870 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 4829 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::0 712 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::1 716 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 1428 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::0 245481 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::1 51259 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 296740 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::0 2012636 # number of demand (read+write) accesses +system.l2c.demand_accesses::1 446853 # number of demand (read+write) accesses system.l2c.demand_accesses::2 0 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2517774 # number of demand (read+write) accesses -system.l2c.overall_accesses::0 1502622 # number of overall (read+write) accesses -system.l2c.overall_accesses::1 1015152 # number of overall (read+write) accesses +system.l2c.demand_accesses::total 2459489 # number of demand (read+write) accesses +system.l2c.overall_accesses::0 2012636 # number of overall (read+write) accesses +system.l2c.overall_accesses::1 446853 # number of overall (read+write) accesses system.l2c.overall_accesses::2 0 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2517774 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::0 0.233857 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::1 0.009023 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::0 0.956345 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::1 0.850153 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::0 0.623656 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::1 0.762590 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::0 0.491860 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::1 0.191920 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::0 0.270336 # miss rate for demand accesses -system.l2c.demand_miss_rate::1 0.027616 # miss rate for demand accesses +system.l2c.overall_accesses::total 2459489 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::0 0.172543 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::1 0.013595 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::0 0.946604 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::1 0.792513 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::0 0.941011 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::1 0.959497 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::0 0.464700 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::1 0.227667 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::0 0.208177 # miss rate for demand accesses +system.l2c.demand_miss_rate::1 0.038151 # miss rate for demand accesses system.l2c.demand_miss_rate::2 no_value # miss rate for demand accesses system.l2c.demand_miss_rate::total no_value # miss rate for demand accesses -system.l2c.overall_miss_rate::0 0.270336 # miss rate for overall accesses -system.l2c.overall_miss_rate::1 0.027616 # miss rate for overall accesses +system.l2c.overall_miss_rate::0 0.208177 # miss rate for overall accesses +system.l2c.overall_miss_rate::1 0.038151 # miss rate for overall accesses system.l2c.overall_miss_rate::2 no_value # miss rate for overall accesses system.l2c.overall_miss_rate::total no_value # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::0 53414.390781 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::1 1958423.806052 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::0 52974.958184 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::1 3003457.512086 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::2 inf # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::0 2301.934236 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::1 10702.338129 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::0 6821.313816 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::1 12892.375169 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::2 inf # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::0 17172.413793 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::1 9396.226415 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::0 4610.447761 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::1 4496.360990 # average SCUpgradeReq miss latency system.l2c.SCUpgradeReq_avg_miss_latency::2 inf # average SCUpgradeReq miss latency system.l2c.SCUpgradeReq_avg_miss_latency::total inf # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::0 62387.108968 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::1 329179.020449 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::0 57821.534078 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::1 565209.211654 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::2 inf # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::0 55722.638123 # average overall miss latency -system.l2c.demand_avg_miss_latency::1 807421.702219 # average overall miss latency +system.l2c.demand_avg_miss_latency::0 54294.511737 # average overall miss latency +system.l2c.demand_avg_miss_latency::1 1334384.443923 # average overall miss latency system.l2c.demand_avg_miss_latency::2 inf # average overall miss latency system.l2c.demand_avg_miss_latency::total inf # average overall miss latency -system.l2c.overall_avg_miss_latency::0 55722.638123 # average overall miss latency -system.l2c.overall_avg_miss_latency::1 807421.702219 # average overall miss latency +system.l2c.overall_avg_miss_latency::0 54294.511737 # average overall miss latency +system.l2c.overall_avg_miss_latency::1 1334384.443923 # average overall miss latency system.l2c.overall_avg_miss_latency::2 inf # average overall miss latency system.l2c.overall_avg_miss_latency::total inf # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked @@ -138,100 +138,100 @@ system.l2c.avg_blocked_cycles::no_mshrs no_value # av system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks 122541 # number of writebacks -system.l2c.ReadReq_mshr_hits 22 # number of ReadReq MSHR hits -system.l2c.demand_mshr_hits 22 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits 22 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses 309921 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses 3141 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses 164 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses 124304 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses 434225 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses 434225 # number of overall MSHR misses +system.l2c.writebacks 121454 # number of writebacks +system.l2c.ReadReq_mshr_hits 17 # number of ReadReq MSHR hits +system.l2c.demand_mshr_hits 17 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits 17 # number of overall MSHR hits +system.l2c.ReadReq_mshr_misses 310271 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses 4283 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses 1357 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses 125745 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses 436016 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses 436016 # number of overall MSHR misses system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.l2c.ReadReq_mshr_miss_latency 12396913500 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency 125650000 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency 6563500 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency 5007569500 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency 17404483000 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency 17404483000 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency 838548000 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency 1423652498 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency 2262200498 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::0 0.240218 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::1 0.339841 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_latency 12421352000 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency 171391500 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency 54292500 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency 5066425000 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency 17487777000 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency 17487777000 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency 838216000 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency 1556318498 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency 2394534498 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::0 0.175577 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::1 0.784317 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::2 inf # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::0 1.162042 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::1 4.802752 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::0 1.447448 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::1 2.290374 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::2 inf # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::0 1.763441 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::1 1.179856 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::0 1.905899 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::1 1.895251 # mshr miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::2 inf # mshr miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::total inf # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::0 0.585078 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::1 1.204566 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::0 0.512239 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::1 2.453130 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::2 inf # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::0 0.288978 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::1 0.427744 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::0 0.216639 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::1 0.975748 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::2 inf # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::0 0.288978 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::1 0.427744 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::0 0.216639 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::1 0.975748 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::2 inf # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency 40000.237157 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency 40003.183699 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency 40021.341463 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency 40284.862112 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency 40081.715700 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency 40081.715700 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency 40033.880060 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency 40016.693906 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency 40009.211496 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency 40291.264066 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency 40108.108418 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency 40108.108418 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.replacements 41701 # number of replacements -system.iocache.tagsinuse 0.379408 # Cycle average of tags in use +system.iocache.replacements 41698 # number of replacements +system.iocache.tagsinuse 0.465119 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.sampled_refs 41717 # Sample count of references to valid blocks. +system.iocache.sampled_refs 41714 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 1709327692000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::1 0.379408 # Average occupied blocks per context -system.iocache.occ_percent::1 0.023713 # Average percentage of cache occupancy +system.iocache.warmup_cycle 1708345431000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::1 0.465119 # Average occupied blocks per context +system.iocache.occ_percent::1 0.029070 # Average percentage of cache occupancy system.iocache.demand_hits::0 0 # number of demand (read+write) hits system.iocache.demand_hits::1 0 # number of demand (read+write) hits system.iocache.demand_hits::total 0 # number of demand (read+write) hits system.iocache.overall_hits::0 0 # number of overall hits system.iocache.overall_hits::1 0 # number of overall hits system.iocache.overall_hits::total 0 # number of overall hits -system.iocache.ReadReq_misses::1 179 # number of ReadReq misses -system.iocache.ReadReq_misses::total 179 # number of ReadReq misses +system.iocache.ReadReq_misses::1 178 # number of ReadReq misses +system.iocache.ReadReq_misses::total 178 # number of ReadReq misses system.iocache.WriteReq_misses::1 41552 # number of WriteReq misses system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses system.iocache.demand_misses::0 0 # number of demand (read+write) misses -system.iocache.demand_misses::1 41731 # number of demand (read+write) misses -system.iocache.demand_misses::total 41731 # number of demand (read+write) misses +system.iocache.demand_misses::1 41730 # number of demand (read+write) misses +system.iocache.demand_misses::total 41730 # number of demand (read+write) misses system.iocache.overall_misses::0 0 # number of overall misses -system.iocache.overall_misses::1 41731 # number of overall misses -system.iocache.overall_misses::total 41731 # number of overall misses -system.iocache.ReadReq_miss_latency 20617998 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency 5720950806 # number of WriteReq miss cycles -system.iocache.demand_miss_latency 5741568804 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency 5741568804 # number of overall miss cycles -system.iocache.ReadReq_accesses::1 179 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 179 # number of ReadReq accesses(hits+misses) +system.iocache.overall_misses::1 41730 # number of overall misses +system.iocache.overall_misses::total 41730 # number of overall misses +system.iocache.ReadReq_miss_latency 20503998 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency 5720495806 # number of WriteReq miss cycles +system.iocache.demand_miss_latency 5740999804 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency 5740999804 # number of overall miss cycles +system.iocache.ReadReq_accesses::1 178 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 178 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::1 41552 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses -system.iocache.demand_accesses::1 41731 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 41731 # number of demand (read+write) accesses +system.iocache.demand_accesses::1 41730 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 41730 # number of demand (read+write) accesses system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses -system.iocache.overall_accesses::1 41731 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 41731 # number of overall (read+write) accesses +system.iocache.overall_accesses::1 41730 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 41730 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::1 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::1 1 # miss rate for WriteReq accesses system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses @@ -241,37 +241,37 @@ system.iocache.overall_miss_rate::0 no_value # mi system.iocache.overall_miss_rate::1 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::0 inf # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::1 115184.346369 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::1 115191 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::0 inf # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::1 137681.719436 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::1 137670.769301 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency system.iocache.demand_avg_miss_latency::0 inf # average overall miss latency -system.iocache.demand_avg_miss_latency::1 137585.219717 # average overall miss latency +system.iocache.demand_avg_miss_latency::1 137574.881476 # average overall miss latency system.iocache.demand_avg_miss_latency::total inf # average overall miss latency system.iocache.overall_avg_miss_latency::0 inf # average overall miss latency -system.iocache.overall_avg_miss_latency::1 137585.219717 # average overall miss latency +system.iocache.overall_avg_miss_latency::1 137574.881476 # average overall miss latency system.iocache.overall_avg_miss_latency::total inf # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 64667028 # number of cycles access was blocked +system.iocache.blocked_cycles::no_mshrs 64616068 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 10458 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 6183.498566 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6178.625741 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks 41522 # number of writebacks +system.iocache.writebacks 41520 # number of writebacks system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.iocache.overall_mshr_hits 0 # number of overall MSHR hits -system.iocache.ReadReq_mshr_misses 179 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses 178 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses 41552 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses 41731 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses 41731 # number of overall MSHR misses +system.iocache.demand_mshr_misses 41730 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses 41730 # number of overall MSHR misses system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.iocache.ReadReq_mshr_miss_latency 11309998 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency 3560091958 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency 3571401956 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency 3571401956 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency 11247998 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency 3559637996 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency 3570885994 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency 3570885994 # number of overall MSHR miss cycles system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_mshr_miss_rate::0 inf # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::1 1 # mshr miss rate for ReadReq accesses @@ -285,10 +285,10 @@ system.iocache.demand_mshr_miss_rate::total inf # system.iocache.overall_mshr_miss_rate::0 inf # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::1 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency 63184.346369 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency 85677.992828 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency 85581.509094 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency 85581.509094 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency 63191 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency 85667.067674 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency 85571.195639 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency 85571.195639 # average overall mshr miss latency system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions @@ -309,22 +309,22 @@ system.cpu0.dtb.fetch_hits 0 # IT system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 6880123 # DTB read hits -system.cpu0.dtb.read_misses 27029 # DTB read misses -system.cpu0.dtb.read_acv 463 # DTB read access violations -system.cpu0.dtb.read_accesses 649764 # DTB read accesses -system.cpu0.dtb.write_hits 4434059 # DTB write hits -system.cpu0.dtb.write_misses 4980 # DTB write misses -system.cpu0.dtb.write_acv 206 # DTB write access violations -system.cpu0.dtb.write_accesses 207730 # DTB write accesses -system.cpu0.dtb.data_hits 11314182 # DTB hits -system.cpu0.dtb.data_misses 32009 # DTB misses -system.cpu0.dtb.data_acv 669 # DTB access violations -system.cpu0.dtb.data_accesses 857494 # DTB accesses -system.cpu0.itb.fetch_hits 880445 # ITB hits -system.cpu0.itb.fetch_misses 30276 # ITB misses -system.cpu0.itb.fetch_acv 796 # ITB acv -system.cpu0.itb.fetch_accesses 910721 # ITB accesses +system.cpu0.dtb.read_hits 8560359 # DTB read hits +system.cpu0.dtb.read_misses 29048 # DTB read misses +system.cpu0.dtb.read_acv 513 # DTB read access violations +system.cpu0.dtb.read_accesses 619639 # DTB read accesses +system.cpu0.dtb.write_hits 5419292 # DTB write hits +system.cpu0.dtb.write_misses 5351 # DTB write misses +system.cpu0.dtb.write_acv 235 # DTB write access violations +system.cpu0.dtb.write_accesses 205704 # DTB write accesses +system.cpu0.dtb.data_hits 13979651 # DTB hits +system.cpu0.dtb.data_misses 34399 # DTB misses +system.cpu0.dtb.data_acv 748 # DTB access violations +system.cpu0.dtb.data_accesses 825343 # DTB accesses +system.cpu0.itb.fetch_hits 968518 # ITB hits +system.cpu0.itb.fetch_misses 28074 # ITB misses +system.cpu0.itb.fetch_acv 865 # ITB acv +system.cpu0.itb.fetch_accesses 996592 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -337,275 +337,275 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 86706401 # number of cpu cycles simulated +system.cpu0.numCycles 103762975 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.BPredUnit.lookups 9688854 # Number of BP lookups -system.cpu0.BPredUnit.condPredicted 8181343 # Number of conditional branches predicted -system.cpu0.BPredUnit.condIncorrect 315076 # Number of conditional branches incorrect -system.cpu0.BPredUnit.BTBLookups 8774584 # Number of BTB lookups -system.cpu0.BPredUnit.BTBHits 4716459 # Number of BTB hits +system.cpu0.BPredUnit.lookups 12289120 # Number of BP lookups +system.cpu0.BPredUnit.condPredicted 10322639 # Number of conditional branches predicted +system.cpu0.BPredUnit.condIncorrect 425623 # Number of conditional branches incorrect +system.cpu0.BPredUnit.BTBLookups 11096319 # Number of BTB lookups +system.cpu0.BPredUnit.BTBHits 5846860 # Number of BTB hits system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.BPredUnit.usedRAS 623303 # Number of times the RAS was used to get a target. -system.cpu0.BPredUnit.RASInCorrect 24682 # Number of incorrect RAS predictions. -system.cpu0.fetch.icacheStallCycles 18567041 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 50425492 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 9688854 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 5339762 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 9915303 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 1544367 # Number of cycles fetch has spent squashing -system.cpu0.fetch.BlockedCycles 26514797 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 7883 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 184619 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 223130 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 114 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 6371925 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 198240 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.rateDist::samples 56424843 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.893675 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.198082 # Number of instructions fetched each cycle (Total) +system.cpu0.BPredUnit.usedRAS 811980 # Number of times the RAS was used to get a target. +system.cpu0.BPredUnit.RASInCorrect 29936 # Number of incorrect RAS predictions. +system.cpu0.fetch.icacheStallCycles 23947551 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 63604775 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 12289120 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 6658840 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 12410125 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 1977970 # Number of cycles fetch has spent squashing +system.cpu0.fetch.BlockedCycles 32452881 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 32113 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 186103 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 333368 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 97 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 7852316 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 261746 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.rateDist::samples 70661432 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.900134 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.212081 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 46509540 82.43% 82.43% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 722585 1.28% 83.71% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 1421448 2.52% 86.23% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 628845 1.11% 87.34% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 2255580 4.00% 91.34% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 483816 0.86% 92.20% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 510012 0.90% 93.10% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 672132 1.19% 94.29% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 3220885 5.71% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 58251307 82.44% 82.44% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 861864 1.22% 83.66% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 1790389 2.53% 86.19% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 838279 1.19% 87.38% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 2691367 3.81% 91.19% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 597435 0.85% 92.03% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 679704 0.96% 92.99% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 792267 1.12% 94.11% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 4158820 5.89% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 56424843 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.111743 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.581566 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 19801968 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 25882509 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 8989466 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 763548 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 987351 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 383922 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 24849 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 49347154 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 75527 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 987351 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 20629203 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 9499998 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 13447452 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 8452255 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 3408582 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 46738624 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 3619 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 624032 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 1191344 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.RenamedOperands 31596053 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 57298293 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 57042075 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 256218 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 26711174 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 4884879 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 1120422 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 175328 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 8812934 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 7283662 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 4733758 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1431112 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 1440543 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 41212860 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1406639 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 39893176 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 57069 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 5631702 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 3133217 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 960480 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 56424843 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.707014 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.300043 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 70661432 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.118435 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.612981 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 25283379 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 31920291 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 11354348 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 836358 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1267055 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 507127 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 32392 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 62175948 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 94044 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 1267055 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 26303467 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 12206310 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 16544701 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 10563376 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 3776521 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 58802666 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 6783 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 552005 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 1306234 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.RenamedOperands 39659853 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 71942390 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 71601283 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 341107 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 33288864 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 6370981 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 1352745 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 204336 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 10335573 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 9033738 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 5759436 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1575901 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 1714897 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 51649014 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1711174 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 50034185 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 62931 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 7150176 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 3852149 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 1166094 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 70661432 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.708083 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.331294 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 37805881 67.00% 67.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 8674612 15.37% 82.38% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 4282035 7.59% 89.96% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 2440705 4.33% 94.29% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 1659937 2.94% 97.23% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 878759 1.56% 98.79% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 516481 0.92% 99.71% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 131514 0.23% 99.94% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 34919 0.06% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 48300171 68.35% 68.35% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 9930839 14.05% 82.41% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 4875287 6.90% 89.31% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 3134712 4.44% 93.74% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2288875 3.24% 96.98% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1259030 1.78% 98.77% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 656858 0.93% 99.69% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 168442 0.24% 99.93% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 47218 0.07% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 56424843 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 70661432 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 44960 12.13% 12.13% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 2 0.00% 12.13% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 12.13% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 12.13% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 12.13% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 12.13% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 12.13% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 12.13% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 12.13% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 12.13% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 12.13% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 12.13% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 12.13% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 12.13% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 12.13% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 12.13% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 12.13% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 12.13% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 12.13% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 12.13% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 12.13% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 12.13% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 12.13% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 12.13% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 12.13% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 12.13% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 12.13% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 12.13% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 12.13% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 207193 55.91% 68.04% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 118450 31.96% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 64961 14.10% 14.10% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 0 0.00% 14.10% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 14.10% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 14.10% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 14.10% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 14.10% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 14.10% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 14.10% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 14.10% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 14.10% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 14.10% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 14.10% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 14.10% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 14.10% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 14.10% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 14.10% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 14.10% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 14.10% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 14.10% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 14.10% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 14.10% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 14.10% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 14.10% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 14.10% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 14.10% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 14.10% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 14.10% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 14.10% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 14.10% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 248589 53.97% 68.08% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 147038 31.92% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 4482 0.01% 0.01% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 27545306 69.05% 69.06% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 42376 0.11% 69.17% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 69.17% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 14767 0.04% 69.20% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 69.20% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 69.20% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 69.20% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 2231 0.01% 69.21% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 69.21% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 69.21% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 69.21% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 69.21% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 69.21% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 69.21% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 69.21% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 69.21% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 69.21% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 69.21% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.21% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 69.21% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 69.21% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.21% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 69.21% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 69.21% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.21% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 69.21% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 69.21% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.21% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.21% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 7173118 17.98% 87.19% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 4487292 11.25% 98.44% # Type of FU issued -system.cpu0.iq.FU_type_0::IprAccess 623604 1.56% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 3305 0.01% 0.01% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 34793099 69.54% 69.55% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 56077 0.11% 69.66% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 69.66% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 13836 0.03% 69.68% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 69.68% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 69.68% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 69.68% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 1652 0.00% 69.69% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 69.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 69.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 69.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 69.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 69.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 69.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 69.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 69.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 69.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 69.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 69.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 69.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 69.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 69.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 69.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 69.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.69% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 8926243 17.84% 87.53% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 5486267 10.97% 98.49% # Type of FU issued +system.cpu0.iq.FU_type_0::IprAccess 753706 1.51% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 39893176 # Type of FU issued -system.cpu0.iq.rate 0.460095 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 370605 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.009290 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 136270898 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 48090698 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 38918381 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 367971 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 179542 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 176099 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 40067792 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 191507 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 416583 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 50034185 # Type of FU issued +system.cpu0.iq.rate 0.482197 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 460588 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.009205 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 170766492 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 60297186 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 48772869 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 486828 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 236130 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 232978 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 50238035 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 253433 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 485739 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1090641 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 12429 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 20965 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 441226 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1334836 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 17971 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 25456 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 519571 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 12240 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 165915 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 18977 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 164713 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 987351 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 6354184 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 491419 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 45032066 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 578341 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 7283662 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 4733758 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 1245675 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 448555 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 7135 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 20965 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 225122 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 243860 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 468982 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 39459085 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 6924497 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 434091 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 1267055 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 8486951 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 577503 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 56521315 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 733695 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 9033738 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 5759436 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 1510903 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 459190 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 7711 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 25456 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 319028 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 300441 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 619469 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 49457194 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 8612039 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 576990 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 2412567 # number of nop insts executed -system.cpu0.iew.exec_refs 11372805 # number of memory reference insts executed -system.cpu0.iew.exec_branches 6223343 # Number of branches executed -system.cpu0.iew.exec_stores 4448308 # Number of stores executed -system.cpu0.iew.exec_rate 0.455088 # Inst execution rate -system.cpu0.iew.wb_sent 39184807 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 39094480 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 19569580 # num instructions producing a value -system.cpu0.iew.wb_consumers 25865337 # num instructions consuming a value +system.cpu0.iew.exec_nop 3161127 # number of nop insts executed +system.cpu0.iew.exec_refs 14049434 # number of memory reference insts executed +system.cpu0.iew.exec_branches 7908844 # Number of branches executed +system.cpu0.iew.exec_stores 5437395 # Number of stores executed +system.cpu0.iew.exec_rate 0.476636 # Inst execution rate +system.cpu0.iew.wb_sent 49114578 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 49005847 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 24510505 # num instructions producing a value +system.cpu0.iew.wb_consumers 32850763 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.450883 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.756595 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.472286 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.746117 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitCommittedInsts 38900399 # The number of committed instructions -system.cpu0.commit.commitSquashedInsts 6019570 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 446159 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 429799 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 55437492 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.701698 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.560671 # Number of insts commited each cycle +system.cpu0.commit.commitCommittedInsts 48687390 # The number of committed instructions +system.cpu0.commit.commitSquashedInsts 7735637 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 545080 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 563607 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 69394377 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.701604 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.587762 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 40051862 72.25% 72.25% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 6559971 11.83% 84.08% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 3806221 6.87% 90.95% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 1668838 3.01% 93.96% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 1194660 2.15% 96.11% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 396856 0.72% 96.83% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 307618 0.55% 97.38% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 498884 0.90% 98.28% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 952582 1.72% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 50596179 72.91% 72.91% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 7970613 11.49% 84.40% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 4358860 6.28% 90.68% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 2336816 3.37% 94.05% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 1278043 1.84% 95.89% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 512868 0.74% 96.63% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 404165 0.58% 97.21% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 607557 0.88% 98.08% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1329276 1.92% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 55437492 # Number of insts commited each cycle -system.cpu0.commit.count 38900399 # Number of instructions committed +system.cpu0.commit.committed_per_cycle::total 69394377 # Number of insts commited each cycle +system.cpu0.commit.count 48687390 # Number of instructions committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 10485553 # Number of memory references committed -system.cpu0.commit.loads 6193021 # Number of loads committed -system.cpu0.commit.membars 147117 # Number of memory barriers committed -system.cpu0.commit.branches 5834794 # Number of branches committed -system.cpu0.commit.fp_insts 173443 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 36122415 # Number of committed integer instructions. -system.cpu0.commit.function_calls 477666 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 952582 # number cycles where commit BW limit reached +system.cpu0.commit.refs 12938767 # Number of memory references committed +system.cpu0.commit.loads 7698902 # Number of loads committed +system.cpu0.commit.membars 184242 # Number of memory barriers committed +system.cpu0.commit.branches 7372386 # Number of branches committed +system.cpu0.commit.fp_insts 230446 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 45102183 # Number of committed integer instructions. +system.cpu0.commit.function_calls 618802 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 1329276 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 99224913 # The number of ROB reads -system.cpu0.rob.rob_writes 90827622 # The number of ROB writes -system.cpu0.timesIdled 838575 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 30281558 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.committedInsts 36751342 # Number of Instructions Simulated -system.cpu0.committedInsts_total 36751342 # Number of Instructions Simulated -system.cpu0.cpi 2.359272 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.359272 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.423860 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.423860 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 52035955 # number of integer regfile reads -system.cpu0.int_regfile_writes 28508894 # number of integer regfile writes -system.cpu0.fp_regfile_reads 87486 # number of floating regfile reads -system.cpu0.fp_regfile_writes 87606 # number of floating regfile writes -system.cpu0.misc_regfile_reads 1265189 # number of misc regfile reads -system.cpu0.misc_regfile_writes 638472 # number of misc regfile writes +system.cpu0.rob.rob_reads 124302463 # The number of ROB reads +system.cpu0.rob.rob_writes 114114055 # The number of ROB writes +system.cpu0.timesIdled 1107408 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 33101543 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.committedInsts 45891664 # Number of Instructions Simulated +system.cpu0.committedInsts_total 45891664 # Number of Instructions Simulated +system.cpu0.cpi 2.261042 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.261042 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.442274 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.442274 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 65164143 # number of integer regfile reads +system.cpu0.int_regfile_writes 35661718 # number of integer regfile writes +system.cpu0.fp_regfile_reads 113503 # number of floating regfile reads +system.cpu0.fp_regfile_writes 115176 # number of floating regfile writes +system.cpu0.misc_regfile_reads 1562482 # number of misc regfile reads +system.cpu0.misc_regfile_writes 761048 # number of misc regfile writes system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -637,235 +637,233 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal no_value # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.cpu0.icache.replacements 604064 # number of replacements -system.cpu0.icache.tagsinuse 509.990240 # Cycle average of tags in use -system.cpu0.icache.total_refs 5734171 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 604576 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 9.484616 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 23368350000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::0 509.990240 # Average occupied blocks per context -system.cpu0.icache.occ_percent::0 0.996075 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::0 5734171 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 5734171 # number of ReadReq hits -system.cpu0.icache.demand_hits::0 5734171 # number of demand (read+write) hits +system.cpu0.icache.replacements 795450 # number of replacements +system.cpu0.icache.tagsinuse 509.996584 # Cycle average of tags in use +system.cpu0.icache.total_refs 7012391 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 795959 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 8.809990 # Average number of references to valid blocks. +system.cpu0.icache.warmup_cycle 23368345000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.occ_blocks::0 509.996584 # Average occupied blocks per context +system.cpu0.icache.occ_percent::0 0.996087 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::0 7012391 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 7012391 # number of ReadReq hits +system.cpu0.icache.demand_hits::0 7012391 # number of demand (read+write) hits system.cpu0.icache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 5734171 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::0 5734171 # number of overall hits +system.cpu0.icache.demand_hits::total 7012391 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::0 7012391 # number of overall hits system.cpu0.icache.overall_hits::1 0 # number of overall hits -system.cpu0.icache.overall_hits::total 5734171 # number of overall hits -system.cpu0.icache.ReadReq_misses::0 637754 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 637754 # number of ReadReq misses -system.cpu0.icache.demand_misses::0 637754 # number of demand (read+write) misses +system.cpu0.icache.overall_hits::total 7012391 # number of overall hits +system.cpu0.icache.ReadReq_misses::0 839924 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 839924 # number of ReadReq misses +system.cpu0.icache.demand_misses::0 839924 # number of demand (read+write) misses system.cpu0.icache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 637754 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::0 637754 # number of overall misses +system.cpu0.icache.demand_misses::total 839924 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::0 839924 # number of overall misses system.cpu0.icache.overall_misses::1 0 # number of overall misses -system.cpu0.icache.overall_misses::total 637754 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency 9712599996 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency 9712599996 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency 9712599996 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::0 6371925 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 6371925 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::0 6371925 # number of demand (read+write) accesses +system.cpu0.icache.overall_misses::total 839924 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency 12708309496 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency 12708309496 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency 12708309496 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::0 7852315 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 7852315 # 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miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::0 0.106965 # miss rate for demand accesses system.cpu0.icache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu0.icache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::0 0.100088 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::0 0.106965 # miss rate for overall accesses system.cpu0.icache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu0.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::0 15229.383110 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::0 15130.308809 # average ReadReq miss latency system.cpu0.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu0.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::0 15229.383110 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::0 15130.308809 # average overall miss latency system.cpu0.icache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu0.icache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::0 15229.383110 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::0 15130.308809 # average overall miss latency system.cpu0.icache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu0.icache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 1053998 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_mshrs 1208998 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 101 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 102 # 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number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency 9657065498 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency 9657065498 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency 9657065498 # number of overall MSHR miss cycles system.cpu0.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::0 0.094904 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::0 0.101383 # mshr miss rate for ReadReq accesses system.cpu0.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu0.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::0 0.094904 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::0 0.101383 # mshr miss rate for demand accesses system.cpu0.icache.demand_mshr_miss_rate::1 inf # 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Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 8.292954 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::0 447.158722 # Average occupied blocks per context +system.cpu0.dcache.occ_blocks::0 499.032464 # Average occupied blocks per context system.cpu0.dcache.occ_blocks::1 -1.000000 # Average occupied blocks per context -system.cpu0.dcache.occ_percent::0 0.873357 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::0 0.974673 # Average percentage of cache occupancy system.cpu0.dcache.occ_percent::1 -0.001953 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::0 5166195 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 5166195 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::0 2708345 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 2708345 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::0 133652 # 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miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::0 0.343844 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::0 0.081082 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::0 0.004872 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::0 0.239762 # miss rate for demand accesses +system.cpu0.dcache.overall_accesses::total 12860430 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::0 0.189453 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::0 0.317978 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::0 0.110140 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::0 0.023991 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::0 0.239880 # miss rate for demand accesses system.cpu0.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu0.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::0 0.239762 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::0 0.239880 # miss rate for overall accesses system.cpu0.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu0.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::0 26213.646269 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::0 23031.276258 # average ReadReq miss latency system.cpu0.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu0.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::0 33299.955004 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::0 32484.113400 # average WriteReq miss latency system.cpu0.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency system.cpu0.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::0 15576.316459 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::0 14742.718191 # average LoadLockedReq miss latency system.cpu0.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::0 9903.897849 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::0 13738.006521 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::0 30263.346680 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::0 27947.614931 # average overall miss latency system.cpu0.dcache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu0.dcache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::0 30263.346680 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::0 27947.614931 # average overall miss latency system.cpu0.dcache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu0.dcache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 831922069 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 188000 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 93842 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 8 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 8865.135749 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 23500 # average number of cycles each access was blocked +system.cpu0.dcache.blocked_cycles::no_mshrs 874274400 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 238500 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 96465 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 10 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 9063.125486 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 23850 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks 419465 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits 382209 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits 1203298 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits 2986 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits 1585507 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits 1585507 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses 681994 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses 215951 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses 8807 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses 744 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses 897945 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses 897945 # number of overall MSHR misses +system.cpu0.dcache.writebacks 701727 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits 509168 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits 1351881 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits 4474 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits 1861049 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits 1861049 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses 971332 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses 252581 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses 14546 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses 4294 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses 1223913 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses 1223913 # number of overall MSHR misses system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency 19802710500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency 7045833069 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency 103680500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency 5132500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency 5001 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency 26848543569 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency 26848543569 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency 634638000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency 1036991998 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency 1671629998 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::0 0.109462 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_latency 23290479000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency 7870556900 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency 149366500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency 46100000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency 31161035900 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency 31161035900 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency 917406500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency 1329367998 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency 2246774498 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::0 0.124297 # mshr miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::0 0.052319 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::0 0.050057 # mshr miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::0 0.060552 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::0 0.084232 # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::0 0.004872 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::0 0.023991 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::0 0.086691 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::0 0.095169 # mshr miss rate for demand accesses system.cpu0.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu0.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::0 0.086691 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::0 0.095169 # mshr miss rate for overall accesses system.cpu0.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu0.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 29036.487858 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 32626.999037 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency 11772.510503 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency 6898.521505 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency 29899.986713 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency 29899.986713 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 23977.876771 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 31160.526326 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency 10268.561804 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency 10735.910573 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency 25460.172333 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency 25460.172333 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency @@ -876,22 +874,22 @@ system.cpu1.dtb.fetch_hits 0 # IT system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 4024884 # DTB read hits -system.cpu1.dtb.read_misses 17321 # DTB read misses -system.cpu1.dtb.read_acv 119 # DTB read access violations -system.cpu1.dtb.read_accesses 318700 # DTB read accesses -system.cpu1.dtb.write_hits 2545920 # DTB write hits -system.cpu1.dtb.write_misses 4459 # DTB write misses -system.cpu1.dtb.write_acv 131 # DTB write access violations -system.cpu1.dtb.write_accesses 133305 # DTB write accesses -system.cpu1.dtb.data_hits 6570804 # DTB hits -system.cpu1.dtb.data_misses 21780 # DTB misses -system.cpu1.dtb.data_acv 250 # DTB access violations -system.cpu1.dtb.data_accesses 452005 # DTB accesses -system.cpu1.itb.fetch_hits 565000 # ITB hits -system.cpu1.itb.fetch_misses 8360 # ITB misses -system.cpu1.itb.fetch_acv 355 # ITB acv -system.cpu1.itb.fetch_accesses 573360 # ITB accesses +system.cpu1.dtb.read_hits 2434396 # DTB read hits +system.cpu1.dtb.read_misses 12632 # DTB read misses +system.cpu1.dtb.read_acv 51 # DTB read access violations +system.cpu1.dtb.read_accesses 349555 # DTB read accesses +system.cpu1.dtb.write_hits 1633702 # DTB write hits +system.cpu1.dtb.write_misses 3988 # DTB write misses +system.cpu1.dtb.write_acv 91 # DTB write access violations +system.cpu1.dtb.write_accesses 134749 # DTB write accesses +system.cpu1.dtb.data_hits 4068098 # DTB hits +system.cpu1.dtb.data_misses 16620 # DTB misses +system.cpu1.dtb.data_acv 142 # DTB access violations +system.cpu1.dtb.data_accesses 484304 # DTB accesses +system.cpu1.itb.fetch_hits 488641 # ITB hits +system.cpu1.itb.fetch_misses 8868 # ITB misses +system.cpu1.itb.fetch_acv 207 # ITB acv +system.cpu1.itb.fetch_accesses 497509 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -904,500 +902,500 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 36324508 # number of cpu cycles simulated +system.cpu1.numCycles 20348668 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.BPredUnit.lookups 5837794 # Number of BP lookups -system.cpu1.BPredUnit.condPredicted 4807752 # Number of conditional branches predicted -system.cpu1.BPredUnit.condIncorrect 236405 # Number of conditional branches incorrect -system.cpu1.BPredUnit.BTBLookups 5114419 # Number of BTB lookups -system.cpu1.BPredUnit.BTBHits 2355373 # Number of BTB hits +system.cpu1.BPredUnit.lookups 3352403 # Number of BP lookups +system.cpu1.BPredUnit.condPredicted 2780204 # Number of conditional branches predicted +system.cpu1.BPredUnit.condIncorrect 112990 # Number of conditional branches incorrect +system.cpu1.BPredUnit.BTBLookups 3035961 # Number of BTB lookups +system.cpu1.BPredUnit.BTBHits 1319312 # Number of BTB hits system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.BPredUnit.usedRAS 425756 # Number of times the RAS was used to get a target. -system.cpu1.BPredUnit.RASInCorrect 18870 # Number of incorrect RAS predictions. -system.cpu1.fetch.icacheStallCycles 12975380 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 28382917 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 5837794 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 2781129 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 5303525 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 1029370 # Number of cycles fetch has spent squashing -system.cpu1.fetch.BlockedCycles 12998724 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 3277 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 80064 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 157005 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 37 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 3308770 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 142735 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.rateDist::samples 32191429 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.881692 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.232987 # Number of instructions fetched each cycle (Total) +system.cpu1.BPredUnit.usedRAS 232566 # Number of times the RAS was used to get a target. +system.cpu1.BPredUnit.RASInCorrect 9070 # Number of incorrect RAS predictions. +system.cpu1.fetch.icacheStallCycles 8042198 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 15968682 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 3352403 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 1551878 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 2969461 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 549599 # Number of cycles fetch has spent squashing +system.cpu1.fetch.BlockedCycles 7368633 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 27992 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 74441 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 61172 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 29 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 1904129 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 71381 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.rateDist::samples 18894151 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.845165 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.201588 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 26887904 83.53% 83.53% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 353233 1.10% 84.62% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 711039 2.21% 86.83% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 413904 1.29% 88.12% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 842441 2.62% 90.73% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 260322 0.81% 91.54% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 338125 1.05% 92.59% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 409918 1.27% 93.87% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 1974543 6.13% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 15924690 84.28% 84.28% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 239855 1.27% 85.55% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 362060 1.92% 87.47% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 226098 1.20% 88.67% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 430016 2.28% 90.94% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 142596 0.75% 91.70% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 181045 0.96% 92.65% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 295229 1.56% 94.22% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 1092562 5.78% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 32191429 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.160712 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.781371 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 12951837 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 13394594 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 4901613 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 288063 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 655321 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 259847 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 18216 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 27639459 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 54136 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 655321 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 13441589 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 3341745 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 8668513 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 4556322 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 1527937 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 25800670 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 384 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 324513 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 337358 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.RenamedOperands 16998396 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 30868000 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 30637033 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 230967 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 13782341 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 3216047 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 763704 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 85939 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 4786247 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 4278315 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 2704053 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 527948 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 347634 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 22339353 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 928348 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 21581640 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 44138 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 3694956 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 1842331 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 660792 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 32191429 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.670416 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.349411 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 18894151 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.164748 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.784753 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 7867478 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 7772170 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 2762632 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 150042 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 341828 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 143049 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 8486 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 15583049 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 23483 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 341828 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 8134306 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 601370 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 6389331 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 2635739 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 791575 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 14485157 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 185 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 55864 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 183661 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.RenamedOperands 9468885 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 17315691 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 17110872 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 204819 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 7931339 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 1537546 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 569619 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 61560 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 2500740 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 2578124 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 1732920 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 321113 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 190156 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 12582391 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 647000 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 12202318 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 26509 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 1926210 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 1020296 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 460997 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 18894151 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.645825 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.311169 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 23032002 71.55% 71.55% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 3880534 12.05% 83.60% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 1841751 5.72% 89.32% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 1343655 4.17% 93.50% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 1100926 3.42% 96.92% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 572017 1.78% 98.69% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 269219 0.84% 99.53% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 103064 0.32% 99.85% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 48261 0.15% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 13531447 71.62% 71.62% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 2408615 12.75% 84.37% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 1089992 5.77% 90.13% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 719494 3.81% 93.94% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 600531 3.18% 97.12% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 311690 1.65% 98.77% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 155684 0.82% 99.59% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 53025 0.28% 99.87% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 23673 0.13% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 32191429 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 18894151 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 27325 8.19% 8.19% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 0 0.00% 8.19% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 8.19% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 8.19% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 8.19% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 8.19% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 8.19% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 8.19% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 8.19% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 8.19% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 8.19% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 8.19% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 8.19% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 8.19% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 8.19% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 8.19% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 8.19% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 8.19% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 8.19% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 8.19% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 8.19% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 8.19% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 8.19% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 8.19% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 8.19% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 8.19% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 8.19% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.19% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 8.19% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 173483 52.02% 60.21% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 132688 39.79% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 4502 1.97% 1.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 1.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 1.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 1.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 1.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 1.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 1.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 1.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 1.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 1.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 1.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 1.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 1.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 1.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 1.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 1.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 1.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 1.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 1.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 1.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 1.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 1.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 1.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 1.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 1.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 1.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 1.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 1.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 121874 53.21% 55.17% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 102674 44.83% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 2823 0.01% 0.01% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 14285140 66.19% 66.20% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 29916 0.14% 66.34% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 66.34% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 11006 0.05% 66.39% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 66.39% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 66.39% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 66.39% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 1411 0.01% 66.40% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 66.40% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 66.40% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 66.40% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 66.40% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 66.40% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 66.40% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 66.40% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 66.40% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 66.40% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 66.40% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.40% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 66.40% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.40% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.40% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.40% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.40% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.40% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.40% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 66.40% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.40% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.40% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 4218514 19.55% 85.95% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 2587729 11.99% 97.94% # Type of FU issued -system.cpu1.iq.FU_type_0::IprAccess 445101 2.06% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 3982 0.03% 0.03% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 7613703 62.40% 62.43% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 19536 0.16% 62.59% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.59% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 13122 0.11% 62.70% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.70% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.70% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.70% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 1991 0.02% 62.71% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.71% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 2552683 20.92% 83.63% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 1661486 13.62% 97.25% # Type of FU issued +system.cpu1.iq.FU_type_0::IprAccess 335815 2.75% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 21581640 # Type of FU issued -system.cpu1.iq.rate 0.594134 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 333496 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.015453 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 75401338 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 26810016 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 20892220 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 331004 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 159326 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 156915 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 21738437 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 173876 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 181996 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 12202318 # Type of FU issued +system.cpu1.iq.rate 0.599662 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 229050 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.018771 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 43260661 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 15016823 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 11811979 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 293685 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 142362 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 139746 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 12273711 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 153675 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 108256 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 722762 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 9242 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 8212 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 265030 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 372523 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 7917 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 4307 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 156502 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 7445 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 45661 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 333 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 28285 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 655321 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 2533054 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 130038 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 24654122 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 348083 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 4278315 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 2704053 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 831283 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 42195 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 6811 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 8212 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 170867 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 176891 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 347758 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 21288201 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 4056224 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 293438 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 341828 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 445544 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 34164 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 13910925 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 201807 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 2578124 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 1732920 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 582063 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 21599 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 6281 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 4307 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 78974 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 111447 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 190421 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 12072034 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 2457890 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 130284 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 1386421 # number of nop insts executed -system.cpu1.iew.exec_refs 6615012 # number of memory reference insts executed -system.cpu1.iew.exec_branches 3371082 # Number of branches executed -system.cpu1.iew.exec_stores 2558788 # Number of stores executed -system.cpu1.iew.exec_rate 0.586056 # Inst execution rate -system.cpu1.iew.wb_sent 21107487 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 21049135 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 10120752 # num instructions producing a value -system.cpu1.iew.wb_consumers 14228146 # num instructions consuming a value +system.cpu1.iew.exec_nop 681534 # number of nop insts executed +system.cpu1.iew.exec_refs 4103399 # number of memory reference insts executed +system.cpu1.iew.exec_branches 1804932 # Number of branches executed +system.cpu1.iew.exec_stores 1645509 # Number of stores executed +system.cpu1.iew.exec_rate 0.593259 # Inst execution rate +system.cpu1.iew.wb_sent 11986744 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 11951725 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 5550831 # num instructions producing a value +system.cpu1.iew.wb_consumers 7770927 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.579475 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.711319 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.587347 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.714307 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitCommittedInsts 20574037 # The number of committed instructions -system.cpu1.commit.commitSquashedInsts 4003646 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 267556 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 316871 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 31536108 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.652396 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.582786 # Number of insts commited each cycle +system.cpu1.commit.commitCommittedInsts 11805751 # The number of committed instructions +system.cpu1.commit.commitSquashedInsts 2024872 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 186003 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 175934 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 18552323 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.636349 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.571810 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 23929669 75.88% 75.88% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 3216209 10.20% 86.08% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 1611477 5.11% 91.19% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 871112 2.76% 93.95% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 572339 1.81% 95.77% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 274054 0.87% 96.63% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 208667 0.66% 97.30% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 210738 0.67% 97.96% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 641843 2.04% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 14118650 76.10% 76.10% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 2051209 11.06% 87.16% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 792595 4.27% 91.43% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 477671 2.57% 94.01% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 327821 1.77% 95.77% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 149583 0.81% 96.58% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 116875 0.63% 97.21% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 167462 0.90% 98.11% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 350457 1.89% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 31536108 # Number of insts commited each cycle -system.cpu1.commit.count 20574037 # Number of instructions committed +system.cpu1.commit.committed_per_cycle::total 18552323 # Number of insts commited each cycle +system.cpu1.commit.count 11805751 # Number of instructions committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 5994576 # Number of memory references committed -system.cpu1.commit.loads 3555553 # Number of loads committed -system.cpu1.commit.membars 91088 # Number of memory barriers committed -system.cpu1.commit.branches 3081632 # Number of branches committed -system.cpu1.commit.fp_insts 155618 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 18958031 # Number of committed integer instructions. -system.cpu1.commit.function_calls 316244 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 641843 # number cycles where commit BW limit reached +system.cpu1.commit.refs 3782019 # Number of memory references committed +system.cpu1.commit.loads 2205601 # Number of loads committed +system.cpu1.commit.membars 61380 # Number of memory barriers committed +system.cpu1.commit.branches 1685692 # Number of branches committed +system.cpu1.commit.fp_insts 138212 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 10911872 # Number of committed integer instructions. +system.cpu1.commit.function_calls 184868 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 350457 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 55370614 # The number of ROB reads -system.cpu1.rob.rob_writes 49810796 # The number of ROB writes -system.cpu1.timesIdled 461933 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 4133079 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.committedInsts 19384686 # Number of Instructions Simulated -system.cpu1.committedInsts_total 19384686 # Number of Instructions Simulated -system.cpu1.cpi 1.873877 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.873877 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.533653 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.533653 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 27536671 # number of integer regfile reads -system.cpu1.int_regfile_writes 15012037 # number of integer regfile writes -system.cpu1.fp_regfile_reads 81305 # number of floating regfile reads -system.cpu1.fp_regfile_writes 82180 # number of floating regfile writes -system.cpu1.misc_regfile_reads 884105 # number of misc regfile reads -system.cpu1.misc_regfile_writes 384773 # number of misc regfile writes -system.cpu1.icache.replacements 474445 # number of replacements -system.cpu1.icache.tagsinuse 505.356684 # Cycle average of tags in use -system.cpu1.icache.total_refs 2809266 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 474955 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 5.914805 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 46541421000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::0 505.356684 # Average occupied blocks per context -system.cpu1.icache.occ_percent::0 0.987025 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::0 2809266 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 2809266 # number of ReadReq hits -system.cpu1.icache.demand_hits::0 2809266 # number of demand (read+write) hits +system.cpu1.rob.rob_reads 31928567 # The number of ROB reads +system.cpu1.rob.rob_writes 28001823 # The number of ROB writes +system.cpu1.timesIdled 205057 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 1454517 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.committedInsts 11204705 # Number of Instructions Simulated +system.cpu1.committedInsts_total 11204705 # Number of Instructions Simulated +system.cpu1.cpi 1.816082 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.816082 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.550636 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.550636 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 15543323 # number of integer regfile reads +system.cpu1.int_regfile_writes 8446180 # number of integer regfile writes +system.cpu1.fp_regfile_reads 74822 # number of floating regfile reads +system.cpu1.fp_regfile_writes 74815 # number of floating regfile writes +system.cpu1.misc_regfile_reads 675670 # number of misc regfile reads +system.cpu1.misc_regfile_writes 285692 # number of misc regfile writes +system.cpu1.icache.replacements 294345 # number of replacements +system.cpu1.icache.tagsinuse 471.340417 # Cycle average of tags in use +system.cpu1.icache.total_refs 1598818 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 294856 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 5.422369 # Average number of references to valid blocks. +system.cpu1.icache.warmup_cycle 1874432600000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.occ_blocks::0 471.340417 # Average occupied blocks per context +system.cpu1.icache.occ_percent::0 0.920587 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::0 1598818 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 1598818 # number of ReadReq hits +system.cpu1.icache.demand_hits::0 1598818 # number of demand (read+write) hits system.cpu1.icache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 2809266 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::0 2809266 # number of overall hits +system.cpu1.icache.demand_hits::total 1598818 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::0 1598818 # number of overall hits system.cpu1.icache.overall_hits::1 0 # number of overall hits -system.cpu1.icache.overall_hits::total 2809266 # number of overall hits -system.cpu1.icache.ReadReq_misses::0 499504 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 499504 # number of ReadReq misses -system.cpu1.icache.demand_misses::0 499504 # number of demand (read+write) misses +system.cpu1.icache.overall_hits::total 1598818 # number of overall hits +system.cpu1.icache.ReadReq_misses::0 305311 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 305311 # number of ReadReq misses +system.cpu1.icache.demand_misses::0 305311 # number of demand (read+write) misses system.cpu1.icache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 499504 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::0 499504 # number of overall misses +system.cpu1.icache.demand_misses::total 305311 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::0 305311 # number of overall misses system.cpu1.icache.overall_misses::1 0 # number of overall misses -system.cpu1.icache.overall_misses::total 499504 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency 7358434998 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency 7358434998 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency 7358434998 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::0 3308770 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 3308770 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::0 3308770 # number of demand (read+write) accesses +system.cpu1.icache.overall_misses::total 305311 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency 4483412500 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency 4483412500 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency 4483412500 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::0 1904129 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 1904129 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::0 1904129 # number of demand (read+write) accesses system.cpu1.icache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 3308770 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::0 3308770 # number of overall (read+write) accesses +system.cpu1.icache.demand_accesses::total 1904129 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::0 1904129 # number of overall (read+write) accesses system.cpu1.icache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 3308770 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::0 0.150964 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::0 0.150964 # miss rate for demand accesses +system.cpu1.icache.overall_accesses::total 1904129 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::0 0.160342 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::0 0.160342 # miss rate for demand accesses system.cpu1.icache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu1.icache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::0 0.150964 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::0 0.160342 # miss rate for overall accesses system.cpu1.icache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu1.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::0 14731.483628 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::0 14684.739495 # average ReadReq miss latency system.cpu1.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu1.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::0 14731.483628 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::0 14684.739495 # average overall miss latency system.cpu1.icache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu1.icache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::0 14731.483628 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::0 14684.739495 # average overall miss latency system.cpu1.icache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu1.icache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 428499 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles::no_mshrs 116500 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 44 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 18 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 9738.613636 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 6472.222222 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.writebacks 33 # number of writebacks -system.cpu1.icache.ReadReq_mshr_hits 24498 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits 24498 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits 24498 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses 475006 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses 475006 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses 475006 # number of overall MSHR misses +system.cpu1.icache.writebacks 49 # number of writebacks +system.cpu1.icache.ReadReq_mshr_hits 10391 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits 10391 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits 10391 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses 294920 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses 294920 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses 294920 # number of overall MSHR misses system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu1.icache.ReadReq_mshr_miss_latency 5595943999 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency 5595943999 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency 5595943999 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency 3431981500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency 3431981500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency 3431981500 # number of overall MSHR miss cycles system.cpu1.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::0 0.143560 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::0 0.154884 # mshr miss rate for ReadReq accesses system.cpu1.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu1.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::0 0.143560 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::0 0.154884 # mshr miss rate for demand accesses system.cpu1.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu1.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::0 0.143560 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::0 0.154884 # mshr miss rate for overall accesses system.cpu1.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu1.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11780.785925 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency 11780.785925 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency 11780.785925 # average overall mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11636.991387 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency 11636.991387 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency 11636.991387 # average overall mshr miss latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 557180 # number of replacements -system.cpu1.dcache.tagsinuse 488.553100 # Cycle average of tags in use -system.cpu1.dcache.total_refs 4834021 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 557692 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 8.667905 # Average number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 34444090000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::0 488.553100 # Average occupied blocks per context -system.cpu1.dcache.occ_percent::0 0.954205 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::0 2945256 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 2945256 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::0 1749855 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 1749855 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::0 63493 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 63493 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::0 71374 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 71374 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::0 4695111 # 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number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 47069 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::0 45973 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 45973 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::0 3169926 # number of demand (read+write) hits system.cpu1.dcache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 4695111 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::0 4695111 # number of overall hits +system.cpu1.dcache.demand_hits::total 3169926 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::0 3169926 # number of overall hits system.cpu1.dcache.overall_hits::1 0 # number of overall hits -system.cpu1.dcache.overall_hits::total 4695111 # number of overall hits -system.cpu1.dcache.ReadReq_misses::0 787154 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 787154 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::0 609216 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 609216 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::0 13718 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 13718 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::0 830 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 830 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::0 1396370 # number of demand (read+write) misses +system.cpu1.dcache.overall_hits::total 3169926 # number of overall hits +system.cpu1.dcache.ReadReq_misses::0 282407 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 282407 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::0 325995 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 325995 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::0 7824 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 7824 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::0 4577 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 4577 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::0 608402 # number of demand (read+write) misses system.cpu1.dcache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 1396370 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::0 1396370 # number of overall misses +system.cpu1.dcache.demand_misses::total 608402 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::0 608402 # number of overall misses system.cpu1.dcache.overall_misses::1 0 # number of overall misses -system.cpu1.dcache.overall_misses::total 1396370 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency 11151181000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency 13606670637 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency 199877000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency 10316000 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency 24757851637 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency 24757851637 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::0 3732410 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 3732410 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::0 2359071 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 2359071 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::0 77211 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 77211 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::0 72204 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 72204 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::0 6091481 # number of demand (read+write) accesses +system.cpu1.dcache.overall_misses::total 608402 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency 4155262000 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency 7647875941 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency 85879000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency 62313500 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency 11803137941 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency 11803137941 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::0 2259152 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 2259152 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::0 1519176 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 1519176 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::0 54893 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 54893 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::0 50550 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 50550 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::0 3778328 # number of demand (read+write) accesses system.cpu1.dcache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 6091481 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::0 6091481 # number of overall (read+write) accesses +system.cpu1.dcache.demand_accesses::total 3778328 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::0 3778328 # number of overall (read+write) accesses system.cpu1.dcache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 6091481 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::0 0.210897 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::0 0.258244 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::0 0.177669 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::0 0.011495 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::0 0.229233 # miss rate for demand accesses +system.cpu1.dcache.overall_accesses::total 3778328 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::0 0.125006 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::0 0.214587 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::0 0.142532 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::0 0.090544 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::0 0.161024 # miss rate for demand accesses system.cpu1.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu1.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::0 0.229233 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::0 0.161024 # miss rate for overall accesses system.cpu1.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu1.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::0 14166.454086 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::0 14713.735849 # average ReadReq miss latency system.cpu1.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu1.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::0 22334.723049 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::0 23460.101968 # average WriteReq miss latency system.cpu1.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency system.cpu1.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::0 14570.418428 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::0 10976.354806 # average LoadLockedReq miss latency system.cpu1.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::0 12428.915663 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::0 13614.485471 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency system.cpu1.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::0 17730.151491 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::0 19400.228699 # average overall miss latency system.cpu1.dcache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu1.dcache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::0 17730.151491 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::0 19400.228699 # average overall miss latency system.cpu1.dcache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu1.dcache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 143111212 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 22000 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 13232 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 10815.538996 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets 22000 # average number of cycles each access was blocked +system.cpu1.dcache.blocked_cycles::no_mshrs 94033995 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 7725 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 12172.685437 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks 434743 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits 338033 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits 504690 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits 2893 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits 842723 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits 842723 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses 449121 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses 104526 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses 10825 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses 830 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses 553647 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses 553647 # number of overall MSHR misses +system.cpu1.dcache.writebacks 103879 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits 174324 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits 267778 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits 757 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits 442102 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits 442102 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses 108083 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses 58217 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses 7067 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses 4577 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses 166300 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses 166300 # number of overall MSHR misses system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency 5367032500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency 2133420198 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency 121712000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency 7814500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency 7500452698 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency 7500452698 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency 301848000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency 539476500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency 841324500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::0 0.120330 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_latency 1297456000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency 1215847490 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency 55744000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency 48574500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency 2513303490 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency 2513303490 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency 18621500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency 393979500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency 412601000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::0 0.047842 # mshr miss rate for ReadReq accesses system.cpu1.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu1.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::0 0.044308 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::0 0.038321 # mshr miss rate for WriteReq accesses system.cpu1.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses system.cpu1.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::0 0.140200 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::0 0.128741 # mshr miss rate for LoadLockedReq accesses system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::0 0.011495 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::0 0.090544 # mshr miss rate for StoreCondReq accesses system.cpu1.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::0 0.090889 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::0 0.044014 # mshr miss rate for demand accesses system.cpu1.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu1.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::0 0.090889 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::0 0.044014 # mshr miss rate for overall accesses system.cpu1.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu1.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 11950.081381 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 20410.426095 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency 11243.602771 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency 9415.060241 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency 13547.355441 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency 13547.355441 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 12004.255988 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 20884.749987 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency 7887.929815 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency 10612.737601 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency 15113.069693 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency 15113.069693 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency @@ -1405,169 +1403,164 @@ system.cpu1.dcache.mshr_cap_events 0 # nu system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 4836 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 139328 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 46150 38.89% 38.89% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 238 0.20% 39.09% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1923 1.62% 40.71% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 16 0.01% 40.73% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 70336 59.27% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 118663 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 45525 48.84% 48.84% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::21 238 0.26% 49.10% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1923 2.06% 51.16% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::30 16 0.02% 51.18% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 45509 48.82% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 93211 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1865602561500 98.27% 98.27% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 91021500 0.00% 98.28% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 389859500 0.02% 98.30% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 7895500 0.00% 98.30% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 32350102500 1.70% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1898441440500 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.986457 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.inst.quiesce 6679 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 170123 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 59613 40.27% 40.27% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 237 0.16% 40.44% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::22 1922 1.30% 41.73% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::30 309 0.21% 41.94% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 85934 58.06% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 148015 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 58855 49.10% 49.10% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::21 237 0.20% 49.30% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::22 1922 1.60% 50.90% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::30 309 0.26% 51.16% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 58546 48.84% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 119869 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1860434296000 98.05% 98.05% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 90872000 0.00% 98.05% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 391830000 0.02% 98.07% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 123760000 0.01% 98.08% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 36487097000 1.92% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1897527855000 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.987285 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.647023 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.syscall::2 5 2.39% 2.39% # number of syscalls executed -system.cpu0.kern.syscall::3 17 8.13% 10.53% # number of syscalls executed -system.cpu0.kern.syscall::4 3 1.44% 11.96% # number of syscalls executed -system.cpu0.kern.syscall::6 28 13.40% 25.36% # number of syscalls executed -system.cpu0.kern.syscall::12 1 0.48% 25.84% # number of syscalls executed -system.cpu0.kern.syscall::15 1 0.48% 26.32% # number of syscalls executed -system.cpu0.kern.syscall::17 9 4.31% 30.62% # number of syscalls executed -system.cpu0.kern.syscall::19 5 2.39% 33.01% # number of syscalls executed -system.cpu0.kern.syscall::20 4 1.91% 34.93% # number of syscalls executed -system.cpu0.kern.syscall::23 2 0.96% 35.89% # number of syscalls executed -system.cpu0.kern.syscall::24 4 1.91% 37.80% # number of syscalls executed -system.cpu0.kern.syscall::33 7 3.35% 41.15% # number of syscalls executed -system.cpu0.kern.syscall::41 2 0.96% 42.11% # number of syscalls executed -system.cpu0.kern.syscall::45 35 16.75% 58.85% # number of syscalls executed -system.cpu0.kern.syscall::47 4 1.91% 60.77% # number of syscalls executed -system.cpu0.kern.syscall::48 6 2.87% 63.64% # number of syscalls executed -system.cpu0.kern.syscall::54 9 4.31% 67.94% # number of syscalls executed -system.cpu0.kern.syscall::58 1 0.48% 68.42% # number of syscalls executed -system.cpu0.kern.syscall::59 4 1.91% 70.33% # number of syscalls executed -system.cpu0.kern.syscall::71 32 15.31% 85.65% # number of syscalls executed -system.cpu0.kern.syscall::73 3 1.44% 87.08% # number of syscalls executed -system.cpu0.kern.syscall::74 9 4.31% 91.39% # number of syscalls executed -system.cpu0.kern.syscall::87 1 0.48% 91.87% # number of syscalls executed -system.cpu0.kern.syscall::90 1 0.48% 92.34% # number of syscalls executed -system.cpu0.kern.syscall::92 7 3.35% 95.69% # number of syscalls executed +system.cpu0.kern.ipl_used::31 0.681290 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.syscall::2 7 3.35% 3.35% # number of syscalls executed +system.cpu0.kern.syscall::3 17 8.13% 11.48% # number of syscalls executed +system.cpu0.kern.syscall::4 3 1.44% 12.92% # number of syscalls executed +system.cpu0.kern.syscall::6 31 14.83% 27.75% # number of syscalls executed +system.cpu0.kern.syscall::12 1 0.48% 28.23% # number of syscalls executed +system.cpu0.kern.syscall::17 8 3.83% 32.06% # number of syscalls executed +system.cpu0.kern.syscall::19 9 4.31% 36.36% # number of syscalls executed +system.cpu0.kern.syscall::20 6 2.87% 39.23% # number of syscalls executed +system.cpu0.kern.syscall::23 1 0.48% 39.71% # number of syscalls executed +system.cpu0.kern.syscall::24 3 1.44% 41.15% # number of syscalls executed +system.cpu0.kern.syscall::33 6 2.87% 44.02% # number of syscalls executed +system.cpu0.kern.syscall::41 2 0.96% 44.98% # number of syscalls executed +system.cpu0.kern.syscall::45 33 15.79% 60.77% # number of syscalls executed +system.cpu0.kern.syscall::47 3 1.44% 62.20% # number of syscalls executed +system.cpu0.kern.syscall::48 9 4.31% 66.51% # number of syscalls executed +system.cpu0.kern.syscall::54 10 4.78% 71.29% # number of syscalls executed +system.cpu0.kern.syscall::58 1 0.48% 71.77% # number of syscalls executed +system.cpu0.kern.syscall::59 5 2.39% 74.16% # number of syscalls executed +system.cpu0.kern.syscall::71 23 11.00% 85.17% # number of syscalls executed +system.cpu0.kern.syscall::73 3 1.44% 86.60% # number of syscalls executed +system.cpu0.kern.syscall::74 6 2.87% 89.47% # number of syscalls executed +system.cpu0.kern.syscall::87 1 0.48% 89.95% # number of syscalls executed +system.cpu0.kern.syscall::90 3 1.44% 91.39% # number of syscalls executed +system.cpu0.kern.syscall::92 9 4.31% 95.69% # number of syscalls executed system.cpu0.kern.syscall::97 2 0.96% 96.65% # number of syscalls executed system.cpu0.kern.syscall::98 2 0.96% 97.61% # number of syscalls executed -system.cpu0.kern.syscall::132 2 0.96% 98.56% # number of syscalls executed -system.cpu0.kern.syscall::144 1 0.48% 99.04% # number of syscalls executed +system.cpu0.kern.syscall::132 1 0.48% 98.09% # number of syscalls executed +system.cpu0.kern.syscall::144 2 0.96% 99.04% # number of syscalls executed system.cpu0.kern.syscall::147 2 0.96% 100.00% # number of syscalls executed system.cpu0.kern.syscall::total 209 # number of syscalls executed system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wripir 105 0.08% 0.08% # number of callpals executed -system.cpu0.kern.callpal::wrmces 1 0.00% 0.09% # number of callpals executed -system.cpu0.kern.callpal::wrfen 1 0.00% 0.09% # number of callpals executed -system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.09% # number of callpals executed -system.cpu0.kern.callpal::swpctx 2219 1.77% 1.85% # number of callpals executed -system.cpu0.kern.callpal::tbi 37 0.03% 1.88% # number of callpals executed -system.cpu0.kern.callpal::wrent 7 0.01% 1.89% # number of callpals executed -system.cpu0.kern.callpal::swpipl 112588 89.60% 91.49% # number of callpals executed -system.cpu0.kern.callpal::rdps 6309 5.02% 96.51% # number of callpals executed -system.cpu0.kern.callpal::wrkgp 1 0.00% 96.51% # number of callpals executed -system.cpu0.kern.callpal::wrusp 3 0.00% 96.52% # number of callpals executed -system.cpu0.kern.callpal::rdusp 6 0.00% 96.52% # number of callpals executed -system.cpu0.kern.callpal::whami 2 0.00% 96.52% # number of callpals executed -system.cpu0.kern.callpal::rti 3897 3.10% 99.62% # number of callpals executed -system.cpu0.kern.callpal::callsys 326 0.26% 99.88% # number of callpals executed -system.cpu0.kern.callpal::imb 146 0.12% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 125650 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 5507 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1097 # number of protection mode switches +system.cpu0.kern.callpal::wripir 406 0.26% 0.26% # number of callpals executed +system.cpu0.kern.callpal::wrmces 1 0.00% 0.26% # number of callpals executed +system.cpu0.kern.callpal::wrfen 1 0.00% 0.26% # number of callpals executed +system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.26% # number of callpals executed +system.cpu0.kern.callpal::swpctx 3167 2.03% 2.29% # number of callpals executed +system.cpu0.kern.callpal::tbi 45 0.03% 2.32% # number of callpals executed +system.cpu0.kern.callpal::wrent 7 0.00% 2.33% # number of callpals executed +system.cpu0.kern.callpal::swpipl 141170 90.48% 92.80% # number of callpals executed +system.cpu0.kern.callpal::rdps 6359 4.08% 96.88% # number of callpals executed +system.cpu0.kern.callpal::wrkgp 1 0.00% 96.88% # number of callpals executed +system.cpu0.kern.callpal::wrusp 2 0.00% 96.88% # number of callpals executed +system.cpu0.kern.callpal::rdusp 8 0.01% 96.89% # number of callpals executed +system.cpu0.kern.callpal::whami 2 0.00% 96.89% # number of callpals executed +system.cpu0.kern.callpal::rti 4376 2.80% 99.69% # number of callpals executed +system.cpu0.kern.callpal::callsys 348 0.22% 99.91% # number of callpals executed +system.cpu0.kern.callpal::imb 134 0.09% 100.00% # number of callpals executed +system.cpu0.kern.callpal::total 156029 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 6806 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1160 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1097 -system.cpu0.kern.mode_good::user 1097 +system.cpu0.kern.mode_good::kernel 1159 +system.cpu0.kern.mode_good::user 1160 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.199201 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.170291 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle no_value # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::total no_value # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1896108272000 99.90% 99.90% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 1865257500 0.10% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::kernel 1895695413000 99.90% 99.90% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 1832434000 0.10% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 2220 # number of times the context was actually changed +system.cpu0.kern.swap_context 3168 # number of times the context was actually changed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 3828 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 98562 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 35646 40.41% 40.41% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1921 2.18% 42.59% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 105 0.12% 42.71% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 50532 57.29% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 88204 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 34894 48.66% 48.66% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1921 2.68% 51.34% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 105 0.15% 51.49% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 34789 48.51% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 71709 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1866332283500 98.30% 98.30% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 346173000 0.02% 98.32% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 42378500 0.00% 98.32% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 31930549500 1.68% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1898651384500 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.978904 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.quiesce 2565 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 71341 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 23380 38.18% 38.18% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1920 3.14% 41.31% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::30 406 0.66% 41.98% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 35533 58.02% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 61239 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 22761 47.98% 47.98% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1920 4.05% 52.02% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 406 0.86% 52.88% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 22355 47.12% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 47442 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1868516653000 98.47% 98.47% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 343880500 0.02% 98.49% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 155607500 0.01% 98.50% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 28447585000 1.50% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1897463726000 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.973524 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.688455 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.syscall::2 3 2.56% 2.56% # number of syscalls executed -system.cpu1.kern.syscall::3 13 11.11% 13.68% # number of syscalls executed -system.cpu1.kern.syscall::4 1 0.85% 14.53% # number of syscalls executed -system.cpu1.kern.syscall::6 14 11.97% 26.50% # number of syscalls executed -system.cpu1.kern.syscall::17 6 5.13% 31.62% # number of syscalls executed -system.cpu1.kern.syscall::19 5 4.27% 35.90% # number of syscalls executed -system.cpu1.kern.syscall::20 2 1.71% 37.61% # number of syscalls executed -system.cpu1.kern.syscall::23 2 1.71% 39.32% # number of syscalls executed -system.cpu1.kern.syscall::24 2 1.71% 41.03% # number of syscalls executed -system.cpu1.kern.syscall::33 4 3.42% 44.44% # number of syscalls executed -system.cpu1.kern.syscall::45 19 16.24% 60.68% # number of syscalls executed -system.cpu1.kern.syscall::47 2 1.71% 62.39% # number of syscalls executed -system.cpu1.kern.syscall::48 4 3.42% 65.81% # number of syscalls executed -system.cpu1.kern.syscall::54 1 0.85% 66.67% # number of syscalls executed -system.cpu1.kern.syscall::59 3 2.56% 69.23% # number of syscalls executed -system.cpu1.kern.syscall::71 22 18.80% 88.03% # number of syscalls executed -system.cpu1.kern.syscall::74 7 5.98% 94.02% # number of syscalls executed -system.cpu1.kern.syscall::90 2 1.71% 95.73% # number of syscalls executed -system.cpu1.kern.syscall::92 2 1.71% 97.44% # number of syscalls executed -system.cpu1.kern.syscall::132 2 1.71% 99.15% # number of syscalls executed -system.cpu1.kern.syscall::144 1 0.85% 100.00% # number of syscalls executed +system.cpu1.kern.ipl_used::31 0.629133 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.syscall::2 1 0.85% 0.85% # number of syscalls executed +system.cpu1.kern.syscall::3 13 11.11% 11.97% # number of syscalls executed +system.cpu1.kern.syscall::4 1 0.85% 12.82% # number of syscalls executed +system.cpu1.kern.syscall::6 11 9.40% 22.22% # number of syscalls executed +system.cpu1.kern.syscall::15 1 0.85% 23.08% # number of syscalls executed +system.cpu1.kern.syscall::17 7 5.98% 29.06% # number of syscalls executed +system.cpu1.kern.syscall::19 1 0.85% 29.91% # number of syscalls executed +system.cpu1.kern.syscall::23 3 2.56% 32.48% # number of syscalls executed +system.cpu1.kern.syscall::24 3 2.56% 35.04% # number of syscalls executed +system.cpu1.kern.syscall::33 5 4.27% 39.32% # number of syscalls executed +system.cpu1.kern.syscall::45 21 17.95% 57.26% # number of syscalls executed +system.cpu1.kern.syscall::47 3 2.56% 59.83% # number of syscalls executed +system.cpu1.kern.syscall::48 1 0.85% 60.68% # number of syscalls executed +system.cpu1.kern.syscall::59 2 1.71% 62.39% # number of syscalls executed +system.cpu1.kern.syscall::71 31 26.50% 88.89% # number of syscalls executed +system.cpu1.kern.syscall::74 10 8.55% 97.44% # number of syscalls executed +system.cpu1.kern.syscall::132 3 2.56% 100.00% # number of syscalls executed system.cpu1.kern.syscall::total 117 # number of syscalls executed system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal::wripir 16 0.02% 0.02% # number of callpals executed -system.cpu1.kern.callpal::wrmces 1 0.00% 0.02% # number of callpals executed -system.cpu1.kern.callpal::wrfen 1 0.00% 0.02% # number of callpals executed -system.cpu1.kern.callpal::swpctx 2023 2.23% 2.25% # number of callpals executed -system.cpu1.kern.callpal::tbi 16 0.02% 2.26% # number of callpals executed -system.cpu1.kern.callpal::wrent 7 0.01% 2.27% # number of callpals executed -system.cpu1.kern.callpal::swpipl 82767 91.03% 93.30% # number of callpals executed -system.cpu1.kern.callpal::rdps 2444 2.69% 95.99% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 95.99% # number of callpals executed -system.cpu1.kern.callpal::wrusp 4 0.00% 96.00% # number of callpals executed -system.cpu1.kern.callpal::rdusp 3 0.00% 96.00% # number of callpals executed -system.cpu1.kern.callpal::whami 3 0.00% 96.00% # number of callpals executed -system.cpu1.kern.callpal::rti 3410 3.75% 99.75% # number of callpals executed -system.cpu1.kern.callpal::callsys 189 0.21% 99.96% # number of callpals executed -system.cpu1.kern.callpal::imb 34 0.04% 100.00% # number of callpals executed +system.cpu1.kern.callpal::wripir 309 0.49% 0.49% # number of callpals executed +system.cpu1.kern.callpal::wrmces 1 0.00% 0.49% # number of callpals executed +system.cpu1.kern.callpal::wrfen 1 0.00% 0.49% # number of callpals executed +system.cpu1.kern.callpal::swpctx 1667 2.62% 3.12% # number of callpals executed +system.cpu1.kern.callpal::tbi 9 0.01% 3.13% # number of callpals executed +system.cpu1.kern.callpal::wrent 7 0.01% 3.14% # number of callpals executed +system.cpu1.kern.callpal::swpipl 55390 87.20% 90.34% # number of callpals executed +system.cpu1.kern.callpal::rdps 2392 3.77% 94.10% # number of callpals executed +system.cpu1.kern.callpal::wrkgp 1 0.00% 94.10% # number of callpals executed +system.cpu1.kern.callpal::wrusp 5 0.01% 94.11% # number of callpals executed +system.cpu1.kern.callpal::rdusp 1 0.00% 94.11% # number of callpals executed +system.cpu1.kern.callpal::whami 3 0.00% 94.12% # number of callpals executed +system.cpu1.kern.callpal::rti 3522 5.54% 99.66% # number of callpals executed +system.cpu1.kern.callpal::callsys 167 0.26% 99.92% # number of callpals executed +system.cpu1.kern.callpal::imb 47 0.07% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 90921 # number of callpals executed -system.cpu1.kern.mode_switch::kernel 2651 # number of protection mode switches -system.cpu1.kern.mode_switch::user 640 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2049 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 706 -system.cpu1.kern.mode_good::user 640 -system.cpu1.kern.mode_good::idle 66 -system.cpu1.kern.mode_switch_good::kernel 0.266315 # fraction of useful protection mode switches +system.cpu1.kern.callpal::total 63524 # number of callpals executed +system.cpu1.kern.mode_switch::kernel 1934 # number of protection mode switches +system.cpu1.kern.mode_switch::user 578 # number of protection mode switches +system.cpu1.kern.mode_switch::idle 2650 # number of protection mode switches +system.cpu1.kern.mode_good::kernel 909 +system.cpu1.kern.mode_good::user 578 +system.cpu1.kern.mode_good::idle 331 +system.cpu1.kern.mode_switch_good::kernel 0.470010 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.032211 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 1.298525 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 43748791000 2.30% 2.30% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 905692500 0.05% 2.35% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1853996893000 97.65% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 2024 # number of times the context was actually changed +system.cpu1.kern.mode_switch_good::idle 0.124906 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 1.594916 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 6826914500 0.36% 0.36% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 949063500 0.05% 0.41% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1889043105000 99.59% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 1668 # number of times the context was actually changed ---------- End Simulation Statistics ---------- diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini index be4d1c60b..496218c55 100644 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini @@ -10,13 +10,13 @@ type=LinuxAlphaSystem children=bridge cpu disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 -console=/chips/pd/randd/dist/binaries/console +console=/dist/m5/system/binaries/console init_param=0 -kernel=/chips/pd/randd/dist/binaries/vmlinux +kernel=/dist/m5/system/binaries/vmlinux load_addr_mask=1099511627775 mem_mode=timing memories=system.physmem -pal=/chips/pd/randd/dist/binaries/ts_osfpal +pal=/dist/m5/system/binaries/ts_osfpal physmem=system.physmem readfile=tests/halt.sh symbolfile= @@ -496,7 +496,7 @@ table_size=65536 [system.disk0.image.child] type=RawDiskImage -image_file=/chips/pd/randd/dist/disks/linux-latest.img +image_file=/dist/m5/system/disks/linux-latest.img read_only=true [system.disk2] @@ -516,7 +516,7 @@ table_size=65536 [system.disk2.image.child] type=RawDiskImage -image_file=/chips/pd/randd/dist/disks/linux-bigswap2.img +image_file=/dist/m5/system/disks/linux-bigswap2.img read_only=true [system.intrctrl] @@ -645,7 +645,7 @@ system=system [system.simple_disk.disk] type=RawDiskImage -image_file=/chips/pd/randd/dist/disks/linux-latest.img +image_file=/dist/m5/system/disks/linux-latest.img read_only=true [system.terminal] diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout index 9aa3b6fd7..df759602b 100755 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 8 2011 15:02:59 -gem5 started Jul 8 2011 18:21:28 -gem5 executing on u200439-lin.austin.arm.com +gem5 compiled Aug 9 2011 03:11:31 +gem5 started Aug 9 2011 03:11:36 +gem5 executing on burrito command line: build/ALPHA_FS/gem5.opt -d build/ALPHA_FS/tests/opt/long/10.linux-boot/alpha/linux/tsunami-o3 -re tests/run.py build/ALPHA_FS/tests/opt/long/10.linux-boot/alpha/linux/tsunami-o3 Global frequency set at 1000000000000 ticks per second -info: kernel located at: /chips/pd/randd/dist/binaries/vmlinux +info: kernel located at: /dist/m5/system/binaries/vmlinux 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 1860642398500 because m5_exit instruction encountered +Exiting @ tick 1858690543500 because m5_exit instruction encountered diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt index 3bf0e1e63..615b7b1c5 100644 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt @@ -1,94 +1,94 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.860642 # Number of seconds simulated -sim_ticks 1860642398500 # Number of ticks simulated +sim_seconds 1.858691 # Number of seconds simulated +sim_ticks 1858690543500 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 59629 # Simulator instruction rate (inst/s) -host_tick_rate 2089604255 # Simulator tick rate (ticks/s) -host_mem_usage 333232 # Number of bytes of host memory used -host_seconds 890.43 # Real time elapsed on the host -sim_insts 53094994 # Number of instructions simulated -system.l2c.replacements 391412 # number of replacements -system.l2c.tagsinuse 34941.270648 # Cycle average of tags in use -system.l2c.total_refs 2407591 # Total number of references to valid blocks. -system.l2c.sampled_refs 424295 # Sample count of references to valid blocks. -system.l2c.avg_refs 5.674333 # Average number of references to valid blocks. +host_inst_rate 131020 # Simulator instruction rate (inst/s) +host_tick_rate 4587017100 # Simulator tick rate (ticks/s) +host_mem_usage 315160 # Number of bytes of host memory used +host_seconds 405.21 # Real time elapsed on the host +sim_insts 53090369 # Number of instructions simulated +system.l2c.replacements 391395 # number of replacements +system.l2c.tagsinuse 34960.020004 # Cycle average of tags in use +system.l2c.total_refs 2406151 # Total number of references to valid blocks. +system.l2c.sampled_refs 424265 # Sample count of references to valid blocks. +system.l2c.avg_refs 5.671340 # Average number of references to valid blocks. system.l2c.warmup_cycle 5621019000 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::0 12366.621064 # Average occupied blocks per context -system.l2c.occ_blocks::1 22574.649583 # Average occupied blocks per context -system.l2c.occ_percent::0 0.188700 # Average percentage of cache occupancy -system.l2c.occ_percent::1 0.344462 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::0 1801894 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1801894 # number of ReadReq hits -system.l2c.Writeback_hits::0 835599 # number of Writeback hits -system.l2c.Writeback_hits::total 835599 # number of Writeback hits -system.l2c.UpgradeReq_hits::0 17 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 17 # number of UpgradeReq hits +system.l2c.occ_blocks::0 12378.384666 # Average occupied blocks per context +system.l2c.occ_blocks::1 22581.635338 # Average occupied blocks per context +system.l2c.occ_percent::0 0.188879 # Average percentage of cache occupancy +system.l2c.occ_percent::1 0.344568 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::0 1801346 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1801346 # number of ReadReq hits +system.l2c.Writeback_hits::0 835143 # number of Writeback hits +system.l2c.Writeback_hits::total 835143 # number of Writeback hits +system.l2c.UpgradeReq_hits::0 15 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 15 # number of UpgradeReq hits system.l2c.SCUpgradeReq_hits::0 2 # number of SCUpgradeReq hits system.l2c.SCUpgradeReq_hits::total 2 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::0 183225 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 183225 # number of ReadExReq hits -system.l2c.demand_hits::0 1985119 # number of demand (read+write) hits +system.l2c.ReadExReq_hits::0 183109 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 183109 # number of ReadExReq hits +system.l2c.demand_hits::0 1984455 # number of demand (read+write) hits system.l2c.demand_hits::1 0 # number of demand (read+write) hits -system.l2c.demand_hits::total 1985119 # number of demand (read+write) hits -system.l2c.overall_hits::0 1985119 # number of overall hits +system.l2c.demand_hits::total 1984455 # number of demand (read+write) hits +system.l2c.overall_hits::0 1984455 # number of overall hits system.l2c.overall_hits::1 0 # number of overall hits -system.l2c.overall_hits::total 1985119 # number of overall hits -system.l2c.ReadReq_misses::0 308127 # number of ReadReq misses -system.l2c.ReadReq_misses::total 308127 # number of ReadReq misses -system.l2c.UpgradeReq_misses::0 31 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 31 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::0 116938 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 116938 # number of ReadExReq misses -system.l2c.demand_misses::0 425065 # number of demand (read+write) misses +system.l2c.overall_hits::total 1984455 # number of overall hits +system.l2c.ReadReq_misses::0 308108 # number of ReadReq misses +system.l2c.ReadReq_misses::total 308108 # number of ReadReq misses +system.l2c.UpgradeReq_misses::0 34 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 34 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::0 116921 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 116921 # number of ReadExReq misses +system.l2c.demand_misses::0 425029 # number of demand (read+write) misses system.l2c.demand_misses::1 0 # number of demand (read+write) misses -system.l2c.demand_misses::total 425065 # number of demand (read+write) misses -system.l2c.overall_misses::0 425065 # number of overall misses +system.l2c.demand_misses::total 425029 # number of demand (read+write) misses +system.l2c.overall_misses::0 425029 # number of overall misses system.l2c.overall_misses::1 0 # number of overall misses -system.l2c.overall_misses::total 425065 # number of overall misses -system.l2c.ReadReq_miss_latency 16037568500 # number of ReadReq miss cycles +system.l2c.overall_misses::total 425029 # number of overall misses +system.l2c.ReadReq_miss_latency 16037313500 # number of ReadReq miss cycles system.l2c.UpgradeReq_miss_latency 372000 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency 6135692000 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency 22173260500 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency 22173260500 # number of overall miss cycles -system.l2c.ReadReq_accesses::0 2110021 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2110021 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::0 835599 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 835599 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::0 48 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 48 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_miss_latency 6133457500 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency 22170771000 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency 22170771000 # number of overall miss cycles +system.l2c.ReadReq_accesses::0 2109454 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2109454 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::0 835143 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 835143 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::0 49 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 49 # number of UpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::0 2 # number of SCUpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::0 300163 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 300163 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::0 2410184 # number of demand (read+write) accesses +system.l2c.ReadExReq_accesses::0 300030 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 300030 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::0 2409484 # number of demand (read+write) accesses system.l2c.demand_accesses::1 0 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2410184 # number of demand (read+write) accesses -system.l2c.overall_accesses::0 2410184 # number of overall (read+write) accesses +system.l2c.demand_accesses::total 2409484 # number of demand (read+write) accesses +system.l2c.overall_accesses::0 2409484 # number of overall (read+write) accesses system.l2c.overall_accesses::1 0 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2410184 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::0 0.146030 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::0 0.645833 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::0 0.389582 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::0 0.176362 # miss rate for demand accesses +system.l2c.overall_accesses::total 2409484 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::0 0.146061 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::0 0.693878 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::0 0.389698 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::0 0.176398 # miss rate for demand accesses system.l2c.demand_miss_rate::1 no_value # miss rate for demand accesses system.l2c.demand_miss_rate::total no_value # miss rate for demand accesses -system.l2c.overall_miss_rate::0 0.176362 # miss rate for overall accesses +system.l2c.overall_miss_rate::0 0.176398 # miss rate for overall accesses system.l2c.overall_miss_rate::1 no_value # miss rate for overall accesses system.l2c.overall_miss_rate::total no_value # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::0 52048.566013 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::0 52050.948044 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::0 12000 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::0 10941.176471 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::1 inf # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::0 52469.616378 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::0 52458.134125 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::1 inf # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::0 52164.399562 # average overall miss latency +system.l2c.demand_avg_miss_latency::0 52162.960645 # average overall miss latency system.l2c.demand_avg_miss_latency::1 inf # average overall miss latency system.l2c.demand_avg_miss_latency::total inf # average overall miss latency -system.l2c.overall_avg_miss_latency::0 52164.399562 # average overall miss latency +system.l2c.overall_avg_miss_latency::0 52162.960645 # average overall miss latency system.l2c.overall_avg_miss_latency::1 inf # average overall miss latency system.l2c.overall_avg_miss_latency::total inf # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked @@ -99,43 +99,43 @@ system.l2c.avg_blocked_cycles::no_mshrs no_value # av system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks 117788 # number of writebacks +system.l2c.writebacks 117784 # number of writebacks system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.l2c.overall_mshr_hits 0 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses 308127 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses 31 # number of UpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses 116938 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses 425065 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses 425065 # number of overall MSHR misses +system.l2c.ReadReq_mshr_misses 308108 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses 34 # number of UpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses 116921 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses 425029 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses 425029 # number of overall MSHR misses system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.l2c.ReadReq_mshr_miss_latency 12333883500 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency 1300000 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency 4713361500 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency 17047245000 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency 17047245000 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency 810033500 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency 1115471498 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency 1925504998 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::0 0.146030 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_latency 12333770000 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency 1420000 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency 4711661500 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency 17045431500 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency 17045431500 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency 810039500 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency 1115188998 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency 1925228498 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::0 0.146061 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::0 0.645833 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::0 0.693878 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::0 0.389582 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::0 0.389698 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::1 inf # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::0 0.176362 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::0 0.176398 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::0 0.176362 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::0 0.176398 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency 40028.571011 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency 41935.483871 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency 40306.500026 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency 40105.030995 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency 40105.030995 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency 40030.671063 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency 41764.705882 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency 40297.820751 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency 40104.161128 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency 40104.161128 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency @@ -143,13 +143,13 @@ system.l2c.mshr_cap_events 0 # nu system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 41685 # number of replacements -system.iocache.tagsinuse 1.282104 # Cycle average of tags in use +system.iocache.tagsinuse 1.266648 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. system.iocache.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 1708339230000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::1 1.282104 # Average occupied blocks per context -system.iocache.occ_percent::1 0.080132 # Average percentage of cache occupancy +system.iocache.warmup_cycle 1708339298000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::1 1.266648 # Average occupied blocks per context +system.iocache.occ_percent::1 0.079165 # Average percentage of cache occupancy system.iocache.demand_hits::0 0 # number of demand (read+write) hits system.iocache.demand_hits::1 0 # number of demand (read+write) hits system.iocache.demand_hits::total 0 # number of demand (read+write) hits @@ -166,10 +166,10 @@ system.iocache.demand_misses::total 41725 # nu system.iocache.overall_misses::0 0 # number of overall misses system.iocache.overall_misses::1 41725 # number of overall misses system.iocache.overall_misses::total 41725 # number of overall misses -system.iocache.ReadReq_miss_latency 19937998 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency 5723029806 # number of WriteReq miss cycles -system.iocache.demand_miss_latency 5742967804 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency 5742967804 # number of overall miss cycles +system.iocache.ReadReq_miss_latency 19939998 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency 5722104806 # number of WriteReq miss cycles +system.iocache.demand_miss_latency 5742044804 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency 5742044804 # number of overall miss cycles system.iocache.ReadReq_accesses::1 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::1 41552 # number of WriteReq accesses(hits+misses) @@ -189,22 +189,22 @@ system.iocache.overall_miss_rate::0 no_value # mi system.iocache.overall_miss_rate::1 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::0 inf # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::1 115248.543353 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::1 115260.104046 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::0 inf # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::1 137731.753129 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::1 137709.491866 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency system.iocache.demand_avg_miss_latency::0 inf # average overall miss latency -system.iocache.demand_avg_miss_latency::1 137638.533349 # average overall miss latency +system.iocache.demand_avg_miss_latency::1 137616.412319 # average overall miss latency system.iocache.demand_avg_miss_latency::total inf # average overall miss latency system.iocache.overall_avg_miss_latency::0 inf # average overall miss latency -system.iocache.overall_avg_miss_latency::1 137638.533349 # average overall miss latency +system.iocache.overall_avg_miss_latency::1 137616.412319 # average overall miss latency system.iocache.overall_avg_miss_latency::total inf # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 64649956 # number of cycles access was blocked +system.iocache.blocked_cycles::no_mshrs 64599068 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 10476 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 10462 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 6171.244368 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6174.638501 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -216,10 +216,10 @@ system.iocache.WriteReq_mshr_misses 41552 # nu system.iocache.demand_mshr_misses 41725 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses 41725 # number of overall MSHR misses system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.iocache.ReadReq_mshr_miss_latency 10941998 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency 3562178882 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency 3573120880 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency 3573120880 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency 10943998 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency 3561252994 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency 3572196992 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency 3572196992 # number of overall MSHR miss cycles system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_mshr_miss_rate::0 inf # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::1 1 # mshr miss rate for ReadReq accesses @@ -233,10 +233,10 @@ system.iocache.demand_mshr_miss_rate::total inf # system.iocache.overall_mshr_miss_rate::0 inf # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::1 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency 63248.543353 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency 85728.217222 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency 85635.012103 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency 85635.012103 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency 63260.104046 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency 85705.934588 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency 85612.869790 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency 85612.869790 # average overall mshr miss latency system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions @@ -257,22 +257,22 @@ system.cpu.dtb.fetch_hits 0 # IT system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 10181490 # DTB read hits -system.cpu.dtb.read_misses 43507 # DTB read misses -system.cpu.dtb.read_acv 584 # DTB read access violations -system.cpu.dtb.read_accesses 956517 # DTB read accesses -system.cpu.dtb.write_hits 6638592 # DTB write hits -system.cpu.dtb.write_misses 9235 # DTB write misses -system.cpu.dtb.write_acv 315 # DTB write access violations -system.cpu.dtb.write_accesses 335365 # DTB write accesses -system.cpu.dtb.data_hits 16820082 # DTB hits -system.cpu.dtb.data_misses 52742 # DTB misses -system.cpu.dtb.data_acv 899 # DTB access violations -system.cpu.dtb.data_accesses 1291882 # DTB accesses -system.cpu.itb.fetch_hits 1343321 # ITB hits -system.cpu.itb.fetch_misses 39871 # ITB misses -system.cpu.itb.fetch_acv 1097 # ITB acv -system.cpu.itb.fetch_accesses 1383192 # ITB accesses +system.cpu.dtb.read_hits 10172213 # DTB read hits +system.cpu.dtb.read_misses 43494 # DTB read misses +system.cpu.dtb.read_acv 580 # DTB read access violations +system.cpu.dtb.read_accesses 956567 # DTB read accesses +system.cpu.dtb.write_hits 6637652 # DTB write hits +system.cpu.dtb.write_misses 9272 # DTB write misses +system.cpu.dtb.write_acv 322 # DTB write access violations +system.cpu.dtb.write_accesses 335213 # DTB write accesses +system.cpu.dtb.data_hits 16809865 # DTB hits +system.cpu.dtb.data_misses 52766 # DTB misses +system.cpu.dtb.data_acv 902 # DTB access violations +system.cpu.dtb.data_accesses 1291780 # DTB accesses +system.cpu.itb.fetch_hits 1342789 # ITB hits +system.cpu.itb.fetch_misses 39758 # ITB misses +system.cpu.itb.fetch_acv 1040 # ITB acv +system.cpu.itb.fetch_accesses 1382547 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -285,275 +285,275 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 117574512 # number of cpu cycles simulated +system.cpu.numCycles 117561370 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 14520870 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 12129881 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 536127 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 13102888 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 6784816 # Number of BTB hits +system.cpu.BPredUnit.lookups 14512096 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 12124763 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 534985 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 13082442 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 6780681 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 988023 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 45439 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 29297731 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 74578036 # Number of instructions fetch has processed -system.cpu.fetch.Branches 14520870 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 7772839 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 14464966 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2480365 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 37381696 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 11813 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 262360 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 335674 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 148 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 9188867 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 332159 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 83395171 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.894273 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.211331 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 985415 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 44835 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 29301348 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 74523128 # Number of instructions fetch has processed +system.cpu.fetch.Branches 14512096 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 7766096 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 14456496 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2475230 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 37352483 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 32620 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 262284 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 336025 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 123 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 9183314 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 332127 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 83379045 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.893787 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.210786 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 68930205 82.65% 82.65% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1027253 1.23% 83.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2037570 2.44% 86.33% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 996261 1.19% 87.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2986489 3.58% 91.11% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 701042 0.84% 91.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 810374 0.97% 92.92% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1074366 1.29% 94.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 4831611 5.79% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 68922549 82.66% 82.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1028480 1.23% 83.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2035774 2.44% 86.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 998762 1.20% 87.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2982144 3.58% 91.11% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 700003 0.84% 91.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 807750 0.97% 92.92% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1076941 1.29% 94.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 4826642 5.79% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 83395171 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.123504 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.634304 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 30605129 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 36986989 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 13179583 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1024525 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1598944 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 618757 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 42149 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 72864512 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 127083 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1598944 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 31853597 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 12955306 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 19880213 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 12336598 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 4770511 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 68839007 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 4216 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 997134 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 1470879 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 46134135 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 83694616 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 83214897 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 479719 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 38263079 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 7871048 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1701317 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 251479 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12958659 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 10852157 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 7063465 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 2081084 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2219281 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 60395993 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2119342 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 58286883 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 83117 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 9015512 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 4849087 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1451479 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 83395171 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.698924 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.313462 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 83379045 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.123443 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.633908 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 30625799 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 36960246 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 13171913 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1025264 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1595822 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 618911 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 42154 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 72819380 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 127184 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1595822 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 31874108 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 12944384 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 19864625 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 12330385 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 4769719 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 68803114 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 4210 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 997602 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 1469982 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 46108022 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 83655268 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 83175686 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 479582 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 38259780 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 7848234 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1700711 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 251216 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12962201 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 10843547 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 7060604 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 2097425 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2214211 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 60377206 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2118999 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 58263583 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 82757 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 9009938 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 4851831 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1451256 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 83379045 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.698780 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.313076 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 56889866 68.22% 68.22% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 11980340 14.37% 82.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 5968113 7.16% 89.74% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 3572850 4.28% 94.02% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 2610876 3.13% 97.15% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 1337370 1.60% 98.76% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 787156 0.94% 99.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 190323 0.23% 99.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 58277 0.07% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 56881095 68.22% 68.22% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 11965083 14.35% 82.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 5985120 7.18% 89.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 3573465 4.29% 94.03% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 2606291 3.13% 97.16% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 1333403 1.60% 98.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 786052 0.94% 99.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 188914 0.23% 99.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 59622 0.07% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 83395171 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 83379045 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 67430 12.00% 12.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 12.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 12.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 12.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 12.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 12.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 12.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 12.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 12.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 12.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 12.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 12.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 12.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 12.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 12.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 12.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 12.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 12.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 12.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 12.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 12.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 12.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 12.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 12.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 12.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 12.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 12.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 12.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 12.00% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 313148 55.72% 67.72% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 181376 32.28% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 66647 11.94% 11.94% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 11.94% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 11.94% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.94% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.94% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.94% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 11.94% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.94% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.94% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.94% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.94% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.94% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.94% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.94% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.94% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 11.94% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.94% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 11.94% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.94% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.94% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.94% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.94% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.94% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.94% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.94% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.94% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.94% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.94% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.94% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 311938 55.88% 67.82% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 179673 32.18% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 7281 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 39850306 68.37% 68.38% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 63779 0.11% 68.49% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.49% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 25609 0.04% 68.54% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 39837502 68.37% 68.39% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 63640 0.11% 68.50% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.50% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 25605 0.04% 68.54% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.54% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.54% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.54% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.54% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.54% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 10660229 18.29% 86.83% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 6723519 11.54% 98.37% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 952524 1.63% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.55% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.55% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 10651640 18.28% 86.83% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 6721971 11.54% 98.37% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 952308 1.63% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 58286883 # Type of FU issued -system.cpu.iq.rate 0.495744 # Inst issue rate -system.cpu.iq.fu_busy_cnt 561954 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.009641 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 199927311 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 71222511 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 56715823 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 686696 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 334075 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 327925 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 58483404 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 358152 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 548522 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 58263583 # Type of FU issued +system.cpu.iq.rate 0.495601 # Inst issue rate +system.cpu.iq.fu_busy_cnt 558258 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.009582 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 199861715 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 71197744 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 56697880 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 685510 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 334104 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 327554 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 58457489 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 357071 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 546714 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1737768 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 13937 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 28744 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 670362 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1730283 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 13242 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 28963 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 668160 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 19001 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 170467 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 18982 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 168763 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1598944 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 9012018 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 624424 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 66178582 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 871819 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 10852157 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 7063465 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1871966 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 491038 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 13897 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 28744 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 390552 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 383693 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 774245 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 57578164 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 10255391 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 708718 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1595822 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 9001389 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 625458 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 66156357 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 866739 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 10843547 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 7060604 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1871783 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 491434 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 13753 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 28963 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 389249 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 383472 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 772721 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 57555020 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 10245935 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 708562 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 3663247 # number of nop insts executed -system.cpu.iew.exec_refs 16918441 # number of memory reference insts executed -system.cpu.iew.exec_branches 9135643 # Number of branches executed -system.cpu.iew.exec_stores 6663050 # Number of stores executed -system.cpu.iew.exec_rate 0.489716 # Inst execution rate -system.cpu.iew.wb_sent 57177610 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 57043748 # cumulative count of insts written-back -system.cpu.iew.wb_producers 28229071 # num instructions producing a value -system.cpu.iew.wb_consumers 38069273 # num instructions consuming a value +system.cpu.iew.exec_nop 3660152 # number of nop insts executed +system.cpu.iew.exec_refs 16908045 # number of memory reference insts executed +system.cpu.iew.exec_branches 9133755 # Number of branches executed +system.cpu.iew.exec_stores 6662110 # Number of stores executed +system.cpu.iew.exec_rate 0.489574 # Inst execution rate +system.cpu.iew.wb_sent 57159115 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 57025434 # cumulative count of insts written-back +system.cpu.iew.wb_producers 28218942 # num instructions producing a value +system.cpu.iew.wb_consumers 38051860 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.485171 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.741519 # average fanout of values written-back +system.cpu.iew.wb_rate 0.485069 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.741592 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 56289833 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 9752851 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 667863 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 705919 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 81796227 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.688172 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.561050 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 56284997 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 9746037 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 667743 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 704725 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 81783223 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.688222 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.561458 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 59880576 73.21% 73.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 9259582 11.32% 84.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 5272761 6.45% 90.97% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2451209 3.00% 93.97% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1681883 2.06% 96.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 629564 0.77% 96.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 461991 0.56% 97.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 785484 0.96% 98.32% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 1373177 1.68% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 59869495 73.21% 73.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 9271272 11.34% 84.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 5260342 6.43% 90.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2449132 2.99% 93.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1675900 2.05% 96.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 634046 0.78% 96.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 464374 0.57% 97.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 783725 0.96% 98.32% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 1374937 1.68% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 81796227 # Number of insts commited each cycle -system.cpu.commit.count 56289833 # Number of instructions committed +system.cpu.commit.committed_per_cycle::total 81783223 # Number of insts commited each cycle +system.cpu.commit.count 56284997 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 15507492 # Number of memory references committed -system.cpu.commit.loads 9114389 # Number of loads committed -system.cpu.commit.membars 227923 # Number of memory barriers committed -system.cpu.commit.branches 8462531 # Number of branches committed -system.cpu.commit.fp_insts 324451 # Number of committed floating point instructions. -system.cpu.commit.int_insts 52127847 # Number of committed integer instructions. -system.cpu.commit.function_calls 744622 # Number of function calls committed. -system.cpu.commit.bw_lim_events 1373177 # number cycles where commit BW limit reached +system.cpu.commit.refs 15505708 # Number of memory references committed +system.cpu.commit.loads 9113264 # Number of loads committed +system.cpu.commit.membars 227891 # Number of memory barriers committed +system.cpu.commit.branches 8461884 # Number of branches committed +system.cpu.commit.fp_insts 324250 # Number of committed floating point instructions. +system.cpu.commit.int_insts 52123418 # Number of committed integer instructions. +system.cpu.commit.function_calls 744517 # Number of function calls committed. +system.cpu.commit.bw_lim_events 1374937 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 146214633 # The number of ROB reads -system.cpu.rob.rob_writes 133687068 # The number of ROB writes -system.cpu.timesIdled 1253330 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 34179341 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 53094994 # Number of Instructions Simulated -system.cpu.committedInsts_total 53094994 # Number of Instructions Simulated -system.cpu.cpi 2.214418 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.214418 # CPI: Total CPI of All Threads -system.cpu.ipc 0.451586 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.451586 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 75460784 # number of integer regfile reads -system.cpu.int_regfile_writes 41231418 # number of integer regfile writes -system.cpu.fp_regfile_reads 165968 # number of floating regfile reads -system.cpu.fp_regfile_writes 167480 # number of floating regfile writes -system.cpu.misc_regfile_reads 1996655 # number of misc regfile reads -system.cpu.misc_regfile_writes 950059 # number of misc regfile writes +system.cpu.rob.rob_reads 146188247 # The number of ROB reads +system.cpu.rob.rob_writes 133660667 # The number of ROB writes +system.cpu.timesIdled 1252693 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 34182325 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 53090369 # Number of Instructions Simulated +system.cpu.committedInsts_total 53090369 # Number of Instructions Simulated +system.cpu.cpi 2.214363 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.214363 # CPI: Total CPI of All Threads +system.cpu.ipc 0.451597 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.451597 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 75435318 # number of integer regfile reads +system.cpu.int_regfile_writes 41215589 # number of integer regfile writes +system.cpu.fp_regfile_reads 165687 # number of floating regfile reads +system.cpu.fp_regfile_writes 167399 # number of floating regfile writes +system.cpu.misc_regfile_reads 1995946 # number of misc regfile reads +system.cpu.misc_regfile_writes 949866 # number of misc regfile writes system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -585,231 +585,231 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal no_value # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.cpu.icache.replacements 1005236 # number of replacements -system.cpu.icache.tagsinuse 509.950687 # Cycle average of tags in use -system.cpu.icache.total_refs 8124069 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1005745 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 8.077663 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 23367185000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 509.950687 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.995997 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::0 8124070 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 8124070 # number of ReadReq hits -system.cpu.icache.demand_hits::0 8124070 # number of demand (read+write) hits +system.cpu.icache.replacements 1005223 # number of replacements +system.cpu.icache.tagsinuse 509.948854 # Cycle average of tags in use +system.cpu.icache.total_refs 8118172 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 1005732 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 8.071904 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 23367175000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::0 509.948854 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.995994 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::0 8118173 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 8118173 # number of ReadReq hits +system.cpu.icache.demand_hits::0 8118173 # number of demand (read+write) hits system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 8124070 # number of demand (read+write) hits -system.cpu.icache.overall_hits::0 8124070 # number of overall hits +system.cpu.icache.demand_hits::total 8118173 # number of demand (read+write) hits +system.cpu.icache.overall_hits::0 8118173 # number of overall hits system.cpu.icache.overall_hits::1 0 # number of overall hits -system.cpu.icache.overall_hits::total 8124070 # number of overall hits -system.cpu.icache.ReadReq_misses::0 1064797 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1064797 # number of ReadReq misses -system.cpu.icache.demand_misses::0 1064797 # number of demand (read+write) misses +system.cpu.icache.overall_hits::total 8118173 # number of overall hits +system.cpu.icache.ReadReq_misses::0 1065140 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1065140 # number of ReadReq misses +system.cpu.icache.demand_misses::0 1065140 # number of demand (read+write) misses system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1064797 # number of demand (read+write) misses -system.cpu.icache.overall_misses::0 1064797 # number of overall misses +system.cpu.icache.demand_misses::total 1065140 # number of demand (read+write) misses +system.cpu.icache.overall_misses::0 1065140 # number of overall misses system.cpu.icache.overall_misses::1 0 # number of overall misses -system.cpu.icache.overall_misses::total 1064797 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 15924471495 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 15924471495 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 15924471495 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::0 9188867 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 9188867 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::0 9188867 # number of demand (read+write) accesses +system.cpu.icache.overall_misses::total 1065140 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 15927800996 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 15927800996 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 15927800996 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::0 9183313 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 9183313 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::0 9183313 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 9188867 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::0 9188867 # number of overall (read+write) accesses +system.cpu.icache.demand_accesses::total 9183313 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::0 9183313 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 9188867 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::0 0.115879 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::0 0.115879 # miss rate for demand accesses +system.cpu.icache.overall_accesses::total 9183313 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::0 0.115986 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::0 0.115986 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::0 0.115879 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::0 0.115986 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::0 14955.406049 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::0 14953.715940 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::0 14955.406049 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::0 14953.715940 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu.icache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::0 14955.406049 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::0 14953.715940 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 1315997 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_mshrs 1340497 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 122 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 10786.860656 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 10987.680328 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 236 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 58840 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 58840 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 58840 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 1005957 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 1005957 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 1005957 # number of overall MSHR misses +system.cpu.icache.writebacks 231 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits 59195 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 59195 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 59195 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 1005945 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 1005945 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 1005945 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 12050949497 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 12050949497 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 12050949497 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 12050423497 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 12050423497 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 12050423497 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::0 0.109476 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::0 0.109541 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::0 0.109476 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::0 0.109541 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::0 0.109476 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::0 0.109541 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 11979.587097 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 11979.587097 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 11979.587097 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 11979.207111 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 11979.207111 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 11979.207111 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1403927 # number of replacements -system.cpu.dcache.tagsinuse 511.995946 # Cycle average of tags in use -system.cpu.dcache.total_refs 12182577 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1404439 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 8.674337 # Average number of references to valid blocks. +system.cpu.dcache.replacements 1403249 # number of replacements +system.cpu.dcache.tagsinuse 511.995942 # Cycle average of tags in use +system.cpu.dcache.total_refs 12177929 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1403761 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 8.675215 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 19464000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 511.995946 # Average occupied blocks per context +system.cpu.dcache.occ_blocks::0 511.995942 # Average occupied blocks per context system.cpu.dcache.occ_percent::0 0.999992 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::0 7545727 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7545727 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::0 4224455 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4224455 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::0 192092 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 192092 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::0 220106 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 220106 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::0 11770182 # number of demand (read+write) hits +system.cpu.dcache.ReadReq_hits::0 7541924 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7541924 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::0 4223581 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4223581 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::0 192169 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 192169 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::0 220074 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 220074 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::0 11765505 # number of demand (read+write) hits system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 11770182 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::0 11770182 # number of overall hits +system.cpu.dcache.demand_hits::total 11765505 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::0 11765505 # number of overall hits system.cpu.dcache.overall_hits::1 0 # number of overall hits -system.cpu.dcache.overall_hits::total 11770182 # number of overall hits -system.cpu.dcache.ReadReq_misses::0 1787142 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1787142 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::0 1933396 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1933396 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::0 23327 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 23327 # number of LoadLockedReq misses +system.cpu.dcache.overall_hits::total 11765505 # number of overall hits +system.cpu.dcache.ReadReq_misses::0 1785380 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1785380 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::0 1933647 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1933647 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::0 23245 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 23245 # number of LoadLockedReq misses system.cpu.dcache.StoreCondReq_misses::0 2 # number of StoreCondReq misses system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::0 3720538 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::0 3719027 # number of demand (read+write) misses system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3720538 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::0 3720538 # number of overall misses +system.cpu.dcache.demand_misses::total 3719027 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::0 3719027 # number of overall misses system.cpu.dcache.overall_misses::1 0 # number of overall misses -system.cpu.dcache.overall_misses::total 3720538 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 38546414500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 57324684255 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency 362132500 # number of LoadLockedReq miss cycles +system.cpu.dcache.overall_misses::total 3719027 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 38531981000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 57348648047 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency 361113000 # number of LoadLockedReq miss cycles system.cpu.dcache.StoreCondReq_miss_latency 28500 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency 95871098755 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 95871098755 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::0 9332869 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 9332869 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::0 6157851 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6157851 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::0 215419 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 215419 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::0 220108 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 220108 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::0 15490720 # number of demand (read+write) accesses +system.cpu.dcache.demand_miss_latency 95880629047 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 95880629047 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::0 9327304 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 9327304 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::0 6157228 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6157228 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::0 215414 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 215414 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::0 220076 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 220076 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::0 15484532 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 15490720 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::0 15490720 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::total 15484532 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::0 15484532 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15490720 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::0 0.191489 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::0 0.313973 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::0 0.108287 # miss rate for LoadLockedReq accesses +system.cpu.dcache.overall_accesses::total 15484532 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::0 0.191414 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::0 0.314045 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::0 0.107908 # miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_miss_rate::0 0.000009 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::0 0.240179 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::0 0.240177 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::0 0.240179 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::0 0.240177 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::0 21568.747475 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::0 21581.949501 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::0 29649.737692 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::0 29658.282017 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 15524.177991 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 15535.082814 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::0 14250 # average StoreCondReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::0 25768.074068 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::0 25781.105931 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::0 25768.074068 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::0 25781.105931 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 901455332 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 264000 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 100284 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 904772827 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 266500 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 99710 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 12 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 8989.024490 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 22000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 9074.042995 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 22208.333333 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 835363 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 699045 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 1634457 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits 5750 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits 2333502 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 2333502 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 1088097 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 298939 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses 17577 # number of LoadLockedReq MSHR misses +system.cpu.dcache.writebacks 834912 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 697810 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 1634824 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits 5710 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits 2332634 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 2332634 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 1087570 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 298823 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses 17535 # number of LoadLockedReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses 2 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses 1387036 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 1387036 # number of overall MSHR misses +system.cpu.dcache.demand_mshr_misses 1386393 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 1386393 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 24799761000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 8488468332 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency 207628000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 24793495000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 8488664327 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency 207086500 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.StoreCondReq_mshr_miss_latency 22000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 33288229332 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 33288229332 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency 904499500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1234765498 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 2139264998 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.116588 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_miss_latency 33282159327 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 33282159327 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency 904509000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1234461998 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency 2138970998 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.116601 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.048546 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.048532 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.081594 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.081401 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::0 0.000009 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::0 0.089540 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::0 0.089534 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::0 0.089540 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::0 0.089534 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22791.865983 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 28395.319219 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11812.482221 # average LoadLockedReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22797.148689 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 28406.997878 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11809.894497 # average LoadLockedReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency 11000 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 23999.542429 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 23999.542429 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 24006.294988 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 24006.294988 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency @@ -817,27 +817,27 @@ system.cpu.dcache.mshr_cap_events 0 # nu system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 6436 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 211631 # number of hwrei instructions executed -system.cpu.kern.ipl_count::0 74888 40.95% 40.95% # number of times we switched to this ipl -system.cpu.kern.ipl_count::21 243 0.13% 41.09% # number of times we switched to this ipl -system.cpu.kern.ipl_count::22 1884 1.03% 42.12% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 105841 57.88% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 182856 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73521 49.29% 49.29% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::21 243 0.16% 49.45% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::22 1884 1.26% 50.71% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73524 49.29% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 149172 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1821901267000 97.92% 97.92% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 94071500 0.01% 97.92% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 385060500 0.02% 97.94% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 38261139000 2.06% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1860641538000 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981746 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.inst.quiesce 6434 # number of quiesce instructions executed +system.cpu.kern.inst.hwrei 211584 # number of hwrei instructions executed +system.cpu.kern.ipl_count::0 74877 40.96% 40.96% # number of times we switched to this ipl +system.cpu.kern.ipl_count::21 244 0.13% 41.09% # number of times we switched to this ipl +system.cpu.kern.ipl_count::22 1882 1.03% 42.12% # number of times we switched to this ipl +system.cpu.kern.ipl_count::31 105811 57.88% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 182814 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73510 49.29% 49.29% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::21 244 0.16% 49.45% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::22 1882 1.26% 50.71% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::31 73514 49.29% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 149150 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1819958547500 97.92% 97.92% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 94089500 0.01% 97.92% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 384592500 0.02% 97.94% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 38252453500 2.06% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1858689683000 # number of cycles we spent at this ipl +system.cpu.kern.ipl_used::0 0.981743 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.694665 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.694767 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -873,32 +873,32 @@ system.cpu.kern.callpal::cserve 1 0.00% 0.00% # nu system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal::swpctx 4177 2.17% 2.17% # number of callpals executed +system.cpu.kern.callpal::swpctx 4174 2.17% 2.17% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed -system.cpu.kern.callpal::swpipl 175513 91.19% 93.39% # number of callpals executed -system.cpu.kern.callpal::rdps 6789 3.53% 96.92% # number of callpals executed +system.cpu.kern.callpal::swpipl 175475 91.19% 93.39% # number of callpals executed +system.cpu.kern.callpal::rdps 6787 3.53% 96.92% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.92% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.92% # number of callpals executed system.cpu.kern.callpal::rdusp 9 0.00% 96.93% # number of callpals executed system.cpu.kern.callpal::whami 2 0.00% 96.93% # number of callpals executed -system.cpu.kern.callpal::rti 5218 2.71% 99.64% # number of callpals executed +system.cpu.kern.callpal::rti 5216 2.71% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 192477 # number of callpals executed +system.cpu.kern.callpal::total 192432 # number of callpals executed system.cpu.kern.mode_switch::kernel 5955 # number of protection mode switches system.cpu.kern.mode_switch::user 1737 # number of protection mode switches -system.cpu.kern.mode_switch::idle 2106 # number of protection mode switches -system.cpu.kern.mode_good::kernel 1907 +system.cpu.kern.mode_switch::idle 2101 # number of protection mode switches +system.cpu.kern.mode_good::kernel 1906 system.cpu.kern.mode_good::user 1737 -system.cpu.kern.mode_good::idle 170 -system.cpu.kern.mode_switch_good::kernel 0.320235 # fraction of useful protection mode switches +system.cpu.kern.mode_good::idle 169 +system.cpu.kern.mode_switch_good::kernel 0.320067 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::idle 0.080722 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 1.400957 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 29480216500 1.58% 1.58% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 2869428500 0.15% 1.74% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1828291885000 98.26% 100.00% # number of ticks spent at the given mode -system.cpu.kern.swap_context 4178 # number of times the context was actually changed +system.cpu.kern.mode_switch_good::idle 0.080438 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::total 1.400505 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 29488985500 1.59% 1.59% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 2865820500 0.15% 1.74% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1826334869000 98.26% 100.00% # number of ticks spent at the given mode +system.cpu.kern.swap_context 4175 # number of times the context was actually changed ---------- End Simulation Statistics ---------- diff --git a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/simout b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/simout index ca8b2388d..707979289 100755 --- a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/simout +++ b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/simout @@ -1,11 +1,11 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 7 2011 09:26:50 -gem5 started Aug 7 2011 09:26:59 +gem5 compiled Aug 9 2011 03:11:31 +gem5 started Aug 9 2011 03:11:37 gem5 executing on burrito command line: build/ARM_FS/gem5.opt -d build/ARM_FS/tests/opt/long/10.linux-boot/arm/linux/realview-o3 -re tests/run.py build/ARM_FS/tests/opt/long/10.linux-boot/arm/linux/realview-o3 Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/vmlinux.arm info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 80737865500 because m5_exit instruction encountered +Exiting @ tick 80748998500 because m5_exit instruction encountered diff --git a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/stats.txt b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/stats.txt index 784e14cb5..d56f088ea 100644 --- a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/stats.txt +++ b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/stats.txt @@ -1,97 +1,97 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.080738 # Number of seconds simulated -sim_ticks 80737865500 # Number of ticks simulated +sim_seconds 0.080749 # Number of seconds simulated +sim_ticks 80748998500 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 39525 # Simulator instruction rate (inst/s) -host_tick_rate 61513284 # Simulator tick rate (ticks/s) -host_mem_usage 368852 # Number of bytes of host memory used -host_seconds 1312.53 # Real time elapsed on the host -sim_insts 51877265 # Number of instructions simulated -system.l2c.replacements 94990 # number of replacements -system.l2c.tagsinuse 38163.791653 # Cycle average of tags in use -system.l2c.total_refs 1058289 # Total number of references to valid blocks. -system.l2c.sampled_refs 127415 # Sample count of references to valid blocks. -system.l2c.avg_refs 8.305843 # Average number of references to valid blocks. +host_inst_rate 110010 # Simulator instruction rate (inst/s) +host_tick_rate 171236576 # Simulator tick rate (ticks/s) +host_mem_usage 368976 # Number of bytes of host memory used +host_seconds 471.56 # Real time elapsed on the host +sim_insts 51876948 # Number of instructions simulated +system.l2c.replacements 94981 # number of replacements +system.l2c.tagsinuse 38166.685860 # Cycle average of tags in use +system.l2c.total_refs 1060946 # Total number of references to valid blocks. +system.l2c.sampled_refs 127430 # Sample count of references to valid blocks. +system.l2c.avg_refs 8.325716 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::0 6719.704145 # Average occupied blocks per context -system.l2c.occ_blocks::1 31444.087508 # Average occupied blocks per context -system.l2c.occ_percent::0 0.102535 # Average percentage of cache occupancy -system.l2c.occ_percent::1 0.479799 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::0 746044 # number of ReadReq hits -system.l2c.ReadReq_hits::1 122406 # number of ReadReq hits -system.l2c.ReadReq_hits::total 868450 # number of ReadReq hits -system.l2c.Writeback_hits::0 435356 # number of Writeback hits -system.l2c.Writeback_hits::total 435356 # number of Writeback hits -system.l2c.UpgradeReq_hits::0 23 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 23 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::0 60912 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 60912 # number of ReadExReq hits -system.l2c.demand_hits::0 806956 # number of demand (read+write) hits -system.l2c.demand_hits::1 122406 # number of demand (read+write) hits -system.l2c.demand_hits::total 929362 # number of demand (read+write) hits -system.l2c.overall_hits::0 806956 # number of overall hits -system.l2c.overall_hits::1 122406 # number of overall hits -system.l2c.overall_hits::total 929362 # number of overall hits -system.l2c.ReadReq_misses::0 21087 # number of ReadReq misses -system.l2c.ReadReq_misses::1 100 # number of ReadReq misses -system.l2c.ReadReq_misses::total 21187 # number of ReadReq misses -system.l2c.UpgradeReq_misses::0 1678 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 1678 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::0 107779 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 107779 # number of ReadExReq misses -system.l2c.demand_misses::0 128866 # number of demand (read+write) misses -system.l2c.demand_misses::1 100 # number of demand (read+write) misses -system.l2c.demand_misses::total 128966 # number of demand (read+write) misses -system.l2c.overall_misses::0 128866 # number of overall misses -system.l2c.overall_misses::1 100 # number of overall misses -system.l2c.overall_misses::total 128966 # number of overall misses -system.l2c.ReadReq_miss_latency 1107503500 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency 728500 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency 5653158500 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency 6760662000 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency 6760662000 # number of overall miss cycles -system.l2c.ReadReq_accesses::0 767131 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::1 122506 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 889637 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::0 435356 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 435356 # number of Writeback accesses(hits+misses) +system.l2c.occ_blocks::0 6723.855274 # Average occupied blocks per context +system.l2c.occ_blocks::1 31442.830586 # Average occupied blocks per context +system.l2c.occ_percent::0 0.102598 # Average percentage of cache occupancy +system.l2c.occ_percent::1 0.479780 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::0 746399 # number of ReadReq hits +system.l2c.ReadReq_hits::1 123135 # number of ReadReq hits +system.l2c.ReadReq_hits::total 869534 # number of ReadReq hits +system.l2c.Writeback_hits::0 435298 # number of Writeback hits +system.l2c.Writeback_hits::total 435298 # number of Writeback hits +system.l2c.UpgradeReq_hits::0 24 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 24 # number of UpgradeReq hits +system.l2c.ReadExReq_hits::0 60890 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 60890 # number of ReadExReq hits +system.l2c.demand_hits::0 807289 # number of demand (read+write) hits +system.l2c.demand_hits::1 123135 # number of demand (read+write) hits +system.l2c.demand_hits::total 930424 # number of demand (read+write) hits +system.l2c.overall_hits::0 807289 # number of overall hits +system.l2c.overall_hits::1 123135 # number of overall hits +system.l2c.overall_hits::total 930424 # number of overall hits +system.l2c.ReadReq_misses::0 21130 # number of ReadReq misses +system.l2c.ReadReq_misses::1 101 # number of ReadReq misses +system.l2c.ReadReq_misses::total 21231 # number of ReadReq misses +system.l2c.UpgradeReq_misses::0 1677 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 1677 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::0 107756 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 107756 # number of ReadExReq misses +system.l2c.demand_misses::0 128886 # number of demand (read+write) misses +system.l2c.demand_misses::1 101 # number of demand (read+write) misses +system.l2c.demand_misses::total 128987 # number of demand (read+write) misses +system.l2c.overall_misses::0 128886 # number of overall misses +system.l2c.overall_misses::1 101 # number of overall misses +system.l2c.overall_misses::total 128987 # number of overall misses +system.l2c.ReadReq_miss_latency 1109806000 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency 780500 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency 5651942000 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency 6761748000 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency 6761748000 # number of overall miss cycles +system.l2c.ReadReq_accesses::0 767529 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::1 123236 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 890765 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::0 435298 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 435298 # number of Writeback accesses(hits+misses) system.l2c.UpgradeReq_accesses::0 1701 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::total 1701 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::0 168691 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 168691 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::0 935822 # number of demand (read+write) accesses -system.l2c.demand_accesses::1 122506 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 1058328 # number of demand (read+write) accesses -system.l2c.overall_accesses::0 935822 # number of overall (read+write) accesses -system.l2c.overall_accesses::1 122506 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 1058328 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::0 0.027488 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::1 0.000816 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.028304 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::0 0.986479 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::0 0.638914 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::0 0.137704 # miss rate for demand accesses -system.l2c.demand_miss_rate::1 0.000816 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.138520 # miss rate for demand accesses -system.l2c.overall_miss_rate::0 0.137704 # miss rate for overall accesses -system.l2c.overall_miss_rate::1 0.000816 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.138520 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::0 52520.676246 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::1 11075035 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 11127555.676246 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::0 434.147795 # average UpgradeReq miss latency +system.l2c.ReadExReq_accesses::0 168646 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 168646 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::0 936175 # number of demand (read+write) accesses +system.l2c.demand_accesses::1 123236 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 1059411 # number of demand (read+write) accesses +system.l2c.overall_accesses::0 936175 # number of overall (read+write) accesses +system.l2c.overall_accesses::1 123236 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 1059411 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::0 0.027530 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::1 0.000820 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.028349 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::0 0.985891 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::0 0.638948 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::0 0.137673 # miss rate for demand accesses +system.l2c.demand_miss_rate::1 0.000820 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.138493 # miss rate for demand accesses +system.l2c.overall_miss_rate::0 0.137673 # miss rate for overall accesses +system.l2c.overall_miss_rate::1 0.000820 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.138493 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::0 52522.763843 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::1 10988178.217822 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 11040700.981665 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::0 465.414431 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::1 inf # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::0 52451.391273 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::0 52451.297376 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::1 inf # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::0 52462.728726 # average overall miss latency -system.l2c.demand_avg_miss_latency::1 67606620 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 67659082.728726 # average overall miss latency -system.l2c.overall_avg_miss_latency::0 52462.728726 # average overall miss latency -system.l2c.overall_avg_miss_latency::1 67606620 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 67659082.728726 # average overall miss latency +system.l2c.demand_avg_miss_latency::0 52463.013826 # average overall miss latency +system.l2c.demand_avg_miss_latency::1 66948000 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 67000463.013826 # average overall miss latency +system.l2c.overall_avg_miss_latency::0 52463.013826 # average overall miss latency +system.l2c.overall_avg_miss_latency::1 66948000 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 67000463.013826 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -100,44 +100,44 @@ system.l2c.avg_blocked_cycles::no_mshrs no_value # av system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks 87808 # number of writebacks +system.l2c.writebacks 87796 # number of writebacks system.l2c.ReadReq_mshr_hits 58 # number of ReadReq MSHR hits system.l2c.demand_mshr_hits 58 # number of demand (read+write) MSHR hits system.l2c.overall_mshr_hits 58 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses 21129 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses 1678 # number of UpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses 107779 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses 128908 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses 128908 # number of overall MSHR misses +system.l2c.ReadReq_mshr_misses 21173 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses 1677 # number of UpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses 107756 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses 128929 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses 128929 # number of overall MSHR misses system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.l2c.ReadReq_mshr_miss_latency 846277000 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency 67121500 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency 4312433500 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency 5158710500 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency 5158710500 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency 28946618500 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency 748700947 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency 29695319447 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::0 0.027543 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::1 0.172473 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.200016 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::0 0.986479 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadReq_mshr_miss_latency 848032500 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency 67081500 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency 4311568500 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency 5159601000 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency 5159601000 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency 28946618000 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency 748818447 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency 29695436447 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::0 0.027586 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::1 0.171809 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.199394 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::0 0.985891 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::0 0.638914 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::0 0.638948 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::1 inf # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::0 0.137748 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::1 1.052259 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 1.190007 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::0 0.137748 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::1 1.052259 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 1.190007 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency 40052.865730 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency 40000.893921 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency 40011.815845 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency 40018.544233 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency 40018.544233 # average overall mshr miss latency +system.l2c.demand_mshr_miss_rate::0 0.137719 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::1 1.046196 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 1.183915 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::0 0.137719 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::1 1.046196 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 1.183915 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency 40052.543333 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency 40000.894454 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency 40012.328780 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency 40018.932901 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency 40018.932901 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency @@ -146,27 +146,27 @@ system.l2c.soft_prefetch_mshr_full 0 # nu system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 28173336 # DTB read hits -system.cpu.dtb.read_misses 72357 # DTB read misses -system.cpu.dtb.write_hits 7689868 # DTB write hits -system.cpu.dtb.write_misses 13508 # DTB write misses +system.cpu.dtb.read_hits 28177040 # DTB read hits +system.cpu.dtb.read_misses 72386 # DTB read misses +system.cpu.dtb.write_hits 7691310 # DTB write hits +system.cpu.dtb.write_misses 13556 # DTB write misses system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 33678 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 40 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 2893 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 4130 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 1099 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 2922 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 4054 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 1092 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 947 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 28245693 # DTB read accesses -system.cpu.dtb.write_accesses 7703376 # DTB write accesses +system.cpu.dtb.perms_faults 940 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 28249426 # DTB read accesses +system.cpu.dtb.write_accesses 7704866 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 35863204 # DTB hits -system.cpu.dtb.misses 85865 # DTB misses -system.cpu.dtb.accesses 35949069 # DTB accesses -system.cpu.itb.inst_hits 7353914 # ITB inst hits -system.cpu.itb.inst_misses 7640 # ITB inst misses +system.cpu.dtb.hits 35868350 # DTB hits +system.cpu.dtb.misses 85942 # DTB misses +system.cpu.dtb.accesses 35954292 # DTB accesses +system.cpu.itb.inst_hits 7355634 # ITB inst hits +system.cpu.itb.inst_misses 7654 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -175,121 +175,121 @@ system.cpu.itb.flush_tlb 2 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 33678 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 40 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 1653 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 1641 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 4537 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 4616 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 7361554 # ITB inst accesses -system.cpu.itb.hits 7353914 # DTB hits -system.cpu.itb.misses 7640 # DTB misses -system.cpu.itb.accesses 7361554 # DTB accesses -system.cpu.numCycles 161475732 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 7363288 # ITB inst accesses +system.cpu.itb.hits 7355634 # DTB hits +system.cpu.itb.misses 7654 # DTB misses +system.cpu.itb.accesses 7363288 # DTB accesses +system.cpu.numCycles 161497998 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 13591178 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 11457422 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 648522 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 12128132 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 9358408 # Number of BTB hits +system.cpu.BPredUnit.lookups 13590326 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 11456360 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 648707 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 12127952 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 9362916 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 895734 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 148980 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 16857885 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 67476093 # Number of instructions fetch has processed -system.cpu.fetch.Branches 13591178 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 10254142 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 17027869 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 4121673 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 92046 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 55386928 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 18221 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 89652 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 207 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 7348854 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 337711 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 4423 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 92501381 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.899926 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.157722 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 895596 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 148738 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 16866017 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 67484906 # Number of instructions fetch has processed +system.cpu.fetch.Branches 13590326 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 10258512 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 17034266 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 4123173 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 93207 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 55393473 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 18245 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 90602 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 223 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 7350509 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 337942 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 4453 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 92525962 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.899758 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.157294 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 75492420 81.61% 81.61% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1419002 1.53% 83.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1862378 2.01% 85.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1400658 1.51% 86.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 4890175 5.29% 91.96% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 936188 1.01% 92.97% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 816395 0.88% 93.86% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 714688 0.77% 94.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 4969477 5.37% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 75510639 81.61% 81.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1420262 1.53% 83.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1864587 2.02% 85.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1402898 1.52% 86.68% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 4892259 5.29% 91.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 936046 1.01% 92.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 818442 0.88% 93.86% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 713663 0.77% 94.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 4967166 5.37% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 92501381 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.084169 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.417871 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 18958860 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 54056295 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 15357354 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1172463 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 2956409 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 1326398 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 73852 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 80374481 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 240410 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 2956409 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 20599609 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 33473612 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 16533693 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 13871976 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 5066082 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 77012867 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 458143 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 143852 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 2656312 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 95 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 79085152 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 335784610 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 335718375 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 66235 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 51887619 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 27197532 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 847968 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 665693 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 14024127 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 13553811 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 9176054 # Number of stores inserted to the mem dependence unit. +system.cpu.fetch.rateDist::total 92525962 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.084152 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.417868 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 18966191 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 54065669 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 15364429 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1171991 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 2957682 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 1326698 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 73964 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 80385244 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 241077 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 2957682 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 20606631 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 33478689 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 16542065 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 13879452 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 5061443 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 77021348 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 458130 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 143873 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 2652425 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 147 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 79088993 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 335825078 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 335758422 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 66656 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 51887194 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 27201798 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 847863 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 665654 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 14013888 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 13554810 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 9178167 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 336 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 727 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 69112553 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 4041097 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 82084831 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 240436 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 20591364 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 41997995 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1078252 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 92501381 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.887390 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.470670 # Number of insts issued each cycle +system.cpu.iq.iqInstsAdded 69117949 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 4041398 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 82091279 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 240337 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 20597655 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 41996969 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1078579 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 92525962 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.887224 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.470662 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 58092899 62.80% 62.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 14059432 15.20% 78.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 6650253 7.19% 85.19% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 4536722 4.90% 90.10% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 6374682 6.89% 96.99% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 1627400 1.76% 98.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 756790 0.82% 99.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 287365 0.31% 99.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 115838 0.13% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 58116859 62.81% 62.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 14058568 15.19% 78.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 6650411 7.19% 85.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 4537690 4.90% 90.10% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 6374184 6.89% 96.99% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 1626800 1.76% 98.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 758213 0.82% 99.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 287091 0.31% 99.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 116146 0.13% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 92501381 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 92525962 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 27880 0.57% 0.57% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 2 0.00% 0.57% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 27856 0.57% 0.57% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 1 0.00% 0.57% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 0.57% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.57% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.57% # attempts to use FU when none available @@ -317,360 +317,360 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.57% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.57% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.57% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.57% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 4534214 92.60% 93.17% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 334260 6.83% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 4535089 92.61% 93.18% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 334124 6.82% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2393223 2.92% 2.92% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 42161035 51.36% 54.28% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 71794 0.09% 54.37% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 54.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 54.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 54.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 54.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 54.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 54.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 54.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 54.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 54.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 54.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 54.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 54.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 20 0.00% 54.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 54.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 54.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 54.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 16 0.00% 54.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 54.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 54.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 54.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 54.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 54.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 54.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 886 0.00% 54.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 54.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 16 0.00% 54.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 54.37% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 29245049 35.63% 89.99% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 8212792 10.01% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 42162127 51.36% 54.28% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 71788 0.09% 54.36% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 54.36% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 54.36% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 54.36% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 54.36% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 54.36% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 54.36% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 54.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 54.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 54.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 54.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 54.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 54.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 14 0.00% 54.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 54.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 54.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 54.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 13 0.00% 54.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 54.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 54.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 54.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 54.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 54.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 54.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 883 0.00% 54.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 54.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 13 0.00% 54.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 54.36% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 29248881 35.63% 89.99% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 8214337 10.01% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 82084831 # Type of FU issued -system.cpu.iq.rate 0.508342 # Inst issue rate -system.cpu.iq.fu_busy_cnt 4896356 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.059650 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 261876505 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 94085418 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 62678710 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 16660 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 9610 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 6498 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 84579214 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 8750 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 426405 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 82091279 # Type of FU issued +system.cpu.iq.rate 0.508311 # Inst issue rate +system.cpu.iq.fu_busy_cnt 4897070 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.059654 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 261914662 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 94097771 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 62682872 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 16678 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 9625 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 6496 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 84586375 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 8751 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 425783 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 4374283 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 13506 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 404883 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2098607 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 4375336 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 13490 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 405193 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2100755 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 17025185 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 9489 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 17024856 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 9533 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 2956409 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 21375540 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 254618 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 73323080 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 354650 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 13553811 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 9176054 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 4009524 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 13227 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 41701 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 404883 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 534659 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 173860 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 708519 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 80709483 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 28679216 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1375348 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 2957682 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 21379595 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 254604 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 73328942 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 354348 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 13554810 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 9178167 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 4009809 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 13226 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 41705 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 405193 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 534373 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 174123 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 708496 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 80713996 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 28682342 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1377283 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 169430 # number of nop insts executed -system.cpu.iew.exec_refs 36683219 # number of memory reference insts executed -system.cpu.iew.exec_branches 10550397 # Number of branches executed -system.cpu.iew.exec_stores 8004003 # Number of stores executed -system.cpu.iew.exec_rate 0.499824 # Inst execution rate -system.cpu.iew.wb_sent 80077641 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 62685208 # cumulative count of insts written-back -system.cpu.iew.wb_producers 33194716 # num instructions producing a value -system.cpu.iew.wb_consumers 59585530 # num instructions consuming a value +system.cpu.iew.exec_nop 169595 # number of nop insts executed +system.cpu.iew.exec_refs 36687563 # number of memory reference insts executed +system.cpu.iew.exec_branches 10549834 # Number of branches executed +system.cpu.iew.exec_stores 8005221 # Number of stores executed +system.cpu.iew.exec_rate 0.499783 # Inst execution rate +system.cpu.iew.wb_sent 80082379 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 62689368 # cumulative count of insts written-back +system.cpu.iew.wb_producers 33196620 # num instructions producing a value +system.cpu.iew.wb_consumers 59589146 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.388202 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.557094 # average fanout of values written-back +system.cpu.iew.wb_rate 0.388174 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.557092 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 52000495 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 19085580 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 2962845 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 622953 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 89545000 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.580719 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.463730 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 52000178 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 19092846 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 2962819 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 623054 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 89568308 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.580564 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.463287 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 69882025 78.04% 78.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 9239055 10.32% 88.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 2669928 2.98% 91.34% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 1384390 1.55% 92.89% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 3444558 3.85% 96.73% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 816353 0.91% 97.65% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 554324 0.62% 98.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 352463 0.39% 98.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 1201904 1.34% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 69902534 78.04% 78.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 9240090 10.32% 88.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 2668754 2.98% 91.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 1387483 1.55% 92.89% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 3444879 3.85% 96.73% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 818955 0.91% 97.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 553093 0.62% 98.27% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 352878 0.39% 98.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 1199642 1.34% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 89545000 # Number of insts commited each cycle -system.cpu.commit.count 52000495 # Number of instructions committed +system.cpu.commit.committed_per_cycle::total 89568308 # Number of insts commited each cycle +system.cpu.commit.count 52000178 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 16256975 # Number of memory references committed -system.cpu.commit.loads 9179528 # Number of loads committed +system.cpu.commit.refs 16256886 # Number of memory references committed +system.cpu.commit.loads 9179474 # Number of loads committed system.cpu.commit.membars 3 # Number of memory barriers committed -system.cpu.commit.branches 8429180 # Number of branches committed +system.cpu.commit.branches 8429121 # Number of branches committed system.cpu.commit.fp_insts 6017 # Number of committed floating point instructions. -system.cpu.commit.int_insts 42424017 # Number of committed integer instructions. -system.cpu.commit.function_calls 530190 # Number of function calls committed. -system.cpu.commit.bw_lim_events 1201904 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 42423758 # Number of committed integer instructions. +system.cpu.commit.function_calls 530189 # Number of function calls committed. +system.cpu.commit.bw_lim_events 1199642 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 158488078 # The number of ROB reads -system.cpu.rob.rob_writes 145173632 # The number of ROB writes -system.cpu.timesIdled 1073836 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 68974351 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 51877265 # Number of Instructions Simulated -system.cpu.committedInsts_total 51877265 # Number of Instructions Simulated -system.cpu.cpi 3.112649 # CPI: Cycles Per Instruction -system.cpu.cpi_total 3.112649 # CPI: Total CPI of All Threads -system.cpu.ipc 0.321270 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.321270 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 356080640 # number of integer regfile reads -system.cpu.int_regfile_writes 64700984 # number of integer regfile writes -system.cpu.fp_regfile_reads 5701 # number of floating regfile reads -system.cpu.fp_regfile_writes 1958 # number of floating regfile writes -system.cpu.misc_regfile_reads 88406544 # number of misc regfile reads -system.cpu.misc_regfile_writes 512521 # number of misc regfile writes -system.cpu.icache.replacements 512688 # number of replacements -system.cpu.icache.tagsinuse 496.953841 # Cycle average of tags in use -system.cpu.icache.total_refs 6780185 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 513200 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 13.211584 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 158520597 # The number of ROB reads +system.cpu.rob.rob_writes 145188457 # The number of ROB writes +system.cpu.timesIdled 1073623 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 68972036 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 51876948 # Number of Instructions Simulated +system.cpu.committedInsts_total 51876948 # Number of Instructions Simulated +system.cpu.cpi 3.113098 # CPI: Cycles Per Instruction +system.cpu.cpi_total 3.113098 # CPI: Total CPI of All Threads +system.cpu.ipc 0.321223 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.321223 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 356113054 # number of integer regfile reads +system.cpu.int_regfile_writes 64703490 # number of integer regfile writes +system.cpu.fp_regfile_reads 5644 # number of floating regfile reads +system.cpu.fp_regfile_writes 1932 # number of floating regfile writes +system.cpu.misc_regfile_reads 88421211 # number of misc regfile reads +system.cpu.misc_regfile_writes 512467 # number of misc regfile writes +system.cpu.icache.replacements 513097 # number of replacements +system.cpu.icache.tagsinuse 496.956364 # Cycle average of tags in use +system.cpu.icache.total_refs 6781343 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 513609 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 13.203318 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 5987250000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 496.953841 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.970613 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::0 6780185 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 6780185 # number of ReadReq hits -system.cpu.icache.demand_hits::0 6780185 # number of demand (read+write) hits +system.cpu.icache.occ_blocks::0 496.956364 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.970618 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::0 6781343 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 6781343 # number of ReadReq hits +system.cpu.icache.demand_hits::0 6781343 # number of demand (read+write) hits system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 6780185 # number of demand (read+write) hits -system.cpu.icache.overall_hits::0 6780185 # number of overall hits +system.cpu.icache.demand_hits::total 6781343 # number of demand (read+write) hits +system.cpu.icache.overall_hits::0 6781343 # number of overall hits system.cpu.icache.overall_hits::1 0 # number of overall hits -system.cpu.icache.overall_hits::total 6780185 # number of overall hits -system.cpu.icache.ReadReq_misses::0 568554 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 568554 # number of ReadReq misses -system.cpu.icache.demand_misses::0 568554 # number of demand (read+write) misses +system.cpu.icache.overall_hits::total 6781343 # number of overall hits +system.cpu.icache.ReadReq_misses::0 569051 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 569051 # number of ReadReq misses +system.cpu.icache.demand_misses::0 569051 # number of demand (read+write) misses system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 568554 # number of demand (read+write) misses -system.cpu.icache.overall_misses::0 568554 # number of overall misses +system.cpu.icache.demand_misses::total 569051 # number of demand (read+write) misses +system.cpu.icache.overall_misses::0 569051 # number of overall misses system.cpu.icache.overall_misses::1 0 # number of overall misses -system.cpu.icache.overall_misses::total 568554 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 8372040495 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 8372040495 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 8372040495 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::0 7348739 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 7348739 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::0 7348739 # number of demand (read+write) accesses +system.cpu.icache.overall_misses::total 569051 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 8379802495 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 8379802495 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 8379802495 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::0 7350394 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 7350394 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::0 7350394 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 7348739 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::0 7348739 # number of overall (read+write) accesses +system.cpu.icache.demand_accesses::total 7350394 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::0 7350394 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 7348739 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::0 0.077368 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::0 0.077368 # miss rate for demand accesses +system.cpu.icache.overall_accesses::total 7350394 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::0 0.077418 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::0 0.077418 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::0 0.077368 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::0 0.077418 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::0 14725.145712 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::0 14725.925260 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::0 14725.145712 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::0 14725.925260 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu.icache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::0 14725.145712 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::0 14725.925260 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 1711497 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_mshrs 1742497 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 225 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 223 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 7606.653333 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 7813.887892 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 43018 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 55350 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 55350 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 55350 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 513204 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 513204 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 513204 # number of overall MSHR misses +system.cpu.icache.writebacks 42974 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits 55439 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 55439 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 55439 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 513612 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 513612 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 513612 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 6207353497 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 6207353497 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 6207353497 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 6212945497 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 6212945497 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 6212945497 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency 5831500 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency 5831500 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::0 0.069836 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::0 0.069875 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::0 0.069836 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::0 0.069875 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::0 0.069836 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::0 0.069875 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 12095.294458 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 12095.294458 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 12095.294458 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 12096.573867 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 12096.573867 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 12096.573867 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 424603 # number of replacements -system.cpu.dcache.tagsinuse 511.742300 # Cycle average of tags in use -system.cpu.dcache.total_refs 14088098 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 425115 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 33.139499 # Average number of references to valid blocks. +system.cpu.dcache.replacements 424539 # number of replacements +system.cpu.dcache.tagsinuse 511.742336 # Cycle average of tags in use +system.cpu.dcache.total_refs 14092021 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 425051 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 33.153718 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 48622000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 511.742300 # Average occupied blocks per context +system.cpu.dcache.occ_blocks::0 511.742336 # Average occupied blocks per context system.cpu.dcache.occ_percent::0 0.999497 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::0 9259812 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 9259812 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::0 4617727 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4617727 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::0 103769 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 103769 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::0 104969 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 104969 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::0 13877539 # number of demand (read+write) hits +system.cpu.dcache.ReadReq_hits::0 9263117 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 9263117 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::0 4618459 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4618459 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::0 103676 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 103676 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::0 104941 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 104941 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::0 13881576 # number of demand (read+write) hits system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 13877539 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::0 13877539 # number of overall hits +system.cpu.dcache.demand_hits::total 13881576 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::0 13881576 # number of overall hits system.cpu.dcache.overall_hits::1 0 # number of overall hits -system.cpu.dcache.overall_hits::total 13877539 # number of overall hits -system.cpu.dcache.ReadReq_misses::0 532190 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 532190 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::0 2045201 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2045201 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::0 6628 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 6628 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::0 2577391 # number of demand (read+write) misses +system.cpu.dcache.overall_hits::total 13881576 # number of overall hits +system.cpu.dcache.ReadReq_misses::0 533393 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 533393 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::0 2044461 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2044461 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::0 6632 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 6632 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::0 2577854 # number of demand (read+write) misses system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2577391 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::0 2577391 # number of overall misses +system.cpu.dcache.demand_misses::total 2577854 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::0 2577854 # number of overall misses system.cpu.dcache.overall_misses::1 0 # number of overall misses -system.cpu.dcache.overall_misses::total 2577391 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 7843477000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 81654653268 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency 99384000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency 89498130268 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 89498130268 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::0 9792002 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 9792002 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::0 6662928 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6662928 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::0 110397 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 110397 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::0 104969 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 104969 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::0 16454930 # number of demand (read+write) accesses +system.cpu.dcache.overall_misses::total 2577854 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 7849628500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 81637522770 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency 99339500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency 89487151270 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 89487151270 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::0 9796510 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 9796510 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::0 6662920 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6662920 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::0 110308 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 110308 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::0 104941 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 104941 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::0 16459430 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 16454930 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::0 16454930 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::total 16459430 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::0 16459430 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 16454930 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::0 0.054349 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::0 0.306952 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::0 0.060038 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::0 0.156633 # miss rate for demand accesses +system.cpu.dcache.overall_accesses::total 16459430 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::0 0.054447 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::0 0.306842 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::0 0.060123 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::0 0.156619 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::0 0.156633 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::0 0.156619 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::0 14738.114207 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::0 14716.407039 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::0 39925.001635 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::0 39931.073652 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 14994.568497 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 14978.814837 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::0 34724.312403 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::0 34713.816713 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::0 34724.312403 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::0 34713.816713 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 9952489 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 866000 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1361 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 31 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 7312.629684 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 27935.483871 # average number of cycles each access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 9881489 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 841000 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1354 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 29 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 7297.997784 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 29000 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 392338 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 281320 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 1874850 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits 1033 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits 2156170 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 2156170 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 250870 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 170351 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses 5595 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses 421221 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 421221 # number of overall MSHR misses +system.cpu.dcache.writebacks 392324 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 282537 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 1874151 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits 1046 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits 2156688 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 2156688 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 250856 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 170310 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses 5586 # number of LoadLockedReq MSHR misses +system.cpu.dcache.demand_mshr_misses 421166 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 421166 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 3354520500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 6559724489 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency 66444000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 9914244989 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 9914244989 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency 38199664000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency 946836164 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 39146500164 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.025620 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency 3355794000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 6558107489 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency 66303500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 9913901489 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 9913901489 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency 38199628000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency 946945664 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency 39146573664 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.025607 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.025567 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.025561 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.050681 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.050640 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::0 0.025598 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::0 0.025588 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::0 0.025598 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::0 0.025588 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13371.549009 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 38507.108787 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11875.603217 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 23536.920023 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 23536.920023 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13377.371879 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 38506.884440 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11869.584676 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 23539.178113 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 23539.178113 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency |