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authorAli Saidi <Ali.Saidi@ARM.com>2011-07-15 11:53:35 -0500
committerAli Saidi <Ali.Saidi@ARM.com>2011-07-15 11:53:35 -0500
commit147095cb0886a962620e60b6950a68931fbd734a (patch)
treeb81211a4e2441c897149b4823506a60f49966a79 /tests/long
parent69ef57fd0f226af90faf46ac877343b5493df693 (diff)
downloadgem5-147095cb0886a962620e60b6950a68931fbd734a.tar.xz
Mem: Fix issue with prefetches originating at non-L1 caches getting stale data
Prefetch requests issued from the L2 or below wouldn't check if valid data is present higher in the system. If a prefetch into the L2 occured at the same time as writeback from a higher-level cache the dirty data could be replaced in by unmodified data in memory.
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