diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2015-08-05 04:36:29 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2015-08-05 04:36:29 -0400 |
| commit | 646994e599bb21459237f1d7001ff4e887f07f33 (patch) | |
| tree | 3e91d7eca0a236a3a31fb932dd57bddb353b5684 /tests/long | |
| parent | 7c904d9d3faff80d724c8ab3e6f1d3815545e2f5 (diff) | |
| download | gem5-646994e599bb21459237f1d7001ff4e887f07f33.tar.xz | |
stats: Reflect current behaviour
Not sure what went wrong in the pushing of the Ruby patches, but
somehow these regressions are not updated.
Diffstat (limited to 'tests/long')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/stats.txt | 826 | ||||
| -rw-r--r-- | tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt | 1566 |
2 files changed, 1196 insertions, 1196 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/stats.txt index 221f5a4a8..5b46ed4d9 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/stats.txt @@ -4,13 +4,13 @@ sim_seconds 5.305855 # Nu sim_ticks 5305855051000 # Number of ticks simulated final_tick 5305855051000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 136389 # Simulator instruction rate (inst/s) -host_op_rate 261386 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 6751430632 # Simulator tick rate (ticks/s) -host_mem_usage 1106140 # Number of bytes of host memory used -host_seconds 785.89 # Real time elapsed on the host -sim_insts 107186053 # Number of instructions simulated -sim_ops 205419480 # Number of ops (including micro ops) simulated +host_inst_rate 191709 # Simulator instruction rate (inst/s) +host_op_rate 367405 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 9489836408 # Simulator tick rate (ticks/s) +host_mem_usage 1155664 # Number of bytes of host memory used +host_seconds 559.11 # Real time elapsed on the host +sim_insts 107186064 # Number of instructions simulated +sim_ops 205419446 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.mem_ctrls.bytes_read::ruby.dir_cntrl0 11371136 # Number of bytes read from this memory @@ -88,8 +88,8 @@ system.mem_ctrls.writePktSize::3 0 # Wr system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::6 142679 # Write request sizes (log2) -system.mem_ctrls.rdQLenPdf::0 176703 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::1 67 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::0 176699 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::1 71 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -135,35 +135,35 @@ system.mem_ctrls.wrQLenPdf::11 1 # Wh system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::15 2059 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::16 2790 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::17 8563 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::18 9122 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::19 8572 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::15 2068 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::16 2801 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::17 8555 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::18 9120 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::19 8578 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::20 9212 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::21 9228 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::22 8314 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::23 9034 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::24 9060 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::25 8413 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::26 8500 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::27 8357 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::28 8453 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::29 8029 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::30 8097 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::31 8147 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::21 9227 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::22 8319 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::23 9035 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::24 9059 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::25 8416 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::26 8503 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::27 8354 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::28 8443 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::29 8032 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::30 8092 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::31 8140 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::32 7952 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::33 108 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::33 106 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::34 85 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::35 89 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::36 75 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::36 72 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::37 64 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::38 57 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::38 58 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::39 48 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::40 39 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::41 28 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::40 37 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::41 29 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::42 18 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::43 9 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::43 10 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::44 4 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::45 2 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::46 1 # What write queue length does an incoming req see @@ -184,73 +184,73 @@ system.mem_ctrls.wrQLenPdf::60 0 # Wh system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrls.bytesPerActivate::samples 60336 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::mean 338.676213 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::gmean 200.551275 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::stdev 343.723517 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::0-127 20068 33.26% 33.26% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::128-255 14736 24.42% 57.68% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::256-383 6373 10.56% 68.25% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::384-511 3491 5.79% 74.03% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::512-639 2657 4.40% 78.44% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::640-767 1861 3.08% 81.52% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::768-895 1364 2.26% 83.78% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::896-1023 1338 2.22% 86.00% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::1024-1151 8448 14.00% 100.00% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::total 60336 # Bytes accessed per row activation -system.mem_ctrls.rdPerTurnAround::samples 7897 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::mean 22.382170 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::stdev 317.489285 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::0-1023 7891 99.92% 99.92% # Reads before turning the bus around for writes +system.mem_ctrls.bytesPerActivate::samples 60326 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 338.732354 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 200.613193 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 343.695896 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 20059 33.25% 33.25% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 14736 24.43% 57.68% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 6379 10.57% 68.25% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 3472 5.76% 74.01% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 2656 4.40% 78.41% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 1882 3.12% 81.53% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 1369 2.27% 83.80% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 1326 2.20% 86.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 8447 14.00% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 60326 # Bytes accessed per row activation +system.mem_ctrls.rdPerTurnAround::samples 7898 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::mean 22.379337 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::stdev 317.468114 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::0-1023 7892 99.92% 99.92% # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::1024-2047 3 0.04% 99.96% # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::2048-3071 1 0.01% 99.97% # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::10240-11263 1 0.01% 99.99% # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::25600-26623 1 0.01% 100.00% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::total 7897 # Reads before turning the bus around for writes -system.mem_ctrls.wrPerTurnAround::samples 7897 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::mean 18.047106 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::gmean 17.696875 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::stdev 4.065797 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::16 5800 73.45% 73.45% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::17 9 0.11% 73.56% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::18 169 2.14% 75.70% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::19 20 0.25% 75.95% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::20 37 0.47% 76.42% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::21 500 6.33% 82.75% # Writes before turning the bus around for reads +system.mem_ctrls.rdPerTurnAround::total 7898 # Reads before turning the bus around for writes +system.mem_ctrls.wrPerTurnAround::samples 7898 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::mean 18.044821 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::gmean 17.697162 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::stdev 4.041167 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::16 5792 73.34% 73.34% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::17 9 0.11% 73.45% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::18 176 2.23% 75.68% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::19 20 0.25% 75.93% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::20 36 0.46% 76.39% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::21 503 6.37% 82.76% # Writes before turning the bus around for reads system.mem_ctrls.wrPerTurnAround::22 145 1.84% 84.59% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::23 43 0.54% 85.13% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::24 653 8.27% 93.40% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::25 111 1.41% 94.81% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::26 12 0.15% 94.96% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::27 19 0.24% 95.20% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::28 304 3.85% 99.05% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::23 45 0.57% 85.16% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::24 652 8.26% 93.42% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::25 114 1.44% 94.86% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::26 12 0.15% 95.01% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::27 18 0.23% 95.24% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::28 301 3.81% 99.05% # Writes before turning the bus around for reads system.mem_ctrls.wrPerTurnAround::29 7 0.09% 99.14% # Writes before turning the bus around for reads system.mem_ctrls.wrPerTurnAround::30 3 0.04% 99.18% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::31 6 0.08% 99.25% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::32 6 0.08% 99.33% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::33 2 0.03% 99.35% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::34 1 0.01% 99.37% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::35 3 0.04% 99.40% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::37 1 0.01% 99.42% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::38 3 0.04% 99.46% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::39 7 0.09% 99.54% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::40 3 0.04% 99.58% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::41 3 0.04% 99.62% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::42 6 0.08% 99.70% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::43 2 0.03% 99.72% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::44 6 0.08% 99.80% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::45 1 0.01% 99.81% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::47 1 0.01% 99.82% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::48 4 0.05% 99.87% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::51 9 0.11% 99.99% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::31 7 0.09% 99.27% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::32 6 0.08% 99.34% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::33 2 0.03% 99.37% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::34 1 0.01% 99.38% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::35 3 0.04% 99.42% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::37 1 0.01% 99.43% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::38 3 0.04% 99.47% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::39 7 0.09% 99.56% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::40 3 0.04% 99.59% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::41 3 0.04% 99.63% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::42 6 0.08% 99.71% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::43 2 0.03% 99.73% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::44 7 0.09% 99.82% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::45 1 0.01% 99.84% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::47 1 0.01% 99.85% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::48 4 0.05% 99.90% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::51 7 0.09% 99.99% # Writes before turning the bus around for reads system.mem_ctrls.wrPerTurnAround::52 1 0.01% 100.00% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::total 7897 # Writes before turning the bus around for reads -system.mem_ctrls.totQLat 1934453242 # Total ticks spent queuing -system.mem_ctrls.totMemAccLat 5248890742 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.wrPerTurnAround::total 7898 # Writes before turning the bus around for reads +system.mem_ctrls.totQLat 1934412994 # Total ticks spent queuing +system.mem_ctrls.totMemAccLat 5248850494 # Total ticks spent from burst creation until serviced by the DRAM system.mem_ctrls.totBusLat 883850000 # Total ticks spent in databus transfers -system.mem_ctrls.avgQLat 10943.33 # Average queueing delay per DRAM burst +system.mem_ctrls.avgQLat 10943.11 # Average queueing delay per DRAM burst system.mem_ctrls.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.mem_ctrls.avgMemAccLat 29693.33 # Average memory access latency per DRAM burst +system.mem_ctrls.avgMemAccLat 29693.11 # Average memory access latency per DRAM burst system.mem_ctrls.avgRdBW 2.13 # Average DRAM read bandwidth in MiByte/s system.mem_ctrls.avgWrBW 1.72 # Average achieved write bandwidth in MiByte/s system.mem_ctrls.avgRdBWSys 2.14 # Average system read bandwidth in MiByte/s @@ -261,71 +261,71 @@ system.mem_ctrls.busUtilRead 0.02 # Da system.mem_ctrls.busUtilWrite 0.01 # Data bus utilization in percentage for writes system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing system.mem_ctrls.avgWrQLen 24.42 # Average write queue length when enqueuing -system.mem_ctrls.readRowHits 140774 # Number of row buffer hits during reads -system.mem_ctrls.writeRowHits 118177 # Number of row buffer hits during writes +system.mem_ctrls.readRowHits 140781 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 118180 # Number of row buffer hits during writes system.mem_ctrls.readRowHitRate 79.64 # Row buffer hit rate for reads system.mem_ctrls.writeRowHitRate 82.91 # Row buffer hit rate for writes system.mem_ctrls.avgGap 16562526.08 # Average gap between requests system.mem_ctrls.pageHitRate 81.10 # Row buffer hit rate, read and write combined -system.mem_ctrls_0.actEnergy 229839120 # Energy for activate commands per rank (pJ) -system.mem_ctrls_0.preEnergy 125408250 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_0.actEnergy 229725720 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 125346375 # Energy for precharge commands per rank (pJ) system.mem_ctrls_0.readEnergy 694816200 # Energy for read commands per rank (pJ) system.mem_ctrls_0.writeEnergy 465892560 # Energy for write commands per rank (pJ) system.mem_ctrls_0.refreshEnergy 346552617840 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_0.actBackEnergy 149179147425 # Energy for active background per rank (pJ) -system.mem_ctrls_0.preBackEnergy 3052653894750 # Energy for precharge background per rank (pJ) -system.mem_ctrls_0.totalEnergy 3549901616145 # Total energy per rank (pJ) -system.mem_ctrls_0.averagePower 669.053686 # Core power per rank (mW) -system.mem_ctrls_0.memoryStateTime::IDLE 5078195767000 # Time in different power states +system.mem_ctrls_0.actBackEnergy 149158105020 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 3052672353000 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.totalEnergy 3549898856715 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 669.053166 # Core power per rank (mW) +system.mem_ctrls_0.memoryStateTime::IDLE 5078226654500 # Time in different power states system.mem_ctrls_0.memoryStateTime::REF 177174140000 # Time in different power states system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls_0.memoryStateTime::ACT 50484766750 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 50453879250 # Time in different power states system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrls_1.actEnergy 226301040 # Energy for activate commands per rank (pJ) -system.mem_ctrls_1.preEnergy 123477750 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_1.actEnergy 226338840 # Energy for activate commands per rank (pJ) +system.mem_ctrls_1.preEnergy 123498375 # Energy for precharge commands per rank (pJ) system.mem_ctrls_1.readEnergy 683982000 # Energy for read commands per rank (pJ) system.mem_ctrls_1.writeEnergy 457624080 # Energy for write commands per rank (pJ) system.mem_ctrls_1.refreshEnergy 346552617840 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_1.actBackEnergy 148537848690 # Energy for active background per rank (pJ) -system.mem_ctrls_1.preBackEnergy 3053216437500 # Energy for precharge background per rank (pJ) -system.mem_ctrls_1.totalEnergy 3549798288900 # Total energy per rank (pJ) -system.mem_ctrls_1.averagePower 669.034212 # Core power per rank (mW) -system.mem_ctrls_1.memoryStateTime::IDLE 5079136661250 # Time in different power states +system.mem_ctrls_1.actBackEnergy 148581064665 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 3053178528750 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.totalEnergy 3549803654550 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 669.035223 # Core power per rank (mW) +system.mem_ctrls_1.memoryStateTime::IDLE 5079073326250 # Time in different power states system.mem_ctrls_1.memoryStateTime::REF 177174140000 # Time in different power states system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls_1.memoryStateTime::ACT 49544125250 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT 49607460250 # Time in different power states system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu0.numCycles 10611710102 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 59039296 # Number of instructions committed -system.cpu0.committedOps 113305650 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 106292214 # Number of integer alu accesses +system.cpu0.committedInsts 59039301 # Number of instructions committed +system.cpu0.committedOps 113305603 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 106292175 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 48 # Number of float alu accesses system.cpu0.num_func_calls 1017385 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 10037497 # number of instructions that are conditional controls -system.cpu0.num_int_insts 106292214 # number of integer instructions +system.cpu0.num_conditional_control_insts 10037487 # number of instructions that are conditional controls +system.cpu0.num_int_insts 106292175 # number of integer instructions system.cpu0.num_fp_insts 48 # number of float instructions -system.cpu0.num_int_register_reads 200616677 # number of times the integer registers were read -system.cpu0.num_int_register_writes 90211380 # number of times the integer registers were written +system.cpu0.num_int_register_reads 200616462 # number of times the integer registers were read +system.cpu0.num_int_register_writes 90211252 # number of times the integer registers were written system.cpu0.num_fp_register_reads 48 # number of times the floating registers were read system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 60966470 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 44030878 # number of times the CC registers were written -system.cpu0.num_mem_refs 12456031 # number of memory refs -system.cpu0.num_load_insts 7518228 # Number of load instructions +system.cpu0.num_cc_register_reads 60966419 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 44030869 # number of times the CC registers were written +system.cpu0.num_mem_refs 12456032 # number of memory refs +system.cpu0.num_load_insts 7518229 # Number of load instructions system.cpu0.num_store_insts 4937803 # Number of store instructions -system.cpu0.num_idle_cycles 10088651138.334099 # Number of idle cycles -system.cpu0.num_busy_cycles 523058963.665901 # Number of busy cycles +system.cpu0.num_idle_cycles 10088651128.334099 # Number of idle cycles +system.cpu0.num_busy_cycles 523058973.665901 # Number of busy cycles system.cpu0.not_idle_fraction 0.049291 # Percentage of non-idle cycles system.cpu0.idle_fraction 0.950709 # Percentage of idle cycles -system.cpu0.Branches 11416966 # Number of branches fetched -system.cpu0.op_class::No_OpClass 131109 0.12% 0.12% # Class of executed instruction -system.cpu0.op_class::IntAlu 100580264 88.77% 88.88% # Class of executed instruction +system.cpu0.Branches 11416956 # Number of branches fetched +system.cpu0.op_class::No_OpClass 131098 0.12% 0.12% # Class of executed instruction +system.cpu0.op_class::IntAlu 100580271 88.77% 88.88% # Class of executed instruction system.cpu0.op_class::IntMult 86269 0.08% 88.96% # Class of executed instruction -system.cpu0.op_class::IntDiv 57079 0.05% 89.01% # Class of executed instruction +system.cpu0.op_class::IntDiv 57035 0.05% 89.01% # Class of executed instruction system.cpu0.op_class::FloatAdd 0 0.00% 89.01% # Class of executed instruction system.cpu0.op_class::FloatCmp 0 0.00% 89.01% # Class of executed instruction system.cpu0.op_class::FloatCvt 16 0.00% 89.01% # Class of executed instruction @@ -352,41 +352,41 @@ system.cpu0.op_class::SimdFloatMisc 0 0.00% 89.01% # Cl system.cpu0.op_class::SimdFloatMult 0 0.00% 89.01% # Class of executed instruction system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 89.01% # Class of executed instruction system.cpu0.op_class::SimdFloatSqrt 0 0.00% 89.01% # Class of executed instruction -system.cpu0.op_class::MemRead 7514027 6.63% 95.64% # Class of executed instruction +system.cpu0.op_class::MemRead 7514028 6.63% 95.64% # Class of executed instruction system.cpu0.op_class::MemWrite 4937803 4.36% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 113306567 # Class of executed instruction +system.cpu0.op_class::total 113306520 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 0 # number of quiesce instructions executed system.cpu1.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu1.numCycles 10608777066 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 48146757 # Number of instructions committed -system.cpu1.committedOps 92113830 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 88441893 # Number of integer alu accesses +system.cpu1.committedInsts 48146763 # Number of instructions committed +system.cpu1.committedOps 92113843 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 88441904 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 48 # Number of float alu accesses system.cpu1.num_func_calls 1752446 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 8219760 # number of instructions that are conditional controls -system.cpu1.num_int_insts 88441893 # number of integer instructions +system.cpu1.num_conditional_control_insts 8219762 # number of instructions that are conditional controls +system.cpu1.num_int_insts 88441904 # number of integer instructions system.cpu1.num_fp_insts 48 # number of float instructions -system.cpu1.num_int_register_reads 171408328 # number of times the integer registers were read -system.cpu1.num_int_register_writes 73196137 # number of times the integer registers were written +system.cpu1.num_int_register_reads 171408346 # number of times the integer registers were read +system.cpu1.num_int_register_writes 73196146 # number of times the integer registers were written system.cpu1.num_fp_register_reads 48 # number of times the floating registers were read system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 50924734 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 32745964 # number of times the CC registers were written -system.cpu1.num_mem_refs 14124901 # number of memory refs -system.cpu1.num_load_insts 9133293 # Number of load instructions +system.cpu1.num_cc_register_reads 50924744 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 32745968 # number of times the CC registers were written +system.cpu1.num_mem_refs 14124903 # number of memory refs +system.cpu1.num_load_insts 9133295 # Number of load instructions system.cpu1.num_store_insts 4991608 # Number of store instructions -system.cpu1.num_idle_cycles 10274072284.207695 # Number of idle cycles -system.cpu1.num_busy_cycles 334704781.792306 # Number of busy cycles +system.cpu1.num_idle_cycles 10274072236.220961 # Number of idle cycles +system.cpu1.num_busy_cycles 334704829.779039 # Number of busy cycles system.cpu1.not_idle_fraction 0.031550 # Percentage of non-idle cycles system.cpu1.idle_fraction 0.968450 # Percentage of idle cycles -system.cpu1.Branches 10581617 # Number of branches fetched +system.cpu1.Branches 10581619 # Number of branches fetched system.cpu1.op_class::No_OpClass 169787 0.18% 0.18% # Class of executed instruction -system.cpu1.op_class::IntAlu 77653530 84.30% 84.49% # Class of executed instruction +system.cpu1.op_class::IntAlu 77653541 84.30% 84.49% # Class of executed instruction system.cpu1.op_class::IntMult 98479 0.11% 84.59% # Class of executed instruction system.cpu1.op_class::IntDiv 71918 0.08% 84.67% # Class of executed instruction system.cpu1.op_class::FloatAdd 0 0.00% 84.67% # Class of executed instruction @@ -415,11 +415,11 @@ system.cpu1.op_class::SimdFloatMisc 0 0.00% 84.67% # Cl system.cpu1.op_class::SimdFloatMult 0 0.00% 84.67% # Class of executed instruction system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 84.67% # Class of executed instruction system.cpu1.op_class::SimdFloatSqrt 0 0.00% 84.67% # Class of executed instruction -system.cpu1.op_class::MemRead 9129153 9.91% 94.58% # Class of executed instruction +system.cpu1.op_class::MemRead 9129155 9.91% 94.58% # Class of executed instruction system.cpu1.op_class::MemWrite 4991608 5.42% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 92114491 # Class of executed instruction +system.cpu1.op_class::total 92114504 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed system.iobus.trans_dist::ReadReq 842290 # Transaction distribution @@ -508,11 +508,11 @@ system.iobus.reqLayer0.occupancy 43500 # La system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 6500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 9032500 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 9032000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer3.occupancy 154500 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer4.occupancy 940000 # Layer occupancy (ticks) +system.iobus.reqLayer4.occupancy 939000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer5.occupancy 92000 # Layer occupancy (ticks) system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) @@ -522,7 +522,7 @@ system.iobus.reqLayer7.occupancy 20247500 # La system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer8.occupancy 458718000 # Layer occupancy (ticks) system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer9.occupancy 1157500 # Layer occupancy (ticks) +system.iobus.reqLayer9.occupancy 1168984 # Layer occupancy (ticks) system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer10.occupancy 30508000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) @@ -538,17 +538,17 @@ system.iobus.reqLayer16.occupancy 9000 # La system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 11500 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 369412820 # Layer occupancy (ticks) +system.iobus.reqLayer18.occupancy 369423793 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer19.occupancy 7528580 # Layer occupancy (ticks) +system.iobus.reqLayer19.occupancy 7540555 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer21.occupancy 1593000 # Layer occupancy (ticks) system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 2422900 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer2.occupancy 1846190500 # Layer occupancy (ticks) +system.iobus.respLayer2.occupancy 1846208467 # Layer occupancy (ticks) system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer4.occupancy 57610000 # Layer occupancy (ticks) +system.iobus.respLayer4.occupancy 57630965 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 32768 # Number of bytes transfered via DMA reads (not PRD). @@ -565,48 +565,48 @@ system.pc.south_bridge.ide.disks1.dma_write_txs 1 system.ruby.clk_domain.clock 500 # Clock period in ticks system.ruby.delayHist::bucket_size 4 # delay histogram for all message system.ruby.delayHist::max_bucket 39 # delay histogram for all message -system.ruby.delayHist::samples 10891010 # delay histogram for all message -system.ruby.delayHist::mean 0.442804 # delay histogram for all message -system.ruby.delayHist::stdev 1.830720 # delay histogram for all message -system.ruby.delayHist | 10288683 94.47% 94.47% | 1238 0.01% 94.48% | 600635 5.51% 100.00% | 152 0.00% 100.00% | 257 0.00% 100.00% | 11 0.00% 100.00% | 34 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message -system.ruby.delayHist::total 10891010 # delay histogram for all message +system.ruby.delayHist::samples 10891037 # delay histogram for all message +system.ruby.delayHist::mean 0.442781 # delay histogram for all message +system.ruby.delayHist::stdev 1.830637 # delay histogram for all message +system.ruby.delayHist | 10288749 94.47% 94.47% | 1200 0.01% 94.48% | 600645 5.52% 100.00% | 149 0.00% 100.00% | 250 0.00% 100.00% | 10 0.00% 100.00% | 34 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message +system.ruby.delayHist::total 10891037 # delay histogram for all message system.ruby.outstanding_req_hist::bucket_size 1 system.ruby.outstanding_req_hist::max_bucket 9 -system.ruby.outstanding_req_hist::samples 152756591 +system.ruby.outstanding_req_hist::samples 152756607 system.ruby.outstanding_req_hist::mean 1.000166 system.ruby.outstanding_req_hist::gmean 1.000115 system.ruby.outstanding_req_hist::stdev 0.012901 -system.ruby.outstanding_req_hist | 0 0.00% 0.00% | 152731162 99.98% 99.98% | 25429 0.02% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.outstanding_req_hist::total 152756591 +system.ruby.outstanding_req_hist | 0 0.00% 0.00% | 152731178 99.98% 99.98% | 25429 0.02% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.outstanding_req_hist::total 152756607 system.ruby.latency_hist::bucket_size 128 system.ruby.latency_hist::max_bucket 1279 -system.ruby.latency_hist::samples 152756590 +system.ruby.latency_hist::samples 152756606 system.ruby.latency_hist::mean 3.433707 system.ruby.latency_hist::gmean 3.107293 -system.ruby.latency_hist::stdev 5.733578 -system.ruby.latency_hist | 152719525 99.98% 99.98% | 28048 0.02% 99.99% | 2695 0.00% 100.00% | 3637 0.00% 100.00% | 2109 0.00% 100.00% | 523 0.00% 100.00% | 9 0.00% 100.00% | 20 0.00% 100.00% | 17 0.00% 100.00% | 7 0.00% 100.00% -system.ruby.latency_hist::total 152756590 +system.ruby.latency_hist::stdev 5.733417 +system.ruby.latency_hist | 152719535 99.98% 99.98% | 28054 0.02% 99.99% | 2709 0.00% 100.00% | 3616 0.00% 100.00% | 2121 0.00% 100.00% | 519 0.00% 100.00% | 10 0.00% 100.00% | 19 0.00% 100.00% | 16 0.00% 100.00% | 7 0.00% 100.00% +system.ruby.latency_hist::total 152756606 system.ruby.hit_latency_hist::bucket_size 1 system.ruby.hit_latency_hist::max_bucket 9 -system.ruby.hit_latency_hist::samples 150094333 +system.ruby.hit_latency_hist::samples 150094340 system.ruby.hit_latency_hist::mean 3 system.ruby.hit_latency_hist::gmean 3.000000 -system.ruby.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 150094333 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.hit_latency_hist::total 150094333 +system.ruby.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 150094340 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.hit_latency_hist::total 150094340 system.ruby.miss_latency_hist::bucket_size 128 system.ruby.miss_latency_hist::max_bucket 1279 -system.ruby.miss_latency_hist::samples 2662257 -system.ruby.miss_latency_hist::mean 27.885506 -system.ruby.miss_latency_hist::gmean 22.530762 -system.ruby.miss_latency_hist::stdev 35.745831 -system.ruby.miss_latency_hist | 2625192 98.61% 98.61% | 28048 1.05% 99.66% | 2695 0.10% 99.76% | 3637 0.14% 99.90% | 2109 0.08% 99.98% | 523 0.02% 100.00% | 9 0.00% 100.00% | 20 0.00% 100.00% | 17 0.00% 100.00% | 7 0.00% 100.00% -system.ruby.miss_latency_hist::total 2662257 -system.ruby.l1_cntrl0.L1Dcache.demand_hits 11119260 # Number of cache demand hits -system.ruby.l1_cntrl0.L1Dcache.demand_misses 532503 # Number of cache demand misses -system.ruby.l1_cntrl0.L1Dcache.demand_accesses 11651763 # Number of cache demand accesses -system.ruby.l1_cntrl0.L1Icache.demand_hits 68488995 # Number of cache demand hits -system.ruby.l1_cntrl0.L1Icache.demand_misses 323914 # Number of cache demand misses -system.ruby.l1_cntrl0.L1Icache.demand_accesses 68812909 # Number of cache demand accesses +system.ruby.miss_latency_hist::samples 2662266 +system.ruby.miss_latency_hist::mean 27.885415 +system.ruby.miss_latency_hist::gmean 22.530675 +system.ruby.miss_latency_hist::stdev 35.744325 +system.ruby.miss_latency_hist | 2625195 98.61% 98.61% | 28054 1.05% 99.66% | 2709 0.10% 99.76% | 3616 0.14% 99.90% | 2121 0.08% 99.98% | 519 0.02% 100.00% | 10 0.00% 100.00% | 19 0.00% 100.00% | 16 0.00% 100.00% | 7 0.00% 100.00% +system.ruby.miss_latency_hist::total 2662266 +system.ruby.l1_cntrl0.L1Dcache.demand_hits 11119259 # Number of cache demand hits +system.ruby.l1_cntrl0.L1Dcache.demand_misses 532505 # Number of cache demand misses +system.ruby.l1_cntrl0.L1Dcache.demand_accesses 11651764 # Number of cache demand accesses +system.ruby.l1_cntrl0.L1Icache.demand_hits 68488994 # Number of cache demand hits +system.ruby.l1_cntrl0.L1Icache.demand_misses 323919 # Number of cache demand misses +system.ruby.l1_cntrl0.L1Icache.demand_accesses 68812913 # Number of cache demand accesses system.ruby.l1_cntrl0.prefetcher.miss_observed 0 # number of misses observed system.ruby.l1_cntrl0.prefetcher.allocated_streams 0 # number of streams allocated for prefetching system.ruby.l1_cntrl0.prefetcher.prefetches_requested 0 # number of prefetch requests made @@ -618,11 +618,11 @@ system.ruby.l1_cntrl0.prefetcher.pages_crossed 0 system.ruby.l1_cntrl0.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed system.ruby.l1_cntrl0.fully_busy_cycles 16 # cycles for which number of transistions == max transitions system.ruby.l1_cntrl1.L1Dcache.demand_hits 12794938 # Number of cache demand hits -system.ruby.l1_cntrl1.L1Dcache.demand_misses 1313574 # Number of cache demand misses -system.ruby.l1_cntrl1.L1Dcache.demand_accesses 14108512 # Number of cache demand accesses -system.ruby.l1_cntrl1.L1Icache.demand_hits 57691140 # Number of cache demand hits +system.ruby.l1_cntrl1.L1Dcache.demand_misses 1313576 # Number of cache demand misses +system.ruby.l1_cntrl1.L1Dcache.demand_accesses 14108514 # Number of cache demand accesses +system.ruby.l1_cntrl1.L1Icache.demand_hits 57691149 # Number of cache demand hits system.ruby.l1_cntrl1.L1Icache.demand_misses 492266 # Number of cache demand misses -system.ruby.l1_cntrl1.L1Icache.demand_accesses 58183406 # Number of cache demand accesses +system.ruby.l1_cntrl1.L1Icache.demand_accesses 58183415 # Number of cache demand accesses system.ruby.l1_cntrl1.prefetcher.miss_observed 0 # number of misses observed system.ruby.l1_cntrl1.prefetcher.allocated_streams 0 # number of streams allocated for prefetching system.ruby.l1_cntrl1.prefetcher.prefetches_requested 0 # number of prefetch requests made @@ -633,62 +633,62 @@ system.ruby.l1_cntrl1.prefetcher.partial_hits 0 system.ruby.l1_cntrl1.prefetcher.pages_crossed 0 # number of prefetches across pages system.ruby.l1_cntrl1.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed system.ruby.l1_cntrl1.fully_busy_cycles 7 # cycles for which number of transistions == max transitions -system.ruby.l2_cntrl0.L2cache.demand_hits 2435460 # Number of cache demand hits +system.ruby.l2_cntrl0.L2cache.demand_hits 2435469 # Number of cache demand hits system.ruby.l2_cntrl0.L2cache.demand_misses 226797 # Number of cache demand misses -system.ruby.l2_cntrl0.L2cache.demand_accesses 2662257 # Number of cache demand accesses -system.ruby.l2_cntrl0.fully_busy_cycles 5 # cycles for which number of transistions == max transitions +system.ruby.l2_cntrl0.L2cache.demand_accesses 2662266 # Number of cache demand accesses +system.ruby.l2_cntrl0.fully_busy_cycles 4 # cycles for which number of transistions == max transitions system.ruby.memctrl_clk_domain.clock 1500 # Clock period in ticks system.ruby.network.routers0.percent_links_utilized 0.030013 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system.ruby.network.routers0.msg_bytes.Request_Control::2 341280 -system.ruby.network.routers0.msg_bytes.Response_Data::1 63716400 -system.ruby.network.routers0.msg_bytes.Response_Control::1 4081128 -system.ruby.network.routers0.msg_bytes.Response_Control::2 4059640 -system.ruby.network.routers0.msg_bytes.Writeback_Data::0 21491424 +system.ruby.network.routers0.msg_bytes.Response_Data::1 63716904 +system.ruby.network.routers0.msg_bytes.Response_Control::1 4081136 +system.ruby.network.routers0.msg_bytes.Response_Control::2 4059648 +system.ruby.network.routers0.msg_bytes.Writeback_Data::0 21491496 system.ruby.network.routers0.msg_bytes.Writeback_Data::1 12816 system.ruby.network.routers0.msg_bytes.Writeback_Control::0 1363216 system.ruby.network.routers1.percent_links_utilized 0.057139 -system.ruby.network.routers1.msg_count.Control::0 1805840 +system.ruby.network.routers1.msg_count.Control::0 1805842 system.ruby.network.routers1.msg_count.Request_Control::2 40537 -system.ruby.network.routers1.msg_count.Response_Data::1 1830038 -system.ruby.network.routers1.msg_count.Response_Control::1 1255303 -system.ruby.network.routers1.msg_count.Response_Control::2 1254313 -system.ruby.network.routers1.msg_count.Writeback_Data::0 276120 +system.ruby.network.routers1.msg_count.Response_Data::1 1830040 +system.ruby.network.routers1.msg_count.Response_Control::1 1255305 +system.ruby.network.routers1.msg_count.Response_Control::2 1254315 +system.ruby.network.routers1.msg_count.Writeback_Data::0 276121 system.ruby.network.routers1.msg_count.Writeback_Data::1 190 -system.ruby.network.routers1.msg_count.Writeback_Control::0 940436 -system.ruby.network.routers1.msg_bytes.Control::0 14446720 +system.ruby.network.routers1.msg_count.Writeback_Control::0 940437 +system.ruby.network.routers1.msg_bytes.Control::0 14446736 system.ruby.network.routers1.msg_bytes.Request_Control::2 324296 -system.ruby.network.routers1.msg_bytes.Response_Data::1 131762736 -system.ruby.network.routers1.msg_bytes.Response_Control::1 10042424 -system.ruby.network.routers1.msg_bytes.Response_Control::2 10034504 -system.ruby.network.routers1.msg_bytes.Writeback_Data::0 19880640 +system.ruby.network.routers1.msg_bytes.Response_Data::1 131762880 +system.ruby.network.routers1.msg_bytes.Response_Control::1 10042440 +system.ruby.network.routers1.msg_bytes.Response_Control::2 10034520 +system.ruby.network.routers1.msg_bytes.Writeback_Data::0 19880712 system.ruby.network.routers1.msg_bytes.Writeback_Data::1 13680 -system.ruby.network.routers1.msg_bytes.Writeback_Control::0 7523488 +system.ruby.network.routers1.msg_bytes.Writeback_Control::0 7523496 system.ruby.network.routers2.percent_links_utilized 0.091475 -system.ruby.network.routers2.msg_count.Control::0 2839469 +system.ruby.network.routers2.msg_count.Control::0 2839478 system.ruby.network.routers2.msg_count.Request_Control::2 81710 -system.ruby.network.routers2.msg_count.Response_Data::1 2890401 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0 system.ruby.network.routers6.percent_links_utilized 0.030942 -system.ruby.network.routers6.msg_count.Control::0 2839469 +system.ruby.network.routers6.msg_count.Control::0 2839478 system.ruby.network.routers6.msg_count.Request_Control::2 83197 -system.ruby.network.routers6.msg_count.Response_Data::1 2940795 -system.ruby.network.routers6.msg_count.Response_Control::1 1870415 -system.ruby.network.routers6.msg_count.Response_Control::2 1761768 -system.ruby.network.routers6.msg_count.Writeback_Data::0 574612 +system.ruby.network.routers6.msg_count.Response_Data::1 2940804 +system.ruby.network.routers6.msg_count.Response_Control::1 1870418 +system.ruby.network.routers6.msg_count.Response_Control::2 1761771 +system.ruby.network.routers6.msg_count.Writeback_Data::0 574614 system.ruby.network.routers6.msg_count.Writeback_Data::1 368 -system.ruby.network.routers6.msg_count.Writeback_Control::0 1158383 +system.ruby.network.routers6.msg_count.Writeback_Control::0 1158384 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-system.ruby.network.routers6.throttle1.msg_bytes.Response_Data::1 129283920 -system.ruby.network.routers6.throttle1.msg_bytes.Response_Control::1 9904304 -system.ruby.network.routers6.throttle2.link_utilization 0.059642 -system.ruby.network.routers6.throttle2.msg_count.Control::0 2662257 +system.ruby.network.routers6.throttle1.msg_bytes.Response_Data::1 129284064 +system.ruby.network.routers6.throttle1.msg_bytes.Response_Control::1 9904320 +system.ruby.network.routers6.throttle2.link_utilization 0.059643 +system.ruby.network.routers6.throttle2.msg_count.Control::0 2662266 system.ruby.network.routers6.throttle2.msg_count.Response_Data::1 202813 system.ruby.network.routers6.throttle2.msg_count.Response_Control::1 123155 -system.ruby.network.routers6.throttle2.msg_count.Response_Control::2 1761768 -system.ruby.network.routers6.throttle2.msg_count.Writeback_Data::0 574612 +system.ruby.network.routers6.throttle2.msg_count.Response_Control::2 1761771 +system.ruby.network.routers6.throttle2.msg_count.Writeback_Data::0 574614 system.ruby.network.routers6.throttle2.msg_count.Writeback_Data::1 368 -system.ruby.network.routers6.throttle2.msg_count.Writeback_Control::0 1110838 -system.ruby.network.routers6.throttle2.msg_bytes.Control::0 21298056 +system.ruby.network.routers6.throttle2.msg_count.Writeback_Control::0 1110839 +system.ruby.network.routers6.throttle2.msg_bytes.Control::0 21298128 system.ruby.network.routers6.throttle2.msg_bytes.Response_Data::1 14602536 system.ruby.network.routers6.throttle2.msg_bytes.Response_Control::1 985240 -system.ruby.network.routers6.throttle2.msg_bytes.Response_Control::2 14094144 -system.ruby.network.routers6.throttle2.msg_bytes.Writeback_Data::0 41372064 +system.ruby.network.routers6.throttle2.msg_bytes.Response_Control::2 14094168 +system.ruby.network.routers6.throttle2.msg_bytes.Writeback_Data::0 41372208 system.ruby.network.routers6.throttle2.msg_bytes.Writeback_Data::1 26496 -system.ruby.network.routers6.throttle2.msg_bytes.Writeback_Control::0 8886704 +system.ruby.network.routers6.throttle2.msg_bytes.Writeback_Control::0 8886712 system.ruby.network.routers6.throttle3.link_utilization 0.005259 system.ruby.network.routers6.throttle3.msg_count.Control::0 177212 system.ruby.network.routers6.throttle3.msg_count.Response_Data::1 97371 @@ -879,55 +879,55 @@ system.ruby.network.routers6.throttle4.msg_bytes.Writeback_Control::1 3738 system.ruby.network.routers6.throttle5.link_utilization 0 system.ruby.delayVCHist.vnet_0::bucket_size 4 # delay histogram for vnet_0 system.ruby.delayVCHist.vnet_0::max_bucket 39 # delay histogram for vnet_0 -system.ruby.delayVCHist.vnet_0::samples 6109475 # delay histogram for vnet_0 -system.ruby.delayVCHist.vnet_0::mean 0.754304 # delay histogram for vnet_0 -system.ruby.delayVCHist.vnet_0::stdev 2.340275 # delay histogram for vnet_0 -system.ruby.delayVCHist.vnet_0 | 5534056 90.58% 90.58% | 362 0.01% 90.59% | 574616 9.41% 99.99% | 149 0.00% 100.00% | 247 0.00% 100.00% | 11 0.00% 100.00% | 34 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_0 -system.ruby.delayVCHist.vnet_0::total 6109475 # delay histogram for vnet_0 +system.ruby.delayVCHist.vnet_0::samples 6109490 # delay histogram for vnet_0 +system.ruby.delayVCHist.vnet_0::mean 0.754288 # delay histogram for vnet_0 +system.ruby.delayVCHist.vnet_0::stdev 2.340197 # delay histogram for vnet_0 +system.ruby.delayVCHist.vnet_0 | 5534078 90.58% 90.58% | 346 0.01% 90.59% | 574634 9.41% 99.99% | 147 0.00% 100.00% | 241 0.00% 100.00% | 10 0.00% 100.00% | 34 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_0 +system.ruby.delayVCHist.vnet_0::total 6109490 # delay histogram for vnet_0 system.ruby.delayVCHist.vnet_1::bucket_size 2 # delay histogram for vnet_1 system.ruby.delayVCHist.vnet_1::max_bucket 19 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::samples 4698338 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::mean 0.045583 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::stdev 0.599791 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1 | 4670953 99.42% 99.42% | 477 0.01% 99.43% | 336 0.01% 99.43% | 540 0.01% 99.45% | 25880 0.55% 100.00% | 139 0.00% 100.00% | 2 0.00% 100.00% | 1 0.00% 100.00% | 10 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::total 4698338 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::samples 4698350 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::mean 0.045551 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::stdev 0.599594 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1 | 4670978 99.42% 99.42% | 496 0.01% 99.43% | 327 0.01% 99.43% | 527 0.01% 99.45% | 25863 0.55% 100.00% | 148 0.00% 100.00% | 1 0.00% 100.00% | 1 0.00% 100.00% | 9 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::total 4698350 # delay histogram for vnet_1 system.ruby.delayVCHist.vnet_2::bucket_size 1 # delay histogram for vnet_2 system.ruby.delayVCHist.vnet_2::max_bucket 9 # delay histogram for vnet_2 system.ruby.delayVCHist.vnet_2::samples 83197 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::mean 0.000192 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::stdev 0.019611 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2 | 83189 99.99% 99.99% | 0 0.00% 99.99% | 8 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::mean 0.000144 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::stdev 0.016984 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2 | 83191 99.99% 99.99% | 0 0.00% 99.99% | 6 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2 system.ruby.delayVCHist.vnet_2::total 83197 # delay histogram for vnet_2 system.ruby.LD.latency_hist::bucket_size 128 system.ruby.LD.latency_hist::max_bucket 1279 -system.ruby.LD.latency_hist::samples 15027912 -system.ruby.LD.latency_hist::mean 4.869020 -system.ruby.LD.latency_hist::gmean 3.591147 -system.ruby.LD.latency_hist::stdev 9.231737 -system.ruby.LD.latency_hist | 15011958 99.89% 99.89% | 13851 0.09% 99.99% | 851 0.01% 99.99% | 792 0.01% 100.00% | 329 0.00% 100.00% | 121 0.00% 100.00% | 2 0.00% 100.00% | 3 0.00% 100.00% | 4 0.00% 100.00% | 1 0.00% 100.00% -system.ruby.LD.latency_hist::total 15027912 +system.ruby.LD.latency_hist::samples 15027915 +system.ruby.LD.latency_hist::mean 4.869031 +system.ruby.LD.latency_hist::gmean 3.591146 +system.ruby.LD.latency_hist::stdev 9.232635 +system.ruby.LD.latency_hist | 15011953 99.89% 99.89% | 13856 0.09% 99.99% | 858 0.01% 99.99% | 788 0.01% 100.00% | 329 0.00% 100.00% | 120 0.00% 100.00% | 2 0.00% 100.00% | 4 0.00% 100.00% | 4 0.00% 100.00% | 1 0.00% 100.00% +system.ruby.LD.latency_hist::total 15027915 system.ruby.LD.hit_latency_hist::bucket_size 1 system.ruby.LD.hit_latency_hist::max_bucket 9 -system.ruby.LD.hit_latency_hist::samples 13637263 +system.ruby.LD.hit_latency_hist::samples 13637262 system.ruby.LD.hit_latency_hist::mean 3 system.ruby.LD.hit_latency_hist::gmean 3.000000 -system.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 13637263 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.hit_latency_hist::total 13637263 +system.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 13637262 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.hit_latency_hist::total 13637262 system.ruby.LD.miss_latency_hist::bucket_size 128 system.ruby.LD.miss_latency_hist::max_bucket 1279 -system.ruby.LD.miss_latency_hist::samples 1390649 -system.ruby.LD.miss_latency_hist::mean 23.197386 -system.ruby.LD.miss_latency_hist::gmean 20.952196 -system.ruby.LD.miss_latency_hist::stdev 23.468925 -system.ruby.LD.miss_latency_hist | 1374695 98.85% 98.85% | 13851 1.00% 99.85% | 851 0.06% 99.91% | 792 0.06% 99.97% | 329 0.02% 99.99% | 121 0.01% 100.00% | 2 0.00% 100.00% | 3 0.00% 100.00% | 4 0.00% 100.00% | 1 0.00% 100.00% -system.ruby.LD.miss_latency_hist::total 1390649 +system.ruby.LD.miss_latency_hist::samples 1390653 +system.ruby.LD.miss_latency_hist::mean 23.197446 +system.ruby.LD.miss_latency_hist::gmean 20.952063 +system.ruby.LD.miss_latency_hist::stdev 23.472645 +system.ruby.LD.miss_latency_hist | 1374691 98.85% 98.85% | 13856 1.00% 99.85% | 858 0.06% 99.91% | 788 0.06% 99.97% | 329 0.02% 99.99% | 120 0.01% 100.00% | 2 0.00% 100.00% | 4 0.00% 100.00% | 4 0.00% 100.00% | 1 0.00% 100.00% +system.ruby.LD.miss_latency_hist::total 1390653 system.ruby.ST.latency_hist::bucket_size 128 system.ruby.ST.latency_hist::max_bucket 1279 system.ruby.ST.latency_hist::samples 9558783 -system.ruby.ST.latency_hist::mean 5.170026 -system.ruby.ST.latency_hist::gmean 3.300098 -system.ruby.ST.latency_hist::stdev 17.579302 -system.ruby.ST.latency_hist | 9544781 99.85% 99.85% | 8164 0.09% 99.94% | 1330 0.01% 99.95% | 2504 0.03% 99.98% | 1628 0.02% 100.00% | 340 0.00% 100.00% | 7 0.00% 100.00% | 12 0.00% 100.00% | 11 0.00% 100.00% | 6 0.00% 100.00% +system.ruby.ST.latency_hist::mean 5.169851 +system.ruby.ST.latency_hist::gmean 3.300097 +system.ruby.ST.latency_hist::stdev 17.574774 +system.ruby.ST.latency_hist | 9544786 99.85% 99.85% | 8165 0.09% 99.94% | 1340 0.01% 99.95% | 2484 0.03% 99.98% | 1636 0.02% 100.00% | 338 0.00% 100.00% | 8 0.00% 100.00% | 10 0.00% 100.00% | 10 0.00% 100.00% | 6 0.00% 100.00% system.ruby.ST.latency_hist::total 9558783 system.ruby.ST.hit_latency_hist::bucket_size 1 system.ruby.ST.hit_latency_hist::max_bucket 9 @@ -939,41 +939,41 @@ system.ruby.ST.hit_latency_hist::total 9207752 system.ruby.ST.miss_latency_hist::bucket_size 128 system.ruby.ST.miss_latency_hist::max_bucket 1279 system.ruby.ST.miss_latency_hist::samples 351031 -system.ruby.ST.miss_latency_hist::mean 62.091086 -system.ruby.ST.miss_latency_hist::gmean 40.236579 -system.ruby.ST.miss_latency_hist::stdev 71.074662 -system.ruby.ST.miss_latency_hist | 337029 96.01% 96.01% | 8164 2.33% 98.34% | 1330 0.38% 98.72% | 2504 0.71% 99.43% | 1628 0.46% 99.89% | 340 0.10% 99.99% | 7 0.00% 99.99% | 12 0.00% 100.00% | 11 0.00% 100.00% | 6 0.00% 100.00% +system.ruby.ST.miss_latency_hist::mean 62.086337 +system.ruby.ST.miss_latency_hist::gmean 40.235982 +system.ruby.ST.miss_latency_hist::stdev 71.047969 +system.ruby.ST.miss_latency_hist | 337034 96.01% 96.01% | 8165 2.33% 98.34% | 1340 0.38% 98.72% | 2484 0.71% 99.43% | 1636 0.47% 99.89% | 338 0.10% 99.99% | 8 0.00% 99.99% | 10 0.00% 100.00% | 10 0.00% 100.00% | 6 0.00% 100.00% system.ruby.ST.miss_latency_hist::total 351031 system.ruby.IFETCH.latency_hist::bucket_size 128 system.ruby.IFETCH.latency_hist::max_bucket 1279 -system.ruby.IFETCH.latency_hist::samples 126996315 -system.ruby.IFETCH.latency_hist::mean 3.119134 +system.ruby.IFETCH.latency_hist::samples 126996328 +system.ruby.IFETCH.latency_hist::mean 3.119146 system.ruby.IFETCH.latency_hist::gmean 3.036572 -system.ruby.IFETCH.latency_hist::stdev 2.233716 -system.ruby.IFETCH.latency_hist | 126989642 99.99% 99.99% | 5673 0.00% 100.00% | 484 0.00% 100.00% | 317 0.00% 100.00% | 137 0.00% 100.00% | 55 0.00% 100.00% | 0 0.00% 100.00% | 5 0.00% 100.00% | 2 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.latency_hist::total 126996315 +system.ruby.IFETCH.latency_hist::stdev 2.235323 +system.ruby.IFETCH.latency_hist | 126989653 99.99% 99.99% | 5672 0.00% 100.00% | 481 0.00% 100.00% | 320 0.00% 100.00% | 141 0.00% 100.00% | 54 0.00% 100.00% | 0 0.00% 100.00% | 5 0.00% 100.00% | 2 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.latency_hist::total 126996328 system.ruby.IFETCH.hit_latency_hist::bucket_size 1 system.ruby.IFETCH.hit_latency_hist::max_bucket 9 -system.ruby.IFETCH.hit_latency_hist::samples 126180135 +system.ruby.IFETCH.hit_latency_hist::samples 126180143 system.ruby.IFETCH.hit_latency_hist::mean 3 system.ruby.IFETCH.hit_latency_hist::gmean 3.000000 -system.ruby.IFETCH.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 126180135 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.hit_latency_hist::total 126180135 +system.ruby.IFETCH.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 126180143 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.hit_latency_hist::total 126180143 system.ruby.IFETCH.miss_latency_hist::bucket_size 128 system.ruby.IFETCH.miss_latency_hist::max_bucket 1279 -system.ruby.IFETCH.miss_latency_hist::samples 816180 -system.ruby.IFETCH.miss_latency_hist::mean 21.537108 -system.ruby.IFETCH.miss_latency_hist::gmean 19.766480 -system.ruby.IFETCH.miss_latency_hist::stdev 20.855244 -system.ruby.IFETCH.miss_latency_hist | 809507 99.18% 99.18% | 5673 0.70% 99.88% | 484 0.06% 99.94% | 317 0.04% 99.98% | 137 0.02% 99.99% | 55 0.01% 100.00% | 0 0.00% 100.00% | 5 0.00% 100.00% | 2 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.miss_latency_hist::total 816180 +system.ruby.IFETCH.miss_latency_hist::samples 816185 +system.ruby.IFETCH.miss_latency_hist::mean 21.538739 +system.ruby.IFETCH.miss_latency_hist::gmean 19.766603 +system.ruby.IFETCH.miss_latency_hist::stdev 20.880467 +system.ruby.IFETCH.miss_latency_hist | 809510 99.18% 99.18% | 5672 0.69% 99.88% | 481 0.06% 99.94% | 320 0.04% 99.98% | 141 0.02% 99.99% | 54 0.01% 100.00% | 0 0.00% 100.00% | 5 0.00% 100.00% | 2 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.miss_latency_hist::total 816185 system.ruby.RMW_Read.latency_hist::bucket_size 128 system.ruby.RMW_Read.latency_hist::max_bucket 1279 system.ruby.RMW_Read.latency_hist::samples 494272 -system.ruby.RMW_Read.latency_hist::mean 6.020764 -system.ruby.RMW_Read.latency_hist::gmean 3.952362 -system.ruby.RMW_Read.latency_hist::stdev 10.313773 -system.ruby.RMW_Read.latency_hist | 494092 99.96% 99.96% | 129 0.03% 99.99% | 18 0.00% 99.99% | 18 0.00% 100.00% | 11 0.00% 100.00% | 4 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.RMW_Read.latency_hist::mean 6.021773 +system.ruby.RMW_Read.latency_hist::gmean 3.952377 +system.ruby.RMW_Read.latency_hist::stdev 10.350675 +system.ruby.RMW_Read.latency_hist | 494091 99.96% 99.96% | 129 0.03% 99.99% | 18 0.00% 99.99% | 18 0.00% 100.00% | 12 0.00% 100.00% | 4 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.RMW_Read.latency_hist::total 494272 system.ruby.RMW_Read.hit_latency_hist::bucket_size 1 system.ruby.RMW_Read.hit_latency_hist::max_bucket 9 @@ -985,18 +985,18 @@ system.ruby.RMW_Read.hit_latency_hist::total 428940 system.ruby.RMW_Read.miss_latency_hist::bucket_size 128 system.ruby.RMW_Read.miss_latency_hist::max_bucket 1279 system.ruby.RMW_Read.miss_latency_hist::samples 65332 -system.ruby.RMW_Read.miss_latency_hist::mean 25.853716 -system.ruby.RMW_Read.miss_latency_hist::gmean 24.153784 -system.ruby.RMW_Read.miss_latency_hist::stdev 18.748956 -system.ruby.RMW_Read.miss_latency_hist | 65152 99.72% 99.72% | 129 0.20% 99.92% | 18 0.03% 99.95% | 18 0.03% 99.98% | 11 0.02% 99.99% | 4 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.RMW_Read.miss_latency_hist::mean 25.861354 +system.ruby.RMW_Read.miss_latency_hist::gmean 24.154461 +system.ruby.RMW_Read.miss_latency_hist::stdev 18.894168 +system.ruby.RMW_Read.miss_latency_hist | 65151 99.72% 99.72% | 129 0.20% 99.92% | 18 0.03% 99.95% | 18 0.03% 99.98% | 12 0.02% 99.99% | 4 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.RMW_Read.miss_latency_hist::total 65332 system.ruby.Locked_RMW_Read.latency_hist::bucket_size 128 system.ruby.Locked_RMW_Read.latency_hist::max_bucket 1279 system.ruby.Locked_RMW_Read.latency_hist::samples 339654 -system.ruby.Locked_RMW_Read.latency_hist::mean 5.351331 -system.ruby.Locked_RMW_Read.latency_hist::gmean 3.780101 -system.ruby.Locked_RMW_Read.latency_hist::stdev 8.370233 -system.ruby.Locked_RMW_Read.latency_hist | 339398 99.92% 99.92% | 231 0.07% 99.99% | 12 0.00% 100.00% | 6 0.00% 100.00% | 4 0.00% 100.00% | 3 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Locked_RMW_Read.latency_hist::mean 5.350042 +system.ruby.Locked_RMW_Read.latency_hist::gmean 3.780078 +system.ruby.Locked_RMW_Read.latency_hist::stdev 8.318496 +system.ruby.Locked_RMW_Read.latency_hist | 339398 99.92% 99.92% | 232 0.07% 99.99% | 12 0.00% 100.00% | 6 0.00% 100.00% | 3 0.00% 100.00% | 3 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.Locked_RMW_Read.latency_hist::total 339654 system.ruby.Locked_RMW_Read.hit_latency_hist::bucket_size 1 system.ruby.Locked_RMW_Read.hit_latency_hist::max_bucket 9 @@ -1008,10 +1008,10 @@ system.ruby.Locked_RMW_Read.hit_latency_hist::total 300589 system.ruby.Locked_RMW_Read.miss_latency_hist::bucket_size 128 system.ruby.Locked_RMW_Read.miss_latency_hist::max_bucket 1279 system.ruby.Locked_RMW_Read.miss_latency_hist::samples 39065 -system.ruby.Locked_RMW_Read.miss_latency_hist::mean 23.443850 -system.ruby.Locked_RMW_Read.miss_latency_hist::gmean 22.382210 -system.ruby.Locked_RMW_Read.miss_latency_hist::stdev 15.468459 -system.ruby.Locked_RMW_Read.miss_latency_hist | 38809 99.34% 99.34% | 231 0.59% 99.94% | 12 0.03% 99.97% | 6 0.02% 99.98% | 4 0.01% 99.99% | 3 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Locked_RMW_Read.miss_latency_hist::mean 23.432638 +system.ruby.Locked_RMW_Read.miss_latency_hist::gmean 22.380989 +system.ruby.Locked_RMW_Read.miss_latency_hist::stdev 15.237176 +system.ruby.Locked_RMW_Read.miss_latency_hist | 38809 99.34% 99.34% | 232 0.59% 99.94% | 12 0.03% 99.97% | 6 0.02% 99.98% | 3 0.01% 99.99% | 3 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.Locked_RMW_Read.miss_latency_hist::total 39065 system.ruby.Locked_RMW_Write.latency_hist::bucket_size 1 system.ruby.Locked_RMW_Write.latency_hist::max_bucket 9 @@ -1065,16 +1065,16 @@ system.ruby.DMA_Controller.BUSY_RD.Data | 809 100.00% 100.00% | system.ruby.DMA_Controller.BUSY_RD.Data::total 809 system.ruby.DMA_Controller.BUSY_WR.Ack | 46736 100.00% 100.00% | 0 0.00% 100.00% system.ruby.DMA_Controller.BUSY_WR.Ack::total 46736 -system.ruby.L1Cache_Controller.Load | 6279317 41.78% 41.78% | 8748595 58.22% 100.00% -system.ruby.L1Cache_Controller.Load::total 15027912 -system.ruby.L1Cache_Controller.Ifetch | 68812914 54.18% 54.18% | 58183407 45.82% 100.00% -system.ruby.L1Cache_Controller.Ifetch::total 126996321 +system.ruby.L1Cache_Controller.Load | 6279318 41.78% 41.78% | 8748597 58.22% 100.00% +system.ruby.L1Cache_Controller.Load::total 15027915 +system.ruby.L1Cache_Controller.Ifetch | 68812918 54.18% 54.18% | 58183416 45.82% 100.00% +system.ruby.L1Cache_Controller.Ifetch::total 126996334 system.ruby.L1Cache_Controller.Store | 5372446 50.06% 50.06% | 5359917 49.94% 100.00% system.ruby.L1Cache_Controller.Store::total 10732363 system.ruby.L1Cache_Controller.Inv | 16157 48.07% 48.07% | 17455 51.93% 100.00% system.ruby.L1Cache_Controller.Inv::total 33612 -system.ruby.L1Cache_Controller.L1_Replacement | 828605 31.79% 31.79% | 1777971 68.21% 100.00% -system.ruby.L1Cache_Controller.L1_Replacement::total 2606576 +system.ruby.L1Cache_Controller.L1_Replacement | 828612 31.79% 31.79% | 1777973 68.21% 100.00% +system.ruby.L1Cache_Controller.L1_Replacement::total 2606585 system.ruby.L1Cache_Controller.Fwd_GETX | 12248 51.07% 51.07% | 11736 48.93% 100.00% system.ruby.L1Cache_Controller.Fwd_GETX::total 23984 system.ruby.L1Cache_Controller.Fwd_GETS | 14251 55.67% 55.67% | 11346 44.33% 100.00% @@ -1083,23 +1083,23 @@ system.ruby.L1Cache_Controller.Fwd_GET_INSTR | 4 100.00% 100.00% system.ruby.L1Cache_Controller.Fwd_GET_INSTR::total 4 system.ruby.L1Cache_Controller.Data | 818 44.46% 44.46% | 1022 55.54% 100.00% system.ruby.L1Cache_Controller.Data::total 1840 -system.ruby.L1Cache_Controller.Data_Exclusive | 252712 19.73% 19.73% | 1028027 80.27% 100.00% -system.ruby.L1Cache_Controller.Data_Exclusive::total 1280739 +system.ruby.L1Cache_Controller.Data_Exclusive | 252714 19.73% 19.73% | 1028028 80.27% 100.00% +system.ruby.L1Cache_Controller.Data_Exclusive::total 1280742 system.ruby.L1Cache_Controller.DataS_fromL1 | 11346 44.32% 44.32% | 14255 55.68% 100.00% system.ruby.L1Cache_Controller.DataS_fromL1::total 25601 -system.ruby.L1Cache_Controller.Data_all_Acks | 579316 43.50% 43.50% | 752306 56.50% 100.00% -system.ruby.L1Cache_Controller.Data_all_Acks::total 1331622 +system.ruby.L1Cache_Controller.Data_all_Acks | 579321 43.50% 43.50% | 752307 56.50% 100.00% +system.ruby.L1Cache_Controller.Data_all_Acks::total 1331628 system.ruby.L1Cache_Controller.Ack | 12225 54.44% 54.44% | 10230 45.56% 100.00% system.ruby.L1Cache_Controller.Ack::total 22455 system.ruby.L1Cache_Controller.Ack_all | 13043 53.69% 53.69% | 11252 46.31% 100.00% system.ruby.L1Cache_Controller.Ack_all::total 24295 -system.ruby.L1Cache_Controller.WB_Ack | 468894 27.82% 27.82% | 1216556 72.18% 100.00% -system.ruby.L1Cache_Controller.WB_Ack::total 1685450 -system.ruby.L1Cache_Controller.NP.Load | 280382 20.44% 20.44% | 1091184 79.56% 100.00% -system.ruby.L1Cache_Controller.NP.Load::total 1371566 -system.ruby.L1Cache_Controller.NP.Ifetch | 323814 39.71% 39.71% | 491732 60.29% 100.00% -system.ruby.L1Cache_Controller.NP.Ifetch::total 815546 -system.ruby.L1Cache_Controller.NP.Store | 225433 53.48% 53.48% | 196079 46.52% 100.00% +system.ruby.L1Cache_Controller.WB_Ack | 468895 27.82% 27.82% | 1216558 72.18% 100.00% +system.ruby.L1Cache_Controller.WB_Ack::total 1685453 +system.ruby.L1Cache_Controller.NP.Load | 280385 20.44% 20.44% | 1091185 79.56% 100.00% +system.ruby.L1Cache_Controller.NP.Load::total 1371570 +system.ruby.L1Cache_Controller.NP.Ifetch | 323819 39.71% 39.71% | 491732 60.29% 100.00% +system.ruby.L1Cache_Controller.NP.Ifetch::total 815551 +system.ruby.L1Cache_Controller.NP.Store | 225432 53.48% 53.48% | 196080 46.52% 100.00% system.ruby.L1Cache_Controller.NP.Store::total 421512 system.ruby.L1Cache_Controller.NP.Inv | 4849 54.09% 54.09% | 4115 45.91% 100.00% system.ruby.L1Cache_Controller.NP.Inv::total 8964 @@ -1111,51 +1111,51 @@ system.ruby.L1Cache_Controller.I.Store | 5739 50.07% 50.07% | system.ruby.L1Cache_Controller.I.Store::total 11461 system.ruby.L1Cache_Controller.I.L1_Replacement | 8993 51.78% 51.78% | 8375 48.22% 100.00% system.ruby.L1Cache_Controller.I.L1_Replacement::total 17368 -system.ruby.L1Cache_Controller.S.Load | 555624 51.88% 51.88% | 515377 48.12% 100.00% +system.ruby.L1Cache_Controller.S.Load | 555622 51.88% 51.88% | 515379 48.12% 100.00% system.ruby.L1Cache_Controller.S.Load::total 1071001 -system.ruby.L1Cache_Controller.S.Ifetch | 68488995 54.28% 54.28% | 57691140 45.72% 100.00% -system.ruby.L1Cache_Controller.S.Ifetch::total 126180135 +system.ruby.L1Cache_Controller.S.Ifetch | 68488994 54.28% 54.28% | 57691149 45.72% 100.00% +system.ruby.L1Cache_Controller.S.Ifetch::total 126180143 system.ruby.L1Cache_Controller.S.Store | 12225 54.44% 54.44% | 10230 45.56% 100.00% system.ruby.L1Cache_Controller.S.Store::total 22455 system.ruby.L1Cache_Controller.S.Inv | 11078 45.79% 45.79% | 13115 54.21% 100.00% system.ruby.L1Cache_Controller.S.Inv::total 24193 -system.ruby.L1Cache_Controller.S.L1_Replacement | 350718 38.81% 38.81% | 553040 61.19% 100.00% -system.ruby.L1Cache_Controller.S.L1_Replacement::total 903758 -system.ruby.L1Cache_Controller.E.Load | 1152084 29.74% 29.74% | 2722150 70.26% 100.00% -system.ruby.L1Cache_Controller.E.Load::total 3874234 -system.ruby.L1Cache_Controller.E.Store | 80726 48.37% 48.37% | 86165 51.63% 100.00% -system.ruby.L1Cache_Controller.E.Store::total 166891 +system.ruby.L1Cache_Controller.S.L1_Replacement | 350724 38.81% 38.81% | 553040 61.19% 100.00% +system.ruby.L1Cache_Controller.S.L1_Replacement::total 903764 +system.ruby.L1Cache_Controller.E.Load | 1152088 29.74% 29.74% | 2722151 70.26% 100.00% +system.ruby.L1Cache_Controller.E.Load::total 3874239 +system.ruby.L1Cache_Controller.E.Store | 80728 48.37% 48.37% | 86165 51.63% 100.00% +system.ruby.L1Cache_Controller.E.Store::total 166893 system.ruby.L1Cache_Controller.E.Inv | 52 59.77% 59.77% | 35 40.23% 100.00% system.ruby.L1Cache_Controller.E.Inv::total 87 -system.ruby.L1Cache_Controller.E.L1_Replacement | 170402 15.34% 15.34% | 940436 84.66% 100.00% -system.ruby.L1Cache_Controller.E.L1_Replacement::total 1110838 +system.ruby.L1Cache_Controller.E.L1_Replacement | 170402 15.34% 15.34% | 940437 84.66% 100.00% +system.ruby.L1Cache_Controller.E.L1_Replacement::total 1110839 system.ruby.L1Cache_Controller.E.Fwd_GETX | 330 72.53% 72.53% | 125 27.47% 100.00% system.ruby.L1Cache_Controller.E.Fwd_GETX::total 455 system.ruby.L1Cache_Controller.E.Fwd_GETS | 996 45.17% 45.17% | 1209 54.83% 100.00% system.ruby.L1Cache_Controller.E.Fwd_GETS::total 2205 -system.ruby.L1Cache_Controller.M.Load | 4282503 49.27% 49.27% | 4409525 50.73% 100.00% -system.ruby.L1Cache_Controller.M.Load::total 8692028 -system.ruby.L1Cache_Controller.M.Store | 5048323 49.93% 49.93% | 5061721 50.07% 100.00% -system.ruby.L1Cache_Controller.M.Store::total 10110044 +system.ruby.L1Cache_Controller.M.Load | 4282499 49.27% 49.27% | 4409523 50.73% 100.00% +system.ruby.L1Cache_Controller.M.Load::total 8692022 +system.ruby.L1Cache_Controller.M.Store | 5048322 49.93% 49.93% | 5061720 50.07% 100.00% +system.ruby.L1Cache_Controller.M.Store::total 10110042 system.ruby.L1Cache_Controller.M.Inv | 178 48.37% 48.37% | 190 51.63% 100.00% system.ruby.L1Cache_Controller.M.Inv::total 368 -system.ruby.L1Cache_Controller.M.L1_Replacement | 298492 51.95% 51.95% | 276120 48.05% 100.00% -system.ruby.L1Cache_Controller.M.L1_Replacement::total 574612 +system.ruby.L1Cache_Controller.M.L1_Replacement | 298493 51.95% 51.95% | 276121 48.05% 100.00% +system.ruby.L1Cache_Controller.M.L1_Replacement::total 574614 system.ruby.L1Cache_Controller.M.Fwd_GETX | 11918 50.65% 50.65% | 11611 49.35% 100.00% system.ruby.L1Cache_Controller.M.Fwd_GETX::total 23529 system.ruby.L1Cache_Controller.M.Fwd_GETS | 13255 56.66% 56.66% | 10137 43.34% 100.00% system.ruby.L1Cache_Controller.M.Fwd_GETS::total 23392 system.ruby.L1Cache_Controller.M.Fwd_GET_INSTR | 4 100.00% 100.00% | 0 0.00% 100.00% system.ruby.L1Cache_Controller.M.Fwd_GET_INSTR::total 4 -system.ruby.L1Cache_Controller.IS.Data_Exclusive | 252712 19.73% 19.73% | 1028027 80.27% 100.00% -system.ruby.L1Cache_Controller.IS.Data_Exclusive::total 1280739 +system.ruby.L1Cache_Controller.IS.Data_Exclusive | 252714 19.73% 19.73% | 1028028 80.27% 100.00% +system.ruby.L1Cache_Controller.IS.Data_Exclusive::total 1280742 system.ruby.L1Cache_Controller.IS.DataS_fromL1 | 11346 44.32% 44.32% | 14255 55.68% 100.00% system.ruby.L1Cache_Controller.IS.DataS_fromL1::total 25601 -system.ruby.L1Cache_Controller.IS.Data_all_Acks | 348962 38.75% 38.75% | 551527 61.25% 100.00% -system.ruby.L1Cache_Controller.IS.Data_all_Acks::total 900489 +system.ruby.L1Cache_Controller.IS.Data_all_Acks | 348968 38.75% 38.75% | 551527 61.25% 100.00% +system.ruby.L1Cache_Controller.IS.Data_all_Acks::total 900495 system.ruby.L1Cache_Controller.IM.Data | 818 44.46% 44.46% | 1022 55.54% 100.00% system.ruby.L1Cache_Controller.IM.Data::total 1840 -system.ruby.L1Cache_Controller.IM.Data_all_Acks | 230354 53.43% 53.43% | 200779 46.57% 100.00% +system.ruby.L1Cache_Controller.IM.Data_all_Acks | 230353 53.43% 53.43% | 200780 46.57% 100.00% system.ruby.L1Cache_Controller.IM.Data_all_Acks::total 431133 system.ruby.L1Cache_Controller.SM.Ack | 12225 54.44% 54.44% | 10230 45.56% 100.00% system.ruby.L1Cache_Controller.SM.Ack::total 22455 @@ -1163,13 +1163,13 @@ system.ruby.L1Cache_Controller.SM.Ack_all | 13043 53.69% 53.69% | system.ruby.L1Cache_Controller.SM.Ack_all::total 24295 system.ruby.L1Cache_Controller.M_I.Ifetch | 5 83.33% 83.33% | 1 16.67% 100.00% system.ruby.L1Cache_Controller.M_I.Ifetch::total 6 -system.ruby.L1Cache_Controller.M_I.WB_Ack | 468894 27.82% 27.82% | 1216556 72.18% 100.00% -system.ruby.L1Cache_Controller.M_I.WB_Ack::total 1685450 -system.ruby.L2Cache_Controller.L1_GET_INSTR 816180 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_GETS 1390821 0.00% 0.00% +system.ruby.L1Cache_Controller.M_I.WB_Ack | 468895 27.82% 27.82% | 1216558 72.18% 100.00% +system.ruby.L1Cache_Controller.M_I.WB_Ack::total 1685453 +system.ruby.L2Cache_Controller.L1_GET_INSTR 816185 0.00% 0.00% +system.ruby.L2Cache_Controller.L1_GETS 1390825 0.00% 0.00% system.ruby.L2Cache_Controller.L1_GETX 432975 0.00% 0.00% system.ruby.L2Cache_Controller.L1_UPGRADE 22455 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_PUTX 1685450 0.00% 0.00% +system.ruby.L2Cache_Controller.L1_PUTX 1685453 0.00% 0.00% system.ruby.L2Cache_Controller.L2_Replacement 95536 0.00% 0.00% system.ruby.L2Cache_Controller.L2_Replacement_clean 15120 0.00% 0.00% system.ruby.L2Cache_Controller.Mem_Data 177212 0.00% 0.00% @@ -1179,20 +1179,20 @@ system.ruby.L2Cache_Controller.WB_Data_clean 2205 0.00% 0.00% system.ruby.L2Cache_Controller.Ack 1487 0.00% 0.00% system.ruby.L2Cache_Controller.Ack_all 7462 0.00% 0.00% system.ruby.L2Cache_Controller.Unblock 25601 0.00% 0.00% -system.ruby.L2Cache_Controller.Exclusive_Unblock 1736167 0.00% 0.00% +system.ruby.L2Cache_Controller.Exclusive_Unblock 1736170 0.00% 0.00% system.ruby.L2Cache_Controller.MEM_Inv 3550 0.00% 0.00% system.ruby.L2Cache_Controller.NP.L1_GET_INSTR 16316 0.00% 0.00% system.ruby.L2Cache_Controller.NP.L1_GETS 33914 0.00% 0.00% system.ruby.L2Cache_Controller.NP.L1_GETX 126982 0.00% 0.00% -system.ruby.L2Cache_Controller.SS.L1_GET_INSTR 799834 0.00% 0.00% -system.ruby.L2Cache_Controller.SS.L1_GETS 84313 0.00% 0.00% +system.ruby.L2Cache_Controller.SS.L1_GET_INSTR 799839 0.00% 0.00% +system.ruby.L2Cache_Controller.SS.L1_GETS 84314 0.00% 0.00% system.ruby.L2Cache_Controller.SS.L1_GETX 1944 0.00% 0.00% system.ruby.L2Cache_Controller.SS.L1_UPGRADE 22455 0.00% 0.00% system.ruby.L2Cache_Controller.SS.L2_Replacement 252 0.00% 0.00% system.ruby.L2Cache_Controller.SS.L2_Replacement_clean 7120 0.00% 0.00% system.ruby.L2Cache_Controller.SS.MEM_Inv 3 0.00% 0.00% system.ruby.L2Cache_Controller.M.L1_GET_INSTR 26 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L1_GETS 1246825 0.00% 0.00% +system.ruby.L2Cache_Controller.M.L1_GETS 1246828 0.00% 0.00% system.ruby.L2Cache_Controller.M.L1_GETX 280063 0.00% 0.00% system.ruby.L2Cache_Controller.M.L2_Replacement 95163 0.00% 0.00% system.ruby.L2Cache_Controller.M.L2_Replacement_clean 7896 0.00% 0.00% @@ -1200,7 +1200,7 @@ system.ruby.L2Cache_Controller.M.MEM_Inv 1542 0.00% 0.00% system.ruby.L2Cache_Controller.MT.L1_GET_INSTR 4 0.00% 0.00% system.ruby.L2Cache_Controller.MT.L1_GETS 25597 0.00% 0.00% system.ruby.L2Cache_Controller.MT.L1_GETX 23984 0.00% 0.00% -system.ruby.L2Cache_Controller.MT.L1_PUTX 1685450 0.00% 0.00% +system.ruby.L2Cache_Controller.MT.L1_PUTX 1685453 0.00% 0.00% system.ruby.L2Cache_Controller.MT.L2_Replacement 121 0.00% 0.00% system.ruby.L2Cache_Controller.MT.L2_Replacement_clean 104 0.00% 0.00% system.ruby.L2Cache_Controller.MT.MEM_Inv 230 0.00% 0.00% @@ -1219,15 +1219,15 @@ system.ruby.L2Cache_Controller.S_I.MEM_Inv 3 0.00% 0.00% system.ruby.L2Cache_Controller.ISS.Mem_Data 33914 0.00% 0.00% system.ruby.L2Cache_Controller.IS.Mem_Data 16316 0.00% 0.00% system.ruby.L2Cache_Controller.IM.Mem_Data 126982 0.00% 0.00% -system.ruby.L2Cache_Controller.SS_MB.L1_GETS 122 0.00% 0.00% +system.ruby.L2Cache_Controller.SS_MB.L1_GETS 124 0.00% 0.00% system.ruby.L2Cache_Controller.SS_MB.Exclusive_Unblock 24399 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_MB.L1_GETS 50 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_MB.L1_GETS 48 0.00% 0.00% system.ruby.L2Cache_Controller.MT_MB.L1_GETX 2 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_MB.Exclusive_Unblock 1711768 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_IIB.WB_Data 23385 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_MB.Exclusive_Unblock 1711771 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_IIB.WB_Data 23386 0.00% 0.00% system.ruby.L2Cache_Controller.MT_IIB.WB_Data_clean 2205 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_IIB.Unblock 11 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_IB.WB_Data 11 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_SB.Unblock 25590 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_IIB.Unblock 10 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_IB.WB_Data 10 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_SB.Unblock 25591 0.00% 0.00% ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt index b95a760f1..0dda4ffb8 100644 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt @@ -1,108 +1,108 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.417356 # Number of seconds simulated -sim_ticks 417356445500 # Number of ticks simulated -final_tick 417356445500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.417316 # Number of seconds simulated +sim_ticks 417315805000 # Number of ticks simulated +final_tick 417315805000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 140228 # Simulator instruction rate (inst/s) -host_op_rate 259297 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 70778301 # Simulator tick rate (ticks/s) -host_mem_usage 373852 # Number of bytes of host memory used -host_seconds 5896.67 # Real time elapsed on the host +host_inst_rate 92447 # Simulator instruction rate (inst/s) +host_op_rate 170945 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 46657066 # Simulator tick rate (ticks/s) +host_mem_usage 432180 # Number of bytes of host memory used +host_seconds 8944.32 # Real time elapsed on the host sim_insts 826877109 # Number of instructions simulated sim_ops 1528988701 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 225408 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24527104 # Number of bytes read from this memory -system.physmem.bytes_read::total 24752512 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 225408 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 225408 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 18881792 # Number of bytes written to this memory -system.physmem.bytes_written::total 18881792 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 3522 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 383236 # Number of read requests responded to by this memory -system.physmem.num_reads::total 386758 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 295028 # Number of write requests responded to by this memory -system.physmem.num_writes::total 295028 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 540085 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 58767761 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 59307846 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 540085 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 540085 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 45241405 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 45241405 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 45241405 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 540085 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 58767761 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 104549252 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 386758 # Number of read requests accepted -system.physmem.writeReqs 295028 # Number of write requests accepted -system.physmem.readBursts 386758 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 295028 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 24731520 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 20992 # Total number of bytes read from write queue -system.physmem.bytesWritten 18879872 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 24752512 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 18881792 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 328 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 223744 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24530944 # Number of bytes read from this memory +system.physmem.bytes_read::total 24754688 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 223744 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 223744 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 18881856 # Number of bytes written to this memory +system.physmem.bytes_written::total 18881856 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 3496 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 383296 # Number of read requests responded to by this memory +system.physmem.num_reads::total 386792 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 295029 # Number of write requests responded to by this memory +system.physmem.num_writes::total 295029 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 536150 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 58782686 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 59318836 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 536150 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 536150 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 45245964 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 45245964 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 45245964 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 536150 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 58782686 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 104564801 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 386792 # Number of read requests accepted +system.physmem.writeReqs 295029 # Number of write requests accepted +system.physmem.readBursts 386792 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 295029 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 24733440 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 21248 # Total number of bytes read from write queue +system.physmem.bytesWritten 18880128 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 24754688 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 18881856 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 332 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 180541 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 24048 # Per bank write bursts -system.physmem.perBankRdBursts::1 26419 # Per bank write bursts -system.physmem.perBankRdBursts::2 24743 # Per bank write bursts -system.physmem.perBankRdBursts::3 24616 # Per bank write bursts -system.physmem.perBankRdBursts::4 23512 # Per bank write bursts -system.physmem.perBankRdBursts::5 23771 # Per bank write bursts -system.physmem.perBankRdBursts::6 24555 # Per bank write bursts -system.physmem.perBankRdBursts::7 24371 # Per bank write bursts -system.physmem.perBankRdBursts::8 23723 # Per bank write bursts -system.physmem.perBankRdBursts::9 23964 # Per bank write bursts -system.physmem.perBankRdBursts::10 24762 # Per bank write bursts -system.physmem.perBankRdBursts::11 24062 # Per bank write bursts -system.physmem.perBankRdBursts::12 23208 # Per bank write bursts -system.physmem.perBankRdBursts::13 22939 # Per bank write bursts -system.physmem.perBankRdBursts::14 23856 # Per bank write bursts -system.physmem.perBankRdBursts::15 23881 # Per bank write bursts -system.physmem.perBankWrBursts::0 18611 # Per bank write bursts -system.physmem.perBankWrBursts::1 19928 # Per bank write bursts -system.physmem.perBankWrBursts::2 18984 # Per bank write bursts -system.physmem.perBankWrBursts::3 19007 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 179000 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 24059 # Per bank write bursts +system.physmem.perBankRdBursts::1 26401 # Per bank write bursts +system.physmem.perBankRdBursts::2 24741 # Per bank write bursts +system.physmem.perBankRdBursts::3 24611 # Per bank write bursts +system.physmem.perBankRdBursts::4 23500 # Per bank write bursts +system.physmem.perBankRdBursts::5 23770 # Per bank write bursts +system.physmem.perBankRdBursts::6 24546 # Per bank write bursts +system.physmem.perBankRdBursts::7 24382 # Per bank write bursts +system.physmem.perBankRdBursts::8 23722 # Per bank write bursts +system.physmem.perBankRdBursts::9 23975 # Per bank write bursts +system.physmem.perBankRdBursts::10 24786 # Per bank write bursts +system.physmem.perBankRdBursts::11 24066 # Per bank write bursts +system.physmem.perBankRdBursts::12 23221 # Per bank write bursts +system.physmem.perBankRdBursts::13 22949 # Per bank write bursts +system.physmem.perBankRdBursts::14 23843 # Per bank write bursts +system.physmem.perBankRdBursts::15 23888 # Per bank write bursts +system.physmem.perBankWrBursts::0 18612 # Per bank write bursts +system.physmem.perBankWrBursts::1 19924 # Per bank write bursts +system.physmem.perBankWrBursts::2 18985 # Per bank write bursts +system.physmem.perBankWrBursts::3 19009 # Per bank write bursts system.physmem.perBankWrBursts::4 18161 # Per bank write bursts -system.physmem.perBankWrBursts::5 18513 # Per bank write bursts +system.physmem.perBankWrBursts::5 18506 # Per bank write bursts system.physmem.perBankWrBursts::6 19135 # Per bank write bursts -system.physmem.perBankWrBursts::7 19081 # Per bank write bursts +system.physmem.perBankWrBursts::7 19090 # Per bank write bursts system.physmem.perBankWrBursts::8 18676 # Per bank write bursts -system.physmem.perBankWrBursts::9 18213 # Per bank write bursts -system.physmem.perBankWrBursts::10 18882 # Per bank write bursts -system.physmem.perBankWrBursts::11 17764 # Per bank write bursts -system.physmem.perBankWrBursts::12 17392 # Per bank write bursts -system.physmem.perBankWrBursts::13 16995 # Per bank write bursts -system.physmem.perBankWrBursts::14 17799 # Per bank write bursts -system.physmem.perBankWrBursts::15 17857 # Per bank write bursts +system.physmem.perBankWrBursts::9 18214 # Per bank write bursts +system.physmem.perBankWrBursts::10 18884 # Per bank write bursts +system.physmem.perBankWrBursts::11 17768 # Per bank write bursts +system.physmem.perBankWrBursts::12 17389 # Per bank write bursts +system.physmem.perBankWrBursts::13 16996 # Per bank write bursts +system.physmem.perBankWrBursts::14 17798 # Per bank write bursts +system.physmem.perBankWrBursts::15 17855 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 417356409500 # Total gap between requests +system.physmem.totGap 417315698500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 386758 # Read request sizes (log2) +system.physmem.readPktSize::6 386792 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 295028 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 381390 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 4646 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 348 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 40 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.writePktSize::6 295029 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 381444 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 4617 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 346 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 42 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 10 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -144,32 +144,32 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 6184 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 6581 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 16955 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 17534 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 17616 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 6179 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 6585 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 16949 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 17533 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 17607 # What write queue length does an incoming req see system.physmem.wrQLenPdf::20 17642 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 17650 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 17659 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 17716 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 17676 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 17722 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 17676 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 17730 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 17732 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 17722 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 17878 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 17608 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 17538 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 38 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 17652 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 17664 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 17717 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 17682 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 17732 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 17672 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 17725 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 17728 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 17715 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 17888 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 17610 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 17539 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 36 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 21 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 19 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 18 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 9 # What write queue length does an incoming req see system.physmem.wrQLenPdf::41 9 # What write queue length does an incoming req see system.physmem.wrQLenPdf::42 11 # What write queue length does an incoming req see system.physmem.wrQLenPdf::43 8 # What write queue length does an incoming req see @@ -193,42 +193,42 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 147597 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 295.460965 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 174.362046 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 322.835917 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 54868 37.17% 37.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 40138 27.19% 64.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 13644 9.24% 73.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 7534 5.10% 78.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 5520 3.74% 82.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 3804 2.58% 85.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 3063 2.08% 87.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 2761 1.87% 88.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 16265 11.02% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 147597 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 17512 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 22.065726 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 218.880570 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 17501 99.94% 99.94% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 5 0.03% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-3071 2 0.01% 99.98% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 147495 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 295.684816 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 174.392327 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 323.222401 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 54844 37.18% 37.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 40100 27.19% 64.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 13710 9.30% 73.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 7409 5.02% 78.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 5412 3.67% 82.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 3888 2.64% 84.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 3038 2.06% 87.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2781 1.89% 88.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 16313 11.06% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 147495 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 17511 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 22.068928 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 218.794243 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 17500 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 6 0.03% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-3071 1 0.01% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::3072-4095 2 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::8192-9215 1 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::26624-27647 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 17512 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 17512 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.845477 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.774806 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 2.552021 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 17320 98.90% 98.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 149 0.85% 99.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 19 0.11% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 6 0.03% 99.90% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 17511 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 17511 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.846668 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.775279 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 2.561224 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 17315 98.88% 98.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 151 0.86% 99.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 21 0.12% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 5 0.03% 99.89% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::32-35 3 0.02% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 1 0.01% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 1 0.01% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 1 0.01% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 1 0.01% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 1 0.01% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 2 0.01% 99.93% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::48-51 1 0.01% 99.94% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::56-59 1 0.01% 99.94% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::60-63 1 0.01% 99.95% # Writes before turning the bus around for reads @@ -239,202 +239,202 @@ system.physmem.wrPerTurnAround::100-103 1 0.01% 99.98% # Wr system.physmem.wrPerTurnAround::104-107 1 0.01% 99.99% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::128-131 1 0.01% 99.99% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::212-215 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 17512 # Writes before turning the bus around for reads -system.physmem.totQLat 4304557750 # Total ticks spent queuing -system.physmem.totMemAccLat 11550120250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1932150000 # Total ticks spent in databus transfers -system.physmem.avgQLat 11139.29 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::total 17511 # Writes before turning the bus around for reads +system.physmem.totQLat 4302860250 # Total ticks spent queuing +system.physmem.totMemAccLat 11548985250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1932300000 # Total ticks spent in databus transfers +system.physmem.avgQLat 11134.04 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29889.29 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 59.26 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 29884.04 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 59.27 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 45.24 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 59.31 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 45.24 # Average system write bandwidth in MiByte/s +system.physmem.avgRdBWSys 59.32 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 45.25 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.82 # Data bus utilization in percentage system.physmem.busUtilRead 0.46 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.35 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.06 # Average read queue length when enqueuing -system.physmem.avgWrQLen 22.21 # Average write queue length when enqueuing -system.physmem.readRowHits 317938 # Number of row buffer hits during reads -system.physmem.writeRowHits 215878 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.28 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 73.17 # Row buffer hit rate for writes -system.physmem.avgGap 612151.63 # Average gap between requests -system.physmem.pageHitRate 78.33 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 570447360 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 311256000 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1528917000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 980987760 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 27259324560 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 63572985495 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 194644842750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 288868760925 # Total energy per rank (pJ) -system.physmem_0.averagePower 692.148188 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 323251825500 # Time in different power states -system.physmem_0.memoryStateTime::REF 13936260000 # Time in different power states +system.physmem.avgWrQLen 22.40 # Average write queue length when enqueuing +system.physmem.readRowHits 318003 # Number of row buffer hits during reads +system.physmem.writeRowHits 215951 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.29 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 73.20 # Row buffer hit rate for writes +system.physmem.avgGap 612060.49 # Average gap between requests +system.physmem.pageHitRate 78.35 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 569562840 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 310773375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1528737600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 980981280 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 27256781760 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 63486572355 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 194697293250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 288830702460 # Total energy per rank (pJ) +system.physmem_0.averagePower 692.121537 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 323337240250 # Time in different power states +system.physmem_0.memoryStateTime::REF 13934960000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 80164105500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 80039955000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 545007960 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 297375375 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1484620800 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 930178080 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 27259324560 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 61751757690 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 196242411000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 288510675465 # Total energy per rank (pJ) -system.physmem_1.averagePower 691.290192 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 325923337000 # Time in different power states -system.physmem_1.memoryStateTime::REF 13936260000 # Time in different power states +system.physmem_1.actEnergy 545136480 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 297445500 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1485127800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 930216960 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 27256781760 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 61714779795 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 196251513750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 288481002045 # Total energy per rank (pJ) +system.physmem_1.averagePower 691.283509 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 325936894250 # Time in different power states +system.physmem_1.memoryStateTime::REF 13934960000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 77492261000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 77440301000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 230114946 # Number of BP lookups -system.cpu.branchPred.condPredicted 230114946 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 9743673 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 131512372 # Number of BTB lookups -system.cpu.branchPred.BTBHits 128773549 # Number of BTB hits +system.cpu.branchPred.lookups 230117471 # Number of BP lookups +system.cpu.branchPred.condPredicted 230117471 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 9743461 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 131565165 # Number of BTB lookups +system.cpu.branchPred.BTBHits 128785895 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 97.917441 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 27735823 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1463178 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 97.887534 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 27740805 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1463511 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 551 # Number of system calls -system.cpu.numCycles 834712892 # number of cpu cycles simulated +system.cpu.numCycles 834631611 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 185096351 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1269592650 # Number of instructions fetch has processed -system.cpu.fetch.Branches 230114946 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 156509372 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 638356055 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 20228139 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 758 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 101258 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 840387 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 2737 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 59 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 179448853 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 2721067 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 4 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 834511674 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.829795 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.382435 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 185091560 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1269611575 # Number of instructions fetch has processed +system.cpu.fetch.Branches 230117471 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 156526700 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 638324625 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 20217139 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 543 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 96744 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 810626 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 1773 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 110 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 179459083 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 2721482 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 2 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 834434550 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.830059 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.382636 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 426826838 51.15% 51.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 33732277 4.04% 55.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 32850671 3.94% 59.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 33472631 4.01% 63.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 27169487 3.26% 66.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 27713856 3.32% 69.71% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 36968785 4.43% 74.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 33631474 4.03% 78.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 182145655 21.83% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 426827210 51.15% 51.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 33688698 4.04% 55.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 32854559 3.94% 59.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 33384869 4.00% 63.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 27147041 3.25% 66.38% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 27739461 3.32% 69.70% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 37019184 4.44% 74.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 33642570 4.03% 78.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 182130958 21.83% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 834511674 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.275682 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.520993 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 127578782 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 374998054 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 240442194 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 81378575 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 10114069 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 2225413878 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 10114069 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 159657843 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 159891555 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 40940 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 285656025 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 219151242 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2175196411 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 168463 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 136638961 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 24413812 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 48161068 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 2279427494 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 5501071808 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3499111667 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 56998 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 834434550 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.275711 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.521164 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 127499737 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 374953474 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 240627559 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 81245211 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 10108569 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 2225588633 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 10108569 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 159647168 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 159927889 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 39744 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 285634401 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 219076779 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2175363345 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 166678 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 136608012 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 24443504 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 48002145 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 2279615876 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 5501425511 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3499355021 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 55759 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1614040854 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 665386640 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 3242 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 3006 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 415340463 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 528372676 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 209866939 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 239161343 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 72330795 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2101128871 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 24703 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1826915153 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 401884 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 572164873 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 974203164 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 24151 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 834511674 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.189203 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.071791 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 665575022 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 3123 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2916 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 415832299 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 528432376 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 209864891 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 239237917 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 72205880 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2101284212 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 24336 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1827034633 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 401491 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 572319847 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 974276898 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 23784 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 834434550 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.189548 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.072515 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 254614117 30.51% 30.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 125714590 15.06% 45.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 119295811 14.30% 59.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 111533246 13.37% 73.24% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 92303012 11.06% 84.30% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 61450543 7.36% 91.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 43061191 5.16% 96.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 19136018 2.29% 99.11% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 7403146 0.89% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 254639697 30.52% 30.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 125724347 15.07% 45.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 119353828 14.30% 59.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 111074898 13.31% 73.20% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 92504387 11.09% 84.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 61470741 7.37% 91.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 43061930 5.16% 96.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 19202673 2.30% 99.11% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 7402049 0.89% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 834511674 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 834434550 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 11328208 42.57% 42.57% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 42.57% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 42.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 42.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 42.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 42.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 42.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 42.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 42.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 42.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 42.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 42.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 42.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 42.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 42.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 42.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 42.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 42.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 42.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 42.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 42.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 42.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 42.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 42.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 42.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 42.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 42.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 42.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 42.57% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 12223678 45.94% 88.51% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 3056537 11.49% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 11320186 42.67% 42.67% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 42.67% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 42.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 42.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 42.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 42.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 42.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 42.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 42.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 42.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 42.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 42.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 42.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 42.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 42.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 42.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 42.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 42.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 42.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 42.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 42.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 42.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 42.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 42.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 42.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 42.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 42.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 42.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 42.67% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 12172571 45.88% 88.55% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 3037482 11.45% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 2713479 0.15% 0.15% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1211223502 66.30% 66.45% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 389210 0.02% 66.47% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 3881037 0.21% 66.68% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 114 0.00% 66.68% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 2711288 0.15% 0.15% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1211298887 66.30% 66.45% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 388808 0.02% 66.47% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 3881058 0.21% 66.68% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 134 0.00% 66.68% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.68% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.68% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 41 0.00% 66.68% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 410 0.00% 66.68% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 33 0.00% 66.68% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 403 0.00% 66.68% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.68% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.68% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.68% # Type of FU issued @@ -456,84 +456,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.68% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.68% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.68% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.68% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 435016626 23.81% 90.49% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 173690734 9.51% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 435055867 23.81% 90.49% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 173698155 9.51% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1826915153 # Type of FU issued -system.cpu.iq.rate 2.188675 # Inst issue rate -system.cpu.iq.fu_busy_cnt 26608423 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.014565 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 4515318394 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2673578201 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1796830430 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 33893 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 72228 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 7290 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1850794442 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 15655 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 185328618 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1827034633 # Type of FU issued +system.cpu.iq.rate 2.189031 # Inst issue rate +system.cpu.iq.fu_busy_cnt 26530239 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.014521 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 4515402541 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2673889112 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1796964967 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 33005 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 70700 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 7229 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1850838268 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 15316 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 185431148 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 144273272 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 209540 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 385759 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 60706753 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 144332039 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 211913 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 385225 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 60704705 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 19758 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 975 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 19195 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1040 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 10114069 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 106861853 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 6175689 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2101153574 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 399268 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 528375429 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 209866939 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 7172 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1868361 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3423880 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 385759 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 5745481 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 4570970 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 10316451 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1805502100 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 428802217 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 21413053 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 10108569 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 107095351 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 6179627 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2101308548 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 404076 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 528434196 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 209864891 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 6959 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1875437 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3414890 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 385225 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 5746544 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 4564008 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 10310552 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1805625643 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 428837620 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 21408990 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 598985052 # number of memory reference insts executed -system.cpu.iew.exec_branches 171767135 # Number of branches executed -system.cpu.iew.exec_stores 170182835 # Number of stores executed -system.cpu.iew.exec_rate 2.163022 # Inst execution rate -system.cpu.iew.wb_sent 1802089057 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1796837720 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1367929108 # num instructions producing a value -system.cpu.iew.wb_consumers 2089922877 # num instructions consuming a value +system.cpu.iew.exec_refs 599025712 # number of memory reference insts executed +system.cpu.iew.exec_branches 171773578 # Number of branches executed +system.cpu.iew.exec_stores 170188092 # Number of stores executed +system.cpu.iew.exec_rate 2.163380 # Inst execution rate +system.cpu.iew.wb_sent 1802216227 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1796972196 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1368071729 # num instructions producing a value +system.cpu.iew.wb_consumers 2090120765 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.152642 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.654536 # average fanout of values written-back +system.cpu.iew.wb_rate 2.153012 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.654542 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 572246174 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 572398548 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 552 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 9834163 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 756802524 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.020327 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.547122 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 9828987 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 756729949 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.020521 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.547401 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 287869845 38.04% 38.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 175466926 23.19% 61.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 57310914 7.57% 68.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 86374049 11.41% 80.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 27151308 3.59% 83.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 27112039 3.58% 87.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 9778589 1.29% 88.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 8969993 1.19% 89.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 76768861 10.14% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 287871292 38.04% 38.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 175370720 23.17% 61.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 57379665 7.58% 68.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 86292739 11.40% 80.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 27182541 3.59% 83.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 27109377 3.58% 87.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 9779675 1.29% 88.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 8926185 1.18% 89.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 76817755 10.15% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 756802524 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 756729949 # Number of insts commited each cycle system.cpu.commit.committedInsts 826877109 # Number of instructions committed system.cpu.commit.committedOps 1528988701 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -579,344 +579,344 @@ system.cpu.commit.op_class_0::MemWrite 149160186 9.76% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 1528988701 # Class of committed instruction -system.cpu.commit.bw_lim_events 76768861 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 2781268538 # The number of ROB reads -system.cpu.rob.rob_writes 4280366942 # The number of ROB writes -system.cpu.timesIdled 2320 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 201218 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 76817755 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 2781299443 # The number of ROB reads +system.cpu.rob.rob_writes 4280666670 # The number of ROB writes +system.cpu.timesIdled 2296 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 197061 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 826877109 # Number of Instructions Simulated system.cpu.committedOps 1528988701 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.009476 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.009476 # CPI: Total CPI of All Threads -system.cpu.ipc 0.990613 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.990613 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 2761875097 # number of integer regfile reads -system.cpu.int_regfile_writes 1464994658 # number of integer regfile writes -system.cpu.fp_regfile_reads 7611 # number of floating regfile reads -system.cpu.fp_regfile_writes 469 # number of floating regfile writes -system.cpu.cc_regfile_reads 600894464 # number of cc regfile reads -system.cpu.cc_regfile_writes 409621609 # number of cc regfile writes -system.cpu.misc_regfile_reads 990138198 # number of misc regfile reads +system.cpu.cpi 1.009378 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.009378 # CPI: Total CPI of All Threads +system.cpu.ipc 0.990709 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.990709 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 2762055581 # number of integer regfile reads +system.cpu.int_regfile_writes 1465119637 # number of integer regfile writes +system.cpu.fp_regfile_reads 7518 # number of floating regfile reads +system.cpu.fp_regfile_writes 448 # number of floating regfile writes +system.cpu.cc_regfile_reads 600894138 # number of cc regfile reads +system.cpu.cc_regfile_writes 409652534 # number of cc regfile writes +system.cpu.misc_regfile_reads 990211728 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.dcache.tags.replacements 2534436 # number of replacements -system.cpu.dcache.tags.tagsinuse 4088.023395 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 387994908 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2538532 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 152.842236 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 2534268 # number of replacements +system.cpu.dcache.tags.tagsinuse 4088.022618 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 387933013 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2538364 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 152.827968 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 1679458500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4088.023395 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.998053 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.998053 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 4088.022618 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.998052 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.998052 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 26 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 27 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 883 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 3160 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 24 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 875 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 3171 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 785123968 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 785123968 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 239346850 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 239346850 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 148188204 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 148188204 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 387535054 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 387535054 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 387535054 # number of overall hits -system.cpu.dcache.overall_hits::total 387535054 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2785666 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2785666 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 971998 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 971998 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 3757664 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3757664 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3757664 # number of overall misses -system.cpu.dcache.overall_misses::total 3757664 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 59489424500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 59489424500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 30574204499 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 30574204499 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 90063628999 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 90063628999 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 90063628999 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 90063628999 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 242132516 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 242132516 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 784997698 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 784997698 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 239283827 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 239283827 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 148189705 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 148189705 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 387473532 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 387473532 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 387473532 # number of overall hits +system.cpu.dcache.overall_hits::total 387473532 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2785638 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2785638 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 970497 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 970497 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 3756135 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3756135 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3756135 # number of overall misses +system.cpu.dcache.overall_misses::total 3756135 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 59461217500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 59461217500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 30522057998 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 30522057998 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 89983275498 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 89983275498 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 89983275498 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 89983275498 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 242069465 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 242069465 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 149160202 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 149160202 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 391292718 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 391292718 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 391292718 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 391292718 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011505 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.011505 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006516 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.006516 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.009603 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.009603 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.009603 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.009603 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21355.548188 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 21355.548188 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31455.007622 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 31455.007622 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 23967.983566 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 23967.983566 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 23967.983566 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 23967.983566 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 10943 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 29 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1141 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 3 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.590710 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 9.666667 # average number of cycles each access was blocked +system.cpu.dcache.demand_accesses::cpu.data 391229667 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 391229667 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 391229667 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 391229667 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011508 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.011508 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006506 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.006506 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.009601 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.009601 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.009601 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.009601 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21345.636978 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 21345.636978 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31449.925139 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 31449.925139 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 23956.347548 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 23956.347548 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 23956.347548 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 23956.347548 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 11065 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 19 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1184 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.345439 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 9.500000 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2332856 # number of writebacks -system.cpu.dcache.writebacks::total 2332856 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1017532 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1017532 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 19229 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 19229 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1036761 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1036761 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1036761 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1036761 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1768134 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1768134 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 952769 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 952769 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2720903 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2720903 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2720903 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2720903 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33612540500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 33612540500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 29371438000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 29371438000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 62983978500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 62983978500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 62983978500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 62983978500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007302 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007302 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006388 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006388 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006954 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.006954 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006954 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.006954 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19010.177113 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19010.177113 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30827.449256 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30827.449256 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23148.189590 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 23148.189590 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23148.189590 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 23148.189590 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 2332624 # number of writebacks +system.cpu.dcache.writebacks::total 2332624 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1017670 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1017670 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 19246 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 19246 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1036916 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1036916 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1036916 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1036916 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1767968 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1767968 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 951251 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 951251 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2719219 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2719219 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2719219 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2719219 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33611924000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 33611924000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 29320675500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 29320675500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 62932599500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 62932599500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 62932599500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 62932599500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007304 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007304 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006377 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006377 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006950 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.006950 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006950 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.006950 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19011.613332 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19011.613332 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30823.279555 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30823.279555 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23143.630395 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 23143.630395 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23143.630395 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 23143.630395 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 7110 # number of replacements -system.cpu.icache.tags.tagsinuse 1052.499064 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 179252042 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 8714 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 20570.580904 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 6980 # number of replacements +system.cpu.icache.tags.tagsinuse 1050.498551 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 179263698 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 8570 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 20917.584364 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1052.499064 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.513916 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.513916 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1604 # Occupied blocks per task id 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# average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 71057.053647 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 71057.053647 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70487.591162 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70487.591162 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71057.053647 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69830.463369 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69841.635148 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71057.053647 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69830.463369 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69841.635148 # average overall mshr miss latency +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.989533 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.989533 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.268119 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.268119 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.405779 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.405779 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.099951 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.099951 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.405779 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.151016 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.151878 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.405779 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.151016 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.151878 # mshr miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 21037.656419 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 21037.656419 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69266.841509 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69266.841509 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 71408.921933 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 71408.921933 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70469.652803 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70469.652803 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71408.921933 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69821.196398 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69835.549633 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71408.921933 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69821.196398 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69835.549633 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadResp 1959001 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 2627884 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 256223 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 182372 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 182372 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 770778 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 770778 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 191249 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1767754 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 206660 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7965180 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 8171840 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 560448 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 311768832 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 312329280 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 536571 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 5807780 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.060967 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.239269 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadResp 1957165 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 2627653 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 256317 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 180855 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 180855 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 770784 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 770784 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 189586 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1767580 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 204722 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7961776 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 8166498 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 551488 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 311743232 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 312294720 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 535081 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 5804166 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.061010 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.239349 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 5453699 93.90% 93.90% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 354081 6.10% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 5450053 93.90% 93.90% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 354113 6.10% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 5807780 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 5086087131 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 5804166 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 5083850495 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 286877486 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 284382490 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3898984570 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3897973573 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) -system.membus.trans_dist::ReadResp 180129 # Transaction distribution -system.membus.trans_dist::Writeback 295028 # Transaction distribution -system.membus.trans_dist::CleanEvict 57486 # Transaction distribution -system.membus.trans_dist::UpgradeReq 180541 # Transaction distribution -system.membus.trans_dist::UpgradeResp 180541 # Transaction distribution -system.membus.trans_dist::ReadExReq 206628 # Transaction distribution -system.membus.trans_dist::ReadExResp 206628 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 180130 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1487111 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1487111 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1487111 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43634240 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43634240 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 43634240 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadResp 180168 # Transaction distribution +system.membus.trans_dist::Writeback 295029 # Transaction distribution +system.membus.trans_dist::CleanEvict 57519 # Transaction distribution +system.membus.trans_dist::UpgradeReq 179000 # Transaction distribution +system.membus.trans_dist::UpgradeResp 179000 # Transaction distribution +system.membus.trans_dist::ReadExReq 206624 # Transaction distribution +system.membus.trans_dist::ReadExResp 206624 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 180168 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1484132 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1484132 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1484132 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43636544 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43636544 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 43636544 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 919813 # Request fanout histogram +system.membus.snoop_fanout::samples 918340 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 919813 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 918340 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 919813 # Request fanout histogram -system.membus.reqLayer0.occupancy 2222161296 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 918340 # Request fanout histogram +system.membus.reqLayer0.occupancy 2219848930 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.5 # Layer utilization (%) -system.membus.respLayer1.occupancy 2406907271 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2404009566 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.6 # Layer utilization (%) ---------- End Simulation Statistics ---------- |