tests: update config.ini and stdout for the various tests.

These files were a bit too out of date and resulted in a bit of confusion.

64 files changed, 587 insertions, 188 deletions

diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini
index 595b91bdc..737f0dea4 100644
--- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini
@@ -394,6 +394,8 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side
 type=PhysicalMemory
 file=
 latency=1
+latency_var=0
+null=false
 range=0:134217727
 zero=false
 port=system.membus.port[0]
diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stdout b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stdout
index 9aaca3eeb..cbeafd848 100644
--- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stdout
+++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stdout
@@ -1,3 +1,17 @@
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Jul 21 2008 20:12:56
+M5 started Mon Jul 21 20:22:47 2008
+M5 executing on zizzer
+M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881
+M5 commit date Tue Jul 15 14:38:51 2008 -0400
+command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing tests/run.py long/00.gzip/alpha/tru64/o3-timing
+Global frequency set at 1000000000000 ticks per second
 spec_init
 Loading Input Data
 Duplicating 262144 bytes
diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.ini
index e21c42f32..471b28d35 100644
--- a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.ini
+++ b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.ini
@@ -25,7 +25,8 @@ max_loads_all_threads=0
 max_loads_any_thread=0
 phase=0
 progress_interval=0
-simulate_stalls=false
+simulate_data_stalls=false
+simulate_inst_stalls=false
 system=system
 tracer=system.cpu.tracer
 width=1
@@ -54,9 +55,11 @@ euid=100
 executable=/dist/m5/cpu2000/binaries/alpha/tru64/gzip
 gid=100
 input=cin
+max_stack_size=67108864
 output=cout
 pid=100
 ppid=99
+simpoint=0
 system=system
 uid=100
 
@@ -65,6 +68,7 @@ type=Bus
 block_size=64
 bus_id=0
 clock=1000
+header_cycles=1
 responder_set=false
 width=64
 port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
@@ -73,6 +77,8 @@ port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
 type=PhysicalMemory
 file=
 latency=1
+latency_var=0
+null=false
 range=0:134217727
 zero=false
 port=system.membus.port[0]
diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stdout b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stdout
index 9aaca3eeb..26bc81b05 100644
--- a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stdout
+++ b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stdout
@@ -1,3 +1,17 @@
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Jul 21 2008 20:12:56
+M5 started Mon Jul 21 20:12:59 2008
+M5 executing on zizzer
+M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881
+M5 commit date Tue Jul 15 14:38:51 2008 -0400
+command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-atomic tests/run.py long/00.gzip/alpha/tru64/simple-atomic
+Global frequency set at 1000000000000 ticks per second
 spec_init
 Loading Input Data
 Duplicating 262144 bytes
diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini
index 87443a024..0c02ed13c 100644
--- a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini
@@ -174,6 +174,7 @@ max_stack_size=67108864
 output=cout
 pid=100
 ppid=99
+simpoint=0
 system=system
 uid=100
 
@@ -191,6 +192,8 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side
 type=PhysicalMemory
 file=
 latency=1
+latency_var=0
+null=false
 range=0:134217727
 zero=false
 port=system.membus.port[0]
diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stdout b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stdout
index 9aaca3eeb..1faa3f4e8 100644
--- a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stdout
+++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stdout
@@ -1,3 +1,17 @@
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Jul 21 2008 20:12:56
+M5 started Mon Jul 21 20:13:00 2008
+M5 executing on zizzer
+M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881
+M5 commit date Tue Jul 15 14:38:51 2008 -0400
+command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-timing tests/run.py long/00.gzip/alpha/tru64/simple-timing
+Global frequency set at 1000000000000 ticks per second
 spec_init
 Loading Input Data
 Duplicating 262144 bytes
diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini b/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini
index 4e87924ca..4219e15b7 100644
--- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini
+++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini
@@ -394,6 +394,8 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side
 type=PhysicalMemory
 file=
 latency=1
+latency_var=0
+null=false
 range=0:134217727
 zero=false
 port=system.membus.port[0]
diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/stdout b/tests/long/00.gzip/ref/sparc/linux/o3-timing/stdout
index d3d1e3cfb..ce2e79d1f 100644
--- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/stdout
+++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/stdout
@@ -1,3 +1,17 @@
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Jul 21 2008 20:33:06
+M5 started Mon Jul 21 20:33:25 2008
+M5 executing on zizzer
+M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881
+M5 commit date Tue Jul 15 14:38:51 2008 -0400
+command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing tests/run.py long/00.gzip/sparc/linux/o3-timing
+Global frequency set at 1000000000000 ticks per second
 spec_init
 Loading Input Data
 Duplicating 262144 bytes
@@ -29,16 +43,4 @@ Uncompressing Data
 Uncompressed data 1048576 bytes in length
 Uncompressed data compared correctly
 Tested 1MB buffer: OK!
-M5 Simulator System
-
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Mar 17 2008 06:14:16
-M5 started Mon Mar 17 06:14:18 2008
-M5 executing on zizzer
-command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing tests/run.py long/00.gzip/sparc/linux/o3-timing
-Global frequency set at 1000000000000 ticks per second
 Exiting @ tick 1102714100000 because target called exit()
diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/config.ini b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/config.ini
index b267c8dc4..70a42097e 100644
--- a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/config.ini
+++ b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/config.ini
@@ -25,7 +25,8 @@ max_loads_all_threads=0
 max_loads_any_thread=0
 phase=0
 progress_interval=0
-simulate_stalls=false
+simulate_data_stalls=false
+simulate_inst_stalls=false
 system=system
 tracer=system.cpu.tracer
 width=1
@@ -58,6 +59,7 @@ max_stack_size=67108864
 output=cout
 pid=100
 ppid=99
+simpoint=0
 system=system
 uid=100
 
@@ -66,6 +68,7 @@ type=Bus
 block_size=64
 bus_id=0
 clock=1000
+header_cycles=1
 responder_set=false
 width=64
 port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
@@ -74,6 +77,8 @@ port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
 type=PhysicalMemory
 file=
 latency=1
+latency_var=0
+null=false
 range=0:134217727
 zero=false
 port=system.membus.port[0]
diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stdout b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stdout
index 5f4ac4eab..e334149fe 100644
--- a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stdout
+++ b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stdout
@@ -1,3 +1,17 @@
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Jul 21 2008 20:33:06
+M5 started Mon Jul 21 20:33:20 2008
+M5 executing on zizzer
+M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881
+M5 commit date Tue Jul 15 14:38:51 2008 -0400
+command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-atomic tests/run.py long/00.gzip/sparc/linux/simple-atomic
+Global frequency set at 1000000000000 ticks per second
 spec_init
 Loading Input Data
 Duplicating 262144 bytes
@@ -29,16 +43,4 @@ Uncompressing Data
 Uncompressed data 1048576 bytes in length
 Uncompressed data compared correctly
 Tested 1MB buffer: OK!
-M5 Simulator System
-
-Copyright (c) 2001-2006
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Nov 28 2007 18:29:37
-M5 started Wed Nov 28 18:29:38 2007
-M5 executing on nacho
-command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-atomic tests/run.py long/00.gzip/sparc/linux/simple-atomic
-Global frequency set at 1000000000000 ticks per second
 Exiting @ tick 744759833500 because target called exit()
diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini b/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini
index 6c34c6dee..af1b3a07f 100644
--- a/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini
+++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini
@@ -174,6 +174,7 @@ max_stack_size=67108864
 output=cout
 pid=100
 ppid=99
+simpoint=0
 system=system
 uid=100
 
@@ -191,6 +192,8 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side
 type=PhysicalMemory
 file=
 latency=1
+latency_var=0
+null=false
 range=0:134217727
 zero=false
 port=system.membus.port[0]
diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/stdout b/tests/long/00.gzip/ref/sparc/linux/simple-timing/stdout
index ce05ca938..5597eb1d2 100644
--- a/tests/long/00.gzip/ref/sparc/linux/simple-timing/stdout
+++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/stdout
@@ -1,3 +1,17 @@
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Jul 21 2008 20:33:06
+M5 started Mon Jul 21 20:33:09 2008
+M5 executing on zizzer
+M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881
+M5 commit date Tue Jul 15 14:38:51 2008 -0400
+command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-timing tests/run.py long/00.gzip/sparc/linux/simple-timing
+Global frequency set at 1000000000000 ticks per second
 spec_init
 Loading Input Data
 Duplicating 262144 bytes
@@ -29,16 +43,4 @@ Uncompressing Data
 Uncompressed data 1048576 bytes in length
 Uncompressed data compared correctly
 Tested 1MB buffer: OK!
-M5 Simulator System
-
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Feb 24 2008 13:27:50
-M5 started Mon Feb 25 16:16:45 2008
-M5 executing on tater
-command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-timing tests/run.py long/00.gzip/sparc/linux/simple-timing
-Global frequency set at 1000000000000 ticks per second
 Exiting @ tick 2070157841000 because target called exit()
diff --git a/tests/long/00.gzip/ref/x86/linux/simple-atomic/config.ini b/tests/long/00.gzip/ref/x86/linux/simple-atomic/config.ini
index 3572e375e..7f66790fb 100644
--- a/tests/long/00.gzip/ref/x86/linux/simple-atomic/config.ini
+++ b/tests/long/00.gzip/ref/x86/linux/simple-atomic/config.ini
@@ -25,7 +25,8 @@ max_loads_all_threads=0
 max_loads_any_thread=0
 phase=0
 progress_interval=0
-simulate_stalls=false
+simulate_data_stalls=false
+simulate_inst_stalls=false
 system=system
 tracer=system.cpu.tracer
 width=1
@@ -77,6 +78,7 @@ type=PhysicalMemory
 file=
 latency=1
 latency_var=0
+null=false
 range=0:134217727
 zero=false
 port=system.membus.port[0]
diff --git a/tests/long/00.gzip/ref/x86/linux/simple-atomic/stdout b/tests/long/00.gzip/ref/x86/linux/simple-atomic/stdout
index 682b64f8a..79273f082 100644
--- a/tests/long/00.gzip/ref/x86/linux/simple-atomic/stdout
+++ b/tests/long/00.gzip/ref/x86/linux/simple-atomic/stdout
@@ -1,3 +1,17 @@
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Jul 21 2008 20:45:28
+M5 started Mon Jul 21 20:48:56 2008
+M5 executing on zizzer
+M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881
+M5 commit date Tue Jul 15 14:38:51 2008 -0400
+command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-atomic tests/run.py long/00.gzip/x86/linux/simple-atomic
+Global frequency set at 1000000000000 ticks per second
 spec_init
 Loading Input Data
 Duplicating 262144 bytes
@@ -29,16 +43,4 @@ Uncompressing Data
 Uncompressed data 1048576 bytes in length
 Uncompressed data compared correctly
 Tested 1MB buffer: OK!
-M5 Simulator System
-
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled May 17 2008 13:48:04
-M5 started Sat May 17 13:48:05 2008
-M5 executing on tater
-command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-atomic tests/run.py long/00.gzip/x86/linux/simple-atomic
-Global frequency set at 1000000000000 ticks per second
 Exiting @ tick 955075963000 because target called exit()
diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/config.ini b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/config.ini
index ef3141a33..5c55bdb1c 100644
--- a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/config.ini
+++ b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/config.ini
@@ -25,7 +25,8 @@ max_loads_all_threads=0
 max_loads_any_thread=0
 phase=0
 progress_interval=0
-simulate_stalls=false
+simulate_data_stalls=false
+simulate_inst_stalls=false
 system=system
 tracer=system.cpu.tracer
 width=1
@@ -58,6 +59,7 @@ max_stack_size=67108864
 output=cout
 pid=100
 ppid=99
+simpoint=55300000000
 system=system
 uid=100
 
@@ -66,6 +68,7 @@ type=Bus
 block_size=64
 bus_id=0
 clock=1000
+header_cycles=1
 responder_set=false
 width=64
 port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
@@ -74,6 +77,8 @@ port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
 type=PhysicalMemory
 file=
 latency=1
+latency_var=0
+null=false
 range=0:268435455
 zero=false
 port=system.membus.port[0]
diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/stdout b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/stdout
index eb0a0f196..8fdd56739 100644
--- a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/stdout
+++ b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/stdout
@@ -1,3 +1,17 @@
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Jul 21 2008 20:33:06
+M5 started Mon Jul 21 20:36:22 2008
+M5 executing on zizzer
+M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881
+M5 commit date Tue Jul 15 14:38:51 2008 -0400
+command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-atomic tests/run.py long/10.mcf/sparc/linux/simple-atomic
+Global frequency set at 1000000000000 ticks per second
 
 MCF SPEC version 1.6.I
 by  Andreas Loebel
@@ -14,16 +28,4 @@ simplex iterations         : 2663
 flow value                 : 3080014995
 checksum                   : 68389
 optimal
-M5 Simulator System
-
-Copyright (c) 2001-2006
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Nov 28 2007 18:29:37
-M5 started Wed Nov 28 18:29:38 2007
-M5 executing on nacho
-command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-atomic tests/run.py long/10.mcf/sparc/linux/simple-atomic
-Global frequency set at 1000000000000 ticks per second
 Exiting @ tick 122212687000 because target called exit()
diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini b/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini
index a0f77bf10..a9213133f 100644
--- a/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini
+++ b/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini
@@ -174,6 +174,7 @@ max_stack_size=67108864
 output=cout
 pid=100
 ppid=99
+simpoint=55300000000
 system=system
 uid=100
 
@@ -191,6 +192,8 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side
 type=PhysicalMemory
 file=
 latency=1
+latency_var=0
+null=false
 range=0:268435455
 zero=false
 port=system.membus.port[0]
diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/stdout b/tests/long/10.mcf/ref/sparc/linux/simple-timing/stdout
index 8270f923d..5fdb31dc0 100644
--- a/tests/long/10.mcf/ref/sparc/linux/simple-timing/stdout
+++ b/tests/long/10.mcf/ref/sparc/linux/simple-timing/stdout
@@ -1,3 +1,17 @@
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Jul 21 2008 20:33:06
+M5 started Mon Jul 21 20:33:32 2008
+M5 executing on zizzer
+M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881
+M5 commit date Tue Jul 15 14:38:51 2008 -0400
+command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-timing tests/run.py long/10.mcf/sparc/linux/simple-timing
+Global frequency set at 1000000000000 ticks per second
 
 MCF SPEC version 1.6.I
 by  Andreas Loebel
@@ -14,16 +28,4 @@ simplex iterations         : 2663
 flow value                 : 3080014995
 checksum                   : 68389
 optimal
-M5 Simulator System
-
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Feb 24 2008 13:27:50
-M5 started Mon Feb 25 16:16:46 2008
-M5 executing on tater
-command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-timing tests/run.py long/10.mcf/sparc/linux/simple-timing
-Global frequency set at 1000000000000 ticks per second
 Exiting @ tick 363652229000 because target called exit()
diff --git a/tests/long/10.mcf/ref/x86/linux/simple-atomic/config.ini b/tests/long/10.mcf/ref/x86/linux/simple-atomic/config.ini
index d878cb424..4ca62bb34 100644
--- a/tests/long/10.mcf/ref/x86/linux/simple-atomic/config.ini
+++ b/tests/long/10.mcf/ref/x86/linux/simple-atomic/config.ini
@@ -25,7 +25,8 @@ max_loads_all_threads=0
 max_loads_any_thread=0
 phase=0
 progress_interval=0
-simulate_stalls=false
+simulate_data_stalls=false
+simulate_inst_stalls=false
 system=system
 tracer=system.cpu.tracer
 width=1
@@ -77,6 +78,7 @@ type=PhysicalMemory
 file=
 latency=1
 latency_var=0
+null=false
 range=0:268435455
 zero=false
 port=system.membus.port[0]
diff --git a/tests/long/10.mcf/ref/x86/linux/simple-atomic/stdout b/tests/long/10.mcf/ref/x86/linux/simple-atomic/stdout
index e519e0a5b..996ca24f1 100644
--- a/tests/long/10.mcf/ref/x86/linux/simple-atomic/stdout
+++ b/tests/long/10.mcf/ref/x86/linux/simple-atomic/stdout
@@ -1,3 +1,17 @@
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Jul 21 2008 20:45:28
+M5 started Mon Jul 21 20:45:29 2008
+M5 executing on zizzer
+M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881
+M5 commit date Tue Jul 15 14:38:51 2008 -0400
+command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-atomic tests/run.py long/10.mcf/x86/linux/simple-atomic
+Global frequency set at 1000000000000 ticks per second
 
 MCF SPEC version 1.6.I
 by  Andreas Loebel
@@ -14,16 +28,4 @@ simplex iterations         : 2663
 flow value                 : 3080014995
 checksum                   : 68389
 optimal
-M5 Simulator System
-
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled May 17 2008 13:48:04
-M5 started Sat May 17 13:48:05 2008
-M5 executing on tater
-command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-atomic tests/run.py long/10.mcf/x86/linux/simple-atomic
-Global frequency set at 1000000000000 ticks per second
 Exiting @ tick 165703651500 because target called exit()
diff --git a/tests/long/20.parser/ref/x86/linux/simple-atomic/config.ini b/tests/long/20.parser/ref/x86/linux/simple-atomic/config.ini
index af0a9ce63..0b6f15f38 100644
--- a/tests/long/20.parser/ref/x86/linux/simple-atomic/config.ini
+++ b/tests/long/20.parser/ref/x86/linux/simple-atomic/config.ini
@@ -25,7 +25,8 @@ max_loads_all_threads=0
 max_loads_any_thread=0
 phase=0
 progress_interval=0
-simulate_stalls=false
+simulate_data_stalls=false
+simulate_inst_stalls=false
 system=system
 tracer=system.cpu.tracer
 width=1
@@ -77,6 +78,7 @@ type=PhysicalMemory
 file=
 latency=1
 latency_var=0
+null=false
 range=0:134217727
 zero=false
 port=system.membus.port[0]
diff --git a/tests/long/20.parser/ref/x86/linux/simple-atomic/stdout b/tests/long/20.parser/ref/x86/linux/simple-atomic/stdout
index b105051a9..2ab0ba3a2 100644
--- a/tests/long/20.parser/ref/x86/linux/simple-atomic/stdout
+++ b/tests/long/20.parser/ref/x86/linux/simple-atomic/stdout
@@ -1,3 +1,17 @@
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Jul 21 2008 20:45:28
+M5 started Mon Jul 21 20:45:29 2008
+M5 executing on zizzer
+M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881
+M5 commit date Tue Jul 15 14:38:51 2008 -0400
+command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-atomic tests/run.py long/20.parser/x86/linux/simple-atomic
+Global frequency set at 1000000000000 ticks per second
 
  Reading the dictionary files: *************************************************
  58924 words stored in 3784810 bytes
@@ -57,16 +71,4 @@ Echoing of input sentence turned on.
   about 2 million people attended 
   the five best costumes got prizes 
 No errors!
-M5 Simulator System
-
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled May 17 2008 13:48:04
-M5 started Sat May 17 13:48:05 2008
-M5 executing on tater
-command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-atomic tests/run.py long/20.parser/x86/linux/simple-atomic
-Global frequency set at 1000000000000 ticks per second
-Exiting @ tick 863350524000 because target called exit()
+Exiting @ tick 863350526500 because target called exit()
diff --git a/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini b/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini
index 56c9263b3..bcc536301 100644
--- a/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini
@@ -394,6 +394,8 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side
 type=PhysicalMemory
 file=
 latency=1
+latency_var=0
+null=false
 range=0:134217727
 zero=false
 port=system.membus.port[0]
diff --git a/tests/long/30.eon/ref/alpha/tru64/o3-timing/stdout b/tests/long/30.eon/ref/alpha/tru64/o3-timing/stdout
index 50ed34325..53e92e76c 100644
--- a/tests/long/30.eon/ref/alpha/tru64/o3-timing/stdout
+++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/stdout
@@ -1,2 +1,16 @@
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Jul 21 2008 20:12:56
+M5 started Mon Jul 21 20:12:58 2008
+M5 executing on zizzer
+M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881
+M5 commit date Tue Jul 15 14:38:51 2008 -0400
+command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/o3-timing tests/run.py long/30.eon/alpha/tru64/o3-timing
+Global frequency set at 1000000000000 ticks per second
 Eon, Version 1.1
 OO-style eon Time= 0.133333
diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/config.ini
index bfc3d0e40..f1d9f437d 100644
--- a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/config.ini
+++ b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/config.ini
@@ -25,7 +25,8 @@ max_loads_all_threads=0
 max_loads_any_thread=0
 phase=0
 progress_interval=0
-simulate_stalls=false
+simulate_data_stalls=false
+simulate_inst_stalls=false
 system=system
 tracer=system.cpu.tracer
 width=1
@@ -54,9 +55,11 @@ euid=100
 executable=/dist/m5/cpu2000/binaries/alpha/tru64/eon
 gid=100
 input=cin
+max_stack_size=67108864
 output=cout
 pid=100
 ppid=99
+simpoint=0
 system=system
 uid=100
 
@@ -65,6 +68,7 @@ type=Bus
 block_size=64
 bus_id=0
 clock=1000
+header_cycles=1
 responder_set=false
 width=64
 port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
@@ -73,6 +77,8 @@ port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
 type=PhysicalMemory
 file=
 latency=1
+latency_var=0
+null=false
 range=0:134217727
 zero=false
 port=system.membus.port[0]
diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/stdout b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/stdout
index 5f057b8dd..285c8d750 100644
--- a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/stdout
+++ b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/stdout
@@ -1,2 +1,16 @@
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Jul 21 2008 20:12:56
+M5 started Mon Jul 21 20:13:02 2008
+M5 executing on zizzer
+M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881
+M5 commit date Tue Jul 15 14:38:51 2008 -0400
+command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-atomic tests/run.py long/30.eon/alpha/tru64/simple-atomic
+Global frequency set at 1000000000000 ticks per second
 Eon, Version 1.1
 OO-style eon Time= 0.183333
diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini b/tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini
index 6912167e0..4e4683ed6 100644
--- a/tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini
@@ -174,6 +174,7 @@ max_stack_size=67108864
 output=cout
 pid=100
 ppid=99
+simpoint=0
 system=system
 uid=100
 
@@ -191,6 +192,8 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side
 type=PhysicalMemory
 file=
 latency=1
+latency_var=0
+null=false
 range=0:134217727
 zero=false
 port=system.membus.port[0]
diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-timing/stdout b/tests/long/30.eon/ref/alpha/tru64/simple-timing/stdout
index f9d497506..9f21edbf0 100644
--- a/tests/long/30.eon/ref/alpha/tru64/simple-timing/stdout
+++ b/tests/long/30.eon/ref/alpha/tru64/simple-timing/stdout
@@ -1,2 +1,16 @@
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Jul 21 2008 20:12:56
+M5 started Mon Jul 21 20:13:28 2008
+M5 executing on zizzer
+M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881
+M5 commit date Tue Jul 15 14:38:51 2008 -0400
+command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-timing tests/run.py long/30.eon/alpha/tru64/simple-timing
+Global frequency set at 1000000000000 ticks per second
 Eon, Version 1.1
 OO-style eon Time= 0.566667
diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini
index 9054cf093..68b00e416 100644
--- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini
+++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini
@@ -25,7 +25,8 @@ max_loads_all_threads=0
 max_loads_any_thread=0
 phase=0
 progress_interval=0
-simulate_stalls=false
+simulate_data_stalls=false
+simulate_inst_stalls=false
 system=system
 tracer=system.cpu.tracer
 width=1
@@ -54,9 +55,11 @@ euid=100
 executable=/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk
 gid=100
 input=cin
+max_stack_size=67108864
 output=cout
 pid=100
 ppid=99
+simpoint=0
 system=system
 uid=100
 
@@ -65,6 +68,7 @@ type=Bus
 block_size=64
 bus_id=0
 clock=1000
+header_cycles=1
 responder_set=false
 width=64
 port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
@@ -73,6 +77,8 @@ port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
 type=PhysicalMemory
 file=
 latency=1
+latency_var=0
+null=false
 range=0:134217727
 zero=false
 port=system.membus.port[0]
diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stdout b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stdout
index d4a078b85..e78146575 100644
--- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stdout
+++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stdout
@@ -1,3 +1,17 @@
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Jul 21 2008 20:12:56
+M5 started Mon Jul 21 20:12:58 2008
+M5 executing on zizzer
+M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881
+M5 commit date Tue Jul 15 14:38:51 2008 -0400
+command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-atomic tests/run.py long/40.perlbmk/alpha/tru64/simple-atomic
+Global frequency set at 1000000000000 ticks per second
 1375000: 2038431008
 1374000: 3487365506
 1373000: 4184770123
diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini
index 7985d0869..360603943 100644
--- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini
@@ -174,6 +174,7 @@ max_stack_size=67108864
 output=cout
 pid=100
 ppid=99
+simpoint=0
 system=system
 uid=100
 
@@ -191,6 +192,8 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side
 type=PhysicalMemory
 file=
 latency=1
+latency_var=0
+null=false
 range=0:134217727
 zero=false
 port=system.membus.port[0]
diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stdout b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stdout
index d4a078b85..722e49f95 100644
--- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stdout
+++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stdout
@@ -1,3 +1,17 @@
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Jul 21 2008 20:12:56
+M5 started Mon Jul 21 20:13:00 2008
+M5 executing on zizzer
+M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881
+M5 commit date Tue Jul 15 14:38:51 2008 -0400
+command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-timing tests/run.py long/40.perlbmk/alpha/tru64/simple-timing
+Global frequency set at 1000000000000 ticks per second
 1375000: 2038431008
 1374000: 3487365506
 1373000: 4184770123
diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini
index 78b7f1eec..162b46290 100644
--- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini
@@ -394,6 +394,8 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side
 type=PhysicalMemory
 file=
 latency=1
+latency_var=0
+null=false
 range=0:134217727
 zero=false
 port=system.membus.port[0]
diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stdout b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stdout
index e69de29bb..f03ee0333 100644
--- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stdout
+++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stdout
@@ -0,0 +1,14 @@
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Jul 21 2008 20:12:56
+M5 started Mon Jul 21 20:19:28 2008
+M5 executing on zizzer
+M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881
+M5 commit date Tue Jul 15 14:38:51 2008 -0400
+command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/o3-timing tests/run.py long/50.vortex/alpha/tru64/o3-timing
+Global frequency set at 1000000000000 ticks per second
diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.ini
index 4745ee94c..337e5e366 100644
--- a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.ini
+++ b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.ini
@@ -25,7 +25,8 @@ max_loads_all_threads=0
 max_loads_any_thread=0
 phase=0
 progress_interval=0
-simulate_stalls=false
+simulate_data_stalls=false
+simulate_inst_stalls=false
 system=system
 tracer=system.cpu.tracer
 width=1
@@ -54,9 +55,11 @@ euid=100
 executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex
 gid=100
 input=cin
+max_stack_size=67108864
 output=cout
 pid=100
 ppid=99
+simpoint=0
 system=system
 uid=100
 
@@ -65,6 +68,7 @@ type=Bus
 block_size=64
 bus_id=0
 clock=1000
+header_cycles=1
 responder_set=false
 width=64
 port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
@@ -73,6 +77,8 @@ port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
 type=PhysicalMemory
 file=
 latency=1
+latency_var=0
+null=false
 range=0:134217727
 zero=false
 port=system.membus.port[0]
diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stdout b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stdout
index e69de29bb..f99b33e5f 100644
--- a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stdout
+++ b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stdout
@@ -0,0 +1,14 @@
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Jul 21 2008 20:12:56
+M5 started Mon Jul 21 20:14:04 2008
+M5 executing on zizzer
+M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881
+M5 commit date Tue Jul 15 14:38:51 2008 -0400
+command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-atomic tests/run.py long/50.vortex/alpha/tru64/simple-atomic
+Global frequency set at 1000000000000 ticks per second
diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini
index 2aab198c9..99587aea2 100644
--- a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini
@@ -174,6 +174,7 @@ max_stack_size=67108864
 output=cout
 pid=100
 ppid=99
+simpoint=0
 system=system
 uid=100
 
@@ -191,6 +192,8 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side
 type=PhysicalMemory
 file=
 latency=1
+latency_var=0
+null=false
 range=0:134217727
 zero=false
 port=system.membus.port[0]
diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stdout b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stdout
index e69de29bb..c568a72c2 100644
--- a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stdout
+++ b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stdout
@@ -0,0 +1,14 @@
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Jul 21 2008 20:12:56
+M5 started Mon Jul 21 20:13:07 2008
+M5 executing on zizzer
+M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881
+M5 commit date Tue Jul 15 14:38:51 2008 -0400
+command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-timing tests/run.py long/50.vortex/alpha/tru64/simple-timing
+Global frequency set at 1000000000000 ticks per second
diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/config.ini b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/config.ini
index 973d6211f..b8eed166b 100644
--- a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/config.ini
+++ b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/config.ini
@@ -25,7 +25,8 @@ max_loads_all_threads=0
 max_loads_any_thread=0
 phase=0
 progress_interval=0
-simulate_stalls=false
+simulate_data_stalls=false
+simulate_inst_stalls=false
 system=system
 tracer=system.cpu.tracer
 width=1
@@ -58,6 +59,7 @@ max_stack_size=67108864
 output=cout
 pid=100
 ppid=99
+simpoint=0
 system=system
 uid=100
 
@@ -66,6 +68,7 @@ type=Bus
 block_size=64
 bus_id=0
 clock=1000
+header_cycles=1
 responder_set=false
 width=64
 port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
@@ -74,6 +77,8 @@ port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
 type=PhysicalMemory
 file=
 latency=1
+latency_var=0
+null=false
 range=0:134217727
 zero=false
 port=system.membus.port[0]
diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stdout b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stdout
index 0a780ccee..b230e2c83 100644
--- a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stdout
+++ b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stdout
@@ -1,13 +1,15 @@
 M5 Simulator System
 
-Copyright (c) 2001-2006
+Copyright (c) 2001-2008
 The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Nov 28 2007 18:29:37
-M5 started Wed Nov 28 18:29:38 2007
-M5 executing on nacho
+M5 compiled Jul 21 2008 20:33:06
+M5 started Mon Jul 21 20:38:08 2008
+M5 executing on zizzer
+M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881
+M5 commit date Tue Jul 15 14:38:51 2008 -0400
 command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-atomic tests/run.py long/50.vortex/sparc/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 Exiting @ tick 68148678500 because target called exit()
diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini b/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini
index 01fab79ce..77a49bdbd 100644
--- a/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini
+++ b/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini
@@ -174,6 +174,7 @@ max_stack_size=67108864
 output=cout
 pid=100
 ppid=99
+simpoint=0
 system=system
 uid=100
 
@@ -191,6 +192,8 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side
 type=PhysicalMemory
 file=
 latency=1
+latency_var=0
+null=false
 range=0:134217727
 zero=false
 port=system.membus.port[0]
diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/stdout b/tests/long/50.vortex/ref/sparc/linux/simple-timing/stdout
index 5b4fb94a9..592b35b7a 100644
--- a/tests/long/50.vortex/ref/sparc/linux/simple-timing/stdout
+++ b/tests/long/50.vortex/ref/sparc/linux/simple-timing/stdout
@@ -5,9 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb 24 2008 13:27:50
-M5 started Mon Feb 25 16:16:46 2008
-M5 executing on tater
+M5 compiled Jul 21 2008 20:33:06
+M5 started Mon Jul 21 20:36:59 2008
+M5 executing on zizzer
+M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881
+M5 commit date Tue Jul 15 14:38:51 2008 -0400
 command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-timing tests/run.py long/50.vortex/sparc/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 Exiting @ tick 200790381000 because target called exit()
diff --git a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini
index abff97de4..be4327e6c 100644
--- a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini
@@ -394,6 +394,8 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side
 type=PhysicalMemory
 file=
 latency=1
+latency_var=0
+null=false
 range=0:134217727
 zero=false
 port=system.membus.port[0]
diff --git a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stdout b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stdout
index 0c5c00118..da44e8643 100644
--- a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stdout
+++ b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stdout
@@ -1,3 +1,17 @@
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Jul 21 2008 20:12:56
+M5 started Mon Jul 21 20:17:14 2008
+M5 executing on zizzer
+M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881
+M5 commit date Tue Jul 15 14:38:51 2008 -0400
+command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/o3-timing tests/run.py long/60.bzip2/alpha/tru64/o3-timing
+Global frequency set at 1000000000000 ticks per second
 spec_init
 Loading Input Data
 Input data 1048576 bytes in length
diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini
index 378e34da6..0768661a6 100644
--- a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini
+++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini
@@ -25,7 +25,8 @@ max_loads_all_threads=0
 max_loads_any_thread=0
 phase=0
 progress_interval=0
-simulate_stalls=false
+simulate_data_stalls=false
+simulate_inst_stalls=false
 system=system
 tracer=system.cpu.tracer
 width=1
@@ -54,9 +55,11 @@ euid=100
 executable=/dist/m5/cpu2000/binaries/alpha/tru64/bzip2
 gid=100
 input=cin
+max_stack_size=67108864
 output=cout
 pid=100
 ppid=99
+simpoint=0
 system=system
 uid=100
 
@@ -65,6 +68,7 @@ type=Bus
 block_size=64
 bus_id=0
 clock=1000
+header_cycles=1
 responder_set=false
 width=64
 port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
@@ -73,6 +77,8 @@ port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
 type=PhysicalMemory
 file=
 latency=1
+latency_var=0
+null=false
 range=0:134217727
 zero=false
 port=system.membus.port[0]
diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stdout b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stdout
index 0c5c00118..469f3b36a 100644
--- a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stdout
+++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stdout
@@ -1,3 +1,17 @@
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Jul 21 2008 20:12:56
+M5 started Mon Jul 21 20:16:25 2008
+M5 executing on zizzer
+M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881
+M5 commit date Tue Jul 15 14:38:51 2008 -0400
+command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-atomic tests/run.py long/60.bzip2/alpha/tru64/simple-atomic
+Global frequency set at 1000000000000 ticks per second
 spec_init
 Loading Input Data
 Input data 1048576 bytes in length
diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini
index 6adec3b74..48686792e 100644
--- a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini
@@ -174,6 +174,7 @@ max_stack_size=67108864
 output=cout
 pid=100
 ppid=99
+simpoint=0
 system=system
 uid=100
 
@@ -191,6 +192,8 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side
 type=PhysicalMemory
 file=
 latency=1
+latency_var=0
+null=false
 range=0:134217727
 zero=false
 port=system.membus.port[0]
diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stdout b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stdout
index 0c5c00118..c0a8b63da 100644
--- a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stdout
+++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stdout
@@ -1,3 +1,17 @@
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Jul 21 2008 20:12:56
+M5 started Mon Jul 21 20:14:59 2008
+M5 executing on zizzer
+M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881
+M5 commit date Tue Jul 15 14:38:51 2008 -0400
+command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-timing tests/run.py long/60.bzip2/alpha/tru64/simple-timing
+Global frequency set at 1000000000000 ticks per second
 spec_init
 Loading Input Data
 Input data 1048576 bytes in length
diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/config.ini b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/config.ini
index d18301e7c..989908e23 100644
--- a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/config.ini
+++ b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/config.ini
@@ -25,7 +25,8 @@ max_loads_all_threads=0
 max_loads_any_thread=0
 phase=0
 progress_interval=0
-simulate_stalls=false
+simulate_data_stalls=false
+simulate_inst_stalls=false
 system=system
 tracer=system.cpu.tracer
 width=1
@@ -77,6 +78,7 @@ type=PhysicalMemory
 file=
 latency=1
 latency_var=0
+null=false
 range=0:134217727
 zero=false
 port=system.membus.port[0]
diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stdout b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stdout
index 01a877484..17f5ab40f 100644
--- a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stdout
+++ b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stdout
@@ -1,3 +1,17 @@
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Jul 21 2008 20:45:28
+M5 started Mon Jul 21 20:49:02 2008
+M5 executing on zizzer
+M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881
+M5 commit date Tue Jul 15 14:38:51 2008 -0400
+command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-atomic tests/run.py long/60.bzip2/x86/linux/simple-atomic
+Global frequency set at 1000000000000 ticks per second
 spec_init
 Loading Input Data
 Input data 1048576 bytes in length
@@ -12,16 +26,4 @@ Uncompressing Data
 Uncompressed data 1048576 bytes in length
 Uncompressed data compared correctly
 Tested 1MB buffer: OK!
-M5 Simulator System
-
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled May 17 2008 13:48:04
-M5 started Sat May 17 13:48:05 2008
-M5 executing on tater
-command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-atomic tests/run.py long/60.bzip2/x86/linux/simple-atomic
-Global frequency set at 1000000000000 ticks per second
 Exiting @ tick 2806437159500 because target called exit()
diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini
index 945804e3d..dbf63ca05 100644
--- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini
@@ -394,6 +394,8 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side
 type=PhysicalMemory
 file=
 latency=1
+latency_var=0
+null=false
 range=0:134217727
 zero=false
 port=system.membus.port[0]
diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stdout b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stdout
index f32f0a972..20e9ee506 100644
--- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stdout
+++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stdout
@@ -1,3 +1,19 @@
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Jul 21 2008 20:12:56
+M5 started Mon Jul 21 20:14:27 2008
+M5 executing on zizzer
+M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881
+M5 commit date Tue Jul 15 14:38:51 2008 -0400
+command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing tests/run.py long/70.twolf/alpha/tru64/o3-timing
+Couldn't unlink  build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing/smred.sav
+Couldn't unlink  build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing/smred.sv2
+Global frequency set at 1000000000000 ticks per second
 
 TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
 Standard Cell Placement and Global Routing Program
diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.ini
index 8fbd6f60b..f0ed922b1 100644
--- a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.ini
+++ b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.ini
@@ -25,7 +25,8 @@ max_loads_all_threads=0
 max_loads_any_thread=0
 phase=0
 progress_interval=0
-simulate_stalls=false
+simulate_data_stalls=false
+simulate_inst_stalls=false
 system=system
 tracer=system.cpu.tracer
 width=1
@@ -54,9 +55,11 @@ euid=100
 executable=/dist/m5/cpu2000/binaries/alpha/tru64/twolf
 gid=100
 input=cin
+max_stack_size=67108864
 output=cout
 pid=100
 ppid=99
+simpoint=0
 system=system
 uid=100
 
@@ -65,6 +68,7 @@ type=Bus
 block_size=64
 bus_id=0
 clock=1000
+header_cycles=1
 responder_set=false
 width=64
 port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
@@ -73,6 +77,8 @@ port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
 type=PhysicalMemory
 file=
 latency=1
+latency_var=0
+null=false
 range=0:134217727
 zero=false
 port=system.membus.port[0]
diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stdout b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stdout
index f32f0a972..0fc73d0d9 100644
--- a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stdout
+++ b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stdout
@@ -1,3 +1,19 @@
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Jul 21 2008 20:12:56
+M5 started Mon Jul 21 20:12:59 2008
+M5 executing on zizzer
+M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881
+M5 commit date Tue Jul 15 14:38:51 2008 -0400
+command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-atomic tests/run.py long/70.twolf/alpha/tru64/simple-atomic
+Couldn't unlink  build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-atomic/smred.sav
+Couldn't unlink  build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-atomic/smred.sv2
+Global frequency set at 1000000000000 ticks per second
 
 TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
 Standard Cell Placement and Global Routing Program
diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini
index fd50e16e0..0190cf0fe 100644
--- a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini
@@ -174,6 +174,7 @@ max_stack_size=67108864
 output=cout
 pid=100
 ppid=99
+simpoint=0
 system=system
 uid=100
 
@@ -191,6 +192,8 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side
 type=PhysicalMemory
 file=
 latency=1
+latency_var=0
+null=false
 range=0:134217727
 zero=false
 port=system.membus.port[0]
diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stdout b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stdout
index f32f0a972..a512928ef 100644
--- a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stdout
+++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stdout
@@ -1,3 +1,19 @@
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Jul 21 2008 20:12:56
+M5 started Mon Jul 21 20:15:31 2008
+M5 executing on zizzer
+M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881
+M5 commit date Tue Jul 15 14:38:51 2008 -0400
+command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-timing tests/run.py long/70.twolf/alpha/tru64/simple-timing
+Couldn't unlink  build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-timing/smred.sav
+Couldn't unlink  build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-timing/smred.sv2
+Global frequency set at 1000000000000 ticks per second
 
 TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
 Standard Cell Placement and Global Routing Program
diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/config.ini b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/config.ini
index 31489ec58..a772db39f 100644
--- a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/config.ini
+++ b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/config.ini
@@ -25,7 +25,8 @@ max_loads_all_threads=0
 max_loads_any_thread=0
 phase=0
 progress_interval=0
-simulate_stalls=false
+simulate_data_stalls=false
+simulate_inst_stalls=false
 system=system
 tracer=system.cpu.tracer
 width=1
@@ -58,6 +59,7 @@ max_stack_size=67108864
 output=cout
 pid=100
 ppid=99
+simpoint=0
 system=system
 uid=100
 
@@ -66,6 +68,7 @@ type=Bus
 block_size=64
 bus_id=0
 clock=1000
+header_cycles=1
 responder_set=false
 width=64
 port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
@@ -74,6 +77,8 @@ port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
 type=PhysicalMemory
 file=
 latency=1
+latency_var=0
+null=false
 range=0:134217727
 zero=false
 port=system.membus.port[0]
diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stdout b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stdout
index 8a70482ca..ab5b187b5 100644
--- a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stdout
+++ b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stdout
@@ -1,3 +1,19 @@
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Jul 21 2008 20:33:06
+M5 started Mon Jul 21 20:33:08 2008
+M5 executing on zizzer
+M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881
+M5 commit date Tue Jul 15 14:38:51 2008 -0400
+command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-atomic tests/run.py long/70.twolf/sparc/linux/simple-atomic
+Couldn't unlink  build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-atomic/smred.sav
+Couldn't unlink  build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-atomic/smred.sv2
+Global frequency set at 1000000000000 ticks per second
 
 TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
 Standard Cell Placement and Global Routing Program
@@ -11,16 +27,4 @@ Authors: Carl Sechen, Bill Swartz
  76  77  78  79  80  81  82  83  84  85  86  87  88  89  90 
  91  92  93  94  95  96  97  98  99 100 101 102 103 104 105 
 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 
-122 123 124 M5 Simulator System
-
-Copyright (c) 2001-2006
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Nov 28 2007 18:29:37
-M5 started Wed Nov 28 18:29:38 2007
-M5 executing on nacho
-command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-atomic tests/run.py long/70.twolf/sparc/linux/simple-atomic
-Global frequency set at 1000000000000 ticks per second
-Exiting @ tick 96718067000 because target called exit()
+122 123 124 Exiting @ tick 96718067000 because target called exit()
diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini b/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini
index fe6c893b2..77060efdc 100644
--- a/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini
+++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini
@@ -174,6 +174,7 @@ max_stack_size=67108864
 output=cout
 pid=100
 ppid=99
+simpoint=0
 system=system
 uid=100
 
@@ -191,6 +192,8 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side
 type=PhysicalMemory
 file=
 latency=1
+latency_var=0
+null=false
 range=0:134217727
 zero=false
 port=system.membus.port[0]
diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/stdout b/tests/long/70.twolf/ref/sparc/linux/simple-timing/stdout
index 0d7eb187f..90bf47617 100644
--- a/tests/long/70.twolf/ref/sparc/linux/simple-timing/stdout
+++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/stdout
@@ -1,3 +1,19 @@
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Jul 21 2008 20:33:06
+M5 started Mon Jul 21 20:34:33 2008
+M5 executing on zizzer
+M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881
+M5 commit date Tue Jul 15 14:38:51 2008 -0400
+command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing tests/run.py long/70.twolf/sparc/linux/simple-timing
+Couldn't unlink  build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing/smred.sav
+Couldn't unlink  build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing/smred.sv2
+Global frequency set at 1000000000000 ticks per second
 
 TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
 Standard Cell Placement and Global Routing Program
@@ -11,18 +27,4 @@ Authors: Carl Sechen, Bill Swartz
  76  77  78  79  80  81  82  83  84  85  86  87  88  89  90 
  91  92  93  94  95  96  97  98  99 100 101 102 103 104 105 
 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 
-122 123 124 M5 Simulator System
-
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Feb 24 2008 13:27:50
-M5 started Mon Feb 25 16:18:16 2008
-M5 executing on tater
-command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing tests/run.py long/70.twolf/sparc/linux/simple-timing
-Couldn't unlink  build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing/smred.sav
-Couldn't unlink  build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing/smred.sv2
-Global frequency set at 1000000000000 ticks per second
-Exiting @ tick 270416976000 because target called exit()
+122 123 124 Exiting @ tick 270416976000 because target called exit()
diff --git a/tests/long/70.twolf/ref/x86/linux/simple-atomic/config.ini b/tests/long/70.twolf/ref/x86/linux/simple-atomic/config.ini
index f3b9dea12..27c1d66f3 100644
--- a/tests/long/70.twolf/ref/x86/linux/simple-atomic/config.ini
+++ b/tests/long/70.twolf/ref/x86/linux/simple-atomic/config.ini
@@ -25,7 +25,8 @@ max_loads_all_threads=0
 max_loads_any_thread=0
 phase=0
 progress_interval=0
-simulate_stalls=false
+simulate_data_stalls=false
+simulate_inst_stalls=false
 system=system
 tracer=system.cpu.tracer
 width=1
@@ -77,6 +78,7 @@ type=PhysicalMemory
 file=
 latency=1
 latency_var=0
+null=false
 range=0:134217727
 zero=false
 port=system.membus.port[0]
diff --git a/tests/long/70.twolf/ref/x86/linux/simple-atomic/stdout b/tests/long/70.twolf/ref/x86/linux/simple-atomic/stdout
index ab6e8b338..a8e5ba7f4 100644
--- a/tests/long/70.twolf/ref/x86/linux/simple-atomic/stdout
+++ b/tests/long/70.twolf/ref/x86/linux/simple-atomic/stdout
@@ -1,3 +1,19 @@
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Jul 21 2008 20:45:28
+M5 started Mon Jul 21 20:50:19 2008
+M5 executing on zizzer
+M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881
+M5 commit date Tue Jul 15 14:38:51 2008 -0400
+command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic tests/run.py long/70.twolf/x86/linux/simple-atomic
+Couldn't unlink  build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic/smred.sav
+Couldn't unlink  build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic/smred.sv2
+Global frequency set at 1000000000000 ticks per second
 
 TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
 Standard Cell Placement and Global Routing Program
@@ -11,16 +27,4 @@ Authors: Carl Sechen, Bill Swartz
  76  77  78  79  80  81  82  83  84  85  86  87  88  89  90 
  91  92  93  94  95  96  97  98  99 100 101 102 103 104 105 
 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 
-122 123 124 M5 Simulator System
-
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled May 17 2008 13:48:04
-M5 started Sat May 17 13:48:05 2008
-M5 executing on tater
-command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic tests/run.py long/70.twolf/x86/linux/simple-atomic
-Global frequency set at 1000000000000 ticks per second
-Exiting @ tick 129915167500 because target called exit()
+122 123 124 Exiting @ tick 129915167500 because target called exit()
diff --git a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini
index 7369c8a0c..2616832f0 100644
--- a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini
+++ b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini
@@ -65,7 +65,8 @@ max_loads_any_thread=0
 phase=0
 profile=0
 progress_interval=0
-simulate_stalls=false
+simulate_data_stalls=false
+simulate_inst_stalls=false
 system=system
 tracer=system.cpu.tracer
 width=1
@@ -109,6 +110,8 @@ read_only=true
 type=PhysicalMemory
 file=
 latency=1
+latency_var=0
+null=false
 range=133446500352:133446508543
 zero=false
 port=system.membus.port[7]
@@ -123,6 +126,7 @@ children=responder
 block_size=64
 bus_id=0
 clock=2
+header_cycles=1
 responder_set=false
 width=64
 default=system.iobus.responder.pio
@@ -150,6 +154,7 @@ children=responder
 block_size=64
 bus_id=1
 clock=2
+header_cycles=1
 responder_set=false
 width=64
 default=system.membus.responder.pio
@@ -175,6 +180,8 @@ pio=system.membus.default
 type=PhysicalMemory
 file=
 latency=1
+latency_var=0
+null=false
 range=133429198848:133429207039
 zero=false
 port=system.membus.port[6]
@@ -183,6 +190,8 @@ port=system.membus.port[6]
 type=PhysicalMemory
 file=
 latency=1
+latency_var=0
+null=false
 range=133445976064:133445984255
 zero=false
 port=system.membus.port[8]
@@ -191,6 +200,8 @@ port=system.membus.port[8]
 type=PhysicalMemory
 file=
 latency=1
+latency_var=0
+null=false
 range=1048576:68157439
 zero=true
 port=system.membus.port[3]
@@ -199,6 +210,8 @@ port=system.membus.port[3]
 type=PhysicalMemory
 file=
 latency=1
+latency_var=0
+null=false
 range=2147483648:2415919103
 zero=true
 port=system.membus.port[4]
@@ -207,13 +220,15 @@ port=system.membus.port[4]
 type=PhysicalMemory
 file=
 latency=1
+latency_var=0
+null=false
 range=1099243192320:1099251580927
 zero=false
 port=system.membus.port[5]
 
 [system.t1000]
 type=T1000
-children=fake_clk fake_jbi fake_l2_1 fake_l2_2 fake_l2_3 fake_l2_4 fake_l2esr_1 fake_l2esr_2 fake_l2esr_3 fake_l2esr_4 fake_membnks fake_ssi hconsole htod hvuart iob pconsole puart0
+children=fake_clk fake_jbi fake_l2_1 fake_l2_2 fake_l2_3 fake_l2_4 fake_l2esr_1 fake_l2esr_2 fake_l2esr_3 fake_l2esr_4 fake_membnks fake_ssi hterm htod hvuart iob pterm puart0
 intrctrl=system.intrctrl
 system=system
 
@@ -409,12 +424,11 @@ update_data=false
 warn_access=
 pio=system.iobus.port[10]
 
-[system.t1000.hconsole]
-type=SimConsole
-append_name=true
+[system.t1000.hterm]
+type=Terminal
 intr_control=system.intrctrl
 number=0
-output=console
+output=true
 port=3456
 
 [system.t1000.htod]
@@ -431,8 +445,8 @@ type=Uart8250
 pio_addr=1099255955456
 pio_latency=2
 platform=system.t1000
-sim_console=system.t1000.hconsole
 system=system
+terminal=system.t1000.hterm
 pio=system.iobus.port[13]
 
 [system.t1000.iob]
@@ -442,12 +456,11 @@ platform=system.t1000
 system=system
 pio=system.membus.port[0]
 
-[system.t1000.pconsole]
-type=SimConsole
-append_name=true
+[system.t1000.pterm]
+type=Terminal
 intr_control=system.intrctrl
 number=0
-output=console
+output=true
 port=3456
 
 [system.t1000.puart0]
@@ -455,7 +468,7 @@ type=Uart8250
 pio_addr=133412421632
 pio_latency=2
 platform=system.t1000
-sim_console=system.t1000.pconsole
 system=system
+terminal=system.t1000.pterm
 pio=system.iobus.port[12]
 
diff --git a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stdout b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stdout
index 4c8cf9392..78a121c17 100644
--- a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stdout
+++ b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stdout
@@ -1,13 +1,15 @@
 M5 Simulator System
 
-Copyright (c) 2001-2006
+Copyright (c) 2001-2008
 The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Aug 21 2007 14:42:25
-M5 started Tue Aug 21 14:44:56 2007
-M5 executing on nacho
+M5 compiled Jul 21 2008 20:41:45
+M5 started Mon Jul 21 20:41:46 2008
+M5 executing on zizzer
+M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881
+M5 commit date Tue Jul 15 14:38:51 2008 -0400
 command line: build/SPARC_FS/m5.fast -d build/SPARC_FS/tests/fast/long/80.solaris-boot/sparc/solaris/t1000-simple-atomic tests/run.py long/80.solaris-boot/sparc/solaris/t1000-simple-atomic
 Global frequency set at 2000000000 ticks per second
 Exiting @ tick 2233777512 because m5_exit instruction encountered