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author | Gabe Black <gblack@eecs.umich.edu> | 2007-08-26 20:27:53 -0700 |
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committer | Gabe Black <gblack@eecs.umich.edu> | 2007-08-26 20:27:53 -0700 |
commit | a51e2fd8bd581d45f8a87874c9a6680f99d11e24 (patch) | |
tree | 8de4626b115b234de0962cc04d32e15b6eb0fa3a /tests/quick/00.hello/ref/alpha/linux/simple-atomic/m5stats.txt | |
parent | e7e2d5ce9072808d94d5fe399e6c4262d92b7923 (diff) | |
download | gem5-a51e2fd8bd581d45f8a87874c9a6680f99d11e24.tar.xz |
Stats: Update the stats.
--HG--
extra : convert_revision : 888b6e3bcd432a9318d4b8741a8b274c6f37f1a8
Diffstat (limited to 'tests/quick/00.hello/ref/alpha/linux/simple-atomic/m5stats.txt')
-rw-r--r-- | tests/quick/00.hello/ref/alpha/linux/simple-atomic/m5stats.txt | 34 |
1 files changed, 25 insertions, 9 deletions
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/m5stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/m5stats.txt index f87ad2cd6..c89057e77 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/m5stats.txt @@ -1,18 +1,34 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 109073 # Simulator instruction rate (inst/s) -host_mem_usage 148564 # Number of bytes of host memory used -host_seconds 0.05 # Real time elapsed on the host -host_tick_rate 54123810 # Simulator tick rate (ticks/s) +host_inst_rate 274181 # Simulator instruction rate (inst/s) +host_mem_usage 172576 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host +host_tick_rate 135418658 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 5642 # Number of instructions simulated +sim_insts 5641 # Number of instructions simulated sim_seconds 0.000003 # Number of seconds simulated -sim_ticks 2820500 # Number of ticks simulated +sim_ticks 2833500 # Number of ticks simulated +system.cpu.dtb.accesses 1801 # DTB accesses +system.cpu.dtb.acv 0 # DTB access violations +system.cpu.dtb.hits 1791 # DTB hits +system.cpu.dtb.misses 10 # DTB misses +system.cpu.dtb.read_accesses 986 # DTB read accesses +system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.read_hits 979 # DTB read hits +system.cpu.dtb.read_misses 7 # DTB read misses +system.cpu.dtb.write_accesses 815 # DTB write accesses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_hits 812 # DTB write hits +system.cpu.dtb.write_misses 3 # DTB write misses system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.itb.accesses 5668 # ITB accesses +system.cpu.itb.acv 0 # ITB acv +system.cpu.itb.hits 5651 # ITB hits +system.cpu.itb.misses 17 # ITB misses system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 5642 # number of cpu cycles simulated -system.cpu.num_insts 5642 # Number of instructions executed -system.cpu.num_refs 1792 # Number of memory references +system.cpu.numCycles 5668 # number of cpu cycles simulated +system.cpu.num_insts 5641 # Number of instructions executed +system.cpu.num_refs 1801 # Number of memory references system.cpu.workload.PROG:num_syscalls 17 # Number of system calls ---------- End Simulation Statistics ---------- |