diff options
author | Steve Reinhardt <stever@gmail.com> | 2007-08-03 18:04:30 -0400 |
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committer | Steve Reinhardt <stever@gmail.com> | 2007-08-03 18:04:30 -0400 |
commit | bb3f7dc83b9a4c7b20aeb893fea447854c855225 (patch) | |
tree | 17d17b775e1155fa42725df488ddd22a3ce65af8 /tests/quick/00.hello/ref/alpha/linux/simple-atomic | |
parent | 851e3c852be4eb031293ed271502a0e14ca9273f (diff) | |
download | gem5-bb3f7dc83b9a4c7b20aeb893fea447854c855225.tar.xz |
tests: new ref outputs for new cache model
--HG--
extra : convert_revision : 244749072f97e425c2ca1cf296f2b95f37e99eb6
Diffstat (limited to 'tests/quick/00.hello/ref/alpha/linux/simple-atomic')
3 files changed, 13 insertions, 8 deletions
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini index e4dfe86d3..d025afdec 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini +++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini @@ -11,7 +11,7 @@ physmem=system.physmem [system.cpu] type=AtomicSimpleCPU -children=workload +children=tracer workload clock=500 cpu_id=0 defer_registration=false @@ -25,11 +25,15 @@ phase=0 progress_interval=0 simulate_stalls=false system=system +tracer=system.cpu.tracer width=1 workload=system.cpu.workload dcache_port=system.membus.port[2] icache_port=system.membus.port[1] +[system.cpu.tracer] +type=ExeTracer + [system.cpu.workload] type=LiveProcess cmd=hello diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/m5stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/m5stats.txt index f1c7bd968..f87ad2cd6 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/m5stats.txt @@ -1,8 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 93019 # Simulator instruction rate (inst/s) -host_seconds 0.06 # Real time elapsed on the host -host_tick_rate 46199079 # Simulator tick rate (ticks/s) +host_inst_rate 109073 # Simulator instruction rate (inst/s) +host_mem_usage 148564 # Number of bytes of host memory used +host_seconds 0.05 # Real time elapsed on the host +host_tick_rate 54123810 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5642 # Number of instructions simulated sim_seconds 0.000003 # Number of seconds simulated diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stdout b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stdout index 58fc0e374..0bec3d18f 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stdout +++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stdout @@ -6,9 +6,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jun 10 2007 14:06:20 -M5 started Sun Jun 10 14:22:34 2007 -M5 executing on iceaxe -command line: /Users/nate/build/outgoing/build/ALPHA_SE/m5.debug -d /Users/nate/build/outgoing/build/ALPHA_SE/tests/debug/quick/00.hello/alpha/linux/simple-atomic tests/run.py quick/00.hello/alpha/linux/simple-atomic +M5 compiled Aug 3 2007 03:56:47 +M5 started Fri Aug 3 04:17:12 2007 +M5 executing on zizzer.eecs.umich.edu +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-atomic tests/run.py quick/00.hello/alpha/linux/simple-atomic Global frequency set at 1000000000000 ticks per second Exiting @ tick 2820500 because target called exit() |