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author | Brad Beckmann <Brad.Beckmann@amd.com> | 2011-02-06 22:14:23 -0800 |
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committer | Brad Beckmann <Brad.Beckmann@amd.com> | 2011-02-06 22:14:23 -0800 |
commit | 45f881919fc9c4d2b2d4ea9f165fb567aad9849a (patch) | |
tree | 2a6ebbec93e62ef5279ec35e27e06f86577372fd /tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt | |
parent | f5aa75fdc528aca122ac1369fa4ac3df8a915027 (diff) | |
download | gem5-45f881919fc9c4d2b2d4ea9f165fb567aad9849a.tar.xz |
regress: Regression Tester output updates
Diffstat (limited to 'tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt')
-rw-r--r-- | tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt | 26 |
1 files changed, 21 insertions, 5 deletions
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt index d59a173b9..1cd8c8088 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 19405 # Simulator instruction rate (inst/s) -host_mem_usage 215700 # Number of bytes of host memory used -host_seconds 0.33 # Real time elapsed on the host -host_tick_rate 1038428 # Simulator tick rate (ticks/s) +host_inst_rate 54314 # Simulator instruction rate (inst/s) +host_mem_usage 214948 # Number of bytes of host memory used +host_seconds 0.12 # Real time elapsed on the host +host_tick_rate 2902474 # Simulator tick rate (ticks/s) sim_freq 1000000000 # Frequency of simulated ticks sim_insts 6404 # Number of instructions simulated sim_seconds 0.000343 # Number of seconds simulated @@ -43,8 +43,24 @@ system.cpu.itb.write_hits 0 # DT system.cpu.itb.write_misses 0 # DTB write misses system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 342698 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.num_busy_cycles 342698 # Number of busy cycles +system.cpu.num_conditional_control_insts 750 # number of instructions that are conditional controls +system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses +system.cpu.num_fp_insts 10 # number of float instructions +system.cpu.num_fp_register_reads 8 # number of times the floating registers were read +system.cpu.num_fp_register_writes 2 # number of times the floating registers were written +system.cpu.num_func_calls 251 # number of times a function call or return occured +system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 6404 # Number of instructions executed -system.cpu.num_refs 2060 # Number of memory references +system.cpu.num_int_alu_accesses 6331 # Number of integer alu accesses +system.cpu.num_int_insts 6331 # number of integer instructions +system.cpu.num_int_register_reads 8304 # number of times the integer registers were read +system.cpu.num_int_register_writes 4581 # number of times the integer registers were written +system.cpu.num_load_insts 1192 # Number of load instructions +system.cpu.num_mem_refs 2060 # number of memory refs +system.cpu.num_store_insts 868 # Number of store instructions system.cpu.workload.PROG:num_syscalls 17 # Number of system calls ---------- End Simulation Statistics ---------- |