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author | Kevin Lim <ktlim@umich.edu> | 2006-10-07 11:32:10 -0400 |
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committer | Kevin Lim <ktlim@umich.edu> | 2006-10-07 11:32:10 -0400 |
commit | 984579a6ada65b56c0552c74ef566bd04f59f755 (patch) | |
tree | 352fb35618d75583a992cfa6627df11bc8d5f755 /tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt | |
parent | 48e89a9d1eb186cce8bc0fab76c28730896b491a (diff) | |
download | gem5-984579a6ada65b56c0552c74ef566bd04f59f755.tar.xz |
Update refs.
tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini:
tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.out:
tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt:
tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stderr:
tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout:
Update refs. (Korey's initial push didn't use the default O3-timing config?)
--HG--
extra : convert_revision : d6bc241534483114def9cf88d7815ddfc9c88fd1
Diffstat (limited to 'tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt')
-rw-r--r-- | tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt index fe2cd43a5..d7688c435 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 113478 # Simulator instruction rate (inst/s) -host_mem_usage 159608 # Number of bytes of host memory used -host_seconds 0.05 # Real time elapsed on the host -host_tick_rate 165749 # Simulator tick rate (ticks/s) +host_inst_rate 305072 # Simulator instruction rate (inst/s) +host_mem_usage 159668 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host +host_tick_rate 439277 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5642 # Number of instructions simulated sim_seconds 0.000000 # Number of seconds simulated @@ -178,7 +178,7 @@ system.cpu.l2cache.no_allocate_misses 0 # Nu system.cpu.l2cache.overall_accesses 447 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 1.968610 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 1 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 1 # number of overall hits system.cpu.l2cache.overall_miss_latency 878 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.997763 # miss rate for overall accesses |