tests: new ref outputs for new cache model

--HG--
extra : convert_revision : 244749072f97e425c2ca1cf296f2b95f37e99eb6

1 files changed, 84 insertions, 64 deletions

diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt
index 1b70f10b3..db7224c2e 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt
@@ -1,12 +1,13 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                  54390                       # Simulator instruction rate (inst/s)
-host_seconds                                     0.10                       # Real time elapsed on the host
-host_tick_rate                              126525357                       # Simulator tick rate (ticks/s)
+host_inst_rate                                  65923                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 154180                       # Number of bytes of host memory used
+host_seconds                                     0.09                       # Real time elapsed on the host
+host_tick_rate                              155349854                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                        5642                       # Number of instructions simulated
 sim_seconds                                  0.000013                       # Number of seconds simulated
-sim_ticks                                    13168000                       # Number of ticks simulated
+sim_ticks                                    13359000                       # Number of ticks simulated
 system.cpu.dcache.ReadReq_accesses                979                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_avg_miss_latency        14000                       # average ReadReq miss latency
 system.cpu.dcache.ReadReq_avg_mshr_miss_latency        13000                       # average ReadReq mshr miss latency
@@ -20,13 +21,13 @@ system.cpu.dcache.ReadReq_mshr_misses              92                       # nu
 system.cpu.dcache.WriteReq_accesses               812                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_avg_miss_latency        14000                       # average WriteReq miss latency
 system.cpu.dcache.WriteReq_avg_mshr_miss_latency        13000                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits                   739                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency       1022000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate         0.089901                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses                  73                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency       949000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.089901                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses             73                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_hits                   725                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency       1218000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate         0.107143                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses                  87                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_miss_latency      1131000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate     0.107143                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses             87                       # number of WriteReq MSHR misses
 system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_refs                   9.854545                       # Average number of references to valid blocks.
@@ -38,14 +39,14 @@ system.cpu.dcache.cache_copies                      0                       # nu
 system.cpu.dcache.demand_accesses                1791                       # number of demand (read+write) accesses
 system.cpu.dcache.demand_avg_miss_latency        14000                       # average overall miss latency
 system.cpu.dcache.demand_avg_mshr_miss_latency        13000                       # average overall mshr miss latency
-system.cpu.dcache.demand_hits                    1626                       # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency         2310000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate           0.092127                       # miss rate for demand accesses
-system.cpu.dcache.demand_misses                   165                       # number of demand (read+write) misses
+system.cpu.dcache.demand_hits                    1612                       # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency         2506000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate           0.099944                       # miss rate for demand accesses
+system.cpu.dcache.demand_misses                   179                       # number of demand (read+write) misses
 system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency      2145000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate      0.092127                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses              165                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_miss_latency      2327000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate      0.099944                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses              179                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
@@ -53,14 +54,14 @@ system.cpu.dcache.overall_accesses               1791                       # nu
 system.cpu.dcache.overall_avg_miss_latency        14000                       # average overall miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency        13000                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits                   1626                       # number of overall hits
-system.cpu.dcache.overall_miss_latency        2310000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate          0.092127                       # miss rate for overall accesses
-system.cpu.dcache.overall_misses                  165                       # number of overall misses
+system.cpu.dcache.overall_hits                   1612                       # number of overall hits
+system.cpu.dcache.overall_miss_latency        2506000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate          0.099944                       # miss rate for overall accesses
+system.cpu.dcache.overall_misses                  179                       # number of overall misses
 system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency      2145000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate     0.092127                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses             165                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_miss_latency      2327000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate     0.099944                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses             179                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
 system.cpu.dcache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
@@ -75,18 +76,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss            0
 system.cpu.dcache.replacements                      0                       # number of replacements
 system.cpu.dcache.sampled_refs                    165                       # Sample count of references to valid blocks.
 system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse                103.640117                       # Cycle average of tags in use
+system.cpu.dcache.tagsinuse                103.895955                       # Cycle average of tags in use
 system.cpu.dcache.total_refs                     1626                       # Total number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.dcache.writebacks                        0                       # number of writebacks
 system.cpu.icache.ReadReq_accesses               5643                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 13960.288809                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 12960.288809                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_miss_latency 13992.779783                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 12992.779783                       # average ReadReq mshr miss latency
 system.cpu.icache.ReadReq_hits                   5366                       # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency        3867000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency        3876000                       # number of ReadReq miss cycles
 system.cpu.icache.ReadReq_miss_rate          0.049087                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_misses                  277                       # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_miss_latency      3590000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency      3599000                       # number of ReadReq MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate     0.049087                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_misses             277                       # number of ReadReq MSHR misses
 system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
@@ -98,29 +99,29 @@ system.cpu.icache.blocked_cycles_no_mshrs            0                       # n
 system.cpu.icache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.demand_accesses                5643                       # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 13960.288809                       # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 12960.288809                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_miss_latency 13992.779783                       # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 12992.779783                       # average overall mshr miss latency
 system.cpu.icache.demand_hits                    5366                       # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency         3867000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency         3876000                       # number of demand (read+write) miss cycles
 system.cpu.icache.demand_miss_rate           0.049087                       # miss rate for demand accesses
 system.cpu.icache.demand_misses                   277                       # number of demand (read+write) misses
 system.cpu.icache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency      3590000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency      3599000                       # number of demand (read+write) MSHR miss cycles
 system.cpu.icache.demand_mshr_miss_rate      0.049087                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_misses              277                       # number of demand (read+write) MSHR misses
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.overall_accesses               5643                       # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 13960.288809                       # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 12960.288809                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_miss_latency 13992.779783                       # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 12992.779783                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
 system.cpu.icache.overall_hits                   5366                       # number of overall hits
-system.cpu.icache.overall_miss_latency        3867000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency        3876000                       # number of overall miss cycles
 system.cpu.icache.overall_miss_rate          0.049087                       # miss rate for overall accesses
 system.cpu.icache.overall_misses                  277                       # number of overall misses
 system.cpu.icache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency      3590000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency      3599000                       # number of overall MSHR miss cycles
 system.cpu.icache.overall_mshr_miss_rate     0.049087                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_misses             277                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
@@ -137,53 +138,72 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss            0
 system.cpu.icache.replacements                      0                       # number of replacements
 system.cpu.icache.sampled_refs                    277                       # Sample count of references to valid blocks.
 system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse                129.241810                       # Cycle average of tags in use
+system.cpu.icache.tagsinuse                129.745202                       # Cycle average of tags in use
 system.cpu.icache.total_refs                     5366                       # Total number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.writebacks                        0                       # number of writebacks
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
-system.cpu.l2cache.ReadReq_accesses               441                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency        13000                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_accesses              73                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_avg_miss_latency        12000                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency        11000                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_miss_latency       876000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_rate              1                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_misses                73                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency       803000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_rate            1                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_misses           73                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadReq_accesses               369                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency        12000                       # average ReadReq miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency        11000                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_miss_latency       5733000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate                1                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses                 441                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency      4851000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate            1                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses            441                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_hits                     1                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency       4416000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate         0.997290                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses                 368                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency      4048000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate     0.997290                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses            368                       # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_accesses             14                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_avg_miss_latency        12000                       # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency        11000                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_miss_latency       168000                       # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_rate             1                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_misses               14                       # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency       154000                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate            1                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_misses           14                       # number of UpgradeReq MSHR misses
 system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs                         0                       # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs                  0.002825                       # Average number of references to valid blocks.
 system.cpu.l2cache.blocked_no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_no_targets               0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles_no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.demand_accesses                441                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency        13000                       # average overall miss latency
+system.cpu.l2cache.demand_accesses                442                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_avg_miss_latency        12000                       # average overall miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency        11000                       # average overall mshr miss latency
-system.cpu.l2cache.demand_hits                      0                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency        5733000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate                 1                       # miss rate for demand accesses
+system.cpu.l2cache.demand_hits                      1                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency        5292000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate          0.997738                       # miss rate for demand accesses
 system.cpu.l2cache.demand_misses                  441                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
 system.cpu.l2cache.demand_mshr_miss_latency      4851000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate            1                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate     0.997738                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_misses             441                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.overall_accesses               441                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency        13000                       # average overall miss latency
+system.cpu.l2cache.overall_accesses               442                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency        12000                       # average overall miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency        11000                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits                     0                       # number of overall hits
-system.cpu.l2cache.overall_miss_latency       5733000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate                1                       # miss rate for overall accesses
+system.cpu.l2cache.overall_hits                     1                       # number of overall hits
+system.cpu.l2cache.overall_miss_latency       5292000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate         0.997738                       # miss rate for overall accesses
 system.cpu.l2cache.overall_misses                 441                       # number of overall misses
 system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
 system.cpu.l2cache.overall_mshr_miss_latency      4851000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate            1                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate     0.997738                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_misses            441                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
@@ -197,14 +217,14 @@ system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit            0
 system.cpu.l2cache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
 system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
 system.cpu.l2cache.replacements                     0                       # number of replacements
-system.cpu.l2cache.sampled_refs                   441                       # Sample count of references to valid blocks.
+system.cpu.l2cache.sampled_refs                   354                       # Sample count of references to valid blocks.
 system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse               232.802947                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                       0                       # Total number of references to valid blocks.
+system.cpu.l2cache.tagsinuse               179.464793                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                       1                       # Total number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
 system.cpu.l2cache.writebacks                       0                       # number of writebacks
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.numCycles                         13168000                       # number of cpu cycles simulated
+system.cpu.numCycles                         13359000                       # number of cpu cycles simulated
 system.cpu.num_insts                             5642                       # Number of instructions executed
 system.cpu.num_refs                              1792                       # Number of memory references
 system.cpu.workload.PROG:num_syscalls              17                       # Number of system calls