Update refs.

--HG--
extra : convert_revision : 61d298fb0d9a66a76209a6bfcdb7c14f2efca947

5 files changed, 52 insertions, 57 deletions

diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini
index f8e1f1bb0..d8fc14e8d 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini
@@ -64,7 +64,6 @@ max_insts_all_threads=0
 max_insts_any_thread=0
 max_loads_all_threads=0
 max_loads_any_thread=0
-mem=system.cpu.dcache
 progress_interval=0
 system=system
 workload=system.cpu.workload
@@ -78,7 +77,6 @@ assoc=2
 block_size=64
 compressed_bus=false
 compression_latency=0
-do_copy=false
 hash_delay=1
 hit_latency=1
 latency=1
@@ -118,7 +116,6 @@ assoc=2
 block_size=64
 compressed_bus=false
 compression_latency=0
-do_copy=false
 hash_delay=1
 hit_latency=1
 latency=1
@@ -158,7 +155,6 @@ assoc=2
 block_size=64
 compressed_bus=false
 compression_latency=0
-do_copy=false
 hash_delay=1
 hit_latency=1
 latency=1
@@ -195,6 +191,7 @@ mem_side=system.membus.port[1]
 type=Bus
 bus_id=0
 clock=1000
+responder_set=false
 width=64
 port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
 
@@ -217,6 +214,7 @@ uid=100
 type=Bus
 bus_id=0
 clock=1000
+responder_set=false
 width=64
 port=system.physmem.port system.cpu.l2cache.mem_side
 
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.out b/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.out
index 2ab7c0150..e9f48f15c 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.out
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.out
@@ -21,45 +21,7 @@ type=Bus
 bus_id=0
 clock=1000
 width=64
-
-[system.cpu.dcache]
-type=BaseCache
-size=262144
-assoc=2
-block_size=64
-latency=1
-mshrs=10
-tgts_per_mshr=5
-write_buffers=8
-prioritizeRequests=false
-do_copy=false
-protocol=null
-trace_addr=0
-hash_delay=1
-repl=null
-compressed_bus=false
-store_compressed=false
-adaptive_compression=false
-compression_latency=0
-block_size=64
-max_miss_count=0
-addr_range=[0,18446744073709551615]
-split=false
-split_size=0
-lifo=false
-two_queue=false
-prefetch_miss=false
-prefetch_access=false
-prefetcher_size=100
-prefetch_past_page=false
-prefetch_serial_squash=false
-prefetch_latency=10
-prefetch_degree=1
-prefetch_policy=none
-prefetch_cache_check_push=true
-prefetch_use_cpu_id=true
-prefetch_data_accesses_only=false
-hit_latency=1
+responder_set=false
 
 [system.cpu.workload]
 type=LiveProcess
@@ -83,7 +45,6 @@ max_insts_all_threads=0
 max_loads_any_thread=0
 max_loads_all_threads=0
 progress_interval=0
-mem=system.cpu.dcache
 system=system
 cpu_id=0
 workload=system.cpu.workload
@@ -99,6 +60,7 @@ type=Bus
 bus_id=0
 clock=1000
 width=64
+responder_set=false
 
 [system.cpu.icache]
 type=BaseCache
@@ -110,7 +72,44 @@ mshrs=10
 tgts_per_mshr=5
 write_buffers=8
 prioritizeRequests=false
-do_copy=false
+protocol=null
+trace_addr=0
+hash_delay=1
+repl=null
+compressed_bus=false
+store_compressed=false
+adaptive_compression=false
+compression_latency=0
+block_size=64
+max_miss_count=0
+addr_range=[0,18446744073709551615]
+split=false
+split_size=0
+lifo=false
+two_queue=false
+prefetch_miss=false
+prefetch_access=false
+prefetcher_size=100
+prefetch_past_page=false
+prefetch_serial_squash=false
+prefetch_latency=10
+prefetch_degree=1
+prefetch_policy=none
+prefetch_cache_check_push=true
+prefetch_use_cpu_id=true
+prefetch_data_accesses_only=false
+hit_latency=1
+
+[system.cpu.dcache]
+type=BaseCache
+size=262144
+assoc=2
+block_size=64
+latency=1
+mshrs=10
+tgts_per_mshr=5
+write_buffers=8
+prioritizeRequests=false
 protocol=null
 trace_addr=0
 hash_delay=1
@@ -149,7 +148,6 @@ mshrs=10
 tgts_per_mshr=5
 write_buffers=8
 prioritizeRequests=false
-do_copy=false
 protocol=null
 trace_addr=0
 hash_delay=1
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt
index 6ab4e0920..27822f334 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                   8293                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 179892                       # Number of bytes of host memory used
-host_seconds                                     0.68                       # Real time elapsed on the host
-host_tick_rate                                2595779                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 179790                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 179436                       # Number of bytes of host memory used
+host_seconds                                     0.03                       # Real time elapsed on the host
+host_tick_rate                               55533187                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                        5642                       # Number of instructions simulated
 sim_seconds                                  0.000002                       # Number of seconds simulated
@@ -53,7 +53,7 @@ system.cpu.dcache.no_allocate_misses                0                       # Nu
 system.cpu.dcache.overall_accesses               1791                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_avg_miss_latency  3984.721212                       # average overall miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency  2984.721212                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no value                       # average overall mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
 system.cpu.dcache.overall_hits                   1626                       # number of overall hits
 system.cpu.dcache.overall_miss_latency         657479                       # number of overall miss cycles
 system.cpu.dcache.overall_miss_rate          0.092127                       # miss rate for overall accesses
@@ -115,7 +115,7 @@ system.cpu.icache.no_allocate_misses                0                       # Nu
 system.cpu.icache.overall_accesses               5643                       # number of overall (read+write) accesses
 system.cpu.icache.overall_avg_miss_latency  3980.490975                       # average overall miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency  2980.490975                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency     no value                       # average overall mshr uncacheable latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
 system.cpu.icache.overall_hits                   5366                       # number of overall hits
 system.cpu.icache.overall_miss_latency        1102596                       # number of overall miss cycles
 system.cpu.icache.overall_miss_rate          0.049087                       # miss rate for overall accesses
@@ -178,7 +178,7 @@ system.cpu.l2cache.no_allocate_misses               0                       # Nu
 system.cpu.l2cache.overall_accesses               442                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_avg_miss_latency  2984.340136                       # average overall miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency  1983.340136                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no value                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
 system.cpu.l2cache.overall_hits                     1                       # number of overall hits
 system.cpu.l2cache.overall_miss_latency       1316094                       # number of overall miss cycles
 system.cpu.l2cache.overall_miss_rate         0.997738                       # miss rate for overall accesses
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/stderr b/tests/quick/00.hello/ref/alpha/linux/simple-timing/stderr
index 5e6a1840a..87866a2a5 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/stderr
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/stderr
@@ -1,2 +1 @@
 warn: Entering event queue @ 0.  Starting simulation...
-warn: Increasing stack 0x11ff92000:0x11ff9b000 to 0x11ff90000:0x11ff9b000 because of access to 0x11ff91ff0
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout b/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout
index 31db8804a..61f79d88f 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout
@@ -6,8 +6,8 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Oct 13 2006 16:07:10
-M5 started Fri Oct 13 16:08:16 2006
+M5 compiled Nov  3 2006 17:10:27
+M5 started Fri Nov  3 17:10:44 2006
 M5 executing on zizzer.eecs.umich.edu
-command line: build/ALPHA_SE/m5.debug -d build/ALPHA_SE/tests/debug/quick/00.hello/alpha/linux/simple-timing tests/run.py quick/00.hello/alpha/linux/simple-timing
+command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/simple-timing tests/run.py quick/00.hello/alpha/linux/simple-timing
 Exiting @ tick 1767066 because target called exit()