Bus: Update the stats for the recent bus fix.

--HG--
extra : convert_revision : dc29f7b5e6fa30a50305193cb0e5aed942f7e407

4 files changed, 57 insertions, 53 deletions

diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini
index 78fe6c01f..7b95a328d 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini
@@ -152,6 +152,7 @@ type=Bus
 block_size=64
 bus_id=0
 clock=1000
+header_cycles=1
 responder_set=false
 width=64
 port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
@@ -169,6 +170,7 @@ euid=100
 executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello
 gid=100
 input=cin
+max_stack_size=67108864
 output=cout
 pid=100
 ppid=99
@@ -180,6 +182,7 @@ type=Bus
 block_size=64
 bus_id=0
 clock=1000
+header_cycles=1
 responder_set=false
 width=64
 port=system.physmem.port[0] system.cpu.l2cache.mem_side
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt
index 51a854d5e..d791e0a2e 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt
@@ -1,31 +1,31 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 341217                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 196644                       # Number of bytes of host memory used
-host_seconds                                     0.02                       # Real time elapsed on the host
-host_tick_rate                             1094407052                       # Simulator tick rate (ticks/s)
+host_inst_rate                                  11324                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 193960                       # Number of bytes of host memory used
+host_seconds                                     0.50                       # Real time elapsed on the host
+host_tick_rate                               38693743                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                        5641                       # Number of instructions simulated
-sim_seconds                                  0.000018                       # Number of seconds simulated
-sim_ticks                                    18374000                       # Number of ticks simulated
+sim_seconds                                  0.000019                       # Number of seconds simulated
+sim_ticks                                    19285000                       # Number of ticks simulated
 system.cpu.dcache.ReadReq_accesses                979                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency        25000                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency        23000                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency        27000                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency        24000                       # average ReadReq mshr miss latency
 system.cpu.dcache.ReadReq_hits                    887                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency        2300000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency        2484000                       # number of ReadReq miss cycles
 system.cpu.dcache.ReadReq_miss_rate          0.093973                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_misses                   92                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency      2116000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency      2208000                       # number of ReadReq MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate     0.093973                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_misses              92                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_accesses               812                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency        25000                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency        23000                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency        27000                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency        24000                       # average WriteReq mshr miss latency
 system.cpu.dcache.WriteReq_hits                   725                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency       2175000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency       2349000                       # number of WriteReq miss cycles
 system.cpu.dcache.WriteReq_miss_rate         0.107143                       # miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_misses                  87                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency      2001000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency      2088000                       # number of WriteReq MSHR miss cycles
 system.cpu.dcache.WriteReq_mshr_miss_rate     0.107143                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_misses             87                       # number of WriteReq MSHR misses
 system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
@@ -37,29 +37,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs            0                       # n
 system.cpu.dcache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.demand_accesses                1791                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency        25000                       # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency        23000                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_miss_latency        27000                       # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency        24000                       # average overall mshr miss latency
 system.cpu.dcache.demand_hits                    1612                       # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency         4475000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency         4833000                       # number of demand (read+write) miss cycles
 system.cpu.dcache.demand_miss_rate           0.099944                       # miss rate for demand accesses
 system.cpu.dcache.demand_misses                   179                       # number of demand (read+write) misses
 system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency      4117000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency      4296000                       # number of demand (read+write) MSHR miss cycles
 system.cpu.dcache.demand_mshr_miss_rate      0.099944                       # mshr miss rate for demand accesses
 system.cpu.dcache.demand_mshr_misses              179                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.overall_accesses               1791                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency        25000                       # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency        23000                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_miss_latency        27000                       # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency        24000                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
 system.cpu.dcache.overall_hits                   1612                       # number of overall hits
-system.cpu.dcache.overall_miss_latency        4475000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency        4833000                       # number of overall miss cycles
 system.cpu.dcache.overall_miss_rate          0.099944                       # miss rate for overall accesses
 system.cpu.dcache.overall_misses                  179                       # number of overall misses
 system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency      4117000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency      4296000                       # number of overall MSHR miss cycles
 system.cpu.dcache.overall_mshr_miss_rate     0.099944                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_misses             179                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
@@ -76,7 +76,7 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss            0
 system.cpu.dcache.replacements                      0                       # number of replacements
 system.cpu.dcache.sampled_refs                    165                       # Sample count of references to valid blocks.
 system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse                102.386256                       # Cycle average of tags in use
+system.cpu.dcache.tagsinuse                102.207107                       # Cycle average of tags in use
 system.cpu.dcache.total_refs                     1626                       # Total number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.dcache.writebacks                        0                       # number of writebacks
@@ -93,13 +93,13 @@ system.cpu.dtb.write_acv                            0                       # DT
 system.cpu.dtb.write_hits                         812                       # DTB write hits
 system.cpu.dtb.write_misses                         3                       # DTB write misses
 system.cpu.icache.ReadReq_accesses               5652                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 24956.678700                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 22956.678700                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_miss_latency 26953.068592                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 23953.068592                       # average ReadReq mshr miss latency
 system.cpu.icache.ReadReq_hits                   5375                       # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency        6913000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency        7466000                       # number of ReadReq miss cycles
 system.cpu.icache.ReadReq_miss_rate          0.049009                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_misses                  277                       # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_miss_latency      6359000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency      6635000                       # number of ReadReq MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate     0.049009                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_misses             277                       # number of ReadReq MSHR misses
 system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
@@ -111,29 +111,29 @@ system.cpu.icache.blocked_cycles_no_mshrs            0                       # n
 system.cpu.icache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.demand_accesses                5652                       # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 24956.678700                       # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 22956.678700                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_miss_latency 26953.068592                       # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 23953.068592                       # average overall mshr miss latency
 system.cpu.icache.demand_hits                    5375                       # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency         6913000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency         7466000                       # number of demand (read+write) miss cycles
 system.cpu.icache.demand_miss_rate           0.049009                       # miss rate for demand accesses
 system.cpu.icache.demand_misses                   277                       # number of demand (read+write) misses
 system.cpu.icache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency      6359000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency      6635000                       # number of demand (read+write) MSHR miss cycles
 system.cpu.icache.demand_mshr_miss_rate      0.049009                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_misses              277                       # number of demand (read+write) MSHR misses
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.overall_accesses               5652                       # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 24956.678700                       # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 22956.678700                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_miss_latency 26953.068592                       # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 23953.068592                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
 system.cpu.icache.overall_hits                   5375                       # number of overall hits
-system.cpu.icache.overall_miss_latency        6913000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency        7466000                       # number of overall miss cycles
 system.cpu.icache.overall_miss_rate          0.049009                       # miss rate for overall accesses
 system.cpu.icache.overall_misses                  277                       # number of overall misses
 system.cpu.icache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency      6359000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency      6635000                       # number of overall MSHR miss cycles
 system.cpu.icache.overall_mshr_miss_rate     0.049009                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_misses             277                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
@@ -150,7 +150,7 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss            0
 system.cpu.icache.replacements                      0                       # number of replacements
 system.cpu.icache.sampled_refs                    277                       # Sample count of references to valid blocks.
 system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse                128.084203                       # Cycle average of tags in use
+system.cpu.icache.tagsinuse                127.893604                       # Cycle average of tags in use
 system.cpu.icache.total_refs                     5375                       # Total number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.writebacks                        0                       # number of writebacks
@@ -160,28 +160,28 @@ system.cpu.itb.acv                                  0                       # IT
 system.cpu.itb.hits                              5652                       # ITB hits
 system.cpu.itb.misses                              17                       # ITB misses
 system.cpu.l2cache.ReadExReq_accesses              73                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency        22000                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency        23000                       # average ReadExReq miss latency
 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency        11000                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_miss_latency      1606000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency      1679000                       # number of ReadExReq miss cycles
 system.cpu.l2cache.ReadExReq_miss_rate              1                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_misses                73                       # number of ReadExReq misses
 system.cpu.l2cache.ReadExReq_mshr_miss_latency       803000                       # number of ReadExReq MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_rate            1                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_misses           73                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadReq_accesses               369                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency        22000                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency        23000                       # average ReadReq miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency        11000                       # average ReadReq mshr miss latency
 system.cpu.l2cache.ReadReq_hits                     1                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency       8096000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency       8464000                       # number of ReadReq miss cycles
 system.cpu.l2cache.ReadReq_miss_rate         0.997290                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_misses                 368                       # number of ReadReq misses
 system.cpu.l2cache.ReadReq_mshr_miss_latency      4048000                       # number of ReadReq MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_miss_rate     0.997290                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_misses            368                       # number of ReadReq MSHR misses
 system.cpu.l2cache.UpgradeReq_accesses             14                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_avg_miss_latency        22000                       # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency        23000                       # average UpgradeReq miss latency
 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency        11000                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_miss_latency       308000                       # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency       322000                       # number of UpgradeReq miss cycles
 system.cpu.l2cache.UpgradeReq_miss_rate             1                       # miss rate for UpgradeReq accesses
 system.cpu.l2cache.UpgradeReq_misses               14                       # number of UpgradeReq misses
 system.cpu.l2cache.UpgradeReq_mshr_miss_latency       154000                       # number of UpgradeReq MSHR miss cycles
@@ -196,10 +196,10 @@ system.cpu.l2cache.blocked_cycles_no_mshrs            0                       #
 system.cpu.l2cache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.demand_accesses                442                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency        22000                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency        23000                       # average overall miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency        11000                       # average overall mshr miss latency
 system.cpu.l2cache.demand_hits                      1                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency        9702000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency       10143000                       # number of demand (read+write) miss cycles
 system.cpu.l2cache.demand_miss_rate          0.997738                       # miss rate for demand accesses
 system.cpu.l2cache.demand_misses                  441                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
@@ -210,11 +210,11 @@ system.cpu.l2cache.fast_writes                      0                       # nu
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.l2cache.overall_accesses               442                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency        22000                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency        23000                       # average overall miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency        11000                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
 system.cpu.l2cache.overall_hits                     1                       # number of overall hits
-system.cpu.l2cache.overall_miss_latency       9702000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency      10143000                       # number of overall miss cycles
 system.cpu.l2cache.overall_miss_rate         0.997738                       # miss rate for overall accesses
 system.cpu.l2cache.overall_misses                 441                       # number of overall misses
 system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
@@ -235,12 +235,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss            0
 system.cpu.l2cache.replacements                     0                       # number of replacements
 system.cpu.l2cache.sampled_refs                   354                       # Sample count of references to valid blocks.
 system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse               177.499846                       # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse               177.260989                       # Cycle average of tags in use
 system.cpu.l2cache.total_refs                       1                       # Total number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
 system.cpu.l2cache.writebacks                       0                       # number of writebacks
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.numCycles                            36748                       # number of cpu cycles simulated
+system.cpu.numCycles                            38570                       # number of cpu cycles simulated
 system.cpu.num_insts                             5641                       # Number of instructions executed
 system.cpu.num_refs                              1801                       # Number of memory references
 system.cpu.workload.PROG:num_syscalls              17                       # Number of system calls
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/stderr b/tests/quick/00.hello/ref/alpha/linux/simple-timing/stderr
index f33d007a7..5992f7131 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/stderr
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/stderr
@@ -1,2 +1,3 @@
+0: system.remote_gdb.listener: listening for remote gdb on port 7000
 warn: Entering event queue @ 0.  Starting simulation...
 warn: Increasing stack size by one page.
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout b/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout
index 67d82b1c5..11d2e9b8e 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout
@@ -1,14 +1,14 @@
 Hello world!
 M5 Simulator System
 
-Copyright (c) 2001-2006
+Copyright (c) 2001-2008
 The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Aug 14 2007 17:58:14
-M5 started Tue Aug 14 17:59:07 2007
-M5 executing on nacho
+M5 compiled Feb 24 2008 12:58:20
+M5 started Sun Feb 24 12:58:22 2008
+M5 executing on tater
 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-timing tests/run.py quick/00.hello/alpha/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
-Exiting @ tick 18374000 because target called exit()
+Exiting @ tick 19285000 because target called exit()