Update refs.

tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini:
tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.out:
tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt:
tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stderr:
tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout:
    Update refs. (Korey's initial push didn't use the default O3-timing config?)

--HG--
extra : convert_revision : d6bc241534483114def9cf88d7815ddfc9c88fd1

4 files changed, 26 insertions, 7 deletions

diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini
index 80d2a27e1..cefcf7f11 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini
@@ -64,6 +64,7 @@ max_insts_any_thread=0
 max_loads_all_threads=0
 max_loads_any_thread=0
 mem=system.cpu.dcache
+progress_interval=0
 system=system
 workload=system.cpu.workload
 dcache_port=system.cpu.dcache.cpu_side
@@ -197,11 +198,17 @@ port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cp
 [system.cpu.workload]
 type=LiveProcess
 cmd=hello
+egid=100
 env=
+euid=100
 executable=tests/test-progs/hello/bin/alpha/linux/hello
+gid=100
 input=cin
 output=cout
+pid=100
+ppid=99
 system=system
+uid=100
 
 [system.membus]
 type=Bus
@@ -217,6 +224,7 @@ port=system.membus.port[0]
 
 [trace]
 bufsize=0
+cycle=0
 dump_on_exit=false
 file=cout
 flags=
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.out b/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.out
index 09d8f0c22..1ed18ff71 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.out
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.out
@@ -67,6 +67,12 @@ input=cin
 output=cout
 env=
 system=system
+uid=100
+euid=100
+gid=100
+egid=100
+pid=100
+ppid=99
 
 [system.cpu]
 type=TimingSimpleCPU
@@ -74,6 +80,7 @@ max_insts_any_thread=0
 max_insts_all_threads=0
 max_loads_any_thread=0
 max_loads_all_threads=0
+progress_interval=0
 mem=system.cpu.dcache
 system=system
 workload=system.cpu.workload
@@ -169,6 +176,7 @@ hit_latency=1
 [trace]
 flags=
 start=0
+cycle=0
 bufsize=0
 file=cout
 dump_on_exit=false
@@ -212,3 +220,6 @@ trace_system=client
 [debug]
 break_cycles=
 
+[statsreset]
+reset_cycle=0
+
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt
index fe2cd43a5..d7688c435 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 113478                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 159608                       # Number of bytes of host memory used
-host_seconds                                     0.05                       # Real time elapsed on the host
-host_tick_rate                                 165749                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 305072                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 159668                       # Number of bytes of host memory used
+host_seconds                                     0.02                       # Real time elapsed on the host
+host_tick_rate                                 439277                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                        5642                       # Number of instructions simulated
 sim_seconds                                  0.000000                       # Number of seconds simulated
@@ -178,7 +178,7 @@ system.cpu.l2cache.no_allocate_misses               0                       # Nu
 system.cpu.l2cache.overall_accesses               447                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_avg_miss_latency     1.968610                       # average overall miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency            1                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no value                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
 system.cpu.l2cache.overall_hits                     1                       # number of overall hits
 system.cpu.l2cache.overall_miss_latency           878                       # number of overall miss cycles
 system.cpu.l2cache.overall_miss_rate         0.997763                       # miss rate for overall accesses
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout b/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout
index 7104aa0ce..3edc94e09 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout
@@ -6,8 +6,8 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Sep  5 2006 15:28:48
-M5 started Tue Sep  5 15:42:15 2006
+M5 compiled Oct  7 2006 11:12:49
+M5 started Sat Oct  7 11:13:04 2006
 M5 executing on zizzer.eecs.umich.edu
 command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/simple-timing tests/run.py quick/00.hello/alpha/linux/simple-timing
 Exiting @ tick 8312 because target called exit()