MOESI Hammer: Update regression test output

5 files changed, 166 insertions, 165 deletions

diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini
index 31dc2c5f8..3c544cad1 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini
@@ -9,6 +9,8 @@ time_sync_spin_threshold=100000
 type=System
 children=cpu dir_cntrl0 l1_cntrl0 physmem ruby
 mem_mode=timing
+memories=system.physmem
+num_work_ids=16
 physmem=system.physmem
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
@@ -41,8 +43,8 @@ progress_interval=0
 system=system
 tracer=system.cpu.tracer
 workload=system.cpu.workload
-dcache_port=system.ruby.cpu_ruby_ports.port[1]
-icache_port=system.ruby.cpu_ruby_ports.port[0]
+dcache_port=system.l1_cntrl0.sequencer.port[1]
+icache_port=system.l1_cntrl0.sequencer.port[0]
 
 [system.cpu.dtb]
 type=AlphaTLB
@@ -63,7 +65,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/linux/hello
+executable=tests/test-progs/hello/bin/alpha/linux/hello
 gid=100
 input=cin
 max_stack_size=67108864
@@ -87,6 +89,7 @@ number_of_TBEs=256
 probeFilter=system.dir_cntrl0.probeFilter
 probe_filter_enabled=false
 recycle_latency=10
+ruby_system=system.ruby
 transitions_per_cycle=32
 version=0
 
@@ -122,6 +125,7 @@ version=0
 [system.dir_cntrl0.probeFilter]
 type=RubyCache
 assoc=4
+is_icache=false
 latency=1
 replacement_policy=PSEUDO_LRU
 size=1024
@@ -129,9 +133,9 @@ start_index_bit=6
 
 [system.l1_cntrl0]
 type=L1Cache_Controller
-children=L2cacheMemory
-L1DcacheMemory=system.ruby.cpu_ruby_ports.dcache
-L1IcacheMemory=system.ruby.cpu_ruby_ports.icache
+children=L1DcacheMemory L1IcacheMemory L2cacheMemory sequencer
+L1DcacheMemory=system.l1_cntrl0.L1DcacheMemory
+L1IcacheMemory=system.l1_cntrl0.L1IcacheMemory
 L2cacheMemory=system.l1_cntrl0.L2cacheMemory
 buffer_size=0
 cache_response_latency=10
@@ -141,18 +145,53 @@ l2_cache_hit_latency=10
 no_mig_atomic=true
 number_of_TBEs=256
 recycle_latency=10
-sequencer=system.ruby.cpu_ruby_ports
+ruby_system=system.ruby
+sequencer=system.l1_cntrl0.sequencer
 transitions_per_cycle=32
 version=0
 
+[system.l1_cntrl0.L1DcacheMemory]
+type=RubyCache
+assoc=2
+is_icache=false
+latency=2
+replacement_policy=PSEUDO_LRU
+size=256
+start_index_bit=6
+
+[system.l1_cntrl0.L1IcacheMemory]
+type=RubyCache
+assoc=2
+is_icache=true
+latency=2
+replacement_policy=PSEUDO_LRU
+size=256
+start_index_bit=6
+
 [system.l1_cntrl0.L2cacheMemory]
 type=RubyCache
 assoc=2
+is_icache=false
 latency=10
 replacement_policy=PSEUDO_LRU
 size=512
 start_index_bit=6
 
+[system.l1_cntrl0.sequencer]
+type=RubySequencer
+access_phys_mem=true
+dcache=system.l1_cntrl0.L1DcacheMemory
+deadlock_threshold=500000
+icache=system.l1_cntrl0.L1IcacheMemory
+max_outstanding_requests=16
+physmem=system.physmem
+ruby_system=system.ruby
+using_network_tester=false
+using_ruby_tester=false
+version=0
+physMemPort=system.physmem.port[0]
+port=system.cpu.icache_port system.cpu.dcache_port
+
 [system.physmem]
 type=PhysicalMemory
 file=
@@ -161,52 +200,18 @@ latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.ruby.cpu_ruby_ports.physMemPort
+port=system.l1_cntrl0.sequencer.physMemPort
 
 [system.ruby]
 type=RubySystem
-children=cpu_ruby_ports network profiler tracer
+children=network profiler tracer
 block_size_bytes=64
 clock=1
 mem_size=134217728
-network=system.ruby.network
 no_mem_vec=false
-profiler=system.ruby.profiler
 random_seed=1234
 randomization=false
 stats_filename=ruby.stats
-tracer=system.ruby.tracer
-
-[system.ruby.cpu_ruby_ports]
-type=RubySequencer
-children=dcache icache
-access_phys_mem=true
-dcache=system.ruby.cpu_ruby_ports.dcache
-deadlock_threshold=500000
-icache=system.ruby.cpu_ruby_ports.icache
-max_outstanding_requests=16
-physmem=system.physmem
-using_network_tester=false
-using_ruby_tester=false
-version=0
-physMemPort=system.physmem.port[0]
-port=system.cpu.icache_port system.cpu.dcache_port
-
-[system.ruby.cpu_ruby_ports.dcache]
-type=RubyCache
-assoc=2
-latency=2
-replacement_policy=PSEUDO_LRU
-size=256
-start_index_bit=6
-
-[system.ruby.cpu_ruby_ports.icache]
-type=RubyCache
-assoc=2
-latency=2
-replacement_policy=PSEUDO_LRU
-size=256
-start_index_bit=6
 
 [system.ruby.network]
 type=SimpleNetwork
@@ -216,6 +221,7 @@ buffer_size=0
 control_msg_size=8
 endpoint_bandwidth=1000
 number_of_virtual_networks=10
+ruby_system=system.ruby
 topology=system.ruby.network.topology
 
 [system.ruby.network.topology]
@@ -280,8 +286,10 @@ type=RubyProfiler
 all_instructions=false
 hot_lines=false
 num_of_sequencers=1
+ruby_system=system.ruby
 
 [system.ruby.tracer]
 type=RubyTracer
+ruby_system=system.ruby
 warmup_length=100000
 
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/ruby.stats b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/ruby.stats
index 026d71a83..c8eb7f5d6 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/ruby.stats
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/ruby.stats
@@ -34,27 +34,27 @@ periodic_stats_period: 1000000
 ================ End RubySystem Configuration Print ================
 
 
-Real time: Apr/28/2011 15:12:18
+Real time: Jan/10/2012 12:41:50
 
 Profiler Stats
 --------------
-Elapsed_time_in_seconds: 0
-Elapsed_time_in_minutes: 0
-Elapsed_time_in_hours: 0
-Elapsed_time_in_days: 0
+Elapsed_time_in_seconds: 1
+Elapsed_time_in_minutes: 0.0166667
+Elapsed_time_in_hours: 0.000277778
+Elapsed_time_in_days: 1.15741e-05
 
-Virtual_time_in_seconds: 0.46
-Virtual_time_in_minutes: 0.00766667
-Virtual_time_in_hours:   0.000127778
-Virtual_time_in_days:    5.32407e-06
+Virtual_time_in_seconds: 0.28
+Virtual_time_in_minutes: 0.00466667
+Virtual_time_in_hours:   7.77778e-05
+Virtual_time_in_days:    3.24074e-06
 
 Ruby_current_time: 208400
 Ruby_start_time: 0
 Ruby_cycles: 208400
 
-mbytes_resident: 39.1133
-mbytes_total: 221.852
-resident_ratio: 0.176357
+mbytes_resident: 39.0547
+mbytes_total: 234.742
+resident_ratio: 0.166439
 
 ruby_cycles_executed: [ 208401 ]
 
@@ -126,8 +126,8 @@ Resource Usage
 page_size: 4096
 user_time: 0
 system_time: 0
-page_reclaims: 11228
-page_faults: 0
+page_reclaims: 10898
+page_faults: 53
 swaps: 0
 block_inputs: 0
 block_outputs: 0
@@ -181,28 +181,28 @@ links_utilized_percent_switch_2: 2.15187
   outgoing_messages_switch_2_link_1_Writeback_Control: 2066 16528 [ 0 0 1143 0 0 923 0 0 0 0 ] base_latency: 1
   outgoing_messages_switch_2_link_1_Unblock_Control: 1159 9272 [ 0 0 0 0 0 1159 0 0 0 0 ] base_latency: 1
 
-Cache Stats: system.ruby.cpu_ruby_ports.icache
-  system.ruby.cpu_ruby_ports.icache_total_misses: 646
-  system.ruby.cpu_ruby_ports.icache_total_demand_misses: 646
-  system.ruby.cpu_ruby_ports.icache_total_prefetches: 0
-  system.ruby.cpu_ruby_ports.icache_total_sw_prefetches: 0
-  system.ruby.cpu_ruby_ports.icache_total_hw_prefetches: 0
+Cache Stats: system.l1_cntrl0.L1IcacheMemory
+  system.l1_cntrl0.L1IcacheMemory_total_misses: 646
+  system.l1_cntrl0.L1IcacheMemory_total_demand_misses: 646
+  system.l1_cntrl0.L1IcacheMemory_total_prefetches: 0
+  system.l1_cntrl0.L1IcacheMemory_total_sw_prefetches: 0
+  system.l1_cntrl0.L1IcacheMemory_total_hw_prefetches: 0
 
-  system.ruby.cpu_ruby_ports.icache_request_type_IFETCH:   100%
+  system.l1_cntrl0.L1IcacheMemory_request_type_IFETCH:   100%
 
-  system.ruby.cpu_ruby_ports.icache_access_mode_type_Supervisor:   646    100%
+  system.l1_cntrl0.L1IcacheMemory_access_mode_type_Supervisor:   646    100%
 
-Cache Stats: system.ruby.cpu_ruby_ports.dcache
-  system.ruby.cpu_ruby_ports.dcache_total_misses: 716
-  system.ruby.cpu_ruby_ports.dcache_total_demand_misses: 716
-  system.ruby.cpu_ruby_ports.dcache_total_prefetches: 0
-  system.ruby.cpu_ruby_ports.dcache_total_sw_prefetches: 0
-  system.ruby.cpu_ruby_ports.dcache_total_hw_prefetches: 0
+Cache Stats: system.l1_cntrl0.L1DcacheMemory
+  system.l1_cntrl0.L1DcacheMemory_total_misses: 716
+  system.l1_cntrl0.L1DcacheMemory_total_demand_misses: 716
+  system.l1_cntrl0.L1DcacheMemory_total_prefetches: 0
+  system.l1_cntrl0.L1DcacheMemory_total_sw_prefetches: 0
+  system.l1_cntrl0.L1DcacheMemory_total_hw_prefetches: 0
 
-  system.ruby.cpu_ruby_ports.dcache_request_type_LD:   73.324%
-  system.ruby.cpu_ruby_ports.dcache_request_type_ST:   26.676%
+  system.l1_cntrl0.L1DcacheMemory_request_type_LD:   73.324%
+  system.l1_cntrl0.L1DcacheMemory_request_type_ST:   26.676%
 
-  system.ruby.cpu_ruby_ports.dcache_access_mode_type_Supervisor:   716    100%
+  system.l1_cntrl0.L1DcacheMemory_access_mode_type_Supervisor:   716    100%
 
 Cache Stats: system.l1_cntrl0.L2cacheMemory
   system.l1_cntrl0.L2cacheMemory_total_misses: 1362
@@ -289,9 +289,9 @@ O  NC_DMA_GETS [0 ] 0
 O  Invalidate [0 ] 0
 O  Flush_line [0 ] 0
 
-M  Load [368 ] 368
-M  Ifetch [5833 ] 5833
-M  Store [66 ] 66
+M  Load [306 ] 306
+M  Ifetch [5768 ] 5768
+M  Store [60 ] 60
 M  L2_Replacement [923 ] 923
 M  L1_to_L2 [1061 ] 1061
 M  Trigger_L2_to_L1D [68 ] 68
@@ -304,9 +304,9 @@ M  NC_DMA_GETS [0 ] 0
 M  Invalidate [0 ] 0
 M  Flush_line [0 ] 0
 
-MM  Load [397 ] 397
+MM  Load [354 ] 354
 MM  Ifetch [0 ] 0
-MM  Store [641 ] 641
+MM  Store [614 ] 614
 MM  L2_Replacement [220 ] 220
 MM  L1_to_L2 [293 ] 293
 MM  Trigger_L2_to_L1D [70 ] 70
@@ -319,6 +319,36 @@ MM  NC_DMA_GETS [0 ] 0
 MM  Invalidate [0 ] 0
 MM  Flush_line [0 ] 0
 
+IR  Load [0 ] 0
+IR  Ifetch [0 ] 0
+IR  Store [0 ] 0
+IR  L1_to_L2 [0 ] 0
+IR  Flush_line [0 ] 0
+
+SR  Load [0 ] 0
+SR  Ifetch [0 ] 0
+SR  Store [0 ] 0
+SR  L1_to_L2 [0 ] 0
+SR  Flush_line [0 ] 0
+
+OR  Load [0 ] 0
+OR  Ifetch [0 ] 0
+OR  Store [0 ] 0
+OR  L1_to_L2 [0 ] 0
+OR  Flush_line [0 ] 0
+
+MR  Load [62 ] 62
+MR  Ifetch [65 ] 65
+MR  Store [6 ] 6
+MR  L1_to_L2 [0 ] 0
+MR  Flush_line [0 ] 0
+
+MMR  Load [43 ] 43
+MMR  Ifetch [0 ] 0
+MMR  Store [27 ] 27
+MMR  L1_to_L2 [0 ] 0
+MMR  Flush_line [0 ] 0
+
 IM  Load [0 ] 0
 IM  Ifetch [0 ] 0
 IM  Store [0 ] 0
@@ -468,13 +498,6 @@ IT  Store [0 ] 0
 IT  L2_Replacement [0 ] 0
 IT  L1_to_L2 [0 ] 0
 IT  Complete_L2_to_L1 [0 ] 0
-IT  Other_GETX [0 ] 0
-IT  Other_GETS [0 ] 0
-IT  Merged_GETS [0 ] 0
-IT  Other_GETS_No_Mig [0 ] 0
-IT  NC_DMA_GETS [0 ] 0
-IT  Invalidate [0 ] 0
-IT  Flush_line [0 ] 0
 
 ST  Load [0 ] 0
 ST  Ifetch [0 ] 0
@@ -482,13 +505,6 @@ ST  Store [0 ] 0
 ST  L2_Replacement [0 ] 0
 ST  L1_to_L2 [0 ] 0
 ST  Complete_L2_to_L1 [0 ] 0
-ST  Other_GETX [0 ] 0
-ST  Other_GETS [0 ] 0
-ST  Merged_GETS [0 ] 0
-ST  Other_GETS_No_Mig [0 ] 0
-ST  NC_DMA_GETS [0 ] 0
-ST  Invalidate [0 ] 0
-ST  Flush_line [0 ] 0
 
 OT  Load [0 ] 0
 OT  Ifetch [0 ] 0
@@ -496,13 +512,6 @@ OT  Store [0 ] 0
 OT  L2_Replacement [0 ] 0
 OT  L1_to_L2 [0 ] 0
 OT  Complete_L2_to_L1 [0 ] 0
-OT  Other_GETX [0 ] 0
-OT  Other_GETS [0 ] 0
-OT  Merged_GETS [0 ] 0
-OT  Other_GETS_No_Mig [0 ] 0
-OT  NC_DMA_GETS [0 ] 0
-OT  Invalidate [0 ] 0
-OT  Flush_line [0 ] 0
 
 MT  Load [0 ] 0
 MT  Ifetch [0 ] 0
@@ -510,13 +519,6 @@ MT  Store [0 ] 0
 MT  L2_Replacement [0 ] 0
 MT  L1_to_L2 [0 ] 0
 MT  Complete_L2_to_L1 [133 ] 133
-MT  Other_GETX [0 ] 0
-MT  Other_GETS [0 ] 0
-MT  Merged_GETS [0 ] 0
-MT  Other_GETS_No_Mig [0 ] 0
-MT  NC_DMA_GETS [0 ] 0
-MT  Invalidate [0 ] 0
-MT  Flush_line [0 ] 0
 
 MMT  Load [0 ] 0
 MMT  Ifetch [0 ] 0
@@ -524,13 +526,6 @@ MMT  Store [0 ] 0
 MMT  L2_Replacement [0 ] 0
 MMT  L1_to_L2 [0 ] 0
 MMT  Complete_L2_to_L1 [70 ] 70
-MMT  Other_GETX [0 ] 0
-MMT  Other_GETS [0 ] 0
-MMT  Merged_GETS [0 ] 0
-MMT  Other_GETS_No_Mig [0 ] 0
-MMT  NC_DMA_GETS [0 ] 0
-MMT  Invalidate [0 ] 0
-MMT  Flush_line [0 ] 0
 
 MI_F  Load [0 ] 0
 MI_F  Ifetch [0 ] 0
@@ -974,4 +969,5 @@ NO_F_W  Pf_Replacement [0 ] 0
 NO_F_W  DMA_READ [0 ] 0
 NO_F_W  DMA_WRITE [0 ] 0
 NO_F_W  Memory_Data [0 ] 0
-NO_F_W  GETF
\ No newline at end of file
+NO_F_W  GETF [0 ] 0
+
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simerr b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simerr
index eabe42249..e45cd058f 100755
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simerr
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simerr
@@ -1,3 +1,2 @@
 warn: Sockets disabled, not accepting gdb connections
-For more information see: http://www.m5sim.org/warn/d946bea6
 hack: be nice to actually delete the event here
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout
index 496de905d..88e64f8c5 100755
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout
@@ -1,14 +1,12 @@
-M5 Simulator System
+Redirecting stdout to build/ALPHA_SE_MOESI_hammer/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer/simout
+Redirecting stderr to build/ALPHA_SE_MOESI_hammer/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer/simerr
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
 
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Apr 28 2011 15:11:39
-M5 started Apr 28 2011 15:12:18
-M5 executing on SC2B0617
-command line: build/ALPHA_SE_MOESI_hammer/m5.opt -d build/ALPHA_SE_MOESI_hammer/tests/opt/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer -re tests/run.py build/ALPHA_SE_MOESI_hammer/tests/opt/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer
+gem5 compiled Jan 10 2012 12:41:45
+gem5 started Jan 10 2012 12:41:49
+gem5 executing on ribera.cs.wisc.edu
+command line: build/ALPHA_SE_MOESI_hammer/gem5.fast -d build/ALPHA_SE_MOESI_hammer/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer -re tests/run.py build/ALPHA_SE_MOESI_hammer/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt
index d6d7f383d..76c45d699 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt
@@ -1,66 +1,66 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                  38626                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 227180                       # Number of bytes of host memory used
-host_seconds                                     0.17                       # Real time elapsed on the host
-host_tick_rate                                1255686                       # Simulator tick rate (ticks/s)
-sim_freq                                   1000000000                       # Frequency of simulated ticks
-sim_insts                                        6404                       # Number of instructions simulated
 sim_seconds                                  0.000208                       # Number of seconds simulated
 sim_ticks                                      208400                       # Number of ticks simulated
-system.cpu.dtb.data_accesses                     2060                       # DTB accesses
-system.cpu.dtb.data_acv                             0                       # DTB access violations
-system.cpu.dtb.data_hits                         2050                       # DTB hits
-system.cpu.dtb.data_misses                         10                       # DTB misses
-system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.fetch_acv                            0                       # ITB acv
+sim_freq                                   1000000000                       # Frequency of simulated ticks
+host_inst_rate                                   9071                       # Simulator instruction rate (inst/s)
+host_tick_rate                                 295192                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 240380                       # Number of bytes of host memory used
+host_seconds                                     0.71                       # Real time elapsed on the host
+sim_insts                                        6404                       # Number of instructions simulated
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
-system.cpu.dtb.read_accesses                     1192                       # DTB read accesses
-system.cpu.dtb.read_acv                             0                       # DTB read access violations
+system.cpu.dtb.fetch_acv                            0                       # ITB acv
+system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
 system.cpu.dtb.read_hits                         1185                       # DTB read hits
 system.cpu.dtb.read_misses                          7                       # DTB read misses
-system.cpu.dtb.write_accesses                     868                       # DTB write accesses
-system.cpu.dtb.write_acv                            0                       # DTB write access violations
+system.cpu.dtb.read_acv                             0                       # DTB read access violations
+system.cpu.dtb.read_accesses                     1192                       # DTB read accesses
 system.cpu.dtb.write_hits                         865                       # DTB write hits
 system.cpu.dtb.write_misses                         3                       # DTB write misses
-system.cpu.idle_fraction                            0                       # Percentage of idle cycles
-system.cpu.itb.data_accesses                        0                       # DTB accesses
-system.cpu.itb.data_acv                             0                       # DTB access violations
-system.cpu.itb.data_hits                            0                       # DTB hits
-system.cpu.itb.data_misses                          0                       # DTB misses
-system.cpu.itb.fetch_accesses                    6432                       # ITB accesses
-system.cpu.itb.fetch_acv                            0                       # ITB acv
+system.cpu.dtb.write_acv                            0                       # DTB write access violations
+system.cpu.dtb.write_accesses                     868                       # DTB write accesses
+system.cpu.dtb.data_hits                         2050                       # DTB hits
+system.cpu.dtb.data_misses                         10                       # DTB misses
+system.cpu.dtb.data_acv                             0                       # DTB access violations
+system.cpu.dtb.data_accesses                     2060                       # DTB accesses
 system.cpu.itb.fetch_hits                        6415                       # ITB hits
 system.cpu.itb.fetch_misses                        17                       # ITB misses
-system.cpu.itb.read_accesses                        0                       # DTB read accesses
-system.cpu.itb.read_acv                             0                       # DTB read access violations
+system.cpu.itb.fetch_acv                            0                       # ITB acv
+system.cpu.itb.fetch_accesses                    6432                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
-system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.write_acv                            0                       # DTB write access violations
+system.cpu.itb.read_acv                             0                       # DTB read access violations
+system.cpu.itb.read_accesses                        0                       # DTB read accesses
 system.cpu.itb.write_hits                           0                       # DTB write hits
 system.cpu.itb.write_misses                         0                       # DTB write misses
-system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
+system.cpu.itb.write_acv                            0                       # DTB write access violations
+system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.data_hits                            0                       # DTB hits
+system.cpu.itb.data_misses                          0                       # DTB misses
+system.cpu.itb.data_acv                             0                       # DTB access violations
+system.cpu.itb.data_accesses                        0                       # DTB accesses
+system.cpu.workload.num_syscalls                   17                       # Number of system calls
 system.cpu.numCycles                           208400                       # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.num_busy_cycles                     208400                       # Number of busy cycles
-system.cpu.num_conditional_control_insts          750                       # number of instructions that are conditional controls
-system.cpu.num_fp_alu_accesses                     10                       # Number of float alu accesses
-system.cpu.num_fp_insts                            10                       # number of float instructions
-system.cpu.num_fp_register_reads                    8                       # number of times the floating registers were read
-system.cpu.num_fp_register_writes                   2                       # number of times the floating registers were written
-system.cpu.num_func_calls                         251                       # number of times a function call or return occured
-system.cpu.num_idle_cycles                          0                       # Number of idle cycles
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.num_insts                             6404                       # Number of instructions executed
 system.cpu.num_int_alu_accesses                  6331                       # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses                     10                       # Number of float alu accesses
+system.cpu.num_func_calls                         251                       # number of times a function call or return occured
+system.cpu.num_conditional_control_insts          750                       # number of instructions that are conditional controls
 system.cpu.num_int_insts                         6331                       # number of integer instructions
+system.cpu.num_fp_insts                            10                       # number of float instructions
 system.cpu.num_int_register_reads                8304                       # number of times the integer registers were read
 system.cpu.num_int_register_writes               4581                       # number of times the integer registers were written
-system.cpu.num_load_insts                        1192                       # Number of load instructions
+system.cpu.num_fp_register_reads                    8                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes                   2                       # number of times the floating registers were written
 system.cpu.num_mem_refs                          2060                       # number of memory refs
+system.cpu.num_load_insts                        1192                       # Number of load instructions
 system.cpu.num_store_insts                        868                       # Number of store instructions
-system.cpu.workload.num_syscalls                   17                       # Number of system calls
+system.cpu.num_idle_cycles                          0                       # Number of idle cycles
+system.cpu.num_busy_cycles                     208400                       # Number of busy cycles
+system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 
 ---------- End Simulation Statistics   ----------