inorder: update hello world for alpha and mips

3 files changed, 116 insertions, 109 deletions

diff --git a/tests/quick/00.hello/ref/alpha/linux/inorder-timing/config.ini b/tests/quick/00.hello/ref/alpha/linux/inorder-timing/config.ini
index 24854ed7e..474a0cfef 100644
--- a/tests/quick/00.hello/ref/alpha/linux/inorder-timing/config.ini
+++ b/tests/quick/00.hello/ref/alpha/linux/inorder-timing/config.ini
@@ -191,7 +191,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/linux/hello
+executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/quick/00.hello/ref/alpha/linux/inorder-timing/simout b/tests/quick/00.hello/ref/alpha/linux/inorder-timing/simout
index c9e5e8882..25216ac09 100755
--- a/tests/quick/00.hello/ref/alpha/linux/inorder-timing/simout
+++ b/tests/quick/00.hello/ref/alpha/linux/inorder-timing/simout
@@ -5,13 +5,13 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb 24 2010 23:12:40
-M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
-M5 started Feb 25 2010 02:21:00
-M5 executing on SC2B0619
+M5 compiled Mar 23 2010 00:24:02
+M5 revision ba1ff0a71710 7040 default tip
+M5 started Mar 23 2010 00:24:03
+M5 executing on zooks
 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/inorder-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/inorder-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
 Hello world!
-Exiting @ tick 31286000 because target called exit()
+Exiting @ tick 31225500 because target called exit()
diff --git a/tests/quick/00.hello/ref/alpha/linux/inorder-timing/stats.txt b/tests/quick/00.hello/ref/alpha/linux/inorder-timing/stats.txt
index 77487dead..6c58ccafe 100644
--- a/tests/quick/00.hello/ref/alpha/linux/inorder-timing/stats.txt
+++ b/tests/quick/00.hello/ref/alpha/linux/inorder-timing/stats.txt
@@ -1,53 +1,60 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                  37021                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 190468                       # Number of bytes of host memory used
-host_seconds                                     0.17                       # Real time elapsed on the host
-host_tick_rate                              180549624                       # Simulator tick rate (ticks/s)
+host_inst_rate                                  30611                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 153332                       # Number of bytes of host memory used
+host_seconds                                     0.21                       # Real time elapsed on the host
+host_tick_rate                              149038484                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                        6404                       # Number of instructions simulated
 sim_seconds                                  0.000031                       # Number of seconds simulated
-sim_ticks                                    31286000                       # Number of ticks simulated
+sim_ticks                                    31225500                       # Number of ticks simulated
 system.cpu.AGEN-Unit.instReqsProcessed           2050                       # Number of Instructions Requests that completed in this resource.
-system.cpu.Branch-Predictor.instReqsProcessed         6581                       # Number of Instructions Requests that completed in this resource.
-system.cpu.Branch-Predictor.predictedNotTaken          924                       # Number of Branches Predicted As Not Taken (False).
-system.cpu.Branch-Predictor.predictedTaken          143                       # Number of Branches Predicted As Taken (True).
-system.cpu.Decode-Unit.instReqsProcessed         6581                       # Number of Instructions Requests that completed in this resource.
+system.cpu.Branch-Predictor.BTBHits               202                       # Number of BTB hits
+system.cpu.Branch-Predictor.BTBLookups            582                       # Number of BTB lookups
+system.cpu.Branch-Predictor.RASInCorrect          125                       # Number of incorrect RAS predictions.
+system.cpu.Branch-Predictor.condIncorrect          957                       # Number of conditional branches incorrect
+system.cpu.Branch-Predictor.condPredicted          751                       # Number of conditional branches predicted
+system.cpu.Branch-Predictor.instReqsProcessed         6537                       # Number of Instructions Requests that completed in this resource.
+system.cpu.Branch-Predictor.lookups              1066                       # Number of BP lookups
+system.cpu.Branch-Predictor.predictedNotTaken          721                       # Number of Branches Predicted As Not Taken (False).
+system.cpu.Branch-Predictor.predictedTaken          345                       # Number of Branches Predicted As Taken (True).
+system.cpu.Branch-Predictor.usedRAS               125                       # Number of times the RAS was used to get a target.
+system.cpu.Decode-Unit.instReqsProcessed         6537                       # Number of Instructions Requests that completed in this resource.
 system.cpu.Execution-Unit.cyclesExecuted         4340                       # Number of Cycles Execution Unit was used.
 system.cpu.Execution-Unit.instReqsProcessed         4354                       # Number of Instructions Requests that completed in this resource.
-system.cpu.Execution-Unit.predictedNotTakenIncorrect          608                       # Number of Branches Incorrectly Predicted As Not Taken).
-system.cpu.Execution-Unit.predictedTakenIncorrect          123                       # Number of Branches Incorrectly Predicted As Taken.
-system.cpu.Execution-Unit.utilization        0.069359                       # Utilization of Execution Unit (cycles / totalCycles).
-system.cpu.Fetch-Seq-Unit.instReqsProcessed        13858                       # Number of Instructions Requests that completed in this resource.
+system.cpu.Execution-Unit.predictedNotTakenIncorrect          447                       # Number of Branches Incorrectly Predicted As Not Taken).
+system.cpu.Execution-Unit.predictedTakenIncorrect          165                       # Number of Branches Incorrectly Predicted As Taken.
+system.cpu.Execution-Unit.utilization        0.069493                       # Utilization of Execution Unit (cycles / totalCycles).
+system.cpu.Fetch-Seq-Unit.instReqsProcessed        13895                       # Number of Instructions Requests that completed in this resource.
 system.cpu.Graduation-Unit.instReqsProcessed         6404                       # Number of Instructions Requests that completed in this resource.
 system.cpu.Mult-Div-Unit.divInstReqsProcessed            0                       # Number of Divide Requests Processed.
 system.cpu.Mult-Div-Unit.instReqsProcessed            2                       # Number of Instructions Requests that completed in this resource.
 system.cpu.Mult-Div-Unit.multInstReqsProcessed            1                       # Number of Multiply Requests Processed.
-system.cpu.RegFile-Manager.instReqsProcessed        19961                       # Number of Instructions Requests that completed in this resource.
-system.cpu.activity                         22.407428                       # Percentage of cycles cpu is active
+system.cpu.RegFile-Manager.instReqsProcessed        19960                       # Number of Instructions Requests that completed in this resource.
+system.cpu.activity                         22.223468                       # Percentage of cycles cpu is active
 system.cpu.committedInsts                        6404                       # Number of Instructions Simulated (Per-Thread)
 system.cpu.committedInsts_total                  6404                       # Number of Instructions Simulated (Total)
 system.cpu.contextSwitches                          1                       # Number of context switches
-system.cpu.cpi                               9.770924                       # CPI: Cycles Per Instruction (Per-Thread)
-system.cpu.cpi_total                         9.770924                       # CPI: Total CPI of All Threads
+system.cpu.cpi                               9.752030                       # CPI: Cycles Per Instruction (Per-Thread)
+system.cpu.cpi_total                         9.752030                       # CPI: Total CPI of All Threads
 system.cpu.dcache.ReadReq_accesses               1185                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 56347.368421                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53347.368421                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency 56342.105263                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53342.105263                       # average ReadReq mshr miss latency
 system.cpu.dcache.ReadReq_hits                   1090                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency        5353000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency        5352500                       # number of ReadReq miss cycles
 system.cpu.dcache.ReadReq_miss_rate          0.080169                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_misses                   95                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency      5068000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency      5067500                       # number of ReadReq MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate     0.080169                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_misses              95                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_accesses               865                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 56074.712644                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53074.712644                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 56063.218391                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53063.218391                       # average WriteReq mshr miss latency
 system.cpu.dcache.WriteReq_hits                   778                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency       4878500                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency       4877500                       # number of WriteReq miss cycles
 system.cpu.dcache.WriteReq_miss_rate         0.100578                       # miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_misses                  87                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency      4617500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency      4616500                       # number of WriteReq MSHR miss cycles
 system.cpu.dcache.WriteReq_mshr_miss_rate     0.100578                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_misses             87                       # number of WriteReq MSHR misses
 system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
@@ -59,31 +66,31 @@ system.cpu.dcache.blocked_cycles::no_mshrs            0                       #
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.demand_accesses                2050                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 56217.032967                       # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 53217.032967                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_miss_latency 56208.791209                       # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 53208.791209                       # average overall mshr miss latency
 system.cpu.dcache.demand_hits                    1868                       # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency        10231500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency        10230000                       # number of demand (read+write) miss cycles
 system.cpu.dcache.demand_miss_rate           0.088780                       # miss rate for demand accesses
 system.cpu.dcache.demand_misses                   182                       # number of demand (read+write) misses
 system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency      9685500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency      9684000                       # number of demand (read+write) MSHR miss cycles
 system.cpu.dcache.demand_mshr_miss_rate      0.088780                       # mshr miss rate for demand accesses
 system.cpu.dcache.demand_mshr_misses              182                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0                   0.025315                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_blocks::0            103.689640                       # Average occupied blocks per context
+system.cpu.dcache.occ_%::0                   0.025299                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0            103.624059                       # Average occupied blocks per context
 system.cpu.dcache.overall_accesses               2050                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 56217.032967                       # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 53217.032967                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_miss_latency 56208.791209                       # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 53208.791209                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
 system.cpu.dcache.overall_hits                   1868                       # number of overall hits
-system.cpu.dcache.overall_miss_latency       10231500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency       10230000                       # number of overall miss cycles
 system.cpu.dcache.overall_miss_rate          0.088780                       # miss rate for overall accesses
 system.cpu.dcache.overall_misses                  182                       # number of overall misses
 system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency      9685500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency      9684000                       # number of overall MSHR miss cycles
 system.cpu.dcache.overall_mshr_miss_rate     0.088780                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_misses             182                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
@@ -91,7 +98,7 @@ system.cpu.dcache.overall_mshr_uncacheable_misses            0
 system.cpu.dcache.replacements                      0                       # number of replacements
 system.cpu.dcache.sampled_refs                    168                       # Sample count of references to valid blocks.
 system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse                103.689640                       # Cycle average of tags in use
+system.cpu.dcache.tagsinuse                103.624059                       # Cycle average of tags in use
 system.cpu.dcache.total_refs                     1882                       # Total number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.dcache.writebacks                        0                       # number of writebacks
@@ -112,73 +119,73 @@ system.cpu.dtb.write_accesses                     868                       # DT
 system.cpu.dtb.write_acv                            0                       # DTB write access violations
 system.cpu.dtb.write_hits                         865                       # DTB write hits
 system.cpu.dtb.write_misses                         3                       # DTB write misses
-system.cpu.icache.ReadReq_accesses               7277                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 55521.594684                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 52863.157895                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits                   6976                       # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency       16712000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate          0.041363                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_accesses               7358                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 55544.850498                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 52868.421053                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits                   7057                       # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency       16719000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate          0.040908                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_misses                  301                       # number of ReadReq misses
 system.cpu.icache.ReadReq_mshr_hits                16                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_miss_latency     15066000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate     0.039164                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_latency     15067500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate     0.038733                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_misses             285                       # number of ReadReq MSHR misses
 system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.avg_refs                  24.563380                       # Average number of references to valid blocks.
+system.cpu.icache.avg_refs                  24.848592                       # Average number of references to valid blocks.
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.demand_accesses                7277                       # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 55521.594684                       # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 52863.157895                       # average overall mshr miss latency
-system.cpu.icache.demand_hits                    6976                       # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency        16712000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate           0.041363                       # miss rate for demand accesses
+system.cpu.icache.demand_accesses                7358                       # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 55544.850498                       # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 52868.421053                       # average overall mshr miss latency
+system.cpu.icache.demand_hits                    7057                       # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency        16719000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate           0.040908                       # miss rate for demand accesses
 system.cpu.icache.demand_misses                   301                       # number of demand (read+write) misses
 system.cpu.icache.demand_mshr_hits                 16                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency     15066000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate      0.039164                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_latency     15067500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate      0.038733                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_misses              285                       # number of demand (read+write) MSHR misses
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0                   0.063659                       # Average percentage of cache occupancy
-system.cpu.icache.occ_blocks::0            130.373495                       # Average occupied blocks per context
-system.cpu.icache.overall_accesses               7277                       # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 55521.594684                       # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 52863.157895                       # average overall mshr miss latency
+system.cpu.icache.occ_%::0                   0.063597                       # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0            130.247335                       # Average occupied blocks per context
+system.cpu.icache.overall_accesses               7358                       # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 55544.850498                       # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 52868.421053                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits                   6976                       # number of overall hits
-system.cpu.icache.overall_miss_latency       16712000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_rate          0.041363                       # miss rate for overall accesses
+system.cpu.icache.overall_hits                   7057                       # number of overall hits
+system.cpu.icache.overall_miss_latency       16719000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_rate          0.040908                       # miss rate for overall accesses
 system.cpu.icache.overall_misses                  301                       # number of overall misses
 system.cpu.icache.overall_mshr_hits                16                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency     15066000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate     0.039164                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_latency     15067500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate     0.038733                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_misses             285                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
 system.cpu.icache.replacements                      0                       # number of replacements
 system.cpu.icache.sampled_refs                    284                       # Sample count of references to valid blocks.
 system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse                130.373495                       # Cycle average of tags in use
-system.cpu.icache.total_refs                     6976                       # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse                130.247335                       # Cycle average of tags in use
+system.cpu.icache.total_refs                     7057                       # Total number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.writebacks                        0                       # number of writebacks
-system.cpu.icache_port.instReqsProcessed         7275                       # Number of Instructions Requests that completed in this resource.
-system.cpu.idleCycles                           48552                       # Number of cycles cpu's stages were not processed
-system.cpu.ipc                               0.102344                       # IPC: Instructions Per Cycle (Per-Thread)
-system.cpu.ipc_total                         0.102344                       # IPC: Total IPC of All Threads
+system.cpu.icache_port.instReqsProcessed         7356                       # Number of Instructions Requests that completed in this resource.
+system.cpu.idleCycles                           48573                       # Number of cycles cpu's stages were not processed
+system.cpu.ipc                               0.102543                       # IPC: Instructions Per Cycle (Per-Thread)
+system.cpu.ipc_total                         0.102543                       # IPC: Total IPC of All Threads
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_hits                            0                       # DTB hits
 system.cpu.itb.data_misses                          0                       # DTB misses
-system.cpu.itb.fetch_accesses                    7294                       # ITB accesses
+system.cpu.itb.fetch_accesses                    7375                       # ITB accesses
 system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_hits                        7277                       # ITB hits
+system.cpu.itb.fetch_hits                        7358                       # ITB hits
 system.cpu.itb.fetch_misses                        17                       # ITB misses
 system.cpu.itb.read_accesses                        0                       # DTB read accesses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -189,22 +196,22 @@ system.cpu.itb.write_acv                            0                       # DT
 system.cpu.itb.write_hits                           0                       # DTB write hits
 system.cpu.itb.write_misses                         0                       # DTB write misses
 system.cpu.l2cache.ReadExReq_accesses              73                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency 52075.342466                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency 52061.643836                       # average ReadExReq miss latency
 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40013.698630                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_miss_latency      3801500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency      3800500                       # number of ReadExReq miss cycles
 system.cpu.l2cache.ReadExReq_miss_rate              1                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_misses                73                       # number of ReadExReq misses
 system.cpu.l2cache.ReadExReq_mshr_miss_latency      2921000                       # number of ReadExReq MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_rate            1                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_misses           73                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadReq_accesses               380                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 52068.601583                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 39945.910290                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency 52069.920844                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 39944.591029                       # average ReadReq mshr miss latency
 system.cpu.l2cache.ReadReq_hits                     1                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency      19734000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency      19734500                       # number of ReadReq miss cycles
 system.cpu.l2cache.ReadReq_miss_rate         0.997368                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_misses                 379                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency     15139500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency     15139000                       # number of ReadReq MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_miss_rate     0.997368                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_misses            379                       # number of ReadReq MSHR misses
 system.cpu.l2cache.UpgradeReq_accesses             14                       # number of UpgradeReq accesses(hits+misses)
@@ -225,31 +232,31 @@ system.cpu.l2cache.blocked_cycles::no_mshrs            0                       #
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.demand_accesses                453                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 52069.690265                       # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 39956.858407                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_miss_latency 52068.584071                       # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 39955.752212                       # average overall mshr miss latency
 system.cpu.l2cache.demand_hits                      1                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency       23535500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency       23535000                       # number of demand (read+write) miss cycles
 system.cpu.l2cache.demand_miss_rate          0.997792                       # miss rate for demand accesses
 system.cpu.l2cache.demand_misses                  452                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency     18060500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency     18060000                       # number of demand (read+write) MSHR miss cycles
 system.cpu.l2cache.demand_mshr_miss_rate     0.997792                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_misses             452                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0                  0.005540                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_blocks::0           181.532273                       # Average occupied blocks per context
+system.cpu.l2cache.occ_%::0                  0.005535                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0           181.381905                       # Average occupied blocks per context
 system.cpu.l2cache.overall_accesses               453                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 52069.690265                       # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 39956.858407                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_miss_latency 52068.584071                       # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 39955.752212                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
 system.cpu.l2cache.overall_hits                     1                       # number of overall hits
-system.cpu.l2cache.overall_miss_latency      23535500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency      23535000                       # number of overall miss cycles
 system.cpu.l2cache.overall_miss_rate         0.997792                       # miss rate for overall accesses
 system.cpu.l2cache.overall_misses                 452                       # number of overall misses
 system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency     18060500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency     18060000                       # number of overall MSHR miss cycles
 system.cpu.l2cache.overall_mshr_miss_rate     0.997792                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_misses            452                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
@@ -257,32 +264,32 @@ system.cpu.l2cache.overall_mshr_uncacheable_misses            0
 system.cpu.l2cache.replacements                     0                       # number of replacements
 system.cpu.l2cache.sampled_refs                   364                       # Sample count of references to valid blocks.
 system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse               181.532273                       # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse               181.381905                       # Cycle average of tags in use
 system.cpu.l2cache.total_refs                       1                       # Total number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
 system.cpu.l2cache.writebacks                       0                       # number of writebacks
-system.cpu.numCycles                            62573                       # number of cpu cycles simulated
-system.cpu.runCycles                            14021                       # Number of cycles cpu stages are processed.
+system.cpu.numCycles                            62452                       # number of cpu cycles simulated
+system.cpu.runCycles                            13879                       # Number of cycles cpu stages are processed.
 system.cpu.smtCommittedInsts                        0                       # Number of SMT Instructions Simulated (Per-Thread)
 system.cpu.smtCycles                                0                       # Total number of cycles that the CPU was in SMT-mode
 system.cpu.smt_cpi                           no_value                       # CPI: Total SMT-CPI
 system.cpu.smt_ipc                           no_value                       # IPC: Total SMT-IPC
-system.cpu.stage-0.idleCycles                   55279                       # Number of cycles 0 instructions are processed.
-system.cpu.stage-0.runCycles                     7294                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage-0.utilization              11.656785                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage-1.idleCycles                   55992                       # Number of cycles 0 instructions are processed.
-system.cpu.stage-1.runCycles                     6581                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage-1.utilization              10.517316                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage-2.idleCycles                   56103                       # Number of cycles 0 instructions are processed.
+system.cpu.stage-0.idleCycles                   55077                       # Number of cycles 0 instructions are processed.
+system.cpu.stage-0.runCycles                     7375                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage-0.utilization              11.809069                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage-1.idleCycles                   55915                       # Number of cycles 0 instructions are processed.
+system.cpu.stage-1.runCycles                     6537                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage-1.utilization              10.467239                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage-2.idleCycles                   55982                       # Number of cycles 0 instructions are processed.
 system.cpu.stage-2.runCycles                     6470                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage-2.utilization              10.339923                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage-3.idleCycles                   60520                       # Number of cycles 0 instructions are processed.
+system.cpu.stage-2.utilization              10.359956                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage-3.idleCycles                   60399                       # Number of cycles 0 instructions are processed.
 system.cpu.stage-3.runCycles                     2053                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage-3.utilization               3.280968                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage-4.idleCycles                   56169                       # Number of cycles 0 instructions are processed.
+system.cpu.stage-3.utilization               3.287325                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage-4.idleCycles                   56048                       # Number of cycles 0 instructions are processed.
 system.cpu.stage-4.runCycles                     6404                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage-4.utilization              10.234446                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.threadCycles                         62573                       # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
+system.cpu.stage-4.utilization              10.254275                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.threadCycles                         62452                       # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
 system.cpu.workload.PROG:num_syscalls              17                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------