diff options
| author | Gabe Black <gblack@eecs.umich.edu> | 2007-04-23 15:34:40 +0000 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2007-04-23 15:34:40 +0000 |
| commit | cca881a5316d686f0be6b437e756a9faba43aa02 (patch) | |
| tree | 1c46278b51c66879e228b696dee64787fc487704 /tests/quick/00.hello/ref/alpha/linux | |
| parent | f0929006965514982603fe58ebc3211acf021cce (diff) | |
| parent | a006aa067a197f5ce2cd3f22ffe30ae3d9103cbf (diff) | |
| download | gem5-cca881a5316d686f0be6b437e756a9faba43aa02.tar.xz | |
Merge zizzer.eecs.umich.edu:/n/wexford/x/gblack/m5/newmem-o3-spec
into ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem-o3-micro
--HG--
extra : convert_revision : 757e1d79033e6f8e0aaaf5ecaf14077d416cff8e
Diffstat (limited to 'tests/quick/00.hello/ref/alpha/linux')
15 files changed, 336 insertions, 539 deletions
diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini b/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini index 4d44e14fe..2a139492e 100644 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini @@ -23,7 +23,7 @@ activity=0 backComSize=5 choiceCtrBits=2 choicePredictorSize=8192 -clock=1 +clock=500 commitToDecodeDelay=1 commitToFetchDelay=1 commitToIEWDelay=1 diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.out b/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.out index 686c3b2f6..8155faf63 100644 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.out +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.out @@ -167,7 +167,7 @@ FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUL [system.cpu] type=DerivO3CPU -clock=1 +clock=500 phase=0 numThreads=1 cpu_id=0 diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt index 988584966..86aa4129f 100644 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt @@ -1,40 +1,40 @@ ---------- Begin Simulation Statistics ---------- global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 615 # Number of BTB hits -global.BPredUnit.BTBLookups 1663 # Number of BTB lookups -global.BPredUnit.RASInCorrect 78 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 439 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 1180 # Number of conditional branches predicted -global.BPredUnit.lookups 2032 # Number of BP lookups -global.BPredUnit.usedRAS 304 # Number of times the RAS was used to get a target. -host_inst_rate 15105 # Simulator instruction rate (inst/s) -host_mem_usage 154056 # Number of bytes of host memory used -host_seconds 0.37 # Real time elapsed on the host -host_tick_rate 3572881 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 24 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 13 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 2144 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 1221 # Number of stores inserted to the mem dependence unit. +global.BPredUnit.BTBHits 606 # Number of BTB hits +global.BPredUnit.BTBLookups 1858 # Number of BTB lookups +global.BPredUnit.RASInCorrect 54 # Number of incorrect RAS predictions. +global.BPredUnit.condIncorrect 415 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 1270 # Number of conditional branches predicted +global.BPredUnit.lookups 2195 # Number of BP lookups +global.BPredUnit.usedRAS 306 # Number of times the RAS was used to get a target. +host_inst_rate 22780 # Simulator instruction rate (inst/s) +host_mem_usage 154084 # Number of bytes of host memory used +host_seconds 0.25 # Real time elapsed on the host +host_tick_rate 14337041 # Simulator tick rate (ticks/s) +memdepunit.memDep.conflictingLoads 31 # Number of conflicting loads. +memdepunit.memDep.conflictingStores 138 # Number of conflicting stores. +memdepunit.memDep.insertedLoads 2061 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 1230 # Number of stores inserted to the mem dependence unit. sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5623 # Number of instructions simulated -sim_seconds 0.000001 # Number of seconds simulated -sim_ticks 1331134 # Number of ticks simulated +sim_seconds 0.000004 # Number of seconds simulated +sim_ticks 3543500 # Number of ticks simulated system.cpu.commit.COM:branches 862 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 101 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 121 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 30311 +system.cpu.commit.COM:committed_per_cycle.samples 6315 system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 27595 9103.96% - 1 1579 520.93% - 2 482 159.02% - 3 232 76.54% - 4 131 43.22% - 5 104 34.31% - 6 60 19.79% - 7 27 8.91% - 8 101 33.32% + 0 4255 6737.93% + 1 915 1448.93% + 2 408 646.08% + 3 162 256.53% + 4 140 221.69% + 5 91 144.10% + 6 121 191.61% + 7 102 161.52% + 8 121 191.61% system.cpu.commit.COM:committed_per_cycle.max_value 8 system.cpu.commit.COM:committed_per_cycle.end_dist @@ -43,69 +43,69 @@ system.cpu.commit.COM:loads 979 # Nu system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 1791 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 370 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 341 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 5640 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 4834 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 4458 # The number of squashed insts skipped by commit system.cpu.committedInsts 5623 # Number of Instructions Simulated system.cpu.committedInsts_total 5623 # Number of Instructions Simulated -system.cpu.cpi 236.730215 # CPI: Cycles Per Instruction -system.cpu.cpi_total 236.730215 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 1606 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 7256.076023 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7095.200000 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 1435 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 1240789 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.106476 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 171 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 71 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 709520 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.062267 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 100 # number of ReadReq MSHR misses +system.cpu.cpi 1.260537 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.260537 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 1516 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 4941.176471 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 4361.386139 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 1380 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 672000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.089710 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 136 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 35 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 440500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.066623 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 101 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 812 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 8026.070225 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 7200.452055 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 456 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 2857281 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.438424 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 356 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 283 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 525633 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.089901 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 73 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_avg_miss_latency 3265.671642 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 3819.444444 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 477 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 1094000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.412562 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 335 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 263 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 275000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.088670 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 72 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 10.930636 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 10.734104 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 2418 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 7776.223909 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 7139.612717 # average overall mshr miss latency -system.cpu.dcache.demand_hits 1891 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 4098070 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.217949 # miss rate for demand accesses -system.cpu.dcache.demand_misses 527 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 354 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 1235153 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.071547 # mshr miss rate for demand accesses +system.cpu.dcache.demand_accesses 2328 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 3749.469214 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 4135.838150 # average overall mshr miss latency +system.cpu.dcache.demand_hits 1857 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 1766000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.202320 # miss rate for demand accesses +system.cpu.dcache.demand_misses 471 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 298 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 715500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.074313 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 173 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 2418 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 7776.223909 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 7139.612717 # average overall mshr miss latency +system.cpu.dcache.overall_accesses 2328 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 3749.469214 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 4135.838150 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 1891 # number of overall hits -system.cpu.dcache.overall_miss_latency 4098070 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.217949 # miss rate for overall accesses -system.cpu.dcache.overall_misses 527 # number of overall misses -system.cpu.dcache.overall_mshr_hits 354 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 1235153 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.071547 # mshr miss rate for overall accesses +system.cpu.dcache.overall_hits 1857 # number of overall hits +system.cpu.dcache.overall_miss_latency 1766000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.202320 # miss rate for overall accesses +system.cpu.dcache.overall_misses 471 # number of overall misses +system.cpu.dcache.overall_mshr_hits 298 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 715500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.074313 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 173 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses @@ -121,89 +121,89 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 173 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 102.478227 # Cycle average of tags in use -system.cpu.dcache.total_refs 1891 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 111.557376 # Cycle average of tags in use +system.cpu.dcache.total_refs 1857 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 17469 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 70 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 169 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 11765 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 10684 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 2098 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 907 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 200 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 61 # Number of cycles decode is unblocking -system.cpu.fetch.Branches 2032 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 1710 # Number of cache lines fetched -system.cpu.fetch.Cycles 3962 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 268 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 12603 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 472 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.065089 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 1710 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 919 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 0.403696 # Number of inst fetches per cycle +system.cpu.decode.DECODE:BlockedCycles 381 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 81 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 172 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 12164 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 3741 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 2151 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 772 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 244 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 43 # Number of cycles decode is unblocking +system.cpu.fetch.Branches 2195 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 1616 # Number of cache lines fetched +system.cpu.fetch.Cycles 3951 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 151 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 13452 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 448 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.309678 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 1616 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 912 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.897856 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 31219 +system.cpu.fetch.rateDist.samples 7088 system.cpu.fetch.rateDist.min_value 0 - 0 28979 9282.49% - 1 197 63.10% - 2 198 63.42% - 3 167 53.49% - 4 197 63.10% - 5 187 59.90% - 6 222 71.11% - 7 122 39.08% - 8 950 304.30% + 0 4755 6708.52% + 1 197 277.93% + 2 177 249.72% + 3 163 229.97% + 4 234 330.14% + 5 170 239.84% + 6 198 279.35% + 7 114 160.84% + 8 1080 1523.70% system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.end_dist -system.cpu.icache.ReadReq_accesses 1710 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 5139.251163 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 4349.151613 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 1280 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 2209878 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.251462 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 430 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 120 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 1348237 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.181287 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 310 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_accesses 1616 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 4068.597561 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 3148.089172 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 1288 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 1334500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.202970 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 328 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 14 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 988500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.194307 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 314 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_refs 4.129032 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 4.101911 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 1710 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 5139.251163 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 4349.151613 # average overall mshr miss latency -system.cpu.icache.demand_hits 1280 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 2209878 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.251462 # miss rate for demand accesses -system.cpu.icache.demand_misses 430 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 120 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 1348237 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.181287 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 310 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_accesses 1616 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 4068.597561 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 3148.089172 # average overall mshr miss latency +system.cpu.icache.demand_hits 1288 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 1334500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.202970 # miss rate for demand accesses +system.cpu.icache.demand_misses 328 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 14 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 988500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.194307 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 314 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 1710 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 5139.251163 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 4349.151613 # average overall mshr miss latency +system.cpu.icache.overall_accesses 1616 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 4068.597561 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 3148.089172 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 1280 # number of overall hits -system.cpu.icache.overall_miss_latency 2209878 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.251462 # miss rate for overall accesses -system.cpu.icache.overall_misses 430 # number of overall misses -system.cpu.icache.overall_mshr_hits 120 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 1348237 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.181287 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 310 # number of overall MSHR misses +system.cpu.icache.overall_hits 1288 # number of overall hits +system.cpu.icache.overall_miss_latency 1334500 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.202970 # miss rate for overall accesses +system.cpu.icache.overall_misses 328 # number of overall misses +system.cpu.icache.overall_mshr_hits 14 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 988500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.194307 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 314 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -216,61 +216,60 @@ system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.sampled_refs 310 # Sample count of references to valid blocks. +system.cpu.icache.sampled_refs 314 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 148.421347 # Cycle average of tags in use -system.cpu.icache.total_refs 1280 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 166.037293 # Cycle average of tags in use +system.cpu.icache.total_refs 1288 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 1299916 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 1267 # Number of branches executed -system.cpu.iew.EXEC:nop 48 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.270476 # Inst execution rate -system.cpu.iew.EXEC:refs 2748 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 1031 # Number of stores executed +system.cpu.iew.EXEC:branches 1203 # Number of branches executed +system.cpu.iew.EXEC:nop 41 # number of nop insts executed +system.cpu.iew.EXEC:rate 1.125423 # Inst execution rate +system.cpu.iew.EXEC:refs 2585 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 989 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 5354 # num instructions consuming a value -system.cpu.iew.WB:count 8160 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.757378 # average fanout of values written-back +system.cpu.iew.WB:consumers 5598 # num instructions consuming a value +system.cpu.iew.WB:count 7767 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.741872 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 4055 # num instructions producing a value -system.cpu.iew.WB:rate 0.261379 # insts written-back per cycle -system.cpu.iew.WB:sent 8228 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 404 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 7230 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 2144 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 24 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 179 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 1221 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 10469 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 1717 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 299 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 8444 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 10 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 4153 # num instructions producing a value +system.cpu.iew.WB:rate 1.095796 # insts written-back per cycle +system.cpu.iew.WB:sent 7849 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 393 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 3 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 2061 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 23 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 240 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 1230 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 10115 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 1596 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 554 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 7977 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 1 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 907 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 39 # Number of cycles IEW is unblocking +system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 772 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 81 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.forwLoads 57 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 60 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.memOrderViolation 68 # Number of memory ordering violations system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 1165 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 409 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 60 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 279 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 125 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 0.004224 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.004224 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 8743 # Type of FU issued +system.cpu.iew.lsq.thread.0.squashedLoads 1082 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 418 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 68 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 284 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 109 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 0.793313 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.793313 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 8531 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist (null) 2 0.02% # Type of FU issued - IntAlu 5868 67.12% # Type of FU issued + IntAlu 5713 66.97% # Type of FU issued IntMult 1 0.01% # Type of FU issued IntDiv 0 0.00% # Type of FU issued FloatAdd 2 0.02% # Type of FU issued @@ -279,16 +278,16 @@ system.cpu.iq.ISSUE:FU_type_0.start_dist FloatMult 0 0.00% # Type of FU issued FloatDiv 0 0.00% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 1809 20.69% # Type of FU issued - MemWrite 1061 12.14% # Type of FU issued + MemRead 1773 20.78% # Type of FU issued + MemWrite 1040 12.19% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 87 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.009951 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_cnt 128 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.015004 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full.start_dist (null) 0 0.00% # attempts to use FU when none available - IntAlu 1 1.15% # attempts to use FU when none available + IntAlu 7 5.47% # attempts to use FU when none available IntMult 0 0.00% # attempts to use FU when none available IntDiv 0 0.00% # attempts to use FU when none available FloatAdd 0 0.00% # attempts to use FU when none available @@ -297,43 +296,43 @@ system.cpu.iq.ISSUE:fu_full.start_dist FloatMult 0 0.00% # attempts to use FU when none available FloatDiv 0 0.00% # attempts to use FU when none available FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 54 62.07% # attempts to use FU when none available - MemWrite 32 36.78% # attempts to use FU when none available + MemRead 78 60.94% # attempts to use FU when none available + MemWrite 43 33.59% # attempts to use FU when none available IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 31219 +system.cpu.iq.ISSUE:issued_per_cycle.samples 7088 system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 27042 8662.03% - 1 1845 590.99% - 2 1151 368.69% - 3 572 183.22% - 4 318 101.86% - 5 182 58.30% - 6 76 24.34% - 7 22 7.05% - 8 11 3.52% + 0 4068 5739.28% + 1 771 1087.75% + 2 763 1076.47% + 3 485 684.26% + 4 504 711.06% + 5 295 416.20% + 6 144 203.16% + 7 40 56.43% + 8 18 25.40% system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.end_dist -system.cpu.iq.ISSUE:rate 0.280054 # Inst issue rate -system.cpu.iq.iqInstsAdded 10397 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 8743 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 24 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 4378 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 68 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 7 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 2580 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.l2cache.ReadReq_accesses 481 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 4807.594595 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2390.114345 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_miss_latency 2312453 # number of ReadReq miss cycles +system.cpu.iq.ISSUE:rate 1.203584 # Inst issue rate +system.cpu.iq.iqInstsAdded 10051 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 8531 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 23 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 4086 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 39 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 6 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 2494 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.l2cache.ReadReq_accesses 485 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 3318.556701 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1934.377320 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_miss_latency 1609500 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 481 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1149645 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_misses 485 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 938173 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 481 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses 485 # number of ReadReq MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks. @@ -342,32 +341,32 @@ system.cpu.l2cache.blocked_no_targets 0 # nu system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 481 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 4807.594595 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 2390.114345 # average overall mshr miss latency +system.cpu.l2cache.demand_accesses 485 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 3318.556701 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 1934.377320 # average overall mshr miss latency system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 2312453 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 1609500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 481 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses 485 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 1149645 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 938173 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 481 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses 485 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 481 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 4807.594595 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 2390.114345 # average overall mshr miss latency +system.cpu.l2cache.overall_accesses 485 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 3318.556701 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 1934.377320 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 0 # number of overall hits -system.cpu.l2cache.overall_miss_latency 2312453 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 1609500 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 481 # number of overall misses +system.cpu.l2cache.overall_misses 485 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 1149645 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 938173 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 481 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses 485 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -380,31 +379,28 @@ system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 481 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 485 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 250.999286 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 277.255174 # Cycle average of tags in use system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.numCycles 31219 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 7810 # Number of cycles rename is blocking +system.cpu.numCycles 7088 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 3 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 4051 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 2 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 10837 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 465 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:ROBFullEvents 6 # Number of times rename has blocked due to ROB full -system.cpu.rename.RENAME:RenameLookups 14384 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 11306 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 8499 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 2010 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 907 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 491 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 4448 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 9164 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:IdleCycles 3933 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 65 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:RenameLookups 14798 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 11577 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 8671 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 2005 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 772 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 115 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 4620 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 260 # count of cycles rename stalled for serializing inst system.cpu.rename.RENAME:serializingInsts 27 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 825 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 21 # count of temporary serializing insts renamed -system.cpu.timesIdled 365 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.rename.RENAME:skidInsts 396 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 22 # count of temporary serializing insts renamed system.cpu.workload.PROG:num_syscalls 17 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stderr b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stderr index 8053728f7..f33d007a7 100644 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stderr +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stderr @@ -1,3 +1,2 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7001 warn: Entering event queue @ 0. Starting simulation... warn: Increasing stack size by one page. diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout index ef47b0265..eeba3846f 100644 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout @@ -6,9 +6,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Mar 30 2007 13:12:55 -M5 started Fri Mar 30 13:13:02 2007 +M5 compiled Apr 21 2007 21:50:58 +M5 started Sat Apr 21 21:51:06 2007 M5 executing on zamp.eecs.umich.edu command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing tests/run.py quick/00.hello/alpha/linux/o3-timing Global frequency set at 1000000000000 ticks per second -Exiting @ tick 1331134 because target called exit() +Exiting @ tick 3543500 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini index 79673d775..26009ca4f 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini +++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini @@ -1,51 +1,7 @@ [root] type=Root children=system -checkpoint= -clock=1000000000000 -max_tick=0 -output_file=cout -progress_interval=0 - -[debug] -break_cycles= - -[exetrace] -intel_format=false -legion_lockstep=false -pc_symbol=true -print_cpseq=false -print_cycle=true -print_data=true -print_effaddr=true -print_fetchseq=false -print_iregs=false -print_opclass=true -print_thread=true -speculative=true -trace_system=client - -[serialize] -count=10 -cycle=0 -dir=cpt.%012d -period=0 - -[stats] -descriptions=true -dump_cycle=0 -dump_period=0 -dump_reset=false -ignore_events= -mysql_db= -mysql_host= -mysql_password= -mysql_user= -project_name=test -simulation_name=test -simulation_sample=0 -text_compat=true -text_file=m5stats.txt +dummy=0 [system] type=System @@ -56,7 +12,7 @@ physmem=system.physmem [system.cpu] type=AtomicSimpleCPU children=workload -clock=1 +clock=500 cpu_id=0 defer_registration=false function_trace=false @@ -65,6 +21,7 @@ max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 +phase=0 progress_interval=0 simulate_stalls=false system=system @@ -76,6 +33,7 @@ icache_port=system.membus.port[1] [system.cpu.workload] type=LiveProcess cmd=hello +cwd= egid=100 env= euid=100 @@ -101,14 +59,6 @@ type=PhysicalMemory file= latency=1 range=0:134217727 +zero=false port=system.membus.port[0] -[trace] -bufsize=0 -cycle=0 -dump_on_exit=false -file=cout -flags= -ignore= -start=0 - diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.out b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.out index 31870d5f3..f8e40871a 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.out +++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.out @@ -1,15 +1,13 @@ [root] type=Root -clock=1000000000000 -max_tick=0 -progress_interval=0 -output_file=cout +dummy=0 [system.physmem] type=PhysicalMemory file= range=[0,134217727] latency=1 +zero=false [system] type=System @@ -30,6 +28,7 @@ executable=tests/test-progs/hello/bin/alpha/linux/hello input=cin output=cout env= +cwd= system=system uid=100 euid=100 @@ -48,61 +47,11 @@ progress_interval=0 system=system cpu_id=0 workload=system.cpu.workload -clock=1 +clock=500 +phase=0 defer_registration=false width=1 function_trace=false function_trace_start=0 simulate_stalls=false -[trace] -flags= -start=0 -cycle=0 -bufsize=0 -file=cout -dump_on_exit=false -ignore= - -[stats] -descriptions=true -project_name=test -simulation_name=test -simulation_sample=0 -text_file=m5stats.txt -text_compat=true -mysql_db= -mysql_user= -mysql_password= -mysql_host= -events_start=-1 -dump_reset=false -dump_cycle=0 -dump_period=0 -ignore_events= - -[random] -seed=1 - -[exetrace] -speculative=true -print_cycle=true -print_opclass=true -print_thread=true -print_effaddr=true -print_data=true -print_iregs=false -print_fetchseq=false -print_cpseq=false -print_reg_delta=false -pc_symbol=true -intel_format=false -legion_lockstep=false -trace_system=client - -[debug] -break_cycles= - -[statsreset] -reset_cycle=0 - diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/m5stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/m5stats.txt index 96973fa46..0f64469e9 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/m5stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 684709 # Simulator instruction rate (inst/s) -host_mem_usage 148256 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host -host_tick_rate 650634 # Simulator tick rate (ticks/s) +host_inst_rate 357156 # Simulator instruction rate (inst/s) +host_mem_usage 148180 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host +host_tick_rate 171417285 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5642 # Number of instructions simulated -sim_seconds 0.000000 # Number of seconds simulated -sim_ticks 5641 # Number of ticks simulated +sim_seconds 0.000003 # Number of seconds simulated +sim_ticks 2820500 # Number of ticks simulated system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 5642 # number of cpu cycles simulated diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stderr b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stderr index 87866a2a5..f33d007a7 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stderr +++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stderr @@ -1 +1,2 @@ warn: Entering event queue @ 0. Starting simulation... +warn: Increasing stack size by one page. diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stdout b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stdout index c451577a3..5acc408a3 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stdout +++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stdout @@ -6,8 +6,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 3 2006 17:10:27 -M5 started Fri Nov 3 17:10:43 2006 -M5 executing on zizzer.eecs.umich.edu -command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/simple-atomic tests/run.py quick/00.hello/alpha/linux/simple-atomic -Exiting @ tick 5641 because target called exit() +M5 compiled Apr 21 2007 21:50:58 +M5 started Sat Apr 21 21:51:08 2007 +M5 executing on zamp.eecs.umich.edu +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-atomic tests/run.py quick/00.hello/alpha/linux/simple-atomic +Global frequency set at 1000000000000 ticks per second +Exiting @ tick 2820500 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini index 13004a42a..025531062 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini @@ -1,51 +1,7 @@ [root] type=Root children=system -checkpoint= -clock=1000000000000 -max_tick=0 -output_file=cout -progress_interval=0 - -[debug] -break_cycles= - -[exetrace] -intel_format=false -legion_lockstep=false -pc_symbol=true -print_cpseq=false -print_cycle=true -print_data=true -print_effaddr=true -print_fetchseq=false -print_iregs=false -print_opclass=true -print_thread=true -speculative=true -trace_system=client - -[serialize] -count=10 -cycle=0 -dir=cpt.%012d -period=0 - -[stats] -descriptions=true -dump_cycle=0 -dump_period=0 -dump_reset=false -ignore_events= -mysql_db= -mysql_host= -mysql_password= -mysql_user= -project_name=test -simulation_name=test -simulation_sample=0 -text_compat=true -text_file=m5stats.txt +dummy=0 [system] type=System @@ -56,7 +12,7 @@ physmem=system.physmem [system.cpu] type=TimingSimpleCPU children=dcache icache l2cache toL2Bus workload -clock=1 +clock=500 cpu_id=0 defer_registration=false function_trace=false @@ -65,6 +21,7 @@ max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 +phase=0 progress_interval=0 system=system workload=system.cpu.workload @@ -199,6 +156,7 @@ port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cp [system.cpu.workload] type=LiveProcess cmd=hello +cwd= egid=100 env= euid=100 @@ -224,14 +182,6 @@ type=PhysicalMemory file= latency=1 range=0:134217727 +zero=false port=system.membus.port[0] -[trace] -bufsize=0 -cycle=0 -dump_on_exit=false -file=cout -flags= -ignore= -start=0 - diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.out b/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.out index 58b3f5296..fa1054e9e 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.out +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.out @@ -1,15 +1,13 @@ [root] type=Root -clock=1000000000000 -max_tick=0 -progress_interval=0 -output_file=cout +dummy=0 [system.physmem] type=PhysicalMemory file= range=[0,134217727] latency=1 +zero=false [system] type=System @@ -30,6 +28,7 @@ executable=tests/test-progs/hello/bin/alpha/linux/hello input=cin output=cout env= +cwd= system=system uid=100 euid=100 @@ -48,7 +47,8 @@ progress_interval=0 system=system cpu_id=0 workload=system.cpu.workload -clock=1 +clock=500 +phase=0 defer_registration=false // width not specified function_trace=false @@ -176,54 +176,3 @@ prefetch_use_cpu_id=true prefetch_data_accesses_only=false hit_latency=1 -[trace] -flags= -start=0 -cycle=0 -bufsize=0 -file=cout -dump_on_exit=false -ignore= - -[stats] -descriptions=true -project_name=test -simulation_name=test -simulation_sample=0 -text_file=m5stats.txt -text_compat=true -mysql_db= -mysql_user= -mysql_password= -mysql_host= -events_start=-1 -dump_reset=false -dump_cycle=0 -dump_period=0 -ignore_events= - -[random] -seed=1 - -[exetrace] -speculative=true -print_cycle=true -print_opclass=true -print_thread=true -print_effaddr=true -print_data=true -print_iregs=false -print_fetchseq=false -print_cpseq=false -print_reg_delta=false -pc_symbol=true -intel_format=false -legion_lockstep=false -trace_system=client - -[debug] -break_cycles= - -[statsreset] -reset_cycle=0 - diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt index 68f6bcca4..afdac247d 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt @@ -1,31 +1,31 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 167195 # Simulator instruction rate (inst/s) -host_mem_usage 179768 # Number of bytes of host memory used +host_inst_rate 215467 # Simulator instruction rate (inst/s) +host_mem_usage 153656 # Number of bytes of host memory used host_seconds 0.03 # Real time elapsed on the host -host_tick_rate 51710933 # Simulator tick rate (ticks/s) +host_tick_rate 193088667 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5642 # Number of instructions simulated -sim_seconds 0.000002 # Number of seconds simulated -sim_ticks 1767066 # Number of ticks simulated +sim_seconds 0.000005 # Number of seconds simulated +sim_ticks 5135000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 979 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 3990.760870 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2990.760870 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 3750 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2750 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 887 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 367150 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 345000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.093973 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 92 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 275150 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 253000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.093973 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 92 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 812 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 3977.109589 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2977.109589 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 3582.191781 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2582.191781 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 739 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 290329 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 261500 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.089901 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 73 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 217329 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 188500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.089901 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 73 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -37,29 +37,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 1791 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 3984.721212 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 2984.721212 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency 3675.757576 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 2675.757576 # average overall mshr miss latency system.cpu.dcache.demand_hits 1626 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 657479 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 606500 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.092127 # miss rate for demand accesses system.cpu.dcache.demand_misses 165 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 492479 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 441500 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.092127 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 165 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 1791 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 3984.721212 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 2984.721212 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 3675.757576 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 2675.757576 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 1626 # number of overall hits -system.cpu.dcache.overall_miss_latency 657479 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 606500 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.092127 # miss rate for overall accesses system.cpu.dcache.overall_misses 165 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 492479 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 441500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.092127 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 165 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -76,18 +76,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 165 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 97.858233 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 105.359700 # Cycle average of tags in use system.cpu.dcache.total_refs 1626 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks system.cpu.icache.ReadReq_accesses 5643 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 3980.490975 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 2980.490975 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_miss_latency 3729.241877 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 2729.241877 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 5366 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 1102596 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency 1033000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.049087 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 277 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 825596 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 756000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.049087 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 277 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -99,29 +99,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 5643 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 3980.490975 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 2980.490975 # average overall mshr miss latency +system.cpu.icache.demand_avg_miss_latency 3729.241877 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 2729.241877 # average overall mshr miss latency system.cpu.icache.demand_hits 5366 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 1102596 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 1033000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.049087 # miss rate for demand accesses system.cpu.icache.demand_misses 277 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 825596 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 756000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.049087 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 277 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.overall_accesses 5643 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 3980.490975 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 2980.490975 # average overall mshr miss latency +system.cpu.icache.overall_avg_miss_latency 3729.241877 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 2729.241877 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.icache.overall_hits 5366 # number of overall hits -system.cpu.icache.overall_miss_latency 1102596 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 1033000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.049087 # miss rate for overall accesses system.cpu.icache.overall_misses 277 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 825596 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 756000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.049087 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 277 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -138,18 +138,18 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 0 # number of replacements system.cpu.icache.sampled_refs 277 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 122.802112 # Cycle average of tags in use +system.cpu.icache.tagsinuse 131.245403 # Cycle average of tags in use system.cpu.icache.total_refs 5366 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.l2cache.ReadReq_accesses 441 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 2984.340136 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1983.340136 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_miss_latency 1316094 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_avg_miss_latency 2712.018141 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1711.018141 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_miss_latency 1196000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 441 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 874653 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 754559 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 441 # number of ReadReq MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -161,29 +161,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 # system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 441 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 2984.340136 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 1983.340136 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_miss_latency 2712.018141 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 1711.018141 # average overall mshr miss latency system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 1316094 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 1196000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses system.cpu.l2cache.demand_misses 441 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 874653 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 754559 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 441 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.overall_accesses 441 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 2984.340136 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 1983.340136 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_miss_latency 2712.018141 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 1711.018141 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 0 # number of overall hits -system.cpu.l2cache.overall_miss_latency 1316094 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 1196000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses system.cpu.l2cache.overall_misses 441 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 874653 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 754559 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 441 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -200,12 +200,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.sampled_refs 441 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 220.802916 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 236.577060 # Cycle average of tags in use system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 1767066 # number of cpu cycles simulated +system.cpu.numCycles 5135000 # number of cpu cycles simulated system.cpu.num_insts 5642 # Number of instructions executed system.cpu.num_refs 1792 # Number of memory references system.cpu.workload.PROG:num_syscalls 17 # Number of system calls diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/stderr b/tests/quick/00.hello/ref/alpha/linux/simple-timing/stderr index 87866a2a5..f33d007a7 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/stderr +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/stderr @@ -1 +1,2 @@ warn: Entering event queue @ 0. Starting simulation... +warn: Increasing stack size by one page. diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout b/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout index 61f79d88f..a79e87c66 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout @@ -6,8 +6,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 3 2006 17:10:27 -M5 started Fri Nov 3 17:10:44 2006 -M5 executing on zizzer.eecs.umich.edu -command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/simple-timing tests/run.py quick/00.hello/alpha/linux/simple-timing -Exiting @ tick 1767066 because target called exit() +M5 compiled Apr 21 2007 21:50:58 +M5 started Sat Apr 21 21:51:09 2007 +M5 executing on zamp.eecs.umich.edu +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-timing tests/run.py quick/00.hello/alpha/linux/simple-timing +Global frequency set at 1000000000000 ticks per second +Exiting @ tick 5135000 because target called exit() |