diff options
| author | Gabe Black <gblack@eecs.umich.edu> | 2006-10-13 18:59:29 -0400 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2006-10-13 18:59:29 -0400 |
| commit | d83ccdfe5d2f22669fd65a90e2f8005cf1ffc5cc (patch) | |
| tree | 6b1bf3497e68f5e3eebc217a01b506b4e62811c5 /tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt | |
| parent | ca4063ac00202b80e11312be62abbe4283cfae7b (diff) | |
| download | gem5-d83ccdfe5d2f22669fd65a90e2f8005cf1ffc5cc.tar.xz | |
Fix stats for new bus model
--HG--
extra : convert_revision : c081754c8eb8fa5b8e7336deb3fefb545789b8ac
Diffstat (limited to 'tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt')
| -rw-r--r-- | tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt | 515 |
1 files changed, 260 insertions, 255 deletions
diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt index 41348bbfb..95835cb62 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt @@ -1,40 +1,40 @@ ---------- Begin Simulation Statistics ---------- global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 155 # Number of BTB hits +global.BPredUnit.BTBHits 200 # Number of BTB hits global.BPredUnit.BTBLookups 711 # Number of BTB lookups -global.BPredUnit.RASInCorrect 37 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 222 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 441 # Number of conditional branches predicted -global.BPredUnit.lookups 888 # Number of BP lookups -global.BPredUnit.usedRAS 160 # Number of times the RAS was used to get a target. -host_inst_rate 26386 # Simulator instruction rate (inst/s) -host_mem_usage 159884 # Number of bytes of host memory used -host_seconds 0.09 # Real time elapsed on the host -host_tick_rate 31792 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 9 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 7 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 675 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 369 # Number of stores inserted to the mem dependence unit. +global.BPredUnit.RASInCorrect 42 # Number of incorrect RAS predictions. +global.BPredUnit.condIncorrect 221 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 451 # Number of conditional branches predicted +global.BPredUnit.lookups 891 # Number of BP lookups +global.BPredUnit.usedRAS 172 # Number of times the RAS was used to get a target. +host_inst_rate 1447 # Simulator instruction rate (inst/s) +host_mem_usage 180084 # Number of bytes of host memory used +host_seconds 1.65 # Real time elapsed on the host +host_tick_rate 455868 # Simulator tick rate (ticks/s) +memdepunit.memDep.conflictingLoads 10 # Number of conflicting loads. +memdepunit.memDep.conflictingStores 8 # Number of conflicting stores. +memdepunit.memDep.insertedLoads 784 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 376 # Number of stores inserted to the mem dependence unit. sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 2387 # Number of instructions simulated -sim_seconds 0.000000 # Number of seconds simulated -sim_ticks 2886 # Number of ticks simulated +sim_seconds 0.000001 # Number of seconds simulated +sim_ticks 752027 # Number of ticks simulated system.cpu.commit.COM:branches 396 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 40 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 56 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 2646 +system.cpu.commit.COM:committed_per_cycle.samples 28113 system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 1713 6473.92% - 1 239 903.25% - 2 322 1216.93% - 3 139 525.32% - 4 78 294.78% - 5 67 253.21% - 6 27 102.04% - 7 21 79.37% - 8 40 151.17% + 0 27203 9676.31% + 1 230 81.81% + 2 313 111.34% + 3 133 47.31% + 4 80 28.46% + 5 53 18.85% + 6 27 9.60% + 7 18 6.40% + 8 56 19.92% system.cpu.commit.COM:committed_per_cycle.max_value 8 system.cpu.commit.COM:committed_per_cycle.end_dist @@ -43,69 +43,69 @@ system.cpu.commit.COM:loads 415 # Nu system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 709 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 138 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 144 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 2576 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 4 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 1258 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 1694 # The number of squashed insts skipped by commit system.cpu.committedInsts 2387 # Number of Instructions Simulated system.cpu.committedInsts_total 2387 # Number of Instructions Simulated -system.cpu.cpi 1.209049 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.209049 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 534 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 3 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 469 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 195 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.121723 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 65 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 4 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 122 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.114232 # mshr miss rate for ReadReq accesses +system.cpu.cpi 315.051110 # CPI: Cycles Per Instruction +system.cpu.cpi_total 315.051110 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 562 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 7254.010870 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7288.590164 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 470 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 667369 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.163701 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 92 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 31 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 444604 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.108541 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 61 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 294 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 3.017241 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2.208333 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 236 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 175 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.197279 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 58 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 34 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 53 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_avg_miss_latency 6647.600000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 6571.583333 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 224 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 465332 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.238095 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 70 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 46 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 157718 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.081633 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 24 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets 1.500000 # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 8.294118 # Average number of references to valid blocks. +system.cpu.dcache.avg_blocked_cycles_no_targets 2980.125000 # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 8.164706 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_no_targets 2 # number of cycles access was blocked +system.cpu.dcache.blocked_no_targets 8 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_targets 3 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_targets 23841 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 828 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 3.008130 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 2.058824 # average overall mshr miss latency -system.cpu.dcache.demand_hits 705 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 370 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.148551 # miss rate for demand accesses -system.cpu.dcache.demand_misses 123 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 38 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 175 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.102657 # mshr miss rate for demand accesses +system.cpu.dcache.demand_accesses 856 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 6991.981481 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 7086.141176 # average overall mshr miss latency +system.cpu.dcache.demand_hits 694 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 1132701 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.189252 # miss rate for demand accesses +system.cpu.dcache.demand_misses 162 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 77 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 602322 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.099299 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 85 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 828 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 3.008130 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 2.058824 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 705 # number of overall hits -system.cpu.dcache.overall_miss_latency 370 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.148551 # miss rate for overall accesses -system.cpu.dcache.overall_misses 123 # number of overall misses -system.cpu.dcache.overall_mshr_hits 38 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 175 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.102657 # mshr miss rate for overall accesses +system.cpu.dcache.overall_accesses 856 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 6991.981481 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 7086.141176 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency +system.cpu.dcache.overall_hits 694 # number of overall hits +system.cpu.dcache.overall_miss_latency 1132701 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.189252 # miss rate for overall accesses +system.cpu.dcache.overall_misses 162 # number of overall misses +system.cpu.dcache.overall_mshr_hits 77 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 602322 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.099299 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 85 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses @@ -121,89 +121,89 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 85 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 54.161413 # Cycle average of tags in use -system.cpu.dcache.total_refs 705 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 46.684937 # Cycle average of tags in use +system.cpu.dcache.total_refs 694 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 82 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 90 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 156 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 4646 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 1691 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 873 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 240 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 315 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 1 # Number of cycles decode is unblocking -system.cpu.fetch.Branches 888 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 740 # Number of cache lines fetched -system.cpu.fetch.Cycles 1663 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 77 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 5518 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 235 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.307586 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 740 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 315 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 1.911327 # Number of inst fetches per cycle +system.cpu.decode.DECODE:BlockedCycles 21872 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 79 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 150 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 4868 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 5315 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 925 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 338 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 286 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 2 # Number of cycles decode is unblocking +system.cpu.fetch.Branches 891 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 814 # Number of cache lines fetched +system.cpu.fetch.Cycles 1788 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 145 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 5562 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 260 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.031316 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 814 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 372 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 0.195487 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 2887 +system.cpu.fetch.rateDist.samples 28452 system.cpu.fetch.rateDist.min_value 0 - 0 1965 6806.37% - 1 36 124.70% - 2 79 273.64% - 3 66 228.61% - 4 125 432.98% - 5 60 207.83% - 6 40 138.55% - 7 42 145.48% - 8 474 1641.84% + 0 27494 9663.29% + 1 51 17.92% + 2 92 32.34% + 3 74 26.01% + 4 117 41.12% + 5 71 24.95% + 6 43 15.11% + 7 56 19.68% + 8 454 159.57% system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.end_dist -system.cpu.icache.ReadReq_accesses 740 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 2.989474 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 2 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 550 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 568 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.256757 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 190 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 1 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 378 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.255405 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 189 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_accesses 814 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 4971.589641 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 4152.244565 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 563 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 1247869 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.308354 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 251 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 67 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 764013 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.226044 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 184 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_refs 2.910053 # Average number of references to valid blocks. +system.cpu.icache.avg_blocked_cycles_no_targets 3445 # average number of cycles each access was blocked +system.cpu.icache.avg_refs 3.059783 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_no_targets 4 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_targets 13780 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 740 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 2.989474 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 2 # average overall mshr miss latency -system.cpu.icache.demand_hits 550 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 568 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.256757 # miss rate for demand accesses -system.cpu.icache.demand_misses 190 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 1 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 378 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.255405 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 189 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_accesses 814 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 4971.589641 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 4152.244565 # average overall mshr miss latency +system.cpu.icache.demand_hits 563 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 1247869 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.308354 # miss rate for demand accesses +system.cpu.icache.demand_misses 251 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 67 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 764013 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.226044 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 184 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 740 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 2.989474 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 2 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 550 # number of overall hits -system.cpu.icache.overall_miss_latency 568 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.256757 # miss rate for overall accesses -system.cpu.icache.overall_misses 190 # number of overall misses -system.cpu.icache.overall_mshr_hits 1 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 378 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.255405 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 189 # number of overall MSHR misses +system.cpu.icache.overall_accesses 814 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 4971.589641 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 4152.244565 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency +system.cpu.icache.overall_hits 563 # number of overall hits +system.cpu.icache.overall_miss_latency 1247869 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.308354 # miss rate for overall accesses +system.cpu.icache.overall_misses 251 # number of overall misses +system.cpu.icache.overall_mshr_hits 67 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 764013 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.226044 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 184 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -216,78 +216,79 @@ system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.sampled_refs 189 # Sample count of references to valid blocks. +system.cpu.icache.sampled_refs 184 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 115.538968 # Cycle average of tags in use -system.cpu.icache.total_refs 550 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 91.596526 # Cycle average of tags in use +system.cpu.icache.total_refs 563 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.iew.EXEC:branches 532 # Number of branches executed -system.cpu.iew.EXEC:nop 247 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.078628 # Inst execution rate -system.cpu.iew.EXEC:refs 910 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 336 # Number of stores executed +system.cpu.idleCycles 723576 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 571 # Number of branches executed +system.cpu.iew.EXEC:nop 266 # number of nop insts executed +system.cpu.iew.EXEC:rate 0.119043 # Inst execution rate +system.cpu.iew.EXEC:refs 1018 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 343 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 1788 # num instructions consuming a value -system.cpu.iew.WB:count 3053 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.790828 # average fanout of values written-back +system.cpu.iew.WB:consumers 1875 # num instructions consuming a value +system.cpu.iew.WB:count 3246 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.785067 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 1414 # num instructions producing a value -system.cpu.iew.WB:rate 1.057499 # insts written-back per cycle -system.cpu.iew.WB:sent 3067 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 158 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 0 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 675 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 7 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 127 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 369 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 3835 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 574 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 143 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 3114 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 1472 # num instructions producing a value +system.cpu.iew.WB:rate 0.114087 # insts written-back per cycle +system.cpu.iew.WB:sent 3258 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 160 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 14741 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 784 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 6 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 71 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 376 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 4271 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 675 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 113 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 3387 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 9 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 240 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking +system.cpu.iew.iewSquashCycles 338 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 13 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 2 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 30 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.cacheBlocked 82 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.0.forwLoads 29 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread.0.memOrderViolation 11 # Number of memory ordering violations system.cpu.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 260 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 75 # Number of stores squashed +system.cpu.iew.lsq.thread.0.squashedLoads 369 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 82 # Number of stores squashed system.cpu.iew.memOrderViolationEvents 11 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 105 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 53 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 0.827096 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.827096 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 3257 # Type of FU issued +system.cpu.iew.predictedNotTakenIncorrect 99 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 61 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 0.003174 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.003174 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 3500 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist - (null) 0 0.00% # Type of FU issued - IntAlu 2308 70.86% # Type of FU issued - IntMult 1 0.03% # Type of FU issued - IntDiv 0 0.00% # Type of FU issued - FloatAdd 0 0.00% # Type of FU issued - FloatCmp 0 0.00% # Type of FU issued - FloatCvt 0 0.00% # Type of FU issued - FloatMult 0 0.00% # Type of FU issued - FloatDiv 0 0.00% # Type of FU issued - FloatSqrt 0 0.00% # Type of FU issued - MemRead 605 18.58% # Type of FU issued - MemWrite 343 10.53% # Type of FU issued - IprAccess 0 0.00% # Type of FU issued - InstPrefetch 0 0.00% # Type of FU issued +(null) 0 0.00% # Type of FU issued +IntAlu 2460 70.29% # Type of FU issued +IntMult 1 0.03% # Type of FU issued +IntDiv 0 0.00% # Type of FU issued +FloatAdd 0 0.00% # Type of FU issued +FloatCmp 0 0.00% # Type of FU issued +FloatCvt 0 0.00% # Type of FU issued +FloatMult 0 0.00% # Type of FU issued +FloatDiv 0 0.00% # Type of FU issued +FloatSqrt 0 0.00% # Type of FU issued +MemRead 695 19.86% # Type of FU issued +MemWrite 344 9.83% # Type of FU issued +IprAccess 0 0.00% # Type of FU issued +InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 40 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.012281 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_cnt 35 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.010000 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full.start_dist (null) 0 0.00% # attempts to use FU when none available - IntAlu 5 12.50% # attempts to use FU when none available + IntAlu 2 5.71% # attempts to use FU when none available IntMult 0 0.00% # attempts to use FU when none available IntDiv 0 0.00% # attempts to use FU when none available FloatAdd 0 0.00% # attempts to use FU when none available @@ -296,43 +297,43 @@ system.cpu.iq.ISSUE:fu_full.start_dist FloatMult 0 0.00% # attempts to use FU when none available FloatDiv 0 0.00% # attempts to use FU when none available FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 12 30.00% # attempts to use FU when none available - MemWrite 23 57.50% # attempts to use FU when none available + MemRead 11 31.43% # attempts to use FU when none available + MemWrite 22 62.86% # attempts to use FU when none available IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 2887 +system.cpu.iq.ISSUE:issued_per_cycle.samples 28452 system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 1607 5566.33% - 1 435 1506.75% - 2 298 1032.21% - 3 221 765.50% - 4 164 568.06% - 5 94 325.60% - 6 46 159.33% - 7 15 51.96% - 8 7 24.25% + 0 26938 9467.88% + 1 609 214.04% + 2 344 120.91% + 3 248 87.16% + 4 180 63.26% + 5 81 28.47% + 6 35 12.30% + 7 12 4.22% + 8 5 1.76% system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.end_dist -system.cpu.iq.ISSUE:rate 1.128161 # Inst issue rate -system.cpu.iq.iqInstsAdded 3581 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 3257 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 7 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 1088 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 1 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 3 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 503 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.l2cache.ReadReq_accesses 274 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 2.018248 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_miss_latency 553 # number of ReadReq miss cycles +system.cpu.iq.ISSUE:rate 0.123014 # Inst issue rate +system.cpu.iq.iqInstsAdded 3999 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 3500 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 6 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 1423 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 25 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 761 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.l2cache.ReadReq_accesses 269 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 4622.063197 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2296.591078 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_miss_latency 1243335 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 274 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 274 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_misses 269 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 617783 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 274 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses 269 # number of ReadReq MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks. @@ -341,32 +342,32 @@ system.cpu.l2cache.blocked_no_targets 0 # nu system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 274 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 2.018248 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 1 # average overall mshr miss latency +system.cpu.l2cache.demand_accesses 269 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 4622.063197 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 2296.591078 # average overall mshr miss latency system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 553 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 1243335 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 274 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses 269 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 274 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 617783 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 274 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses 269 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 274 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 2.018248 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 1 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.l2cache.overall_accesses 269 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 4622.063197 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 2296.591078 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 0 # number of overall hits -system.cpu.l2cache.overall_miss_latency 553 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 1243335 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 274 # number of overall misses +system.cpu.l2cache.overall_misses 269 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 274 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 617783 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 274 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses 269 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -379,27 +380,31 @@ system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 274 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 269 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 169.795289 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 138.802720 # Cycle average of tags in use system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.numCycles 2887 # number of cpu cycles simulated +system.cpu.numCycles 28452 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 14785 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 1768 # Number of HB maps that are committed -system.cpu.rename.RENAME:IdleCycles 1780 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 2 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 4975 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 4400 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 3144 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 785 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 240 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 8 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 1376 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 74 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 10 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 62 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 8 # count of temporary serializing insts renamed +system.cpu.rename.RENAME:IQFullEvents 18 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 5396 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 1 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:ROBFullEvents 2 # Number of times rename has blocked due to ROB full +system.cpu.rename.RENAME:RenameLookups 5263 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 4690 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 3393 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 851 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 338 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 25 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 1625 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 7057 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 8 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 88 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 6 # count of temporary serializing insts renamed +system.cpu.timesIdled 211 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 4 # Number of system calls ---------- End Simulation Statistics ---------- |