Update refs.

--HG--
extra : convert_revision : 61d298fb0d9a66a76209a6bfcdb7c14f2efca947

5 files changed, 66 insertions, 71 deletions

diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini
index e15dd47b7..9f557431e 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini
@@ -102,7 +102,6 @@ max_insts_all_threads=0
 max_insts_any_thread=0
 max_loads_all_threads=0
 max_loads_any_thread=0
-mem=system.cpu.dcache
 numIQEntries=64
 numPhysFloatRegs=256
 numPhysIntRegs=256
@@ -132,7 +131,6 @@ assoc=2
 block_size=64
 compressed_bus=false
 compression_latency=0
-do_copy=false
 hash_delay=1
 hit_latency=1
 latency=1
@@ -309,7 +307,6 @@ assoc=2
 block_size=64
 compressed_bus=false
 compression_latency=0
-do_copy=false
 hash_delay=1
 hit_latency=1
 latency=1
@@ -349,7 +346,6 @@ assoc=2
 block_size=64
 compressed_bus=false
 compression_latency=0
-do_copy=false
 hash_delay=1
 hit_latency=1
 latency=1
@@ -386,6 +382,7 @@ mem_side=system.membus.port[1]
 type=Bus
 bus_id=0
 clock=1000
+responder_set=false
 width=64
 port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
 
@@ -408,6 +405,7 @@ uid=100
 type=Bus
 bus_id=0
 clock=1000
+responder_set=false
 width=64
 port=system.physmem.port system.cpu.l2cache.mem_side
 
diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.out b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.out
index a57dbacf3..bf7a9fe00 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.out
+++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.out
@@ -21,6 +21,7 @@ type=Bus
 bus_id=0
 clock=1000
 width=64
+responder_set=false
 
 [system.cpu.workload]
 type=LiveProcess
@@ -37,45 +38,6 @@ egid=100
 pid=100
 ppid=99
 
-[system.cpu.dcache]
-type=BaseCache
-size=262144
-assoc=2
-block_size=64
-latency=1
-mshrs=10
-tgts_per_mshr=5
-write_buffers=8
-prioritizeRequests=false
-do_copy=false
-protocol=null
-trace_addr=0
-hash_delay=1
-repl=null
-compressed_bus=false
-store_compressed=false
-adaptive_compression=false
-compression_latency=0
-block_size=64
-max_miss_count=0
-addr_range=[0,18446744073709551615]
-split=false
-split_size=0
-lifo=false
-two_queue=false
-prefetch_miss=false
-prefetch_access=false
-prefetcher_size=100
-prefetch_past_page=false
-prefetch_serial_squash=false
-prefetch_latency=10
-prefetch_degree=1
-prefetch_policy=none
-prefetch_cache_check_push=true
-prefetch_use_cpu_id=true
-prefetch_data_accesses_only=false
-hit_latency=1
-
 [system.cpu.fuPool.FUList0.opList0]
 type=OpDesc
 opClass=IntAlu
@@ -210,7 +172,6 @@ clock=1
 numThreads=1
 activity=0
 workload=system.cpu.workload
-mem=system.cpu.dcache
 checker=null
 max_insts_any_thread=0
 max_insts_all_threads=0
@@ -292,7 +253,44 @@ mshrs=10
 tgts_per_mshr=5
 write_buffers=8
 prioritizeRequests=false
-do_copy=false
+protocol=null
+trace_addr=0
+hash_delay=1
+repl=null
+compressed_bus=false
+store_compressed=false
+adaptive_compression=false
+compression_latency=0
+block_size=64
+max_miss_count=0
+addr_range=[0,18446744073709551615]
+split=false
+split_size=0
+lifo=false
+two_queue=false
+prefetch_miss=false
+prefetch_access=false
+prefetcher_size=100
+prefetch_past_page=false
+prefetch_serial_squash=false
+prefetch_latency=10
+prefetch_degree=1
+prefetch_policy=none
+prefetch_cache_check_push=true
+prefetch_use_cpu_id=true
+prefetch_data_accesses_only=false
+hit_latency=1
+
+[system.cpu.dcache]
+type=BaseCache
+size=262144
+assoc=2
+block_size=64
+latency=1
+mshrs=10
+tgts_per_mshr=5
+write_buffers=8
+prioritizeRequests=false
 protocol=null
 trace_addr=0
 hash_delay=1
@@ -331,7 +329,6 @@ mshrs=10
 tgts_per_mshr=5
 write_buffers=8
 prioritizeRequests=false
-do_copy=false
 protocol=null
 trace_addr=0
 hash_delay=1
@@ -365,6 +362,7 @@ type=Bus
 bus_id=0
 clock=1000
 width=64
+responder_set=false
 
 [trace]
 flags=
diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt
index 95835cb62..44f155480 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt
+++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt
@@ -8,10 +8,10 @@ global.BPredUnit.condIncorrect                    221                       # Nu
 global.BPredUnit.condPredicted                    451                       # Number of conditional branches predicted
 global.BPredUnit.lookups                          891                       # Number of BP lookups
 global.BPredUnit.usedRAS                          172                       # Number of times the RAS was used to get a target.
-host_inst_rate                                   1447                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 180084                       # Number of bytes of host memory used
-host_seconds                                     1.65                       # Real time elapsed on the host
-host_tick_rate                                 455868                       # Simulator tick rate (ticks/s)
+host_inst_rate                                  20134                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 179640                       # Number of bytes of host memory used
+host_seconds                                     0.12                       # Real time elapsed on the host
+host_tick_rate                                6326998                       # Simulator tick rate (ticks/s)
 memdepunit.memDep.conflictingLoads                 10                       # Number of conflicting loads.
 memdepunit.memDep.conflictingStores                 8                       # Number of conflicting stores.
 memdepunit.memDep.insertedLoads                   784                       # Number of loads inserted to the mem dependence unit.
@@ -98,7 +98,7 @@ system.cpu.dcache.no_allocate_misses                0                       # Nu
 system.cpu.dcache.overall_accesses                856                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_avg_miss_latency  6991.981481                       # average overall miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency  7086.141176                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no value                       # average overall mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
 system.cpu.dcache.overall_hits                    694                       # number of overall hits
 system.cpu.dcache.overall_miss_latency        1132701                       # number of overall miss cycles
 system.cpu.dcache.overall_miss_rate          0.189252                       # miss rate for overall accesses
@@ -195,7 +195,7 @@ system.cpu.icache.no_allocate_misses                0                       # Nu
 system.cpu.icache.overall_accesses                814                       # number of overall (read+write) accesses
 system.cpu.icache.overall_avg_miss_latency  4971.589641                       # average overall miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency  4152.244565                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency     no value                       # average overall mshr uncacheable latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
 system.cpu.icache.overall_hits                    563                       # number of overall hits
 system.cpu.icache.overall_miss_latency        1247869                       # number of overall miss cycles
 system.cpu.icache.overall_miss_rate          0.308354                       # miss rate for overall accesses
@@ -269,20 +269,20 @@ system.cpu.ipc                               0.003174                       # IP
 system.cpu.ipc_total                         0.003174                       # IPC: Total IPC of All Threads
 system.cpu.iq.ISSUE:FU_type_0                    3500                       # Type of FU issued
 system.cpu.iq.ISSUE:FU_type_0.start_dist
-(null)                                              0      0.00%            # Type of FU issued
-IntAlu                                           2460     70.29%            # Type of FU issued
-IntMult                                             1      0.03%            # Type of FU issued
-IntDiv                                              0      0.00%            # Type of FU issued
-FloatAdd                                            0      0.00%            # Type of FU issued
-FloatCmp                                            0      0.00%            # Type of FU issued
-FloatCvt                                            0      0.00%            # Type of FU issued
-FloatMult                                           0      0.00%            # Type of FU issued
-FloatDiv                                            0      0.00%            # Type of FU issued
-FloatSqrt                                           0      0.00%            # Type of FU issued
-MemRead                                           695     19.86%            # Type of FU issued
-MemWrite                                          344      9.83%            # Type of FU issued
-IprAccess                                           0      0.00%            # Type of FU issued
-InstPrefetch                                        0      0.00%            # Type of FU issued
+                          (null)            0      0.00%            # Type of FU issued
+                          IntAlu         2460     70.29%            # Type of FU issued
+                         IntMult            1      0.03%            # Type of FU issued
+                          IntDiv            0      0.00%            # Type of FU issued
+                        FloatAdd            0      0.00%            # Type of FU issued
+                        FloatCmp            0      0.00%            # Type of FU issued
+                        FloatCvt            0      0.00%            # Type of FU issued
+                       FloatMult            0      0.00%            # Type of FU issued
+                        FloatDiv            0      0.00%            # Type of FU issued
+                       FloatSqrt            0      0.00%            # Type of FU issued
+                         MemRead          695     19.86%            # Type of FU issued
+                        MemWrite          344      9.83%            # Type of FU issued
+                       IprAccess            0      0.00%            # Type of FU issued
+                    InstPrefetch            0      0.00%            # Type of FU issued
 system.cpu.iq.ISSUE:FU_type_0.end_dist
 system.cpu.iq.ISSUE:fu_busy_cnt                    35                       # FU busy when requested
 system.cpu.iq.ISSUE:fu_busy_rate             0.010000                       # FU busy rate (busy events/executed inst)
@@ -359,7 +359,7 @@ system.cpu.l2cache.no_allocate_misses               0                       # Nu
 system.cpu.l2cache.overall_accesses               269                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_avg_miss_latency  4622.063197                       # average overall miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency  2296.591078                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no value                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
 system.cpu.l2cache.overall_hits                     0                       # number of overall hits
 system.cpu.l2cache.overall_miss_latency       1243335                       # number of overall miss cycles
 system.cpu.l2cache.overall_miss_rate                1                       # miss rate for overall accesses
diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stderr b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stderr
index 5f8fafdd1..cb1e9904d 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stderr
+++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stderr
@@ -1,6 +1,5 @@
 warn: Entering event queue @ 0.  Starting simulation...
 warn: cycle 0: fault (page_table_fault) detected @ PC 0x000000
-warn: Increasing stack 0x11ff92000:0x11ff9b000 to 0x11ff90000:0x11ff9b000 because of access to 0x11ff91ff8
 warn: cycle 109049: fault (page_table_fault) detected @ PC 0x000000
 warn: cycle 109050: fault (page_table_fault) detected @ PC 0x000000
 warn: cycle 109051: fault (page_table_fault) detected @ PC 0x000000
diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout
index 6f8154bb0..4453bcfe2 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout
+++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout
@@ -6,8 +6,8 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Oct 13 2006 16:07:10
-M5 started Fri Oct 13 16:08:37 2006
+M5 compiled Nov  3 2006 17:10:27
+M5 started Fri Nov  3 17:10:50 2006
 M5 executing on zizzer.eecs.umich.edu
-command line: build/ALPHA_SE/m5.debug -d build/ALPHA_SE/tests/debug/quick/00.hello/alpha/tru64/o3-timing tests/run.py quick/00.hello/alpha/tru64/o3-timing
+command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/o3-timing tests/run.py quick/00.hello/alpha/tru64/o3-timing
 Exiting @ tick 752027 because target called exit()