regress: Regression Tester output updates

3 files changed, 41 insertions, 10 deletions

diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini
index 2ddfc3365..2b9fce4f2 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini
@@ -1,13 +1,22 @@
 [root]
 type=Root
 children=system
-dummy=0
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
 
 [system]
 type=System
 children=cpu membus physmem
 mem_mode=atomic
 physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
 
 [system.cpu]
 type=DerivO3CPU
@@ -484,7 +493,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello
+executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/tru64/hello
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout
index fe2af5e09..e774ba11e 100755
--- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout
+++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Jan 17 2011 16:24:53
-M5 revision f72d94f8c275 7839 default qtip tip outgoing.patch qbase
-M5 started Jan 17 2011 16:48:46
-M5 executing on zizzer
+M5 compiled Feb  6 2011 20:42:22
+M5 revision b885adc82ab4+ 7924+ default tip qtip brad/regress_updates
+M5 started Feb  6 2011 20:42:36
+M5 executing on SC2B0617
 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt
index 2363f1511..311a86bd4 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                  61982                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 202420                       # Number of bytes of host memory used
-host_seconds                                     0.04                       # Real time elapsed on the host
-host_tick_rate                              188319059                       # Simulator tick rate (ticks/s)
+host_inst_rate                                  78818                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 204536                       # Number of bytes of host memory used
+host_seconds                                     0.03                       # Real time elapsed on the host
+host_tick_rate                              238897798                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                        2387                       # Number of instructions simulated
 sim_seconds                                  0.000007                       # Number of seconds simulated
@@ -37,6 +37,9 @@ system.cpu.commit.COM:committed_per_cycle::min_value            0
 system.cpu.commit.COM:committed_per_cycle::max_value            8                       # Number of insts commited each cycle
 system.cpu.commit.COM:committed_per_cycle::total         6328                       # Number of insts commited each cycle
 system.cpu.commit.COM:count                      2576                       # Number of instructions committed
+system.cpu.commit.COM:fp_insts                      6                       # Number of committed floating point instructions.
+system.cpu.commit.COM:function_calls               71                       # Number of function calls committed.
+system.cpu.commit.COM:int_insts                  2367                       # Number of committed integer instructions.
 system.cpu.commit.COM:loads                       415                       # Number of loads committed
 system.cpu.commit.COM:membars                       0                       # Number of memory barriers committed
 system.cpu.commit.COM:refs                        709                       # Number of memory references committed
@@ -169,6 +172,7 @@ system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Nu
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::total                 6701                       # Number of instructions fetched each cycle (Total)
+system.cpu.fp_regfile_reads                         6                       # number of floating regfile reads
 system.cpu.icache.ReadReq_accesses                782                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_avg_miss_latency 36074.786325                       # average ReadReq miss latency
 system.cpu.icache.ReadReq_avg_mshr_miss_latency 35303.867403                       # average ReadReq mshr miss latency
@@ -268,6 +272,8 @@ system.cpu.iew.lsq.thread.0.squashedStores          141                       #
 system.cpu.iew.memOrderViolationEvents             13                       # Number of memory order violations
 system.cpu.iew.predictedNotTakenIncorrect          109                       # Number of branches that were predicted not taken incorrectly
 system.cpu.iew.predictedTakenIncorrect             55                       # Number of branches that were predicted taken incorrectly
+system.cpu.int_regfile_reads                     4283                       # number of integer regfile reads
+system.cpu.int_regfile_writes                    2601                       # number of integer regfile writes
 system.cpu.ipc                               0.163482                       # IPC: Instructions Per Cycle
 system.cpu.ipc_total                         0.163482                       # IPC: Total IPC of All Threads
 system.cpu.iq.ISSUE:FU_type_0::No_OpClass            0      0.00%      0.00% # Type of FU issued
@@ -359,6 +365,14 @@ system.cpu.iq.ISSUE:issued_per_cycle::min_value            0
 system.cpu.iq.ISSUE:issued_per_cycle::max_value            8                       # Number of insts issued each cycle
 system.cpu.iq.ISSUE:issued_per_cycle::total         6701                       # Number of insts issued each cycle
 system.cpu.iq.ISSUE:rate                     0.248682                       # Inst issue rate
+system.cpu.iq.fp_alu_accesses                       7                       # Number of floating point alu accesses
+system.cpu.iq.fp_inst_queue_reads                  13                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_wakeup_accesses            6                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_writes                  6                       # Number of floating instruction queue writes
+system.cpu.iq.int_alu_accesses                   3659                       # Number of integer alu accesses
+system.cpu.iq.int_inst_queue_reads              14008                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_wakeup_accesses         3396                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.int_inst_queue_writes              5997                       # Number of integer instruction queue writes
 system.cpu.iq.iqInstsAdded                       4276                       # Number of instructions added to the IQ (excludes non-spec)
 system.cpu.iq.iqInstsIssued                      3631                       # Number of instructions issued
 system.cpu.iq.iqNonSpecInstsAdded                   6                       # Number of non-speculative instructions added to the IQ
@@ -449,7 +463,11 @@ system.cpu.memDep0.conflictingLoads                16                       # Nu
 system.cpu.memDep0.conflictingStores               16                       # Number of conflicting stores.
 system.cpu.memDep0.insertedLoads                  793                       # Number of loads inserted to the mem dependence unit.
 system.cpu.memDep0.insertedStores                 435                       # Number of stores inserted to the mem dependence unit.
+system.cpu.misc_regfile_reads                       1                       # number of misc regfile reads
+system.cpu.misc_regfile_writes                      1                       # number of misc regfile writes
 system.cpu.numCycles                            14601                       # number of cpu cycles simulated
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.rename.RENAME:BlockCycles               63                       # Number of cycles rename is blocking
 system.cpu.rename.RENAME:CommittedMaps           1768                       # Number of HB maps that are committed
 system.cpu.rename.RENAME:IQFullEvents               3                       # Number of times rename has blocked due to IQ full
@@ -462,10 +480,14 @@ system.cpu.rename.RENAME:RunCycles                901                       # Nu
 system.cpu.rename.RENAME:SquashCycles             373                       # Number of cycles rename is squashing
 system.cpu.rename.RENAME:UnblockCycles             15                       # Number of cycles rename is unblocking
 system.cpu.rename.RENAME:UndoneMaps              1713                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.RENAME:fp_rename_lookups           12                       # Number of floating rename lookups
+system.cpu.rename.RENAME:int_rename_lookups         5502                       # Number of integer rename lookups
 system.cpu.rename.RENAME:serializeStallCycles          146                       # count of cycles rename stalled for serializing inst
 system.cpu.rename.RENAME:serializingInsts            8                       # count of serializing insts renamed
 system.cpu.rename.RENAME:skidInsts                 78                       # count of insts added to the skid buffer
 system.cpu.rename.RENAME:tempSerializingInsts            6                       # count of temporary serializing insts renamed
+system.cpu.rob.rob_reads                        10620                       # The number of ROB reads
+system.cpu.rob.rob_writes                        9524                       # The number of ROB writes
 system.cpu.timesIdled                             152                       # Number of times that the entire CPU went into an idle state and unscheduled itself
 system.cpu.workload.PROG:num_syscalls               4                       # Number of system calls