Update reference config.ini files to include port mappings.

--HG--
extra : convert_revision : f9e91a60fa09b707d2a26be57f265b7ab1c07263

3 files changed, 17 insertions, 6 deletions

diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini
index 388ddf7b6..790ae6ab3 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini
@@ -121,6 +121,8 @@ trapLatency=13
 wbDepth=1
 wbWidth=8
 workload=system.cpu.workload
+dcache_port=system.cpu.dcache.cpu_side
+icache_port=system.cpu.icache.cpu_side
 
 [system.cpu.dcache]
 type=BaseCache
@@ -159,6 +161,8 @@ tgts_per_mshr=5
 trace_addr=0
 two_queue=false
 write_buffers=8
+cpu_side=system.cpu.dcache_port
+mem_side=system.cpu.toL2Bus.port[1]
 
 [system.cpu.fuPool]
 type=FUPool
@@ -334,6 +338,8 @@ tgts_per_mshr=5
 trace_addr=0
 two_queue=false
 write_buffers=8
+cpu_side=system.cpu.icache_port
+mem_side=system.cpu.toL2Bus.port[0]
 
 [system.cpu.l2cache]
 type=BaseCache
@@ -372,10 +378,13 @@ tgts_per_mshr=5
 trace_addr=0
 two_queue=false
 write_buffers=8
+cpu_side=system.cpu.toL2Bus.port[2]
+mem_side=system.membus.port[1]
 
 [system.cpu.toL2Bus]
 type=Bus
 bus_id=0
+port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
 
 [system.cpu.workload]
 type=LiveProcess
@@ -389,12 +398,14 @@ system=system
 [system.membus]
 type=Bus
 bus_id=0
+port=system.physmem.port system.cpu.l2cache.mem_side
 
 [system.physmem]
 type=PhysicalMemory
 file=
 latency=1
 range=0:134217727
+port=system.membus.port[0]
 
 [trace]
 bufsize=0
diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt
index 5c59263ac..db582e731 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt
+++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt
@@ -8,10 +8,10 @@ global.BPredUnit.condIncorrect                    222                       # Nu
 global.BPredUnit.condPredicted                    441                       # Number of conditional branches predicted
 global.BPredUnit.lookups                          888                       # Number of BP lookups
 global.BPredUnit.usedRAS                          160                       # Number of times the RAS was used to get a target.
-host_inst_rate                                  22611                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 159596                       # Number of bytes of host memory used
-host_seconds                                     0.11                       # Real time elapsed on the host
-host_tick_rate                                  27259                       # Simulator tick rate (ticks/s)
+host_inst_rate                                  26468                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 159864                       # Number of bytes of host memory used
+host_seconds                                     0.09                       # Real time elapsed on the host
+host_tick_rate                                  31894                       # Simulator tick rate (ticks/s)
 memdepunit.memDep.conflictingLoads                  9                       # Number of conflicting loads.
 memdepunit.memDep.conflictingStores                 7                       # Number of conflicting stores.
 memdepunit.memDep.insertedLoads                   675                       # Number of loads inserted to the mem dependence unit.
diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout
index 04a06d3ab..708b9587a 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout
+++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout
@@ -6,8 +6,8 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Sep  1 2006 16:10:44
-M5 started Fri Sep  1 16:23:45 2006
+M5 compiled Sep  5 2006 15:28:48
+M5 started Tue Sep  5 15:42:16 2006
 M5 executing on zizzer.eecs.umich.edu
 command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/o3-timing tests/run.py quick/00.hello/alpha/tru64/o3-timing
 Exiting @ tick 2886 because target called exit()