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authorBrad Beckmann <Brad.Beckmann@amd.com>2011-02-06 22:14:23 -0800
committerBrad Beckmann <Brad.Beckmann@amd.com>2011-02-06 22:14:23 -0800
commit45f881919fc9c4d2b2d4ea9f165fb567aad9849a (patch)
tree2a6ebbec93e62ef5279ec35e27e06f86577372fd /tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stats.txt
parentf5aa75fdc528aca122ac1369fa4ac3df8a915027 (diff)
downloadgem5-45f881919fc9c4d2b2d4ea9f165fb567aad9849a.tar.xz
regress: Regression Tester output updates
Diffstat (limited to 'tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stats.txt')
-rw-r--r--tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stats.txt24
1 files changed, 20 insertions, 4 deletions
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stats.txt
index d0028e484..3874b2441 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stats.txt
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stats.txt
@@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 759729 # Simulator instruction rate (inst/s)
-host_mem_usage 228516 # Number of bytes of host memory used
+host_inst_rate 849934 # Simulator instruction rate (inst/s)
+host_mem_usage 196124 # Number of bytes of host memory used
host_seconds 0.00 # Real time elapsed on the host
-host_tick_rate 362937063 # Simulator tick rate (ticks/s)
+host_tick_rate 396667686 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 2577 # Number of instructions simulated
sim_seconds 0.000001 # Number of seconds simulated
@@ -43,8 +43,24 @@ system.cpu.itb.write_hits 0 # DT
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 2596 # number of cpu cycles simulated
+system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu.num_busy_cycles 2596 # Number of busy cycles
+system.cpu.num_conditional_control_insts 238 # number of instructions that are conditional controls
+system.cpu.num_fp_alu_accesses 6 # Number of float alu accesses
+system.cpu.num_fp_insts 6 # number of float instructions
+system.cpu.num_fp_register_reads 6 # number of times the floating registers were read
+system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
+system.cpu.num_func_calls 140 # number of times a function call or return occured
+system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_insts 2577 # Number of instructions executed
-system.cpu.num_refs 717 # Number of memory references
+system.cpu.num_int_alu_accesses 2375 # Number of integer alu accesses
+system.cpu.num_int_insts 2375 # number of integer instructions
+system.cpu.num_int_register_reads 2998 # number of times the integer registers were read
+system.cpu.num_int_register_writes 1768 # number of times the integer registers were written
+system.cpu.num_load_insts 419 # Number of load instructions
+system.cpu.num_mem_refs 717 # number of memory refs
+system.cpu.num_store_insts 298 # Number of store instructions
system.cpu.workload.PROG:num_syscalls 4 # Number of system calls
---------- End Simulation Statistics ----------