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| author | Nathan Binkert <nate@binkert.org> | 2009-04-08 22:21:30 -0700 |
|---|---|---|
| committer | Nathan Binkert <nate@binkert.org> | 2009-04-08 22:21:30 -0700 |
| commit | 374ba9bae359e68c1496f8db25c38a817af2da19 (patch) | |
| tree | 48fe4ae90f77f19aa6005fa5ec2426e836299bc9 /tests/quick/00.hello/ref/alpha/tru64/simple-atomic | |
| parent | e0de2c34433be76eac7798e58e1ae02f5bffb732 (diff) | |
| download | gem5-374ba9bae359e68c1496f8db25c38a817af2da19.tar.xz | |
tests: update tests for TLB unification
Diffstat (limited to 'tests/quick/00.hello/ref/alpha/tru64/simple-atomic')
3 files changed, 35 insertions, 19 deletions
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini index 8ca1fff45..255dbd855 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini @@ -39,11 +39,11 @@ dcache_port=system.membus.port[2] icache_port=system.membus.port[1] [system.cpu.dtb] -type=AlphaDTB +type=AlphaTLB size=64 [system.cpu.itb] -type=AlphaITB +type=AlphaTLB size=48 [system.cpu.tracer] diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simout b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simout index 7c13e1d4c..fd4dcc4fc 100755 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simout +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 16 2009 00:22:05 -M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase -M5 started Feb 16 2009 00:22:12 -M5 executing on zizzer -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-atomic -re tests/run.py quick/00.hello/alpha/tru64/simple-atomic +M5 compiled Apr 8 2009 12:30:02 +M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff +M5 started Apr 8 2009 12:30:03 +M5 executing on maize +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stats.txt index ddfd1ad69..fc21ca705 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stats.txt @@ -1,17 +1,21 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 147781 # Simulator instruction rate (inst/s) -host_mem_usage 191596 # Number of bytes of host memory used -host_seconds 0.02 # Real time elapsed on the host -host_tick_rate 73371409 # Simulator tick rate (ticks/s) +host_inst_rate 7782 # Simulator instruction rate (inst/s) +host_mem_usage 193364 # Number of bytes of host memory used +host_seconds 0.33 # Real time elapsed on the host +host_tick_rate 3915244 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 2577 # Number of instructions simulated sim_seconds 0.000001 # Number of seconds simulated sim_ticks 1297500 # Number of ticks simulated -system.cpu.dtb.accesses 717 # DTB accesses -system.cpu.dtb.acv 0 # DTB access violations -system.cpu.dtb.hits 709 # DTB hits -system.cpu.dtb.misses 8 # DTB misses +system.cpu.dtb.data_accesses 717 # DTB accesses +system.cpu.dtb.data_acv 0 # DTB access violations +system.cpu.dtb.data_hits 709 # DTB hits +system.cpu.dtb.data_misses 8 # DTB misses +system.cpu.dtb.fetch_accesses 0 # ITB accesses +system.cpu.dtb.fetch_acv 0 # ITB acv +system.cpu.dtb.fetch_hits 0 # ITB hits +system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.read_accesses 419 # DTB read accesses system.cpu.dtb.read_acv 0 # DTB read access violations system.cpu.dtb.read_hits 415 # DTB read hits @@ -21,10 +25,22 @@ system.cpu.dtb.write_acv 0 # DT system.cpu.dtb.write_hits 294 # DTB write hits system.cpu.dtb.write_misses 4 # DTB write misses system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.itb.accesses 2596 # ITB accesses -system.cpu.itb.acv 0 # ITB acv -system.cpu.itb.hits 2585 # ITB hits -system.cpu.itb.misses 11 # ITB misses +system.cpu.itb.data_accesses 0 # DTB accesses +system.cpu.itb.data_acv 0 # DTB access violations +system.cpu.itb.data_hits 0 # DTB hits +system.cpu.itb.data_misses 0 # DTB misses +system.cpu.itb.fetch_accesses 2596 # ITB accesses +system.cpu.itb.fetch_acv 0 # ITB acv +system.cpu.itb.fetch_hits 2585 # ITB hits +system.cpu.itb.fetch_misses 11 # ITB misses +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.read_acv 0 # DTB read access violations +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.write_acv 0 # DTB write access violations +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 2596 # number of cpu cycles simulated system.cpu.num_insts 2577 # Number of instructions executed |