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author | Steve Reinhardt <steve.reinhardt@amd.com> | 2011-03-26 22:24:36 -0700 |
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committer | Steve Reinhardt <steve.reinhardt@amd.com> | 2011-03-26 22:24:36 -0700 |
commit | bb67c706d6753d4c9f225748410c21f8eec4beed (patch) | |
tree | 614b689fac1024d2a07589949973d04a134f5e40 /tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt | |
parent | e0fdd86fd90d16ec7b7f9e2f81a12c2653919a27 (diff) | |
download | gem5-bb67c706d6753d4c9f225748410c21f8eec4beed.tar.xz |
tests: update reference outputs for ruby cache index change
MOESI_CMP_token is the only protocol that showed noticeable stats
differences.
Diffstat (limited to 'tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt')
-rw-r--r-- | tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt index caef5b8f0..ab4470f42 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 44139 # Simulator instruction rate (inst/s) -host_mem_usage 214488 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host -host_tick_rate 1572917 # Simulator tick rate (ticks/s) +host_inst_rate 8652 # Simulator instruction rate (inst/s) +host_mem_usage 203296 # Number of bytes of host memory used +host_seconds 0.30 # Real time elapsed on the host +host_tick_rate 282076 # Simulator tick rate (ticks/s) sim_freq 1000000000 # Frequency of simulated ticks sim_insts 2577 # Number of instructions simulated -sim_seconds 0.000092 # Number of seconds simulated -sim_ticks 92099 # Number of ticks simulated +sim_seconds 0.000084 # Number of seconds simulated +sim_ticks 84059 # Number of ticks simulated system.cpu.dtb.data_accesses 717 # DTB accesses system.cpu.dtb.data_acv 0 # DTB access violations system.cpu.dtb.data_hits 709 # DTB hits @@ -42,10 +42,10 @@ system.cpu.itb.write_acv 0 # DT system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 92099 # number of cpu cycles simulated +system.cpu.numCycles 84059 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.num_busy_cycles 92099 # Number of busy cycles +system.cpu.num_busy_cycles 84059 # Number of busy cycles system.cpu.num_conditional_control_insts 238 # number of instructions that are conditional controls system.cpu.num_fp_alu_accesses 6 # Number of float alu accesses system.cpu.num_fp_insts 6 # number of float instructions |