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authorGabe Black <gblack@eecs.umich.edu>2011-02-07 19:23:11 -0800
committerGabe Black <gblack@eecs.umich.edu>2011-02-07 19:23:11 -0800
commit1b64bfa933745294667158d0ce22180780b2a22e (patch)
tree11822ba69a5ec4c1c4b7ad72fcf08c87e143e4fe /tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token
parent44e5e7e0533ba2544f2d37f8e051a0422966bd9b (diff)
downloadgem5-1b64bfa933745294667158d0ce22180780b2a22e.tar.xz
Stats: Back out broken update.
Diffstat (limited to 'tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token')
-rw-r--r--tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini68
-rw-r--r--tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/ruby.stats62
-rwxr-xr-xtests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout8
-rw-r--r--tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt24
4 files changed, 73 insertions, 89 deletions
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini
index 537819260..1971d2a44 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini
@@ -1,22 +1,13 @@
[root]
type=Root
children=system
-time_sync_enable=false
-time_sync_period=100000000
-time_sync_spin_threshold=100000
+dummy=0
[system]
type=System
children=cpu dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby
mem_mode=timing
physmem=system.physmem
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
[system.cpu]
type=TimingSimpleCPU
@@ -41,8 +32,8 @@ progress_interval=0
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
-dcache_port=system.ruby.cpu_ruby_ports.port[1]
-icache_port=system.ruby.cpu_ruby_ports.port[0]
+dcache_port=system.l1_cntrl0.sequencer.port[1]
+icache_port=system.l1_cntrl0.sequencer.port[0]
[system.cpu.dtb]
type=AlphaTLB
@@ -63,7 +54,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/tru64/hello
+executable=tests/test-progs/hello/bin/alpha/tru64/hello
gid=100
input=cin
max_stack_size=67108864
@@ -120,9 +111,9 @@ version=0
[system.l1_cntrl0]
type=L1Cache_Controller
-children=L1DcacheMemory L1IcacheMemory
-L1DcacheMemory=system.l1_cntrl0.L1DcacheMemory
-L1IcacheMemory=system.l1_cntrl0.L1IcacheMemory
+children=sequencer
+L1DcacheMemory=system.l1_cntrl0.sequencer.dcache
+L1IcacheMemory=system.l1_cntrl0.sequencer.icache
N_tokens=2
buffer_size=0
dynamic_timeout_enabled=true
@@ -134,11 +125,24 @@ no_mig_atomic=true
number_of_TBEs=256
recycle_latency=10
retry_threshold=1
-sequencer=system.ruby.cpu_ruby_ports
+sequencer=system.l1_cntrl0.sequencer
transitions_per_cycle=32
version=0
-[system.l1_cntrl0.L1DcacheMemory]
+[system.l1_cntrl0.sequencer]
+type=RubySequencer
+children=dcache icache
+dcache=system.l1_cntrl0.sequencer.dcache
+deadlock_threshold=500000
+icache=system.l1_cntrl0.sequencer.icache
+max_outstanding_requests=16
+physmem=system.physmem
+using_ruby_tester=false
+version=0
+physMemPort=system.physmem.port[0]
+port=system.cpu.icache_port system.cpu.dcache_port
+
+[system.l1_cntrl0.sequencer.dcache]
type=RubyCache
assoc=2
latency=2
@@ -146,7 +150,7 @@ replacement_policy=PSEUDO_LRU
size=256
start_index_bit=6
-[system.l1_cntrl0.L1IcacheMemory]
+[system.l1_cntrl0.sequencer.icache]
type=RubyCache
assoc=2
latency=2
@@ -184,13 +188,14 @@ latency_var=0
null=false
range=0:134217727
zero=false
-port=system.ruby.cpu_ruby_ports.physMemPort
+port=system.l1_cntrl0.sequencer.physMemPort
[system.ruby]
type=RubySystem
-children=cpu_ruby_ports network profiler tracer
+children=debug network profiler tracer
block_size_bytes=64
clock=1
+debug=system.ruby.debug
mem_size=134217728
network=system.ruby.network
no_mem_vec=false
@@ -200,18 +205,13 @@ randomization=false
stats_filename=ruby.stats
tracer=system.ruby.tracer
-[system.ruby.cpu_ruby_ports]
-type=RubySequencer
-access_phys_mem=true
-dcache=system.l1_cntrl0.L1DcacheMemory
-deadlock_threshold=500000
-icache=system.l1_cntrl0.L1IcacheMemory
-max_outstanding_requests=16
-physmem=system.physmem
-using_ruby_tester=false
-version=0
-physMemPort=system.physmem.port[0]
-port=system.cpu.icache_port system.cpu.dcache_port
+[system.ruby.debug]
+type=RubyDebug
+filter_string=none
+output_filename=none
+protocol_trace=false
+start_time=1
+verbosity_string=none
[system.ruby.network]
type=SimpleNetwork
@@ -227,9 +227,9 @@ topology=system.ruby.network.topology
[system.ruby.network.topology]
type=Topology
children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2
-description=Crossbar
ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2
int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2
+name=Crossbar
num_int_nodes=4
print_config=false
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/ruby.stats b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/ruby.stats
index 9d8b157dc..dbdcc6601 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/ruby.stats
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/ruby.stats
@@ -13,7 +13,7 @@ RubySystem config:
Network Configuration
---------------------
network: SIMPLE_NETWORK
-topology:
+topology: Crossbar
virtual_net_0: active, ordered
virtual_net_1: active, unordered
@@ -34,7 +34,7 @@ periodic_stats_period: 1000000
================ End RubySystem Configuration Print ================
-Real time: Feb/06/2011 20:27:50
+Real time: Aug/05/2010 10:43:25
Profiler Stats
--------------
@@ -43,18 +43,18 @@ Elapsed_time_in_minutes: 0
Elapsed_time_in_hours: 0
Elapsed_time_in_days: 0
-Virtual_time_in_seconds: 0.33
-Virtual_time_in_minutes: 0.0055
-Virtual_time_in_hours: 9.16667e-05
-Virtual_time_in_days: 3.81944e-06
+Virtual_time_in_seconds: 0.25
+Virtual_time_in_minutes: 0.00416667
+Virtual_time_in_hours: 6.94444e-05
+Virtual_time_in_days: 2.89352e-06
Ruby_current_time: 92099
Ruby_start_time: 0
Ruby_cycles: 92099
-mbytes_resident: 35.7734
-mbytes_total: 209.453
-resident_ratio: 0.170832
+mbytes_resident: 33.5859
+mbytes_total: 33.5938
+resident_ratio: 1
ruby_cycles_executed: [ 92100 ]
@@ -127,10 +127,10 @@ Resource Usage
page_size: 4096
user_time: 0
system_time: 0
-page_reclaims: 10358
-page_faults: 0
+page_reclaims: 7341
+page_faults: 2084
swaps: 0
-block_inputs: 16
+block_inputs: 0
block_outputs: 0
Network Stats
@@ -193,28 +193,28 @@ links_utilized_percent_switch_3: 0.205739
outgoing_messages_switch_3_link_2_Writeback_Data: 92 6624 [ 0 0 0 0 92 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_3_link_2_Writeback_Control: 402 3216 [ 0 0 0 0 402 0 0 0 0 0 ] base_latency: 1
-Cache Stats: system.l1_cntrl0.L1IcacheMemory
- system.l1_cntrl0.L1IcacheMemory_total_misses: 270
- system.l1_cntrl0.L1IcacheMemory_total_demand_misses: 270
- system.l1_cntrl0.L1IcacheMemory_total_prefetches: 0
- system.l1_cntrl0.L1IcacheMemory_total_sw_prefetches: 0
- system.l1_cntrl0.L1IcacheMemory_total_hw_prefetches: 0
+Cache Stats: system.l1_cntrl0.sequencer.icache
+ system.l1_cntrl0.sequencer.icache_total_misses: 270
+ system.l1_cntrl0.sequencer.icache_total_demand_misses: 270
+ system.l1_cntrl0.sequencer.icache_total_prefetches: 0
+ system.l1_cntrl0.sequencer.icache_total_sw_prefetches: 0
+ system.l1_cntrl0.sequencer.icache_total_hw_prefetches: 0
- system.l1_cntrl0.L1IcacheMemory_request_type_IFETCH: 100%
+ system.l1_cntrl0.sequencer.icache_request_type_IFETCH: 100%
- system.l1_cntrl0.L1IcacheMemory_access_mode_type_SupervisorMode: 270 100%
+ system.l1_cntrl0.sequencer.icache_access_mode_type_SupervisorMode: 270 100%
-Cache Stats: system.l1_cntrl0.L1DcacheMemory
- system.l1_cntrl0.L1DcacheMemory_total_misses: 243
- system.l1_cntrl0.L1DcacheMemory_total_demand_misses: 243
- system.l1_cntrl0.L1DcacheMemory_total_prefetches: 0
- system.l1_cntrl0.L1DcacheMemory_total_sw_prefetches: 0
- system.l1_cntrl0.L1DcacheMemory_total_hw_prefetches: 0
+Cache Stats: system.l1_cntrl0.sequencer.dcache
+ system.l1_cntrl0.sequencer.dcache_total_misses: 243
+ system.l1_cntrl0.sequencer.dcache_total_demand_misses: 243
+ system.l1_cntrl0.sequencer.dcache_total_prefetches: 0
+ system.l1_cntrl0.sequencer.dcache_total_sw_prefetches: 0
+ system.l1_cntrl0.sequencer.dcache_total_hw_prefetches: 0
- system.l1_cntrl0.L1DcacheMemory_request_type_LD: 74.8971%
- system.l1_cntrl0.L1DcacheMemory_request_type_ST: 25.1029%
+ system.l1_cntrl0.sequencer.dcache_request_type_LD: 74.8971%
+ system.l1_cntrl0.sequencer.dcache_request_type_ST: 25.1029%
- system.l1_cntrl0.L1DcacheMemory_access_mode_type_SupervisorMode: 243 100%
+ system.l1_cntrl0.sequencer.dcache_access_mode_type_SupervisorMode: 243 100%
--- L1Cache ---
- Event Counts -
@@ -222,7 +222,7 @@ Load [415 ] 415
Ifetch [2585 ] 2585
Store [294 ] 294
Atomic [0 ] 0
-L1_Replacement [503 ] 503
+L1_Replacement [506 ] 506
Data_Shared [18 ] 18
Data_Owner [0 ] 0
Data_All_Tokens [495 ] 495
@@ -352,7 +352,7 @@ M_W Load [47 ] 47
M_W Ifetch [1038 ] 1038
M_W Store [6 ] 6
M_W Atomic [0 ] 0
-M_W L1_Replacement [1 ] 1
+M_W L1_Replacement [4 ] 4
M_W Transient_GETX [0 ] 0
M_W Transient_Local_GETX [0 ] 0
M_W Transient_GETS [0 ] 0
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout
index aa7eff126..9cf458143 100755
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Feb 6 2011 20:27:42
-M5 revision b885adc82ab4+ 7924+ default tip qtip brad/regress_updates
-M5 started Feb 6 2011 20:27:50
-M5 executing on SC2B0617
+M5 compiled Aug 5 2010 10:41:36
+M5 revision 1cd2a169499f+ 7535+ default brad/hammer_merge_gets qtip tip
+M5 started Aug 5 2010 10:43:25
+M5 executing on svvint09
command line: build/ALPHA_SE_MOESI_CMP_token/m5.fast -d build/ALPHA_SE_MOESI_CMP_token/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_token -re tests/run.py build/ALPHA_SE_MOESI_CMP_token/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_token
Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt
index e986a3c8f..e8b218502 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt
@@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 45706 # Simulator instruction rate (inst/s)
-host_mem_usage 214484 # Number of bytes of host memory used
+host_inst_rate 42948 # Simulator instruction rate (inst/s)
+host_mem_usage 211392 # Number of bytes of host memory used
host_seconds 0.06 # Real time elapsed on the host
-host_tick_rate 1628169 # Simulator tick rate (ticks/s)
+host_tick_rate 1534907 # Simulator tick rate (ticks/s)
sim_freq 1000000000 # Frequency of simulated ticks
sim_insts 2577 # Number of instructions simulated
sim_seconds 0.000092 # Number of seconds simulated
@@ -43,24 +43,8 @@ system.cpu.itb.write_hits 0 # DT
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 92099 # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.num_busy_cycles 92099 # Number of busy cycles
-system.cpu.num_conditional_control_insts 238 # number of instructions that are conditional controls
-system.cpu.num_fp_alu_accesses 6 # Number of float alu accesses
-system.cpu.num_fp_insts 6 # number of float instructions
-system.cpu.num_fp_register_reads 6 # number of times the floating registers were read
-system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
-system.cpu.num_func_calls 140 # number of times a function call or return occured
-system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_insts 2577 # Number of instructions executed
-system.cpu.num_int_alu_accesses 2375 # Number of integer alu accesses
-system.cpu.num_int_insts 2375 # number of integer instructions
-system.cpu.num_int_register_reads 2998 # number of times the integer registers were read
-system.cpu.num_int_register_writes 1768 # number of times the integer registers were written
-system.cpu.num_load_insts 419 # Number of load instructions
-system.cpu.num_mem_refs 717 # number of memory refs
-system.cpu.num_store_insts 298 # Number of store instructions
+system.cpu.num_refs 717 # Number of memory references
system.cpu.workload.PROG:num_syscalls 4 # Number of system calls
---------- End Simulation Statistics ----------