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authorBrad Beckmann <Brad.Beckmann@amd.com>2011-02-08 18:07:54 -0800
committerBrad Beckmann <Brad.Beckmann@amd.com>2011-02-08 18:07:54 -0800
commit4eab18fd063fe80203751b6b058ea232e402d879 (patch)
treec6a57820ea7aeb7da4f1d66776720f9c2ae7f7d3 /tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token
parentea9d4c3a97b1570a3b30d2fd538514b53ac54944 (diff)
downloadgem5-4eab18fd063fe80203751b6b058ea232e402d879.tar.xz
regess: protocol regression tester updates
Diffstat (limited to 'tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token')
-rw-r--r--tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini68
-rw-r--r--tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/ruby.stats60
-rwxr-xr-xtests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout8
-rw-r--r--tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt24
4 files changed, 88 insertions, 72 deletions
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini
index 1971d2a44..537819260 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini
@@ -1,13 +1,22 @@
[root]
type=Root
children=system
-dummy=0
+time_sync_enable=false
+time_sync_period=100000000
+time_sync_spin_threshold=100000
[system]
type=System
children=cpu dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby
mem_mode=timing
physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
[system.cpu]
type=TimingSimpleCPU
@@ -32,8 +41,8 @@ progress_interval=0
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
-dcache_port=system.l1_cntrl0.sequencer.port[1]
-icache_port=system.l1_cntrl0.sequencer.port[0]
+dcache_port=system.ruby.cpu_ruby_ports.port[1]
+icache_port=system.ruby.cpu_ruby_ports.port[0]
[system.cpu.dtb]
type=AlphaTLB
@@ -54,7 +63,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=tests/test-progs/hello/bin/alpha/tru64/hello
+executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/tru64/hello
gid=100
input=cin
max_stack_size=67108864
@@ -111,9 +120,9 @@ version=0
[system.l1_cntrl0]
type=L1Cache_Controller
-children=sequencer
-L1DcacheMemory=system.l1_cntrl0.sequencer.dcache
-L1IcacheMemory=system.l1_cntrl0.sequencer.icache
+children=L1DcacheMemory L1IcacheMemory
+L1DcacheMemory=system.l1_cntrl0.L1DcacheMemory
+L1IcacheMemory=system.l1_cntrl0.L1IcacheMemory
N_tokens=2
buffer_size=0
dynamic_timeout_enabled=true
@@ -125,24 +134,11 @@ no_mig_atomic=true
number_of_TBEs=256
recycle_latency=10
retry_threshold=1
-sequencer=system.l1_cntrl0.sequencer
+sequencer=system.ruby.cpu_ruby_ports
transitions_per_cycle=32
version=0
-[system.l1_cntrl0.sequencer]
-type=RubySequencer
-children=dcache icache
-dcache=system.l1_cntrl0.sequencer.dcache
-deadlock_threshold=500000
-icache=system.l1_cntrl0.sequencer.icache
-max_outstanding_requests=16
-physmem=system.physmem
-using_ruby_tester=false
-version=0
-physMemPort=system.physmem.port[0]
-port=system.cpu.icache_port system.cpu.dcache_port
-
-[system.l1_cntrl0.sequencer.dcache]
+[system.l1_cntrl0.L1DcacheMemory]
type=RubyCache
assoc=2
latency=2
@@ -150,7 +146,7 @@ replacement_policy=PSEUDO_LRU
size=256
start_index_bit=6
-[system.l1_cntrl0.sequencer.icache]
+[system.l1_cntrl0.L1IcacheMemory]
type=RubyCache
assoc=2
latency=2
@@ -188,14 +184,13 @@ latency_var=0
null=false
range=0:134217727
zero=false
-port=system.l1_cntrl0.sequencer.physMemPort
+port=system.ruby.cpu_ruby_ports.physMemPort
[system.ruby]
type=RubySystem
-children=debug network profiler tracer
+children=cpu_ruby_ports network profiler tracer
block_size_bytes=64
clock=1
-debug=system.ruby.debug
mem_size=134217728
network=system.ruby.network
no_mem_vec=false
@@ -205,13 +200,18 @@ randomization=false
stats_filename=ruby.stats
tracer=system.ruby.tracer
-[system.ruby.debug]
-type=RubyDebug
-filter_string=none
-output_filename=none
-protocol_trace=false
-start_time=1
-verbosity_string=none
+[system.ruby.cpu_ruby_ports]
+type=RubySequencer
+access_phys_mem=true
+dcache=system.l1_cntrl0.L1DcacheMemory
+deadlock_threshold=500000
+icache=system.l1_cntrl0.L1IcacheMemory
+max_outstanding_requests=16
+physmem=system.physmem
+using_ruby_tester=false
+version=0
+physMemPort=system.physmem.port[0]
+port=system.cpu.icache_port system.cpu.dcache_port
[system.ruby.network]
type=SimpleNetwork
@@ -227,9 +227,9 @@ topology=system.ruby.network.topology
[system.ruby.network.topology]
type=Topology
children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2
+description=Crossbar
ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2
int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2
-name=Crossbar
num_int_nodes=4
print_config=false
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/ruby.stats b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/ruby.stats
index dbdcc6601..23d0a1d6f 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/ruby.stats
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/ruby.stats
@@ -13,7 +13,7 @@ RubySystem config:
Network Configuration
---------------------
network: SIMPLE_NETWORK
-topology: Crossbar
+topology:
virtual_net_0: active, ordered
virtual_net_1: active, unordered
@@ -34,7 +34,7 @@ periodic_stats_period: 1000000
================ End RubySystem Configuration Print ================
-Real time: Aug/05/2010 10:43:25
+Real time: Feb/08/2011 17:51:05
Profiler Stats
--------------
@@ -43,18 +43,18 @@ Elapsed_time_in_minutes: 0
Elapsed_time_in_hours: 0
Elapsed_time_in_days: 0
-Virtual_time_in_seconds: 0.25
-Virtual_time_in_minutes: 0.00416667
-Virtual_time_in_hours: 6.94444e-05
-Virtual_time_in_days: 2.89352e-06
+Virtual_time_in_seconds: 0.33
+Virtual_time_in_minutes: 0.0055
+Virtual_time_in_hours: 9.16667e-05
+Virtual_time_in_days: 3.81944e-06
Ruby_current_time: 92099
Ruby_start_time: 0
Ruby_cycles: 92099
-mbytes_resident: 33.5859
-mbytes_total: 33.5938
-resident_ratio: 1
+mbytes_resident: 35.7695
+mbytes_total: 209.457
+resident_ratio: 0.17081
ruby_cycles_executed: [ 92100 ]
@@ -127,8 +127,8 @@ Resource Usage
page_size: 4096
user_time: 0
system_time: 0
-page_reclaims: 7341
-page_faults: 2084
+page_reclaims: 10334
+page_faults: 0
swaps: 0
block_inputs: 0
block_outputs: 0
@@ -193,28 +193,28 @@ links_utilized_percent_switch_3: 0.205739
outgoing_messages_switch_3_link_2_Writeback_Data: 92 6624 [ 0 0 0 0 92 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_3_link_2_Writeback_Control: 402 3216 [ 0 0 0 0 402 0 0 0 0 0 ] base_latency: 1
-Cache Stats: system.l1_cntrl0.sequencer.icache
- system.l1_cntrl0.sequencer.icache_total_misses: 270
- system.l1_cntrl0.sequencer.icache_total_demand_misses: 270
- system.l1_cntrl0.sequencer.icache_total_prefetches: 0
- system.l1_cntrl0.sequencer.icache_total_sw_prefetches: 0
- system.l1_cntrl0.sequencer.icache_total_hw_prefetches: 0
+Cache Stats: system.l1_cntrl0.L1IcacheMemory
+ system.l1_cntrl0.L1IcacheMemory_total_misses: 270
+ system.l1_cntrl0.L1IcacheMemory_total_demand_misses: 270
+ system.l1_cntrl0.L1IcacheMemory_total_prefetches: 0
+ system.l1_cntrl0.L1IcacheMemory_total_sw_prefetches: 0
+ system.l1_cntrl0.L1IcacheMemory_total_hw_prefetches: 0
- system.l1_cntrl0.sequencer.icache_request_type_IFETCH: 100%
+ system.l1_cntrl0.L1IcacheMemory_request_type_IFETCH: 100%
- system.l1_cntrl0.sequencer.icache_access_mode_type_SupervisorMode: 270 100%
+ system.l1_cntrl0.L1IcacheMemory_access_mode_type_SupervisorMode: 270 100%
-Cache Stats: system.l1_cntrl0.sequencer.dcache
- system.l1_cntrl0.sequencer.dcache_total_misses: 243
- system.l1_cntrl0.sequencer.dcache_total_demand_misses: 243
- system.l1_cntrl0.sequencer.dcache_total_prefetches: 0
- system.l1_cntrl0.sequencer.dcache_total_sw_prefetches: 0
- system.l1_cntrl0.sequencer.dcache_total_hw_prefetches: 0
+Cache Stats: system.l1_cntrl0.L1DcacheMemory
+ system.l1_cntrl0.L1DcacheMemory_total_misses: 243
+ system.l1_cntrl0.L1DcacheMemory_total_demand_misses: 243
+ system.l1_cntrl0.L1DcacheMemory_total_prefetches: 0
+ system.l1_cntrl0.L1DcacheMemory_total_sw_prefetches: 0
+ system.l1_cntrl0.L1DcacheMemory_total_hw_prefetches: 0
- system.l1_cntrl0.sequencer.dcache_request_type_LD: 74.8971%
- system.l1_cntrl0.sequencer.dcache_request_type_ST: 25.1029%
+ system.l1_cntrl0.L1DcacheMemory_request_type_LD: 74.8971%
+ system.l1_cntrl0.L1DcacheMemory_request_type_ST: 25.1029%
- system.l1_cntrl0.sequencer.dcache_access_mode_type_SupervisorMode: 243 100%
+ system.l1_cntrl0.L1DcacheMemory_access_mode_type_SupervisorMode: 243 100%
--- L1Cache ---
- Event Counts -
@@ -222,7 +222,7 @@ Load [415 ] 415
Ifetch [2585 ] 2585
Store [294 ] 294
Atomic [0 ] 0
-L1_Replacement [506 ] 506
+L1_Replacement [503 ] 503
Data_Shared [18 ] 18
Data_Owner [0 ] 0
Data_All_Tokens [495 ] 495
@@ -352,7 +352,7 @@ M_W Load [47 ] 47
M_W Ifetch [1038 ] 1038
M_W Store [6 ] 6
M_W Atomic [0 ] 0
-M_W L1_Replacement [4 ] 4
+M_W L1_Replacement [1 ] 1
M_W Transient_GETX [0 ] 0
M_W Transient_Local_GETX [0 ] 0
M_W Transient_GETS [0 ] 0
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout
index 9cf458143..f29df4a71 100755
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Aug 5 2010 10:41:36
-M5 revision 1cd2a169499f+ 7535+ default brad/hammer_merge_gets qtip tip
-M5 started Aug 5 2010 10:43:25
-M5 executing on svvint09
+M5 compiled Feb 8 2011 17:50:56
+M5 revision 685719afafe6+ 7938+ default tip brad/increase_ruby_mem_test_threshold qtip
+M5 started Feb 8 2011 17:51:05
+M5 executing on SC2B0617
command line: build/ALPHA_SE_MOESI_CMP_token/m5.fast -d build/ALPHA_SE_MOESI_CMP_token/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_token -re tests/run.py build/ALPHA_SE_MOESI_CMP_token/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_token
Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt
index e8b218502..caef5b8f0 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt
@@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 42948 # Simulator instruction rate (inst/s)
-host_mem_usage 211392 # Number of bytes of host memory used
+host_inst_rate 44139 # Simulator instruction rate (inst/s)
+host_mem_usage 214488 # Number of bytes of host memory used
host_seconds 0.06 # Real time elapsed on the host
-host_tick_rate 1534907 # Simulator tick rate (ticks/s)
+host_tick_rate 1572917 # Simulator tick rate (ticks/s)
sim_freq 1000000000 # Frequency of simulated ticks
sim_insts 2577 # Number of instructions simulated
sim_seconds 0.000092 # Number of seconds simulated
@@ -43,8 +43,24 @@ system.cpu.itb.write_hits 0 # DT
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 92099 # number of cpu cycles simulated
+system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu.num_busy_cycles 92099 # Number of busy cycles
+system.cpu.num_conditional_control_insts 238 # number of instructions that are conditional controls
+system.cpu.num_fp_alu_accesses 6 # Number of float alu accesses
+system.cpu.num_fp_insts 6 # number of float instructions
+system.cpu.num_fp_register_reads 6 # number of times the floating registers were read
+system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
+system.cpu.num_func_calls 140 # number of times a function call or return occured
+system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_insts 2577 # Number of instructions executed
-system.cpu.num_refs 717 # Number of memory references
+system.cpu.num_int_alu_accesses 2375 # Number of integer alu accesses
+system.cpu.num_int_insts 2375 # number of integer instructions
+system.cpu.num_int_register_reads 2998 # number of times the integer registers were read
+system.cpu.num_int_register_writes 1768 # number of times the integer registers were written
+system.cpu.num_load_insts 419 # Number of load instructions
+system.cpu.num_mem_refs 717 # number of memory refs
+system.cpu.num_store_insts 298 # Number of store instructions
system.cpu.workload.PROG:num_syscalls 4 # Number of system calls
---------- End Simulation Statistics ----------