m5: Regression Tester Update

This patch includes the necessary regression updates to test the new ruby
configuration system.  The patch includes support for multiple ruby protocols
and adds the ruby random tester.  The patch removes atomic mode test for
ruby since ruby does not support atomic mode acceses.  These tests can be
added back in when ruby supports atomic mode for real.

--HG--
rename : tests/quick/50.memtest/test.py => tests/quick/60.rubytest/test.py

5 files changed, 327 insertions, 326 deletions

diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini
index b899a165e..4c150fde0 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini
@@ -5,15 +5,15 @@ dummy=0
 
 [system]
 type=System
-children=cpu membus physmem
-mem_mode=atomic
+children=cpu physmem ruby
+mem_mode=timing
 physmem=system.physmem
 
 [system.cpu]
 type=TimingSimpleCPU
 children=dtb itb tracer workload
 checker=Null
-clock=500
+clock=1
 cpu_id=0
 defer_registration=false
 do_checkpoint_insts=true
@@ -32,8 +32,8 @@ progress_interval=0
 system=system
 tracer=system.cpu.tracer
 workload=system.cpu.workload
-dcache_port=system.membus.port[2]
-icache_port=system.membus.port[1]
+dcache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[1]
+icache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[0]
 
 [system.cpu.dtb]
 type=AlphaTLB
@@ -54,7 +54,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello
+executable=tests/test-progs/hello/bin/alpha/tru64/hello
 gid=100
 input=cin
 max_stack_size=67108864
@@ -65,30 +65,169 @@ simpoint=0
 system=system
 uid=100
 
-[system.membus]
-type=Bus
-block_size=64
-bus_id=0
-clock=1000
-header_cycles=1
-responder_set=false
-width=64
-port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
-
 [system.physmem]
-type=RubyMemory
-clock=1
-config_file=build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby/ruby.config
-debug=false
-debug_file=ruby.debug
+type=PhysicalMemory
 file=
-latency=30000
+latency=30
 latency_var=0
 null=false
-num_cpus=1
-phase=0
 range=0:134217727
-stats_file=ruby.stats
 zero=false
-port=system.membus.port[0]
+port=system.ruby.network.topology.ext_links0.ext_node.sequencer.physMemPort
+
+[system.ruby]
+type=RubySystem
+children=debug network profiler tracer
+block_size_bytes=64
+clock=1
+debug=system.ruby.debug
+mem_size=134217728
+network=system.ruby.network
+profiler=system.ruby.profiler
+random_seed=1234
+randomization=false
+stats_filename=ruby.stats
+tracer=system.ruby.tracer
+
+[system.ruby.debug]
+type=RubyDebug
+filter_string=none
+output_filename=none
+protocol_trace=false
+start_time=1
+verbosity_string=none
+
+[system.ruby.network]
+type=SimpleNetwork
+children=topology
+adaptive_routing=true
+buffer_size=0
+control_msg_size=8
+endpoint_bandwidth=10000
+link_latency=1
+number_of_virtual_networks=10
+topology=system.ruby.network.topology
+
+[system.ruby.network.topology]
+type=Topology
+children=ext_links0 ext_links1 int_links0 int_links1
+ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1
+int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1
+num_int_nodes=3
+print_config=false
+
+[system.ruby.network.topology.ext_links0]
+type=ExtLink
+children=ext_node
+bw_multiplier=64
+ext_node=system.ruby.network.topology.ext_links0.ext_node
+int_node=0
+latency=1
+weight=1
+
+[system.ruby.network.topology.ext_links0.ext_node]
+type=L1Cache_Controller
+children=sequencer
+buffer_size=0
+cacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
+cache_response_latency=12
+issue_latency=2
+number_of_TBEs=256
+recycle_latency=10
+sequencer=system.ruby.network.topology.ext_links0.ext_node.sequencer
+transitions_per_cycle=32
+version=0
+
+[system.ruby.network.topology.ext_links0.ext_node.sequencer]
+type=RubySequencer
+children=icache
+dcache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
+deadlock_threshold=500000
+icache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
+max_outstanding_requests=16
+physmem=system.physmem
+using_ruby_tester=false
+version=0
+physMemPort=system.physmem.port[0]
+port=system.cpu.icache_port system.cpu.dcache_port
+
+[system.ruby.network.topology.ext_links0.ext_node.sequencer.icache]
+type=RubyCache
+assoc=2
+latency=3
+replacement_policy=PSEUDO_LRU
+size=256
+
+[system.ruby.network.topology.ext_links1]
+type=ExtLink
+children=ext_node
+bw_multiplier=64
+ext_node=system.ruby.network.topology.ext_links1.ext_node
+int_node=1
+latency=1
+weight=1
+
+[system.ruby.network.topology.ext_links1.ext_node]
+type=Directory_Controller
+children=directory memBuffer
+buffer_size=0
+directory=system.ruby.network.topology.ext_links1.ext_node.directory
+directory_latency=12
+memBuffer=system.ruby.network.topology.ext_links1.ext_node.memBuffer
+number_of_TBEs=256
+recycle_latency=10
+transitions_per_cycle=32
+version=0
+
+[system.ruby.network.topology.ext_links1.ext_node.directory]
+type=RubyDirectoryMemory
+size=134217728
+version=0
+
+[system.ruby.network.topology.ext_links1.ext_node.memBuffer]
+type=RubyMemoryControl
+bank_bit_0=8
+bank_busy_time=11
+bank_queue_size=12
+banks_per_rank=8
+basic_bus_busy_time=2
+dimm_bit_0=12
+dimms_per_channel=2
+mem_bus_cycle_multiplier=10
+mem_ctl_latency=12
+mem_fixed_delay=0
+mem_random_arbitrate=0
+rank_bit_0=11
+rank_rank_delay=1
+ranks_per_dimm=2
+read_write_delay=2
+refresh_period=1560
+tFaw=0
+version=0
+
+[system.ruby.network.topology.int_links0]
+type=IntLink
+bw_multiplier=16
+latency=1
+node_a=0
+node_b=2
+weight=1
+
+[system.ruby.network.topology.int_links1]
+type=IntLink
+bw_multiplier=16
+latency=1
+node_a=1
+node_b=2
+weight=1
+
+[system.ruby.profiler]
+type=RubyProfiler
+all_instructions=false
+hot_lines=false
+num_of_sequencers=1
+
+[system.ruby.tracer]
+type=RubyTracer
+warmup_length=100000
 
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/ruby.stats b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/ruby.stats
index 9133c865e..edd5bdfcc 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/ruby.stats
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/ruby.stats
@@ -2,73 +2,18 @@
 ================ Begin RubySystem Configuration Print ================
 
 RubySystem config:
-  random_seed: 752800
+  random_seed: 1234
   randomization: 0
-  tech_nm: 45
-  freq_mhz: 3000
+  cycle_period: 1
   block_size_bytes: 64
   block_size_bits: 6
-  memory_size_bytes: 1073741824
-  memory_size_bits: 30
-DMA_Controller config: DMAController_0
-  version: 0
-  buffer_size: 32
-  dma_sequencer: DMASequencer_0
-  number_of_TBEs: 128
-  transitions_per_cycle: 32
-Directory_Controller config: DirectoryController_0
-  version: 0
-  buffer_size: 32
-  directory_latency: 6
-  directory_name: DirectoryMemory_0
-  memory_controller_name: MemoryControl_0
-  memory_latency: 158
-  number_of_TBEs: 128
-  recycle_latency: 10
-  to_mem_ctrl_latency: 1
-  transitions_per_cycle: 32
-L1Cache_Controller config: L1CacheController_0
-  version: 0
-  buffer_size: 32
-  cache: l1u_0
-  cache_response_latency: 12
-  issue_latency: 2
-  number_of_TBEs: 128
-  sequencer: Sequencer_0
-  transitions_per_cycle: 32
-Cache config: l1u_0
-  controller: L1CacheController_0
-  cache_associativity: 8
-  num_cache_sets_bits: 2
-  num_cache_sets: 4
-  cache_set_size_bytes: 256
-  cache_set_size_Kbytes: 0.25
-  cache_set_size_Mbytes: 0.000244141
-  cache_size_bytes: 2048
-  cache_size_Kbytes: 2
-  cache_size_Mbytes: 0.00195312
-DirectoryMemory Global Config: 
-  number of directory memories: 1
-  total memory size bytes: 1073741824
-  total memory size bits: 30
-DirectoryMemory module config: DirectoryMemory_0
-  controller: DirectoryController_0
-  version: 0
-  memory_bits: 30
-  memory_size_bytes: 1073741824
-  memory_size_Kbytes: 1.04858e+06
-  memory_size_Mbytes: 1024
-  memory_size_Gbytes: 1
-Seqeuncer config: Sequencer_0
-  controller: L1CacheController_0
-  version: 0
-  max_outstanding_requests: 16
-  deadlock_threshold: 500000
+  memory_size_bytes: 134217728
+  memory_size_bits: 27
 
 Network Configuration
 ---------------------
 network: SIMPLE_NETWORK
-topology: theTopology
+topology: 
 
 virtual_net_0: active, ordered
 virtual_net_1: active, ordered
@@ -76,25 +21,11 @@ virtual_net_2: active, ordered
 virtual_net_3: inactive
 virtual_net_4: active, ordered
 virtual_net_5: active, ordered
+virtual_net_6: inactive
+virtual_net_7: inactive
+virtual_net_8: inactive
+virtual_net_9: inactive
 
---- Begin Topology Print ---
-
-Topology print ONLY indicates the _NETWORK_ latency between two machines
-It does NOT include the latency within the machines
-
-L1Cache-0 Network Latencies
-  L1Cache-0 -> Directory-0 net_lat: 7
-  L1Cache-0 -> DMA-0 net_lat: 7
-
-Directory-0 Network Latencies
-  Directory-0 -> L1Cache-0 net_lat: 7
-  Directory-0 -> DMA-0 net_lat: 7
-
-DMA-0 Network Latencies
-  DMA-0 -> L1Cache-0 net_lat: 7
-  DMA-0 -> Directory-0 net_lat: 7
-
---- End Topology Print ---
 
 Profiler Configuration
 ----------------------
@@ -103,132 +34,61 @@ periodic_stats_period: 1000000
 ================ End RubySystem Configuration Print ================
 
 
-Real time: Jul/06/2009 11:11:07
+Real time: Jan/28/2010 10:26:06
 
 Profiler Stats
 --------------
-Elapsed_time_in_seconds: 1
-Elapsed_time_in_minutes: 0.0166667
-Elapsed_time_in_hours: 0.000277778
-Elapsed_time_in_days: 1.15741e-05
+Elapsed_time_in_seconds: 0
+Elapsed_time_in_minutes: 0
+Elapsed_time_in_hours: 0
+Elapsed_time_in_days: 0
 
-Virtual_time_in_seconds: 0.44
-Virtual_time_in_minutes: 0.00733333
-Virtual_time_in_hours:   0.000122222
-Virtual_time_in_days:    0.000122222
+Virtual_time_in_seconds: 0.25
+Virtual_time_in_minutes: 0.00416667
+Virtual_time_in_hours:   6.94444e-05
+Virtual_time_in_days:    2.89352e-06
 
-Ruby_current_time: 9880001
-Ruby_start_time: 1
-Ruby_cycles: 9880000
+Ruby_current_time: 123378
+Ruby_start_time: 0
+Ruby_cycles: 123378
 
-mbytes_resident: 143.812
-mbytes_total: 1328.75
-resident_ratio: 0.108234
+mbytes_resident: 32.8828
+mbytes_total: 32.8906
+resident_ratio: 1
 
 Total_misses: 0
 total_misses: 0 [ 0 ]
 user_misses: 0 [ 0 ]
 supervisor_misses: 0 [ 0 ]
 
-instruction_executed: 1 [ 1 ]
-ruby_cycles_executed: 9880001 [ 9880001 ]
-cycles_per_instruction: 9.88e+06 [ 9.88e+06 ]
-misses_per_thousand_instructions: 0 [ 0 ]
+ruby_cycles_executed: 123379 [ 123379 ]
 
 transactions_started: 0 [ 0 ]
 transactions_ended: 0 [ 0 ]
-instructions_per_transaction: 0 [ 0 ]
 cycles_per_transaction: 0 [ 0 ]
 misses_per_transaction: 0 [ 0 ]
 
-L1D_cache cache stats: 
-  L1D_cache_total_misses: 0
-  L1D_cache_total_demand_misses: 0
-  L1D_cache_total_prefetches: 0
-  L1D_cache_total_sw_prefetches: 0
-  L1D_cache_total_hw_prefetches: 0
-  L1D_cache_misses_per_transaction: 0
-  L1D_cache_misses_per_instruction: 0
-  L1D_cache_instructions_per_misses: NaN
-
-  L1D_cache_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-
-L1I_cache cache stats: 
-  L1I_cache_total_misses: 0
-  L1I_cache_total_demand_misses: 0
-  L1I_cache_total_prefetches: 0
-  L1I_cache_total_sw_prefetches: 0
-  L1I_cache_total_hw_prefetches: 0
-  L1I_cache_misses_per_transaction: 0
-  L1I_cache_misses_per_instruction: 0
-  L1I_cache_instructions_per_misses: NaN
-
-  L1I_cache_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-
-L2_cache cache stats: 
-  L2_cache_total_misses: 0
-  L2_cache_total_demand_misses: 0
-  L2_cache_total_prefetches: 0
-  L2_cache_total_sw_prefetches: 0
-  L2_cache_total_hw_prefetches: 0
-  L2_cache_misses_per_transaction: 0
-  L2_cache_misses_per_instruction: 0
-  L2_cache_instructions_per_misses: NaN
-
-  L2_cache_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-
-
-Memory control:
-  memory_total_requests: 658
-  memory_reads: 345
-  memory_writes: 313
-  memory_refreshes: 6486
-  memory_total_request_delays: 795
-  memory_delays_per_request: 1.20821
-  memory_delays_in_input_queue: 313
-  memory_delays_behind_head_of_bank_queue: 1
-  memory_delays_stalled_at_head_of_bank_queue: 481
-  memory_stalls_for_bank_busy: 108
-  memory_stalls_for_random_busy: 0
-  memory_stalls_for_anti_starvation: 0
-  memory_stalls_for_arbitration: 30
-  memory_stalls_for_bus: 335
-  memory_stalls_for_tfaw: 0
-  memory_stalls_for_read_write_turnaround: 8
-  memory_stalls_for_read_read_turnaround: 0
-  accesses_per_bank: 29  14  0  38  34  30  44  23  10  6  5  8  28  46  21  6  8  7  10  16  20  17  20  51  22  10  10  22  18  28  15  42  
 
 Busy Controller Counts:
 L1Cache-0:0  
 Directory-0:0  
-DMA-0:0  
+
 
 Busy Bank Count:0
 
-L1TBE_usage: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-L2TBE_usage: [binsize: 1 max: 1 count: 658 average: 0.475684 | standard deviation: 0.50114 | 345 313 ]
-StopTable_usage: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-sequencer_requests_outstanding: [binsize: 1 max: 1 count: 3294 average:     1 | standard deviation: 0 | 0 3294 ]
-store_buffer_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-unique_blocks_in_store_buffer: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+sequencer_requests_outstanding: [binsize: 1 max: 1 count: 3295 average:     1 | standard deviation: 0 | 0 3295 ]
 
 All Non-Zero Cycle Demand Cache Accesses
 ----------------------------------------
-miss_latency: [binsize: 2 max: 280 count: 3294 average: 19.8021 | standard deviation: 52.3549 | 0 2949 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 28 0 0 0 0 4 0 0 0 0 283 0 0 0 0 7 0 0 0 0 12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 7 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_1: [binsize: 2 max: 280 count: 2585 average: 15.4932 | standard deviation: 46.2081 | 0 2380 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 13 0 0 0 0 3 0 0 0 0 169 0 0 0 0 6 0 0 0 0 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 3 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_2: [binsize: 2 max: 270 count: 415 average: 44.4916 | standard deviation: 74.7872 | 0 312 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 0 0 0 0 0 0 0 0 0 86 0 0 0 0 1 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_3: [binsize: 1 max: 190 count: 294 average: 22.8367 | standard deviation: 55.1047 | 0 0 257 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 28 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 ]
-miss_latency_L2Miss: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+miss_latency: [binsize: 2 max: 375 count: 3294 average: 36.4554 | standard deviation: 69.7725 | 0 2668 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 0 0 0 3 1 1 4 2 101 88 63 177 126 0 1 1 8 0 2 1 1 4 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7 4 5 13 2 0 0 0 1 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 ]
+miss_latency_1: [binsize: 2 max: 375 count: 2585 average: 23.1702 | standard deviation: 56.4841 | 0 2288 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 2 0 0 2 2 31 53 29 71 82 0 1 0 5 0 1 1 1 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 2 1 3 2 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
+miss_latency_2: [binsize: 2 max: 281 count: 415 average: 107.304 | standard deviation: 88.8453 | 0 170 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 0 2 0 56 24 27 75 32 0 0 1 3 0 1 0 0 2 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 0 4 7 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_3: [binsize: 2 max: 265 count: 294 average: 53.2585 | standard deviation: 80.456 | 0 210 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 14 11 7 31 12 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
 
 All Non-Zero Cycle SW Prefetch Requests
 ------------------------------------
 prefetch_latency: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
 prefetch_latency_L2Miss:[binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-multicast_retries: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-gets_mask_prediction_count: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-getx_mask_prediction_count: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-explicit_training_mask: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-
 Request vs. RubySystem State Profile
 --------------------------------
 
@@ -237,104 +97,159 @@ filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN
 
 Message Delayed Cycles
 ----------------------
-Total_delay_cycles: [binsize: 1 max: 0 count: 658 average:     0 | standard deviation: 0 | 658 ]
-Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 658 average:     0 | standard deviation: 0 | 658 ]
+Total_delay_cycles: [binsize: 1 max: 0 count: 1248 average:     0 | standard deviation: 0 | 1248 ]
+Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 1248 average:     0 | standard deviation: 0 | 1248 ]
   virtual_network_0_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-  virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 345 average:     0 | standard deviation: 0 | 345 ]
-  virtual_network_2_delay_cycles: [binsize: 1 max: 0 count: 313 average:     0 | standard deviation: 0 | 313 ]
+  virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 626 average:     0 | standard deviation: 0 | 626 ]
+  virtual_network_2_delay_cycles: [binsize: 1 max: 0 count: 622 average:     0 | standard deviation: 0 | 622 ]
   virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
   virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
   virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+  virtual_network_6_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+  virtual_network_7_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+  virtual_network_8_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+  virtual_network_9_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
 
 Resource Usage
 --------------
 page_size: 4096
 user_time: 0
 system_time: 0
-page_reclaims: 37575
-page_faults: 0
+page_reclaims: 7118
+page_faults: 2103
 swaps: 0
-block_inputs: 8
-block_outputs: 48
+block_inputs: 0
+block_outputs: 0
 
 Network Stats
 -------------
 
 switch_0_inlinks: 2
 switch_0_outlinks: 2
-links_utilized_percent_switch_0: 0.000208122
-  links_utilized_percent_switch_0_link_0: 8.3249e-05 bw: 640000 base_latency: 1
-  links_utilized_percent_switch_0_link_1: 0.000332996 bw: 160000 base_latency: 1
+links_utilized_percent_switch_0: 0.157808
+  links_utilized_percent_switch_0_link_0: 0.0633825 bw: 640000 base_latency: 1
+  links_utilized_percent_switch_0_link_1: 0.252233 bw: 160000 base_latency: 1
 
-  outgoing_messages_switch_0_link_0_Response_Data: 345 2760 [ 0 345 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_0_link_0_Writeback_Control: 313 2504 [ 0 0 313 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_0_link_1_Control: 345 2760 [ 345 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_0_link_1_Data: 313 2504 [ 313 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_0_Response_Data: 626 45072 [ 0 626 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_0_Writeback_Control: 622 4976 [ 0 0 622 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_1_Control: 626 5008 [ 626 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_1_Data: 622 44784 [ 622 0 0 0 0 0 0 0 0 0 ] base_latency: 1
 
 switch_1_inlinks: 2
 switch_1_outlinks: 2
-links_utilized_percent_switch_1: 0.000208122
-  links_utilized_percent_switch_1_link_0: 8.3249e-05 bw: 640000 base_latency: 1
-  links_utilized_percent_switch_1_link_1: 0.000332996 bw: 160000 base_latency: 1
+links_utilized_percent_switch_1: 0.158294
+  links_utilized_percent_switch_1_link_0: 0.0630582 bw: 640000 base_latency: 1
+  links_utilized_percent_switch_1_link_1: 0.25353 bw: 160000 base_latency: 1
 
-  outgoing_messages_switch_1_link_0_Control: 345 2760 [ 345 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_1_link_0_Data: 313 2504 [ 313 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_1_link_1_Response_Data: 345 2760 [ 0 345 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_1_link_1_Writeback_Control: 313 2504 [ 0 0 313 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_0_Control: 626 5008 [ 626 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_0_Data: 622 44784 [ 622 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_1_Response_Data: 626 45072 [ 0 626 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_1_Writeback_Control: 622 4976 [ 0 0 622 0 0 0 0 0 0 0 ] base_latency: 1
 
 switch_2_inlinks: 2
 switch_2_outlinks: 2
-links_utilized_percent_switch_2: 0
-  links_utilized_percent_switch_2_link_0: 0 bw: 640000 base_latency: 1
-  links_utilized_percent_switch_2_link_1: 0 bw: 160000 base_latency: 1
-
-
-switch_3_inlinks: 3
-switch_3_outlinks: 3
-links_utilized_percent_switch_3: 0.000221997
-  links_utilized_percent_switch_3_link_0: 0.000332996 bw: 160000 base_latency: 1
-  links_utilized_percent_switch_3_link_1: 0.000332996 bw: 160000 base_latency: 1
-  links_utilized_percent_switch_3_link_2: 0 bw: 160000 base_latency: 1
-
-  outgoing_messages_switch_3_link_0_Response_Data: 345 2760 [ 0 345 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_3_link_0_Writeback_Control: 313 2504 [ 0 0 313 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_3_link_1_Control: 345 2760 [ 345 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_3_link_1_Data: 313 2504 [ 313 0 0 0 0 0 ] base_latency: 1
-
- --- DMA ---
+links_utilized_percent_switch_2: 0.252881
+  links_utilized_percent_switch_2_link_0: 0.25353 bw: 160000 base_latency: 1
+  links_utilized_percent_switch_2_link_1: 0.252233 bw: 160000 base_latency: 1
+
+  outgoing_messages_switch_2_link_0_Response_Data: 626 45072 [ 0 626 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_0_Writeback_Control: 622 4976 [ 0 0 622 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_1_Control: 626 5008 [ 626 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_1_Data: 622 44784 [ 622 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+
+Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
+  system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_misses: 626
+  system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_demand_misses: 626
+  system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_prefetches: 0
+  system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_sw_prefetches: 0
+  system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_hw_prefetches: 0
+  system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_misses_per_transaction: inf
+
+  system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_type_LD:   39.1374%
+  system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_type_ST:   13.4185%
+  system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_type_IFETCH:   47.4441%
+
+  system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_access_mode_type_SupervisorMode:   626    100%
+  system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_size: [binsize: 1 max: 8 count: 626 average: 5.71885 | standard deviation: 1.98192 | 0 0 0 0 357 0 0 0 269 ]
+
+ --- L1Cache 0 ---
  - Event Counts -
-ReadRequest  0
-WriteRequest  0
-Data  0
-Ack  0
+Load  415
+Ifetch  2585
+Store  294
+Data  626
+Fwd_GETX  0
+Inv  0
+Replacement  622
+Writeback_Ack  622
+Writeback_Nack  0
 
  - Transitions -
-READY  ReadRequest  0 <-- 
-READY  WriteRequest  0 <-- 
+I  Load  245
+I  Ifetch  297
+I  Store  84
+I  Inv  0 <-- 
+I  Replacement  0 <-- 
 
-BUSY_RD  Data  0 <-- 
+II  Writeback_Nack  0 <-- 
 
-BUSY_WR  Ack  0 <-- 
+M  Load  170
+M  Ifetch  2288
+M  Store  210
+M  Fwd_GETX  0 <-- 
+M  Inv  0 <-- 
+M  Replacement  622
+
+MI  Fwd_GETX  0 <-- 
+MI  Inv  0 <-- 
+MI  Writeback_Ack  622
+MI  Writeback_Nack  0 <-- 
+
+MII  Fwd_GETX  0 <-- 
+
+IS  Data  542
+
+IM  Data  84
+
+Memory controller: system.ruby.network.topology.ext_links1.ext_node.memBuffer:
+  memory_total_requests: 1248
+  memory_reads: 626
+  memory_writes: 622
+  memory_refreshes: 258
+  memory_total_request_delays: 1710
+  memory_delays_per_request: 1.37019
+  memory_delays_in_input_queue: 622
+  memory_delays_behind_head_of_bank_queue: 3
+  memory_delays_stalled_at_head_of_bank_queue: 1085
+  memory_stalls_for_bank_busy: 404
+  memory_stalls_for_random_busy: 0
+  memory_stalls_for_anti_starvation: 0
+  memory_stalls_for_arbitration: 39
+  memory_stalls_for_bus: 620
+  memory_stalls_for_tfaw: 0
+  memory_stalls_for_read_write_turnaround: 22
+  memory_stalls_for_read_read_turnaround: 0
+  accesses_per_bank: 55  40  0  100  42  42  88  45  14  10  14  10  46  82  38  6  22  14  14  48  20  52  26  92  34  10  12  24  28  44  38  138  
 
- --- Directory ---
+ --- Directory 0 ---
  - Event Counts -
-GETX  345
+GETX  626
 GETS  0
-PUTX  313
+PUTX  622
 PUTX_NotOwner  0
 DMA_READ  0
 DMA_WRITE  0
-Memory_Data  345
-Memory_Ack  313
+Memory_Data  626
+Memory_Ack  622
 
  - Transitions -
-I  GETX  345
+I  GETX  626
 I  PUTX_NotOwner  0 <-- 
 I  DMA_READ  0 <-- 
 I  DMA_WRITE  0 <-- 
 
 M  GETX  0 <-- 
-M  PUTX  313
+M  PUTX  622
 M  PUTX_NotOwner  0 <-- 
 M  DMA_READ  0 <-- 
 M  DMA_WRITE  0 <-- 
@@ -345,15 +260,19 @@ M_DRD  PUTX  0 <--
 M_DWR  GETX  0 <-- 
 M_DWR  PUTX  0 <-- 
 
+M_DWRI  GETX  0 <-- 
 M_DWRI  Memory_Ack  0 <-- 
 
+M_DRDI  GETX  0 <-- 
+M_DRDI  Memory_Ack  0 <-- 
+
 IM  GETX  0 <-- 
 IM  GETS  0 <-- 
 IM  PUTX  0 <-- 
 IM  PUTX_NotOwner  0 <-- 
 IM  DMA_READ  0 <-- 
 IM  DMA_WRITE  0 <-- 
-IM  Memory_Data  345
+IM  Memory_Data  626
 
 MI  GETX  0 <-- 
 MI  GETS  0 <-- 
@@ -361,7 +280,7 @@ MI  PUTX  0 <--
 MI  PUTX_NotOwner  0 <-- 
 MI  DMA_READ  0 <-- 
 MI  DMA_WRITE  0 <-- 
-MI  Memory_Ack  313
+MI  Memory_Ack  622
 
 ID  GETX  0 <-- 
 ID  GETS  0 <-- 
@@ -379,39 +298,3 @@ ID_W  DMA_READ  0 <--
 ID_W  DMA_WRITE  0 <-- 
 ID_W  Memory_Ack  0 <-- 
 
- --- L1Cache ---
- - Event Counts -
-Load  415
-Ifetch  2585
-Store  294
-Data  345
-Fwd_GETX  0
-Inv  0
-Replacement  313
-Writeback_Ack  313
-Writeback_Nack  0
-
- - Transitions -
-I  Load  103
-I  Ifetch  205
-I  Store  37
-I  Inv  0 <-- 
-I  Replacement  0 <-- 
-
-II  Writeback_Nack  0 <-- 
-
-M  Load  312
-M  Ifetch  2380
-M  Store  257
-M  Fwd_GETX  0 <-- 
-M  Inv  0 <-- 
-M  Replacement  313
-
-MI  Fwd_GETX  0 <-- 
-MI  Inv  0 <-- 
-MI  Writeback_Ack  313
-
-IS  Data  308
-
-IM  Data  37
-
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/simerr b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/simerr
index 7c60b79b0..67f69f09d 100755
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/simerr
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/simerr
@@ -1,25 +1,5 @@
-["-r", "tests/configs/../../src/mem/ruby/config/MI_example-homogeneous.rb", "-p", "1", "-m", "1", "-s", "1024"]
-print config: 1
-Creating new MessageBuffer for 0 0
-Creating new MessageBuffer for 0 1
-Creating new MessageBuffer for 0 2
-Creating new MessageBuffer for 0 3
-Creating new MessageBuffer for 0 4
-Creating new MessageBuffer for 0 5
-Creating new MessageBuffer for 1 0
-Creating new MessageBuffer for 1 1
-Creating new MessageBuffer for 1 2
-Creating new MessageBuffer for 1 3
-Creating new MessageBuffer for 1 4
-Creating new MessageBuffer for 1 5
-Creating new MessageBuffer for 2 0
-Creating new MessageBuffer for 2 1
-Creating new MessageBuffer for 2 2
-Creating new MessageBuffer for 2 3
-Creating new MessageBuffer for 2 4
-Creating new MessageBuffer for 2 5
 warn: Sockets disabled, not accepting gdb connections
 For more information see: http://www.m5sim.org/warn/d946bea6
-warn: ignoring syscall sigprocmask(1, 18446744073709547831, ...)
+warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
 hack: be nice to actually delete the event here
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/simout b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/simout
index 9101498fd..994f7ec2d 100755
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/simout
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/simout
@@ -5,14 +5,13 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Jul  6 2009 11:03:45
-M5 revision d3635cac686a 6289 default ruby_refs.diff qtip tip
-M5 started Jul  6 2009 11:11:06
-M5 executing on maize
+M5 compiled Jan 27 2010 22:23:20
+M5 revision 6068d4fc30d3+ 6931+ default qtip tip brad/rubycfg_regress_udpate
+M5 started Jan 28 2010 10:26:06
+M5 executing on svvint07
 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby
-Global frequency set at 1000000000000 ticks per second
-  Debug: Adding to filter: 'q' (Queue)
+Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
 Hello world!
-Exiting @ tick 9880000 because target called exit()
+Exiting @ tick 123378 because target called exit()
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt
index a0d03e79c..dd60f4239 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt
@@ -1,13 +1,13 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                   7760                       # Simulator instruction rate (inst/s)
-host_mem_usage                                1360644                       # Number of bytes of host memory used
-host_seconds                                     0.33                       # Real time elapsed on the host
-host_tick_rate                               29737002                       # Simulator tick rate (ticks/s)
-sim_freq                                 1000000000000                       # Frequency of simulated ticks
+host_inst_rate                                  51538                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 214632                       # Number of bytes of host memory used
+host_seconds                                     0.05                       # Real time elapsed on the host
+host_tick_rate                                2467461                       # Simulator tick rate (ticks/s)
+sim_freq                                   1000000000                       # Frequency of simulated ticks
 sim_insts                                        2577                       # Number of instructions simulated
-sim_seconds                                  0.000010                       # Number of seconds simulated
-sim_ticks                                     9880000                       # Number of ticks simulated
+sim_seconds                                  0.000123                       # Number of seconds simulated
+sim_ticks                                      123378                       # Number of ticks simulated
 system.cpu.dtb.data_accesses                      717                       # DTB accesses
 system.cpu.dtb.data_acv                             0                       # DTB access violations
 system.cpu.dtb.data_hits                          709                       # DTB hits
@@ -42,7 +42,7 @@ system.cpu.itb.write_acv                            0                       # DT
 system.cpu.itb.write_hits                           0                       # DTB write hits
 system.cpu.itb.write_misses                         0                       # DTB write misses
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.numCycles                            19760                       # number of cpu cycles simulated
+system.cpu.numCycles                           123378                       # number of cpu cycles simulated
 system.cpu.num_insts                             2577                       # Number of instructions executed
 system.cpu.num_refs                               717                       # Number of memory references
 system.cpu.workload.PROG:num_syscalls               4                       # Number of system calls