diff options
| author | Steve Reinhardt <stever@gmail.com> | 2007-08-03 18:04:30 -0400 |
|---|---|---|
| committer | Steve Reinhardt <stever@gmail.com> | 2007-08-03 18:04:30 -0400 |
| commit | bb3f7dc83b9a4c7b20aeb893fea447854c855225 (patch) | |
| tree | 17d17b775e1155fa42725df488ddd22a3ce65af8 /tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini | |
| parent | 851e3c852be4eb031293ed271502a0e14ca9273f (diff) | |
| download | gem5-bb3f7dc83b9a4c7b20aeb893fea447854c855225.tar.xz | |
tests: new ref outputs for new cache model
--HG--
extra : convert_revision : 244749072f97e425c2ca1cf296f2b95f37e99eb6
Diffstat (limited to 'tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini')
| -rw-r--r-- | tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini | 24 |
1 files changed, 8 insertions, 16 deletions
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini index 5a336ab13..a9adf07b9 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini @@ -11,7 +11,7 @@ physmem=system.physmem [system.cpu] type=TimingSimpleCPU -children=dcache icache l2cache toL2Bus workload +children=dcache icache l2cache toL2Bus tracer workload clock=500 cpu_id=0 defer_registration=false @@ -24,17 +24,16 @@ max_loads_any_thread=0 phase=0 progress_interval=0 system=system +tracer=system.cpu.tracer workload=system.cpu.workload dcache_port=system.cpu.dcache.cpu_side icache_port=system.cpu.icache.cpu_side [system.cpu.dcache] type=BaseCache -adaptive_compression=false +addr_range=0:18446744073709551615 assoc=2 block_size=64 -compressed_bus=false -compression_latency=0 hash_delay=1 latency=1000 lifo=false @@ -52,12 +51,10 @@ prefetch_serial_squash=false prefetch_use_cpu_id=true prefetcher_size=100 prioritizeRequests=false -protocol=Null repl=Null size=262144 split=false split_size=0 -store_compressed=false subblock_size=0 tgts_per_mshr=5 trace_addr=0 @@ -68,11 +65,9 @@ mem_side=system.cpu.toL2Bus.port[1] [system.cpu.icache] type=BaseCache -adaptive_compression=false +addr_range=0:18446744073709551615 assoc=2 block_size=64 -compressed_bus=false -compression_latency=0 hash_delay=1 latency=1000 lifo=false @@ -90,12 +85,10 @@ prefetch_serial_squash=false prefetch_use_cpu_id=true prefetcher_size=100 prioritizeRequests=false -protocol=Null repl=Null size=131072 split=false split_size=0 -store_compressed=false subblock_size=0 tgts_per_mshr=5 trace_addr=0 @@ -106,11 +99,9 @@ mem_side=system.cpu.toL2Bus.port[0] [system.cpu.l2cache] type=BaseCache -adaptive_compression=false +addr_range=0:18446744073709551615 assoc=2 block_size=64 -compressed_bus=false -compression_latency=0 hash_delay=1 latency=10000 lifo=false @@ -128,12 +119,10 @@ prefetch_serial_squash=false prefetch_use_cpu_id=true prefetcher_size=100 prioritizeRequests=false -protocol=Null repl=Null size=2097152 split=false split_size=0 -store_compressed=false subblock_size=0 tgts_per_mshr=5 trace_addr=0 @@ -151,6 +140,9 @@ responder_set=false width=64 port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side +[system.cpu.tracer] +type=ExeTracer + [system.cpu.workload] type=LiveProcess cmd=hello |