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| author | Nathan Binkert <binkertn@umich.edu> | 2007-06-12 07:56:53 -0700 |
|---|---|---|
| committer | Nathan Binkert <binkertn@umich.edu> | 2007-06-12 07:56:53 -0700 |
| commit | 1a3e668446e4b2d2c61651c9ae58e643c2aa3ad2 (patch) | |
| tree | c1a0811248e7d8addf4e84d3532e5d506e8aaec8 /tests/quick/00.hello/ref/alpha/tru64/simple-timing | |
| parent | 125237d357be7f2c5adf03da8dcf352ccad32954 (diff) | |
| download | gem5-1a3e668446e4b2d2c61651c9ae58e643c2aa3ad2.tar.xz | |
update for small parameter and statistics name changes
--HG--
extra : convert_revision : d538b79986c11a462ab285c167cef45dd793da32
Diffstat (limited to 'tests/quick/00.hello/ref/alpha/tru64/simple-timing')
4 files changed, 14 insertions, 15 deletions
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini index 1c1daa355..5a336ab13 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini @@ -44,7 +44,7 @@ prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 -prefetch_latency=10 +prefetch_latency=10000 prefetch_miss=false prefetch_past_page=false prefetch_policy=none @@ -82,7 +82,7 @@ prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 -prefetch_latency=10 +prefetch_latency=10000 prefetch_miss=false prefetch_past_page=false prefetch_policy=none @@ -120,7 +120,7 @@ prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 -prefetch_latency=10 +prefetch_latency=100000 prefetch_miss=false prefetch_past_page=false prefetch_policy=none @@ -174,7 +174,7 @@ bus_id=0 clock=1000 responder_set=false width=64 -port=system.physmem.port system.cpu.l2cache.mem_side +port=system.physmem.port[0] system.cpu.l2cache.mem_side [system.physmem] type=PhysicalMemory diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.out b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.out index 45a8521ac..241630ead 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.out +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.out @@ -94,7 +94,7 @@ prefetch_access=false prefetcher_size=100 prefetch_past_page=false prefetch_serial_squash=false -prefetch_latency=10 +prefetch_latency=10000 prefetch_degree=1 prefetch_policy=none prefetch_cache_check_push=true @@ -131,7 +131,7 @@ prefetch_access=false prefetcher_size=100 prefetch_past_page=false prefetch_serial_squash=false -prefetch_latency=10 +prefetch_latency=10000 prefetch_degree=1 prefetch_policy=none prefetch_cache_check_push=true @@ -168,7 +168,7 @@ prefetch_access=false prefetcher_size=100 prefetch_past_page=false prefetch_serial_squash=false -prefetch_latency=10 +prefetch_latency=100000 prefetch_degree=1 prefetch_policy=none prefetch_cache_check_push=true diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt index 756244d02..621520fa3 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt @@ -1,9 +1,8 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 228404 # Simulator instruction rate (inst/s) -host_mem_usage 153176 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host -host_tick_rate 552831639 # Simulator tick rate (ticks/s) +host_inst_rate 51133 # Simulator instruction rate (inst/s) +host_seconds 0.05 # Real time elapsed on the host +host_tick_rate 127514531 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 2578 # Number of instructions simulated sim_seconds 0.000006 # Number of seconds simulated diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout index f5e3a6008..1c6780cf0 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout @@ -6,9 +6,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled May 14 2007 16:35:50 -M5 started Tue May 15 12:18:42 2007 -M5 executing on zizzer.eecs.umich.edu -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-timing tests/run.py quick/00.hello/alpha/tru64/simple-timing +M5 compiled Jun 10 2007 14:06:20 +M5 started Sun Jun 10 14:22:37 2007 +M5 executing on iceaxe +command line: /Users/nate/build/outgoing/build/ALPHA_SE/m5.debug -d /Users/nate/build/outgoing/build/ALPHA_SE/tests/debug/quick/00.hello/alpha/tru64/simple-timing tests/run.py quick/00.hello/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second Exiting @ tick 6472000 because target called exit() |