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| author | Steve Reinhardt <stever@eecs.umich.edu> | 2006-09-05 16:24:47 -0400 |
|---|---|---|
| committer | Steve Reinhardt <stever@eecs.umich.edu> | 2006-09-05 16:24:47 -0400 |
| commit | 6c7a490c2b779ea45adfc5708f50aa16718582e4 (patch) | |
| tree | 3633153645f9f885e8155ba740ef7aaa1a221650 /tests/quick/00.hello/ref/alpha/tru64/simple-timing | |
| parent | 89f0bc9e4c6e1c0bc58f5f5a88cdac5889758b1f (diff) | |
| download | gem5-6c7a490c2b779ea45adfc5708f50aa16718582e4.tar.xz | |
Update reference config.ini files to include port mappings.
--HG--
extra : convert_revision : f9e91a60fa09b707d2a26be57f265b7ab1c07263
Diffstat (limited to 'tests/quick/00.hello/ref/alpha/tru64/simple-timing')
3 files changed, 17 insertions, 6 deletions
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini index 5f05f07dd..e833d841e 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini @@ -66,6 +66,8 @@ max_loads_any_thread=0 mem=system.cpu.dcache system=system workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side [system.cpu.dcache] type=BaseCache @@ -104,6 +106,8 @@ tgts_per_mshr=5 trace_addr=0 two_queue=false write_buffers=8 +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.port[1] [system.cpu.icache] type=BaseCache @@ -142,6 +146,8 @@ tgts_per_mshr=5 trace_addr=0 two_queue=false write_buffers=8 +cpu_side=system.cpu.icache_port +mem_side=system.cpu.toL2Bus.port[0] [system.cpu.l2cache] type=BaseCache @@ -180,10 +186,13 @@ tgts_per_mshr=5 trace_addr=0 two_queue=false write_buffers=8 +cpu_side=system.cpu.toL2Bus.port[2] +mem_side=system.membus.port[1] [system.cpu.toL2Bus] type=Bus bus_id=0 +port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side [system.cpu.workload] type=LiveProcess @@ -197,12 +206,14 @@ system=system [system.membus] type=Bus bus_id=0 +port=system.physmem.port system.cpu.l2cache.mem_side [system.physmem] type=PhysicalMemory file= latency=1 range=0:134217727 +port=system.membus.port[0] [trace] bufsize=0 diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt index ee76bf8d8..47bcc1b3c 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 5953 # Simulator instruction rate (inst/s) -host_mem_usage 159132 # Number of bytes of host memory used -host_seconds 0.43 # Real time elapsed on the host -host_tick_rate 8713 # Simulator tick rate (ticks/s) +host_inst_rate 73626 # Simulator instruction rate (inst/s) +host_mem_usage 159128 # Number of bytes of host memory used +host_seconds 0.04 # Real time elapsed on the host +host_tick_rate 106590 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 2578 # Number of instructions simulated sim_seconds 0.000000 # Number of seconds simulated diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout index f4d7a3959..4a02e57f0 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout @@ -6,8 +6,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 21 2006 14:18:48 -M5 started Mon Aug 21 14:19:22 2006 +M5 compiled Sep 5 2006 15:28:48 +M5 started Tue Sep 5 15:42:18 2006 M5 executing on zizzer.eecs.umich.edu command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/simple-timing tests/run.py quick/00.hello/alpha/tru64/simple-timing Exiting @ tick 3777 because target called exit() |