Stats: Update the stats.

--HG--
extra : convert_revision : 888b6e3bcd432a9318d4b8741a8b274c6f37f1a8

3 files changed, 58 insertions, 32 deletions

diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini
index f8e125ea1..48fcc2b94 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini
@@ -11,12 +11,14 @@ physmem=system.physmem
 
 [system.cpu]
 type=TimingSimpleCPU
-children=dcache icache l2cache toL2Bus tracer workload
+children=dcache dtb icache itb l2cache toL2Bus tracer workload
 clock=500
 cpu_id=0
 defer_registration=false
+dtb=system.cpu.dtb
 function_trace=false
 function_trace_start=0
+itb=system.cpu.itb
 max_insts_all_threads=0
 max_insts_any_thread=0
 max_loads_all_threads=0
@@ -65,6 +67,10 @@ write_buffers=8
 cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.port[1]
 
+[system.cpu.dtb]
+type=AlphaDTB
+size=64
+
 [system.cpu.icache]
 type=BaseCache
 addr_range=0:18446744073709551615
@@ -101,6 +107,10 @@ write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.port[0]
 
+[system.cpu.itb]
+type=AlphaITB
+size=48
+
 [system.cpu.l2cache]
 type=BaseCache
 addr_range=0:18446744073709551615
@@ -156,7 +166,7 @@ cwd=
 egid=100
 env=
 euid=100
-executable=tests/test-progs/hello/bin/alpha/tru64/hello
+executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello
 gid=100
 input=cin
 output=cout
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt
index 23e886f55..942cc1b79 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt
@@ -1,13 +1,13 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 196854                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 195480                       # Number of bytes of host memory used
-host_seconds                                     0.01                       # Real time elapsed on the host
-host_tick_rate                              706389035                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 123219                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 178996                       # Number of bytes of host memory used
+host_seconds                                     0.02                       # Real time elapsed on the host
+host_tick_rate                              443932267                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-sim_insts                                        2578                       # Number of instructions simulated
+sim_insts                                        2577                       # Number of instructions simulated
 sim_seconds                                  0.000009                       # Number of seconds simulated
-sim_ticks                                     9431000                       # Number of ticks simulated
+sim_ticks                                     9438000                       # Number of ticks simulated
 system.cpu.dcache.ReadReq_accesses                415                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_avg_miss_latency        25000                       # average ReadReq miss latency
 system.cpu.dcache.ReadReq_avg_mshr_miss_latency        23000                       # average ReadReq mshr miss latency
@@ -76,53 +76,65 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss            0
 system.cpu.dcache.replacements                      0                       # number of replacements
 system.cpu.dcache.sampled_refs                     82                       # Sample count of references to valid blocks.
 system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse                 48.863963                       # Cycle average of tags in use
+system.cpu.dcache.tagsinuse                 48.838317                       # Cycle average of tags in use
 system.cpu.dcache.total_refs                      627                       # Total number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.dcache.writebacks                        0                       # number of writebacks
-system.cpu.icache.ReadReq_accesses               2579                       # number of ReadReq accesses(hits+misses)
+system.cpu.dtb.accesses                           717                       # DTB accesses
+system.cpu.dtb.acv                                  0                       # DTB access violations
+system.cpu.dtb.hits                               709                       # DTB hits
+system.cpu.dtb.misses                               8                       # DTB misses
+system.cpu.dtb.read_accesses                      419                       # DTB read accesses
+system.cpu.dtb.read_acv                             0                       # DTB read access violations
+system.cpu.dtb.read_hits                          415                       # DTB read hits
+system.cpu.dtb.read_misses                          4                       # DTB read misses
+system.cpu.dtb.write_accesses                     298                       # DTB write accesses
+system.cpu.dtb.write_acv                            0                       # DTB write access violations
+system.cpu.dtb.write_hits                         294                       # DTB write hits
+system.cpu.dtb.write_misses                         4                       # DTB write misses
+system.cpu.icache.ReadReq_accesses               2586                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_avg_miss_latency        25000                       # average ReadReq miss latency
 system.cpu.icache.ReadReq_avg_mshr_miss_latency        23000                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits                   2416                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits                   2423                       # number of ReadReq hits
 system.cpu.icache.ReadReq_miss_latency        4075000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate          0.063203                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate          0.063032                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_misses                  163                       # number of ReadReq misses
 system.cpu.icache.ReadReq_mshr_miss_latency      3749000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate     0.063203                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate     0.063032                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_misses             163                       # number of ReadReq MSHR misses
 system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
-system.cpu.icache.avg_refs                  14.822086                       # Average number of references to valid blocks.
+system.cpu.icache.avg_refs                  14.865031                       # Average number of references to valid blocks.
 system.cpu.icache.blocked_no_mshrs                  0                       # number of cycles access was blocked
 system.cpu.icache.blocked_no_targets                0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles_no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.demand_accesses                2579                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses                2586                       # number of demand (read+write) accesses
 system.cpu.icache.demand_avg_miss_latency        25000                       # average overall miss latency
 system.cpu.icache.demand_avg_mshr_miss_latency        23000                       # average overall mshr miss latency
-system.cpu.icache.demand_hits                    2416                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits                    2423                       # number of demand (read+write) hits
 system.cpu.icache.demand_miss_latency         4075000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate           0.063203                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate           0.063032                       # miss rate for demand accesses
 system.cpu.icache.demand_misses                   163                       # number of demand (read+write) misses
 system.cpu.icache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
 system.cpu.icache.demand_mshr_miss_latency      3749000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate      0.063203                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate      0.063032                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_misses              163                       # number of demand (read+write) MSHR misses
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.overall_accesses               2579                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses               2586                       # number of overall (read+write) accesses
 system.cpu.icache.overall_avg_miss_latency        25000                       # average overall miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency        23000                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits                   2416                       # number of overall hits
+system.cpu.icache.overall_hits                   2423                       # number of overall hits
 system.cpu.icache.overall_miss_latency        4075000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_rate          0.063203                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate          0.063032                       # miss rate for overall accesses
 system.cpu.icache.overall_misses                  163                       # number of overall misses
 system.cpu.icache.overall_mshr_hits                 0                       # number of overall MSHR hits
 system.cpu.icache.overall_mshr_miss_latency      3749000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate     0.063203                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate     0.063032                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_misses             163                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
@@ -138,11 +150,15 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss            0
 system.cpu.icache.replacements                      0                       # number of replacements
 system.cpu.icache.sampled_refs                    163                       # Sample count of references to valid blocks.
 system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse                 83.443652                       # Cycle average of tags in use
-system.cpu.icache.total_refs                     2416                       # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse                 83.395749                       # Cycle average of tags in use
+system.cpu.icache.total_refs                     2423                       # Total number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.writebacks                        0                       # number of writebacks
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
+system.cpu.itb.accesses                          2597                       # ITB accesses
+system.cpu.itb.acv                                  0                       # ITB acv
+system.cpu.itb.hits                              2586                       # ITB hits
+system.cpu.itb.misses                              11                       # ITB misses
 system.cpu.l2cache.ReadExReq_accesses              27                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_avg_miss_latency        22000                       # average ReadExReq miss latency
 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency        11000                       # average ReadExReq mshr miss latency
@@ -218,14 +234,14 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss            0
 system.cpu.l2cache.replacements                     0                       # number of replacements
 system.cpu.l2cache.sampled_refs                   207                       # Sample count of references to valid blocks.
 system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse               106.620093                       # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse               106.559981                       # Cycle average of tags in use
 system.cpu.l2cache.total_refs                       0                       # Total number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
 system.cpu.l2cache.writebacks                       0                       # number of writebacks
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.numCycles                          9431000                       # number of cpu cycles simulated
-system.cpu.num_insts                             2578                       # Number of instructions executed
-system.cpu.num_refs                               710                       # Number of memory references
+system.cpu.numCycles                          9438000                       # number of cpu cycles simulated
+system.cpu.num_insts                             2577                       # Number of instructions executed
+system.cpu.num_refs                               717                       # Number of memory references
 system.cpu.workload.PROG:num_syscalls               4                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout
index eb8910969..8d08b94be 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout
@@ -6,9 +6,9 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Aug 12 2007 00:26:55
-M5 started Sun Aug 12 00:29:42 2007
-M5 executing on zeep
+M5 compiled Aug 14 2007 17:58:14
+M5 started Tue Aug 14 17:59:08 2007
+M5 executing on nacho
 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-timing tests/run.py quick/00.hello/alpha/tru64/simple-timing
 Global frequency set at 1000000000000 ticks per second
-Exiting @ tick 9431000 because target called exit()
+Exiting @ tick 9438000 because target called exit()