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authorLisa Hsu <hsul@eecs.umich.edu>2008-11-06 11:11:42 -0500
committerLisa Hsu <hsul@eecs.umich.edu>2008-11-06 11:11:42 -0500
commitddd179a4189d6f51f7be81567e1119aa67533dae (patch)
tree647c2b6b5a7a947e07c0639bd41b2df8fe3dd99e /tests/quick/00.hello/ref/alpha/tru64/simple-timing
parent46b56bb7b6ac2a5f069aa1f79279f46d0395eb15 (diff)
downloadgem5-ddd179a4189d6f51f7be81567e1119aa67533dae.tar.xz
Reference updates. Since split cache is gone, a lot of config.ini changes, and minor changes to stats that are likely due to the decoupling of insertions/evictions in the cache.
Diffstat (limited to 'tests/quick/00.hello/ref/alpha/tru64/simple-timing')
-rw-r--r--tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini9
-rw-r--r--tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt8
-rwxr-xr-xtests/quick/00.hello/ref/alpha/tru64/simple-timing/stderr2
-rwxr-xr-xtests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout11
4 files changed, 11 insertions, 19 deletions
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini
index bfcd95204..6a2eadca9 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini
@@ -40,7 +40,6 @@ block_size=64
cpu_side_filter_ranges=
hash_delay=1
latency=1000
-lifo=false
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
@@ -58,8 +57,6 @@ prefetcher_size=100
prioritizeRequests=false
repl=Null
size=262144
-split=false
-split_size=0
subblock_size=0
tgts_per_mshr=5
trace_addr=0
@@ -80,7 +77,6 @@ block_size=64
cpu_side_filter_ranges=
hash_delay=1
latency=1000
-lifo=false
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
@@ -98,8 +94,6 @@ prefetcher_size=100
prioritizeRequests=false
repl=Null
size=131072
-split=false
-split_size=0
subblock_size=0
tgts_per_mshr=5
trace_addr=0
@@ -120,7 +114,6 @@ block_size=64
cpu_side_filter_ranges=
hash_delay=1
latency=10000
-lifo=false
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
@@ -138,8 +131,6 @@ prefetcher_size=100
prioritizeRequests=false
repl=Null
size=2097152
-split=false
-split_size=0
subblock_size=0
tgts_per_mshr=5
trace_addr=0
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt
index ae6876b28..5e0dacddf 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt
@@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 96492 # Simulator instruction rate (inst/s)
-host_mem_usage 196528 # Number of bytes of host memory used
-host_seconds 0.03 # Real time elapsed on the host
-host_tick_rate 644436202 # Simulator tick rate (ticks/s)
+host_inst_rate 251832 # Simulator instruction rate (inst/s)
+host_mem_usage 197320 # Number of bytes of host memory used
+host_seconds 0.01 # Real time elapsed on the host
+host_tick_rate 1657349995 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 2577 # Number of instructions simulated
sim_seconds 0.000017 # Number of seconds simulated
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stderr b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stderr
index 8c3c8342e..28251ddf8 100755
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stderr
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stderr
@@ -1,4 +1,4 @@
warn: Sockets disabled, not accepting gdb connections
-warn: Entering event queue @ 0. Starting simulation...
warn: Increasing stack size by one page.
warn: ignoring syscall sigprocmask(1, 18446744073709547831, ...)
+warn: be nice to actually delete the event here
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout
index 1cedfe45b..5af4e5b77 100755
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout
@@ -5,12 +5,13 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Sep 27 2008 21:08:21
-M5 revision 5571:7f81bb1690686883c5b93e8343068a001faf5083
-M5 commit date Sat Sep 27 21:03:50 2008 -0700
-M5 started Sep 27 2008 21:08:24
-M5 executing on piton
+M5 compiled Nov 5 2008 18:30:06
+M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69
+M5 commit date Wed Nov 05 16:19:17 2008 -0500
+M5 started Nov 5 2008 19:15:17
+M5 executing on zizzer
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py quick/00.hello/alpha/tru64/simple-timing
Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
Hello world!
Exiting @ tick 17374000 because target called exit()