diff options
| author | Gabe Black <gblack@eecs.umich.edu> | 2008-02-26 02:20:40 -0500 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2008-02-26 02:20:40 -0500 |
| commit | 8833b4cd44457d50b45a4dfe642cdb5e51c0889d (patch) | |
| tree | 64417a9e2d759dc367848de4b7ee117b3903dc54 /tests/quick/00.hello/ref/alpha/tru64 | |
| parent | ec1a4cbbc73ecc1d7456d11c571c425e226a7d3b (diff) | |
| download | gem5-8833b4cd44457d50b45a4dfe642cdb5e51c0889d.tar.xz | |
Bus: Update the stats for the recent bus fix.
--HG--
extra : convert_revision : dc29f7b5e6fa30a50305193cb0e5aed942f7e407
Diffstat (limited to 'tests/quick/00.hello/ref/alpha/tru64')
8 files changed, 282 insertions, 276 deletions
diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini index dd05152f0..26f63e7be 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini @@ -354,6 +354,7 @@ type=Bus block_size=64 bus_id=0 clock=1000 +header_cycles=1 responder_set=false width=64 port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side @@ -383,6 +384,7 @@ type=Bus block_size=64 bus_id=0 clock=1000 +header_cycles=1 responder_set=false width=64 port=system.physmem.port[0] system.cpu.l2cache.mem_side diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt index dbf983746..a5a67b31d 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt @@ -1,40 +1,40 @@ ---------- Begin Simulation Statistics ---------- global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 156 # Number of BTB hits -global.BPredUnit.BTBLookups 642 # Number of BTB lookups -global.BPredUnit.RASInCorrect 35 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 213 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 401 # Number of conditional branches predicted -global.BPredUnit.lookups 824 # Number of BP lookups -global.BPredUnit.usedRAS 163 # Number of times the RAS was used to get a target. -host_inst_rate 1500 # Simulator instruction rate (inst/s) -host_mem_usage 151288 # Number of bytes of host memory used -host_seconds 1.59 # Real time elapsed on the host -host_tick_rate 1513804 # Simulator tick rate (ticks/s) +global.BPredUnit.BTBHits 155 # Number of BTB hits +global.BPredUnit.BTBLookups 639 # Number of BTB lookups +global.BPredUnit.RASInCorrect 34 # Number of incorrect RAS predictions. +global.BPredUnit.condIncorrect 209 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 405 # Number of conditional branches predicted +global.BPredUnit.lookups 821 # Number of BP lookups +global.BPredUnit.usedRAS 162 # Number of times the RAS was used to get a target. +host_inst_rate 34209 # Simulator instruction rate (inst/s) +host_mem_usage 193660 # Number of bytes of host memory used +host_seconds 0.07 # Real time elapsed on the host +host_tick_rate 38614456 # Simulator tick rate (ticks/s) memdepunit.memDep.conflictingLoads 7 # Number of conflicting loads. memdepunit.memDep.conflictingStores 7 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 698 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 412 # Number of stores inserted to the mem dependence unit. +memdepunit.memDep.insertedLoads 703 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 408 # Number of stores inserted to the mem dependence unit. sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 2387 # Number of instructions simulated -sim_seconds 0.000002 # Number of seconds simulated -sim_ticks 2410000 # Number of ticks simulated +sim_seconds 0.000003 # Number of seconds simulated +sim_ticks 2700000 # Number of ticks simulated system.cpu.commit.COM:branches 396 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 32 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 39 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 4452 +system.cpu.commit.COM:committed_per_cycle.samples 4866 system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 3491 7841.42% - 1 256 575.02% - 2 341 765.95% - 3 140 314.47% - 4 70 157.23% - 5 70 157.23% - 6 32 71.88% - 7 20 44.92% - 8 32 71.88% + 0 3922 8060.01% + 1 255 524.04% + 2 327 672.01% + 3 133 273.33% + 4 67 137.69% + 5 70 143.86% + 6 33 67.82% + 7 20 41.10% + 8 39 80.15% system.cpu.commit.COM:committed_per_cycle.max_value 8 system.cpu.commit.COM:committed_per_cycle.end_dist @@ -43,69 +43,69 @@ system.cpu.commit.COM:loads 415 # Nu system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 709 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 132 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 131 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 2576 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 4 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 1380 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 1414 # The number of squashed insts skipped by commit system.cpu.committedInsts 2387 # Number of Instructions Simulated system.cpu.committedInsts_total 2387 # Number of Instructions Simulated -system.cpu.cpi 2.019690 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.019690 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 528 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 8639.344262 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 5655.737705 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 467 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 527000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.115530 # miss rate for ReadReq accesses +system.cpu.cpi 2.262673 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.262673 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 531 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 11663.934426 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7311.475410 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 470 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 711500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.114878 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 61 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 10 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 345000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.115530 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_hits 11 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 446000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.114878 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 61 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 240 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 18297.297297 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 5986.486486 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 203 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 677000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.154167 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_accesses 230 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 26567.567568 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 7662.162162 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 193 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 983000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.160870 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 37 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 54 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 221500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.154167 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_hits 64 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 283500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.160870 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 37 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 8.035294 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 7.952941 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 768 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 12285.714286 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 5780.612245 # average overall mshr miss latency -system.cpu.dcache.demand_hits 670 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 1204000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.127604 # miss rate for demand accesses +system.cpu.dcache.demand_accesses 761 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 17290.816327 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 7443.877551 # average overall mshr miss latency +system.cpu.dcache.demand_hits 663 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 1694500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.128778 # miss rate for demand accesses system.cpu.dcache.demand_misses 98 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 64 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 566500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.127604 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_hits 75 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 729500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.128778 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 98 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 768 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 12285.714286 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 5780.612245 # average overall mshr miss latency +system.cpu.dcache.overall_accesses 761 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 17290.816327 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 7443.877551 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 670 # number of overall hits -system.cpu.dcache.overall_miss_latency 1204000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.127604 # miss rate for overall accesses +system.cpu.dcache.overall_hits 663 # number of overall hits +system.cpu.dcache.overall_miss_latency 1694500 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.128778 # miss rate for overall accesses system.cpu.dcache.overall_misses 98 # number of overall misses -system.cpu.dcache.overall_mshr_hits 64 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 566500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.127604 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_hits 75 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 729500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.128778 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 98 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses @@ -121,100 +121,100 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 85 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 47.072215 # Cycle average of tags in use -system.cpu.dcache.total_refs 683 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 46.627422 # Cycle average of tags in use +system.cpu.dcache.total_refs 676 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 93 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 83 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 135 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 4564 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 3475 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 884 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 283 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 303 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:BlockedCycles 100 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 81 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 133 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 4610 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 3877 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 889 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 290 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 293 # Number of squashed instructions handled by decode system.cpu.decode.DECODE:UnblockCycles 1 # Number of cycles decode is unblocking -system.cpu.dtb.accesses 931 # DTB accesses +system.cpu.dtb.accesses 936 # DTB accesses system.cpu.dtb.acv 1 # DTB access violations -system.cpu.dtb.hits 904 # DTB hits -system.cpu.dtb.misses 27 # DTB misses -system.cpu.dtb.read_accesses 575 # DTB read accesses +system.cpu.dtb.hits 911 # DTB hits +system.cpu.dtb.misses 25 # DTB misses +system.cpu.dtb.read_accesses 578 # DTB read accesses system.cpu.dtb.read_acv 1 # DTB read access violations -system.cpu.dtb.read_hits 563 # DTB read hits -system.cpu.dtb.read_misses 12 # DTB read misses -system.cpu.dtb.write_accesses 356 # DTB write accesses +system.cpu.dtb.read_hits 567 # DTB read hits +system.cpu.dtb.read_misses 11 # DTB read misses +system.cpu.dtb.write_accesses 358 # DTB write accesses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_hits 341 # DTB write hits -system.cpu.dtb.write_misses 15 # DTB write misses -system.cpu.fetch.Branches 824 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 707 # Number of cache lines fetched -system.cpu.fetch.Cycles 1626 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 101 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 5268 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 242 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.170919 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 707 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 319 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 1.092719 # Number of inst fetches per cycle +system.cpu.dtb.write_hits 344 # DTB write hits +system.cpu.dtb.write_misses 14 # DTB write misses +system.cpu.fetch.Branches 821 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 705 # Number of cache lines fetched +system.cpu.fetch.Cycles 1625 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 104 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 5290 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 238 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.152009 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 705 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 317 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 0.979448 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 4736 +system.cpu.fetch.rateDist.samples 5157 system.cpu.fetch.rateDist.min_value 0 - 0 3845 8118.67% - 1 38 80.24% - 2 85 179.48% - 3 63 133.02% - 4 118 249.16% - 5 55 116.13% - 6 42 88.68% - 7 48 101.35% - 8 442 933.28% + 0 4266 8272.25% + 1 34 65.93% + 2 85 164.82% + 3 67 129.92% + 4 115 223.00% + 5 55 106.65% + 6 41 79.50% + 7 48 93.08% + 8 446 864.84% system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.end_dist -system.cpu.icache.ReadReq_accesses 692 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 7648.351648 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 5370.879121 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 510 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 1392000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.263006 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_accesses 682 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 10041.208791 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 6417.582418 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 500 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 1827500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.266862 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 182 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 15 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 977500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.263006 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_hits 23 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 1168000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.266862 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 182 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_refs 2.802198 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 2.747253 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 692 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 7648.351648 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 5370.879121 # average overall mshr miss latency -system.cpu.icache.demand_hits 510 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 1392000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.263006 # miss rate for demand accesses +system.cpu.icache.demand_accesses 682 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 10041.208791 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 6417.582418 # average overall mshr miss latency +system.cpu.icache.demand_hits 500 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 1827500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.266862 # miss rate for demand accesses system.cpu.icache.demand_misses 182 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 15 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 977500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.263006 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_hits 23 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 1168000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.266862 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 182 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 692 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 7648.351648 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 5370.879121 # average overall mshr miss latency +system.cpu.icache.overall_accesses 682 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 10041.208791 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 6417.582418 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 510 # number of overall hits -system.cpu.icache.overall_miss_latency 1392000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.263006 # miss rate for overall accesses +system.cpu.icache.overall_hits 500 # number of overall hits +system.cpu.icache.overall_miss_latency 1827500 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.266862 # miss rate for overall accesses system.cpu.icache.overall_misses 182 # number of overall misses -system.cpu.icache.overall_mshr_hits 15 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 977500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.263006 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_hits 23 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 1168000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.266862 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 182 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses @@ -230,59 +230,59 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 0 # number of replacements system.cpu.icache.sampled_refs 182 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 92.900452 # Cycle average of tags in use -system.cpu.icache.total_refs 510 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 91.765219 # Cycle average of tags in use +system.cpu.icache.total_refs 500 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 85 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 538 # Number of branches executed -system.cpu.iew.EXEC:nop 274 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.658784 # Inst execution rate -system.cpu.iew.EXEC:refs 934 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 356 # Number of stores executed +system.cpu.idleCycles 244 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 542 # Number of branches executed +system.cpu.iew.EXEC:nop 277 # number of nop insts executed +system.cpu.iew.EXEC:rate 0.591187 # Inst execution rate +system.cpu.iew.EXEC:refs 939 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 358 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 1781 # num instructions consuming a value -system.cpu.iew.WB:count 3084 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.794497 # average fanout of values written-back +system.cpu.iew.WB:consumers 1788 # num instructions consuming a value +system.cpu.iew.WB:count 3104 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.790828 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 1415 # num instructions producing a value -system.cpu.iew.WB:rate 0.639701 # insts written-back per cycle -system.cpu.iew.WB:sent 3123 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 149 # Number of branch mispredicts detected at execute +system.cpu.iew.WB:producers 1414 # num instructions producing a value +system.cpu.iew.WB:rate 0.574708 # insts written-back per cycle +system.cpu.iew.WB:sent 3141 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 150 # Number of branch mispredicts detected at execute system.cpu.iew.iewBlockCycles 0 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 698 # Number of dispatched load instructions +system.cpu.iew.iewDispLoadInsts 703 # Number of dispatched load instructions system.cpu.iew.iewDispNonSpecInsts 6 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 83 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 412 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 4056 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 578 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 105 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 3176 # Number of executed instructions +system.cpu.iew.iewDispSquashedInsts 98 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 408 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 4070 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 581 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 98 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 3193 # Number of executed instructions system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 283 # Number of cycles IEW is squashing +system.cpu.iew.iewSquashCycles 290 # Number of cycles IEW is squashing system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.lsq.thread.0.forwLoads 25 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.ignoredResponses 1 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread.0.memOrderViolation 11 # Number of memory ordering violations system.cpu.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 283 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 118 # Number of stores squashed +system.cpu.iew.lsq.thread.0.squashedLoads 288 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 114 # Number of stores squashed system.cpu.iew.memOrderViolationEvents 11 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 97 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 98 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 52 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 0.495125 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.495125 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 3281 # Type of FU issued +system.cpu.ipc 0.441955 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.441955 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 3291 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist No_OpClass 0 0.00% # Type of FU issued - IntAlu 2319 70.68% # Type of FU issued + IntAlu 2327 70.71% # Type of FU issued IntMult 1 0.03% # Type of FU issued IntDiv 0 0.00% # Type of FU issued FloatAdd 0 0.00% # Type of FU issued @@ -291,13 +291,13 @@ system.cpu.iq.ISSUE:FU_type_0.start_dist FloatMult 0 0.00% # Type of FU issued FloatDiv 0 0.00% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 597 18.20% # Type of FU issued - MemWrite 364 11.09% # Type of FU issued + MemRead 599 18.20% # Type of FU issued + MemWrite 364 11.06% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.end_dist system.cpu.iq.ISSUE:fu_busy_cnt 35 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.010667 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_rate 0.010635 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full.start_dist No_OpClass 0 0.00% # attempts to use FU when none available IntAlu 1 2.86% # attempts to use FU when none available @@ -315,57 +315,57 @@ system.cpu.iq.ISSUE:fu_full.start_dist InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 4736 +system.cpu.iq.ISSUE:issued_per_cycle.samples 5157 system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 3384 7145.27% - 1 494 1043.07% - 2 314 663.01% - 3 237 500.42% - 4 163 344.17% - 5 88 185.81% - 6 40 84.46% - 7 12 25.34% - 8 4 8.45% + 0 3776 7322.09% + 1 540 1047.12% + 2 304 589.49% + 3 226 438.24% + 4 166 321.89% + 5 89 172.58% + 6 40 77.56% + 7 12 23.27% + 8 4 7.76% system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.end_dist -system.cpu.iq.ISSUE:rate 0.680564 # Inst issue rate -system.cpu.iq.iqInstsAdded 3776 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 3281 # Number of instructions issued +system.cpu.iq.ISSUE:rate 0.609332 # Inst issue rate +system.cpu.iq.iqInstsAdded 3787 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 3291 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 6 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 1238 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsExamined 1261 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iq.iqSquashedInstsIssued 1 # Number of squashed instructions issued system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 742 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.itb.accesses 735 # ITB accesses +system.cpu.iq.iqSquashedOperandsExamined 732 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.itb.accesses 734 # ITB accesses system.cpu.itb.acv 0 # ITB acv -system.cpu.itb.hits 707 # ITB hits -system.cpu.itb.misses 28 # ITB misses +system.cpu.itb.hits 705 # ITB hits +system.cpu.itb.misses 29 # ITB misses system.cpu.l2cache.ReadExReq_accesses 24 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 4604.166667 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 2604.166667 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 110500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_avg_miss_latency 5854.166667 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 2854.166667 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 140500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_misses 24 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 62500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 68500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 24 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadReq_accesses 243 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 4304.526749 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2304.526749 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_miss_latency 1046000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_avg_miss_latency 5440.329218 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2440.329218 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_miss_latency 1322000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 243 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 560000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 593000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 243 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_accesses 14 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 4178.571429 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 2178.571429 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 58500 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_avg_miss_latency 5571.428571 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 2571.428571 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 78000 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_misses 14 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 30500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 36000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_misses 14 # number of UpgradeReq MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -377,29 +377,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 # system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 267 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 4331.460674 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 2331.460674 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_miss_latency 5477.528090 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 2477.528090 # average overall mshr miss latency system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 1156500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 1462500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses system.cpu.l2cache.demand_misses 267 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 622500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 661500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 267 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.overall_accesses 267 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 4331.460674 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 2331.460674 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_miss_latency 5477.528090 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 2477.528090 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 0 # number of overall hits -system.cpu.l2cache.overall_miss_latency 1156500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 1462500 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses system.cpu.l2cache.overall_misses 267 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 622500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 661500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 267 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -416,26 +416,26 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.sampled_refs 229 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 115.687599 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 114.387820 # Cycle average of tags in use system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.numCycles 4821 # number of cpu cycles simulated +system.cpu.numCycles 5401 # number of cpu cycles simulated system.cpu.rename.RENAME:CommittedMaps 1768 # Number of HB maps that are committed -system.cpu.rename.RENAME:IdleCycles 3552 # Number of cycles rename is idle +system.cpu.rename.RENAME:IdleCycles 3954 # Number of cycles rename is idle system.cpu.rename.RENAME:LSQFullEvents 2 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 4989 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 4410 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 3154 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 808 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 283 # Number of cycles rename is squashing +system.cpu.rename.RENAME:RenameLookups 5025 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 4444 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 3187 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 813 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 290 # Number of cycles rename is squashing system.cpu.rename.RENAME:UnblockCycles 9 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 1386 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 84 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:UndoneMaps 1419 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 91 # count of cycles rename stalled for serializing inst system.cpu.rename.RENAME:serializingInsts 8 # count of serializing insts renamed system.cpu.rename.RENAME:skidInsts 60 # count of insts added to the skid buffer system.cpu.rename.RENAME:tempSerializingInsts 6 # count of temporary serializing insts renamed -system.cpu.timesIdled 28 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.timesIdled 46 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 4 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stderr b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stderr index 298b6fba0..f26dcb93f 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stderr +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stderr @@ -1,4 +1,4 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7000 +0: system.remote_gdb.listener: listening for remote gdb on port 7003 warn: Entering event queue @ 0. Starting simulation... warn: Increasing stack size by one page. warn: ignoring syscall sigprocmask(1, 18446744073709547831, ...) diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout index ca31124ab..b6bb2d255 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout @@ -1,14 +1,14 @@ Hello world! M5 Simulator System -Copyright (c) 2001-2006 +Copyright (c) 2001-2008 The Regents of The University of Michigan All Rights Reserved -M5 compiled Jan 15 2008 08:14:31 -M5 started Tue Jan 15 08:12:16 2008 -M5 executing on m45-034.pool +M5 compiled Feb 24 2008 12:58:20 +M5 started Sun Feb 24 13:00:07 2008 +M5 executing on tater command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/o3-timing tests/run.py quick/00.hello/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second -Exiting @ tick 2410000 because target called exit() +Exiting @ tick 2700000 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini index 48fcc2b94..4f7ec60f2 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini @@ -152,6 +152,7 @@ type=Bus block_size=64 bus_id=0 clock=1000 +header_cycles=1 responder_set=false width=64 port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side @@ -169,6 +170,7 @@ euid=100 executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello gid=100 input=cin +max_stack_size=67108864 output=cout pid=100 ppid=99 @@ -180,6 +182,7 @@ type=Bus block_size=64 bus_id=0 clock=1000 +header_cycles=1 responder_set=false width=64 port=system.physmem.port[0] system.cpu.l2cache.mem_side diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt index 60bfb7de8..c93b1f19c 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt @@ -1,31 +1,31 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 178240 # Simulator instruction rate (inst/s) -host_mem_usage 195696 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host -host_tick_rate 641473527 # Simulator tick rate (ticks/s) +host_inst_rate 99969 # Simulator instruction rate (inst/s) +host_mem_usage 193012 # Number of bytes of host memory used +host_seconds 0.03 # Real time elapsed on the host +host_tick_rate 383001655 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 2577 # Number of instructions simulated -sim_seconds 0.000009 # Number of seconds simulated -sim_ticks 9438000 # Number of ticks simulated +sim_seconds 0.000010 # Number of seconds simulated +sim_ticks 9950000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 415 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 25000 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 23000 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 27000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 24000 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 360 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 1375000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 1485000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.132530 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 55 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 1265000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 1320000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.132530 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 55 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 294 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 25000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 23000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 27000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 24000 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 256 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 950000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 1026000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.129252 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 38 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 874000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 912000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.129252 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 38 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -37,29 +37,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 709 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 25000 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 23000 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency 27000 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 24000 # average overall mshr miss latency system.cpu.dcache.demand_hits 616 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 2325000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 2511000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.131171 # miss rate for demand accesses system.cpu.dcache.demand_misses 93 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 2139000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 2232000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.131171 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 93 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 709 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 25000 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 23000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 27000 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 24000 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 616 # number of overall hits -system.cpu.dcache.overall_miss_latency 2325000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 2511000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.131171 # miss rate for overall accesses system.cpu.dcache.overall_misses 93 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 2139000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 2232000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.131171 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 93 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -76,7 +76,7 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 82 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 48.838317 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 48.703722 # Cycle average of tags in use system.cpu.dcache.total_refs 627 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks @@ -93,13 +93,13 @@ system.cpu.dtb.write_acv 0 # DT system.cpu.dtb.write_hits 294 # DTB write hits system.cpu.dtb.write_misses 4 # DTB write misses system.cpu.icache.ReadReq_accesses 2586 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 25000 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 23000 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_miss_latency 27000 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 24000 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 2423 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 4075000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency 4401000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.063032 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 163 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 3749000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 3912000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.063032 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 163 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -111,29 +111,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 2586 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 25000 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 23000 # average overall mshr miss latency +system.cpu.icache.demand_avg_miss_latency 27000 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 24000 # average overall mshr miss latency system.cpu.icache.demand_hits 2423 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 4075000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 4401000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.063032 # miss rate for demand accesses system.cpu.icache.demand_misses 163 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 3749000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 3912000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.063032 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 163 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.overall_accesses 2586 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 25000 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 23000 # average overall mshr miss latency +system.cpu.icache.overall_avg_miss_latency 27000 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 24000 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.icache.overall_hits 2423 # number of overall hits -system.cpu.icache.overall_miss_latency 4075000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 4401000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.063032 # miss rate for overall accesses system.cpu.icache.overall_misses 163 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 3749000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 3912000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.063032 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 163 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -150,7 +150,7 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 0 # number of replacements system.cpu.icache.sampled_refs 163 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 83.395749 # Cycle average of tags in use +system.cpu.icache.tagsinuse 83.077797 # Cycle average of tags in use system.cpu.icache.total_refs 2423 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks @@ -160,27 +160,27 @@ system.cpu.itb.acv 0 # IT system.cpu.itb.hits 2586 # ITB hits system.cpu.itb.misses 11 # ITB misses system.cpu.l2cache.ReadExReq_accesses 27 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 22000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 23000 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 594000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 621000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_misses 27 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_mshr_miss_latency 297000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 27 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadReq_accesses 218 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 22000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency 23000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_miss_latency 4796000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency 5014000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 218 # number of ReadReq misses system.cpu.l2cache.ReadReq_mshr_miss_latency 2398000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 218 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_accesses 11 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 22000 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency 23000 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 11000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 242000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency 253000 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_misses 11 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_mshr_miss_latency 121000 # number of UpgradeReq MSHR miss cycles @@ -195,10 +195,10 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 # system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 245 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 22000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency 23000 # average overall miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 5390000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 5635000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses system.cpu.l2cache.demand_misses 245 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits @@ -209,11 +209,11 @@ system.cpu.l2cache.fast_writes 0 # nu system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.overall_accesses 245 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 22000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 23000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 0 # number of overall hits -system.cpu.l2cache.overall_miss_latency 5390000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 5635000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses system.cpu.l2cache.overall_misses 245 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits @@ -234,12 +234,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.sampled_refs 207 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 106.559981 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 106.181819 # Cycle average of tags in use system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 18876 # number of cpu cycles simulated +system.cpu.numCycles 19900 # number of cpu cycles simulated system.cpu.num_insts 2577 # Number of instructions executed system.cpu.num_refs 717 # Number of memory references system.cpu.workload.PROG:num_syscalls 4 # Number of system calls diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stderr b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stderr index 9f8e7c2e9..f26dcb93f 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stderr +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stderr @@ -1,3 +1,4 @@ +0: system.remote_gdb.listener: listening for remote gdb on port 7003 warn: Entering event queue @ 0. Starting simulation... warn: Increasing stack size by one page. warn: ignoring syscall sigprocmask(1, 18446744073709547831, ...) diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout index 8d08b94be..c25792a5f 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout @@ -1,14 +1,14 @@ Hello world! M5 Simulator System -Copyright (c) 2001-2006 +Copyright (c) 2001-2008 The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 14 2007 17:58:14 -M5 started Tue Aug 14 17:59:08 2007 -M5 executing on nacho +M5 compiled Feb 24 2008 12:58:20 +M5 started Sun Feb 24 12:58:25 2008 +M5 executing on tater command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-timing tests/run.py quick/00.hello/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second -Exiting @ tick 9438000 because target called exit() +Exiting @ tick 9950000 because target called exit() |