diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2011-01-18 16:30:06 -0600 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2011-01-18 16:30:06 -0600 |
| commit | 9b67f3723e48efdd0a0b640ff82cfcf8aad3a659 (patch) | |
| tree | 79c5001cce6b9d92d1ad04d4a2cd4e442f56803c /tests/quick/00.hello/ref/alpha/tru64 | |
| parent | 77853b9f529947c3a9db78ef3458289f387289ce (diff) | |
| download | gem5-9b67f3723e48efdd0a0b640ff82cfcf8aad3a659.tar.xz | |
Stats: Update stats for previous set of patches.
Diffstat (limited to 'tests/quick/00.hello/ref/alpha/tru64')
| -rwxr-xr-x | tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout | 6 | ||||
| -rw-r--r-- | tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt | 9 |
2 files changed, 8 insertions, 7 deletions
diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout index 62d772708..fe2af5e09 100755 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout @@ -5,9 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 15 2010 08:52:32 -M5 revision f440cdaf1c2d+ 7743+ default tip -M5 started Nov 15 2010 13:43:59 +M5 compiled Jan 17 2011 16:24:53 +M5 revision f72d94f8c275 7839 default qtip tip outgoing.patch qbase +M5 started Jan 17 2011 16:48:46 M5 executing on zizzer command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt index c55fb3eb0..2363f1511 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 60581 # Simulator instruction rate (inst/s) -host_mem_usage 202656 # Number of bytes of host memory used +host_inst_rate 61982 # Simulator instruction rate (inst/s) +host_mem_usage 202420 # Number of bytes of host memory used host_seconds 0.04 # Real time elapsed on the host -host_tick_rate 184013511 # Simulator tick rate (ticks/s) +host_tick_rate 188319059 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 2387 # Number of instructions simulated sim_seconds 0.000007 # Number of seconds simulated @@ -143,9 +143,10 @@ system.cpu.dtb.write_hits 351 # DT system.cpu.dtb.write_misses 17 # DTB write misses system.cpu.fetch.Branches 926 # Number of branches that fetch encountered system.cpu.fetch.CacheLines 782 # Number of cache lines fetched -system.cpu.fetch.Cycles 1799 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.Cycles 988 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.IcacheSquashes 117 # Number of outstanding Icache misses that were squashed system.cpu.fetch.Insts 5752 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 29 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.SquashCycles 249 # Number of cycles fetch has spent squashing system.cpu.fetch.branchRate 0.063420 # Number of branch fetches per cycle system.cpu.fetch.icacheStallCycles 782 # Number of cycles fetch is stalled on an Icache miss |