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| author | Steve Reinhardt <steve.reinhardt@amd.com> | 2010-08-17 05:06:22 -0700 |
|---|---|---|
| committer | Steve Reinhardt <steve.reinhardt@amd.com> | 2010-08-17 05:06:22 -0700 |
| commit | 0f8b5afd7ad82fda05c3ad42cda4f9046992428d (patch) | |
| tree | 794e8480ec916aa1b7da4c756f71ae1f6b1ffec7 /tests/quick/00.hello/ref/alpha/tru64 | |
| parent | 0685ae7a2dbceaa2b9b264a57c9d5f82868e777e (diff) | |
| download | gem5-0f8b5afd7ad82fda05c3ad42cda4f9046992428d.tar.xz | |
tests: update reference config.ini files for previous cset
Rename 'responder_set' to 'use_default_range'.
Diffstat (limited to 'tests/quick/00.hello/ref/alpha/tru64')
3 files changed, 5 insertions, 5 deletions
diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini index 73089a2aa..9f8bdfba9 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini @@ -343,7 +343,7 @@ block_size=64 bus_id=0 clock=1000 header_cycles=1 -responder_set=false +use_default_range=false width=64 port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side @@ -375,7 +375,7 @@ block_size=64 bus_id=0 clock=1000 header_cycles=1 -responder_set=false +use_default_range=false width=64 port=system.physmem.port[0] system.cpu.l2cache.mem_side diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini index c65c23354..e4650467f 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini @@ -74,7 +74,7 @@ block_size=64 bus_id=0 clock=1000 header_cycles=1 -responder_set=false +use_default_range=false width=64 port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini index f316dec65..ab47c5c67 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini @@ -142,7 +142,7 @@ block_size=64 bus_id=0 clock=1000 header_cycles=1 -responder_set=false +use_default_range=false width=64 port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side @@ -174,7 +174,7 @@ block_size=64 bus_id=0 clock=1000 header_cycles=1 -responder_set=false +use_default_range=false width=64 port=system.physmem.port[0] system.cpu.l2cache.mem_side |