diff options
| author | Nathan Binkert <nate@binkert.org> | 2009-04-22 10:25:17 -0700 |
|---|---|---|
| committer | Nathan Binkert <nate@binkert.org> | 2009-04-22 10:25:17 -0700 |
| commit | 567cab685965e4e627ac1541a9fdacb93fd6e5fe (patch) | |
| tree | d79f8cfd677dfc314ccb48630b77785412a9f1bd /tests/quick/00.hello/ref/alpha/tru64 | |
| parent | ca3d82b38ab92114f5056a35bacf0dceb8b6d4a6 (diff) | |
| download | gem5-567cab685965e4e627ac1541a9fdacb93fd6e5fe.tar.xz | |
stats: update reference outputs now that compatibility is gone
Because of the initialization bug, it wasn't consistent anyway.
Diffstat (limited to 'tests/quick/00.hello/ref/alpha/tru64')
4 files changed, 120 insertions, 124 deletions
diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout index 63832f049..ac3d159cd 100755 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 21 2009 16:38:39 -M5 revision e6dd09514462 6117 default qtip tip stats-update -M5 started Apr 21 2009 16:39:11 -M5 executing on zizzer +M5 compiled Apr 22 2009 06:58:26 +M5 revision ce26a627c841 6126 default qtip tip stats_no_compat.diff +M5 started Apr 22 2009 07:17:21 +M5 executing on maize command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt index 98d731942..2fa8bf1eb 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 48067 # Simulator instruction rate (inst/s) -host_mem_usage 199912 # Number of bytes of host memory used +host_inst_rate 51063 # Simulator instruction rate (inst/s) +host_mem_usage 201612 # Number of bytes of host memory used host_seconds 0.05 # Real time elapsed on the host -host_tick_rate 143884460 # Simulator tick rate (ticks/s) +host_tick_rate 152859058 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 2387 # Number of instructions simulated sim_seconds 0.000007 # Number of seconds simulated @@ -19,23 +19,23 @@ system.cpu.BPredUnit.usedRAS 165 # Nu system.cpu.commit.COM:branches 396 # Number of branches committed system.cpu.commit.COM:bw_lim_events 38 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 6197 -system.cpu.commit.COM:committed_per_cycle::min_value 0 -system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% -system.cpu.commit.COM:committed_per_cycle::0-1 5240 84.56% -system.cpu.commit.COM:committed_per_cycle::1-2 263 4.24% -system.cpu.commit.COM:committed_per_cycle::2-3 334 5.39% -system.cpu.commit.COM:committed_per_cycle::3-4 134 2.16% -system.cpu.commit.COM:committed_per_cycle::4-5 73 1.18% -system.cpu.commit.COM:committed_per_cycle::5-6 63 1.02% -system.cpu.commit.COM:committed_per_cycle::6-7 32 0.52% -system.cpu.commit.COM:committed_per_cycle::7-8 20 0.32% -system.cpu.commit.COM:committed_per_cycle::8 38 0.61% -system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% -system.cpu.commit.COM:committed_per_cycle::total 6197 -system.cpu.commit.COM:committed_per_cycle::max_value 8 -system.cpu.commit.COM:committed_per_cycle::mean 0.415685 -system.cpu.commit.COM:committed_per_cycle::stdev 1.207973 +system.cpu.commit.COM:committed_per_cycle::samples 6197 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0-1 5240 84.56% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1-2 263 4.24% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2-3 334 5.39% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3-4 134 2.16% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4-5 73 1.18% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5-6 63 1.02% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::6-7 32 0.52% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7-8 20 0.32% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::8 38 0.61% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::total 6197 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::mean 0.415685 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::stdev 1.207973 # Number of insts commited each cycle system.cpu.commit.COM:count 2576 # Number of instructions committed system.cpu.commit.COM:loads 415 # Number of loads committed system.cpu.commit.COM:membars 0 # Number of memory barriers committed @@ -71,13 +71,13 @@ system.cpu.dcache.WriteReq_mshr_hits 70 # nu system.cpu.dcache.WriteReq_mshr_miss_latency 1394000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.125850 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 37 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.avg_refs 8.411765 # Average number of references to valid blocks. -system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 867 # number of demand (read+write) accesses system.cpu.dcache.demand_avg_miss_latency 36556.994819 # average overall miss latency @@ -96,7 +96,7 @@ system.cpu.dcache.no_allocate_misses 0 # Nu system.cpu.dcache.overall_accesses 867 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 36556.994819 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 36433.673469 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 674 # number of overall hits system.cpu.dcache.overall_miss_latency 7055500 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.222607 # miss rate for overall accesses @@ -177,13 +177,13 @@ system.cpu.icache.ReadReq_mshr_hits 54 # nu system.cpu.icache.ReadReq_mshr_miss_latency 6389000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.242303 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 181 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.avg_refs 2.828729 # Average number of references to valid blocks. -system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 747 # number of demand (read+write) accesses system.cpu.icache.demand_avg_miss_latency 35989.361702 # average overall miss latency @@ -202,7 +202,7 @@ system.cpu.icache.no_allocate_misses 0 # Nu system.cpu.icache.overall_accesses 747 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 35989.361702 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 35298.342541 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.overall_hits 512 # number of overall hits system.cpu.icache.overall_miss_latency 8457500 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.314592 # miss rate for overall accesses @@ -265,58 +265,54 @@ system.cpu.iew.predictedNotTakenIncorrect 97 # N system.cpu.iew.predictedTakenIncorrect 54 # Number of branches that were predicted taken incorrectly system.cpu.ipc 0.166145 # IPC: Instructions Per Cycle system.cpu.ipc_total 0.166145 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 3514 # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0.start_dist - No_OpClass 0 0.00% # Type of FU issued - IntAlu 2506 71.31% # Type of FU issued - IntMult 1 0.03% # Type of FU issued - IntDiv 0 0.00% # Type of FU issued - FloatAdd 0 0.00% # Type of FU issued - FloatCmp 0 0.00% # Type of FU issued - FloatCvt 0 0.00% # Type of FU issued - FloatMult 0 0.00% # Type of FU issued - FloatDiv 0 0.00% # Type of FU issued - FloatSqrt 0 0.00% # Type of FU issued - MemRead 639 18.18% # Type of FU issued - MemWrite 368 10.47% # Type of FU issued - IprAccess 0 0.00% # Type of FU issued - InstPrefetch 0 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0.end_dist +system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntAlu 2506 71.31% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntMult 1 0.03% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemRead 639 18.18% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemWrite 368 10.47% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::total 3514 # Type of FU issued system.cpu.iq.ISSUE:fu_busy_cnt 34 # FU busy when requested system.cpu.iq.ISSUE:fu_busy_rate 0.009676 # FU busy rate (busy events/executed inst) -system.cpu.iq.ISSUE:fu_full.start_dist - No_OpClass 0 0.00% # attempts to use FU when none available - IntAlu 1 2.94% # attempts to use FU when none available - IntMult 0 0.00% # attempts to use FU when none available - IntDiv 0 0.00% # attempts to use FU when none available - FloatAdd 0 0.00% # attempts to use FU when none available - FloatCmp 0 0.00% # attempts to use FU when none available - FloatCvt 0 0.00% # attempts to use FU when none available - FloatMult 0 0.00% # attempts to use FU when none available - FloatDiv 0 0.00% # attempts to use FU when none available - FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 11 32.35% # attempts to use FU when none available - MemWrite 22 64.71% # attempts to use FU when none available - IprAccess 0 0.00% # attempts to use FU when none available - InstPrefetch 0 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full.end_dist -system.cpu.iq.ISSUE:issued_per_cycle::samples 6528 -system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 -system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% -system.cpu.iq.ISSUE:issued_per_cycle::0-1 5051 77.37% -system.cpu.iq.ISSUE:issued_per_cycle::1-2 569 8.72% -system.cpu.iq.ISSUE:issued_per_cycle::2-3 331 5.07% -system.cpu.iq.ISSUE:issued_per_cycle::3-4 253 3.88% -system.cpu.iq.ISSUE:issued_per_cycle::4-5 172 2.63% -system.cpu.iq.ISSUE:issued_per_cycle::5-6 97 1.49% -system.cpu.iq.ISSUE:issued_per_cycle::6-7 39 0.60% -system.cpu.iq.ISSUE:issued_per_cycle::7-8 11 0.17% -system.cpu.iq.ISSUE:issued_per_cycle::8 5 0.08% -system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% -system.cpu.iq.ISSUE:issued_per_cycle::total 6528 -system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 -system.cpu.iq.ISSUE:issued_per_cycle::mean 0.538297 -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.220228 +system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntAlu 1 2.94% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemRead 11 32.35% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemWrite 22 64.71% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:issued_per_cycle::samples 6528 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::0-1 5051 77.37% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::1-2 569 8.72% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::2-3 331 5.07% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::3-4 253 3.88% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::4-5 172 2.63% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::5-6 97 1.49% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::6-7 39 0.60% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::7-8 11 0.17% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::8 5 0.08% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::total 6528 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::mean 0.538297 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.220228 # Number of insts issued each cycle system.cpu.iq.ISSUE:rate 0.244588 # Inst issue rate system.cpu.iq.iqInstsAdded 4031 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqInstsIssued 3514 # Number of instructions issued @@ -368,13 +364,13 @@ system.cpu.l2cache.UpgradeReq_misses 14 # nu system.cpu.l2cache.UpgradeReq_mshr_miss_latency 434500 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_misses 14 # number of UpgradeReq MSHR misses -system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks. -system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 266 # number of demand (read+write) accesses system.cpu.l2cache.demand_avg_miss_latency 34342.105263 # average overall miss latency @@ -393,7 +389,7 @@ system.cpu.l2cache.no_allocate_misses 0 # Nu system.cpu.l2cache.overall_accesses 266 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 34342.105263 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 31163.533835 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 0 # number of overall hits system.cpu.l2cache.overall_miss_latency 9135000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/simout b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/simout index 82648883e..103381b7c 100755 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/simout +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 21 2009 16:38:39 -M5 revision e6dd09514462 6117 default qtip tip stats-update -M5 started Apr 21 2009 16:59:01 -M5 executing on zizzer +M5 compiled Apr 22 2009 06:58:26 +M5 revision ce26a627c841 6126 default qtip tip stats_no_compat.diff +M5 started Apr 22 2009 07:17:22 +M5 executing on maize command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stats.txt index d6291acb4..72ee5d06d 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 164528 # Simulator instruction rate (inst/s) -host_mem_usage 199264 # Number of bytes of host memory used -host_seconds 0.02 # Real time elapsed on the host -host_tick_rate 1091811726 # Simulator tick rate (ticks/s) +host_inst_rate 89461 # Simulator instruction rate (inst/s) +host_mem_usage 200972 # Number of bytes of host memory used +host_seconds 0.03 # Real time elapsed on the host +host_tick_rate 597928210 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 2577 # Number of instructions simulated sim_seconds 0.000017 # Number of seconds simulated @@ -28,13 +28,13 @@ system.cpu.dcache.WriteReq_misses 38 # nu system.cpu.dcache.WriteReq_mshr_miss_latency 2014000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.129252 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 38 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.avg_refs 7.646341 # Average number of references to valid blocks. -system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 709 # number of demand (read+write) accesses system.cpu.dcache.demand_avg_miss_latency 56000 # average overall miss latency @@ -53,7 +53,7 @@ system.cpu.dcache.no_allocate_misses 0 # Nu system.cpu.dcache.overall_accesses 709 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 616 # number of overall hits system.cpu.dcache.overall_miss_latency 5208000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.131171 # miss rate for overall accesses @@ -97,13 +97,13 @@ system.cpu.icache.ReadReq_misses 163 # nu system.cpu.icache.ReadReq_mshr_miss_latency 8639000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.063032 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 163 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.avg_refs 14.865031 # Average number of references to valid blocks. -system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 2586 # number of demand (read+write) accesses system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency @@ -122,7 +122,7 @@ system.cpu.icache.no_allocate_misses 0 # Nu system.cpu.icache.overall_accesses 2586 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.overall_hits 2423 # number of overall hits system.cpu.icache.overall_miss_latency 9128000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.063032 # miss rate for overall accesses @@ -184,13 +184,13 @@ system.cpu.l2cache.UpgradeReq_misses 11 # nu system.cpu.l2cache.UpgradeReq_mshr_miss_latency 440000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_misses 11 # number of UpgradeReq MSHR misses -system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks. -system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 245 # number of demand (read+write) accesses system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency @@ -209,7 +209,7 @@ system.cpu.l2cache.no_allocate_misses 0 # Nu system.cpu.l2cache.overall_accesses 245 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 0 # number of overall hits system.cpu.l2cache.overall_miss_latency 12740000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses |