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| author | Kevin Lim <ktlim@umich.edu> | 2007-04-22 15:29:59 -0400 |
|---|---|---|
| committer | Kevin Lim <ktlim@umich.edu> | 2007-04-22 15:29:59 -0400 |
| commit | 67a37e83f3b69f832ae05c4612979c2c31bb4d3e (patch) | |
| tree | e817dbbaccb7b5cf64e461dfdcd82c28d75291de /tests/quick/00.hello/ref/alpha/tru64 | |
| parent | 8c7a6e1654bc682677b0e48764183198c2c7e868 (diff) | |
| download | gem5-67a37e83f3b69f832ae05c4612979c2c31bb4d3e.tar.xz | |
Updated refs for calculating IPC/CPI.
--HG--
extra : convert_revision : ee8dfee5eaa345dcb08f5d06d054655b1f6f79da
Diffstat (limited to 'tests/quick/00.hello/ref/alpha/tru64')
| -rw-r--r-- | tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt index cc70d3787..d3074bcf9 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt @@ -8,10 +8,10 @@ global.BPredUnit.condIncorrect 220 # Nu global.BPredUnit.condPredicted 427 # Number of conditional branches predicted global.BPredUnit.lookups 860 # Number of BP lookups global.BPredUnit.usedRAS 174 # Number of times the RAS was used to get a target. -host_inst_rate 32334 # Simulator instruction rate (inst/s) -host_mem_usage 153596 # Number of bytes of host memory used -host_seconds 0.07 # Real time elapsed on the host -host_tick_rate 21839716 # Simulator tick rate (ticks/s) +host_inst_rate 31252 # Simulator instruction rate (inst/s) +host_mem_usage 153592 # Number of bytes of host memory used +host_seconds 0.08 # Real time elapsed on the host +host_tick_rate 21107113 # Simulator tick rate (ticks/s) memdepunit.memDep.conflictingLoads 9 # Number of conflicting loads. memdepunit.memDep.conflictingStores 7 # Number of conflicting stores. memdepunit.memDep.insertedLoads 692 # Number of loads inserted to the mem dependence unit. @@ -49,8 +49,8 @@ system.cpu.commit.commitNonSpecStalls 4 # Th system.cpu.commit.commitSquashedInsts 1420 # The number of squashed insts skipped by commit system.cpu.committedInsts 2387 # Number of Instructions Simulated system.cpu.committedInsts_total 2387 # Number of Instructions Simulated -system.cpu.cpi 678.257227 # CPI: Cycles Per Instruction -system.cpu.cpi_total 678.257227 # CPI: Total CPI of All Threads +system.cpu.cpi 1.356933 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.356933 # CPI: Total CPI of All Threads system.cpu.dcache.ReadReq_accesses 537 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_avg_miss_latency 4625 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 3811.475410 # average ReadReq mshr miss latency @@ -264,8 +264,8 @@ system.cpu.iew.lsq.thread.0.squashedStores 91 # system.cpu.iew.memOrderViolationEvents 10 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 103 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 53 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 0.001474 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.001474 # IPC: Total IPC of All Threads +system.cpu.ipc 0.736956 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.736956 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0 3377 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist (null) 0 0.00% # Type of FU issued |