diff options
| author | Nathan Binkert <nate@binkert.org> | 2011-04-19 18:45:23 -0700 |
|---|---|---|
| committer | Nathan Binkert <nate@binkert.org> | 2011-04-19 18:45:23 -0700 |
| commit | 8c1563096c5aaf4123bf9ce5116aff3ce44dfd3b (patch) | |
| tree | 8caf62f25cfd5047cd4f2c0f357267be9d79d7c4 /tests/quick/00.hello/ref/alpha | |
| parent | 63371c86648ed65a453a95aec80f326f15a9666d (diff) | |
| download | gem5-8c1563096c5aaf4123bf9ce5116aff3ce44dfd3b.tar.xz | |
tests: update stats for name changes
Diffstat (limited to 'tests/quick/00.hello/ref/alpha')
59 files changed, 1177 insertions, 677 deletions
diff --git a/tests/quick/00.hello/ref/alpha/linux/inorder-timing/config.ini b/tests/quick/00.hello/ref/alpha/linux/inorder-timing/config.ini index 92b040488..c06b2c602 100644 --- a/tests/quick/00.hello/ref/alpha/linux/inorder-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/linux/inorder-timing/config.ini @@ -86,6 +86,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=true latency=1000 max_miss_count=0 mshrs=10 @@ -121,6 +122,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=true latency=1000 max_miss_count=0 mshrs=10 @@ -156,6 +158,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=false latency=10000 max_miss_count=0 mshrs=10 diff --git a/tests/quick/00.hello/ref/alpha/linux/inorder-timing/simout b/tests/quick/00.hello/ref/alpha/linux/inorder-timing/simout index fa50fea55..f797f48a3 100755 --- a/tests/quick/00.hello/ref/alpha/linux/inorder-timing/simout +++ b/tests/quick/00.hello/ref/alpha/linux/inorder-timing/simout @@ -5,10 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 18 2011 15:40:30 -M5 revision Unknown -M5 started Feb 18 2011 18:52:59 -M5 executing on m55-001.pool +M5 compiled Apr 19 2011 11:52:53 +M5 started Apr 19 2011 11:58:24 +M5 executing on maize command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/inorder-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/00.hello/ref/alpha/linux/inorder-timing/stats.txt b/tests/quick/00.hello/ref/alpha/linux/inorder-timing/stats.txt index bb298d30a..f36ebb971 100644 --- a/tests/quick/00.hello/ref/alpha/linux/inorder-timing/stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/inorder-timing/stats.txt @@ -1,37 +1,25 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 97475 # Simulator instruction rate (inst/s) -host_mem_usage 190320 # Number of bytes of host memory used -host_seconds 0.07 # Real time elapsed on the host -host_tick_rate 337940129 # Simulator tick rate (ticks/s) +host_inst_rate 116380 # Simulator instruction rate (inst/s) +host_mem_usage 203032 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host +host_tick_rate 403915000 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 6404 # Number of instructions simulated sim_seconds 0.000022 # Number of seconds simulated sim_ticks 22294500 # Number of ticks simulated -system.cpu.AGEN-Unit.agens 2186 # Number of Address Generations -system.cpu.Branch-Predictor.BTBHitPct 23.015873 # BTB Hit Percentage -system.cpu.Branch-Predictor.BTBHits 87 # Number of BTB hits -system.cpu.Branch-Predictor.BTBLookups 378 # Number of BTB lookups -system.cpu.Branch-Predictor.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.Branch-Predictor.condIncorrect 542 # Number of conditional branches incorrect -system.cpu.Branch-Predictor.condPredicted 995 # Number of conditional branches predicted -system.cpu.Branch-Predictor.lookups 1423 # Number of BP lookups -system.cpu.Branch-Predictor.predictedNotTaken 1183 # Number of Branches Predicted As Not Taken (False). -system.cpu.Branch-Predictor.predictedTaken 240 # Number of Branches Predicted As Taken (True). -system.cpu.Branch-Predictor.usedRAS 125 # Number of times the RAS was used to get a target. -system.cpu.Execution-Unit.executions 4596 # Number of Instructions Executed. -system.cpu.Execution-Unit.mispredictPct 51.569933 # Percentage of Incorrect Branches Predicts -system.cpu.Execution-Unit.mispredicted 542 # Number of Branches Incorrectly Predicted -system.cpu.Execution-Unit.predicted 509 # Number of Branches Incorrectly Predicted -system.cpu.Execution-Unit.predictedNotTakenIncorrect 537 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.Execution-Unit.predictedTakenIncorrect 5 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.Mult-Div-Unit.divides 0 # Number of Divide Operations Executed -system.cpu.Mult-Div-Unit.multiplies 1 # Number of Multipy Operations Executed -system.cpu.RegFile-Manager.regFileAccesses 10530 # Number of Total Accesses (Read+Write) to the Register File -system.cpu.RegFile-Manager.regFileReads 5947 # Number of Reads from Register File -system.cpu.RegFile-Manager.regFileWrites 4583 # Number of Writes to Register File -system.cpu.RegFile-Manager.regForwards 2845 # Number of Registers Read Through Forwarding Logic system.cpu.activity 16.075353 # Percentage of cycles cpu is active +system.cpu.agen_unit.agens 2186 # Number of Address Generations +system.cpu.branch_predictor.BTBHitPct 23.015873 # BTB Hit Percentage +system.cpu.branch_predictor.BTBHits 87 # Number of BTB hits +system.cpu.branch_predictor.BTBLookups 378 # Number of BTB lookups +system.cpu.branch_predictor.RASInCorrect 0 # Number of incorrect RAS predictions. +system.cpu.branch_predictor.condIncorrect 542 # Number of conditional branches incorrect +system.cpu.branch_predictor.condPredicted 995 # Number of conditional branches predicted +system.cpu.branch_predictor.lookups 1423 # Number of BP lookups +system.cpu.branch_predictor.predictedNotTaken 1183 # Number of Branches Predicted As Not Taken (False). +system.cpu.branch_predictor.predictedTaken 240 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.usedRAS 125 # Number of times the RAS was used to get a target. system.cpu.comBranches 1051 # Number of Branches instructions committed system.cpu.comFloats 2 # Number of Floating Point instructions committed system.cpu.comInts 3265 # Number of Integer instructions committed @@ -88,8 +76,8 @@ system.cpu.dcache.demand_mshr_misses 168 # nu system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.024898 # Average percentage of cache occupancy system.cpu.dcache.occ_blocks::0 101.981030 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.024898 # Average percentage of cache occupancy system.cpu.dcache.overall_accesses 2050 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 56663.223140 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 53690.476190 # average overall mshr miss latency @@ -127,6 +115,12 @@ system.cpu.dtb.write_accesses 868 # DT system.cpu.dtb.write_acv 0 # DTB write access violations system.cpu.dtb.write_hits 865 # DTB write hits system.cpu.dtb.write_misses 3 # DTB write misses +system.cpu.execution_unit.executions 4596 # Number of Instructions Executed. +system.cpu.execution_unit.mispredictPct 51.569933 # Percentage of Incorrect Branches Predicts +system.cpu.execution_unit.mispredicted 542 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.predicted 509 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.predictedNotTakenIncorrect 537 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.execution_unit.predictedTakenIncorrect 5 # Number of Branches Incorrectly Predicted As Taken. system.cpu.icache.ReadReq_accesses 955 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 55322.580645 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 53094.684385 # average ReadReq mshr miss latency @@ -160,8 +154,8 @@ system.cpu.icache.demand_mshr_misses 301 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.066877 # Average percentage of cache occupancy system.cpu.icache.occ_blocks::0 136.964505 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.066877 # Average percentage of cache occupancy system.cpu.icache.overall_accesses 955 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 55322.580645 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 53094.684385 # average overall mshr miss latency @@ -243,8 +237,8 @@ system.cpu.l2cache.demand_mshr_misses 468 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.005888 # Average percentage of cache occupancy system.cpu.l2cache.occ_blocks::0 192.950109 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.005888 # Average percentage of cache occupancy system.cpu.l2cache.overall_accesses 469 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52243.589744 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40087.606838 # average overall mshr miss latency @@ -266,31 +260,37 @@ system.cpu.l2cache.tagsinuse 192.950109 # Cy system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks +system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed +system.cpu.mult_div_unit.multiplies 1 # Number of Multipy Operations Executed system.cpu.numCycles 44590 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.regfile_manager.regFileAccesses 10530 # Number of Total Accesses (Read+Write) to the Register File +system.cpu.regfile_manager.regFileReads 5947 # Number of Reads from Register File +system.cpu.regfile_manager.regFileWrites 4583 # Number of Writes to Register File +system.cpu.regfile_manager.regForwards 2845 # Number of Registers Read Through Forwarding Logic system.cpu.runCycles 7168 # Number of cycles cpu stages are processed. system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode system.cpu.smt_cpi no_value # CPI: Total SMT-CPI system.cpu.smt_ipc no_value # IPC: Total SMT-IPC -system.cpu.stage-0.idleCycles 39847 # Number of cycles 0 instructions are processed. -system.cpu.stage-0.runCycles 4743 # Number of cycles 1+ instructions are processed. -system.cpu.stage-0.utilization 10.636914 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-1.idleCycles 40758 # Number of cycles 0 instructions are processed. -system.cpu.stage-1.runCycles 3832 # Number of cycles 1+ instructions are processed. -system.cpu.stage-1.utilization 8.593855 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-2.idleCycles 40488 # Number of cycles 0 instructions are processed. -system.cpu.stage-2.runCycles 4102 # Number of cycles 1+ instructions are processed. -system.cpu.stage-2.utilization 9.199372 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-3.idleCycles 43180 # Number of cycles 0 instructions are processed. -system.cpu.stage-3.runCycles 1410 # Number of cycles 1+ instructions are processed. -system.cpu.stage-3.utilization 3.162144 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-4.idleCycles 40181 # Number of cycles 0 instructions are processed. -system.cpu.stage-4.runCycles 4409 # Number of cycles 1+ instructions are processed. -system.cpu.stage-4.utilization 9.887867 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage0.idleCycles 39847 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 4743 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 10.636914 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 40758 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 3832 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 8.593855 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 40488 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 4102 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 9.199372 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 43180 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 1410 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 3.162144 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 40181 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 4409 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 9.887867 # Percentage of cycles stage was utilized (processing insts). system.cpu.threadCycles 11319 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.timesIdled 425 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.workload.PROG:num_syscalls 17 # Number of system calls +system.cpu.workload.num_syscalls 17 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini b/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini index 694ecbd33..08baf7c22 100644 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini @@ -25,6 +25,8 @@ BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 LQEntries=32 +LSQCheckLoads=true +LSQDepCheckShift=4 RASSize=16 SQEntries=32 SSITSize=1024 diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout b/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout index 99080254c..fb1ddd9ef 100755 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout @@ -5,9 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Mar 17 2011 21:44:37 -M5 started Mar 17 2011 21:44:43 -M5 executing on zizzer +M5 compiled Apr 19 2011 11:52:53 +M5 started Apr 19 2011 12:00:29 +M5 executing on maize command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt index 614787416..6483a471a 100644 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 83889 # Simulator instruction rate (inst/s) -host_mem_usage 205772 # Number of bytes of host memory used -host_seconds 0.08 # Real time elapsed on the host -host_tick_rate 161742329 # Simulator tick rate (ticks/s) +host_inst_rate 150919 # Simulator instruction rate (inst/s) +host_mem_usage 203704 # Number of bytes of host memory used +host_seconds 0.04 # Real time elapsed on the host +host_tick_rate 290889761 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 6386 # Number of instructions simulated sim_seconds 0.000012 # Number of seconds simulated @@ -16,38 +16,38 @@ system.cpu.BPredUnit.condIncorrect 443 # Nu system.cpu.BPredUnit.condPredicted 1297 # Number of conditional branches predicted system.cpu.BPredUnit.lookups 2180 # Number of BP lookups system.cpu.BPredUnit.usedRAS 306 # Number of times the RAS was used to get a target. -system.cpu.commit.COM:branches 1051 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 127 # number cycles where commit BW limit reached -system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 12090 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 0.529611 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 1.331978 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0 9222 76.28% 76.28% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1 1613 13.34% 89.62% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2 453 3.75% 93.37% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3 264 2.18% 95.55% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4 157 1.30% 96.85% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5 121 1.00% 97.85% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6 88 0.73% 98.58% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7 45 0.37% 98.95% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 127 1.05% 100.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 12090 # Number of insts commited each cycle -system.cpu.commit.COM:count 6403 # Number of instructions committed -system.cpu.commit.COM:fp_insts 10 # Number of committed floating point instructions. -system.cpu.commit.COM:function_calls 127 # Number of function calls committed. -system.cpu.commit.COM:int_insts 6321 # Number of committed integer instructions. -system.cpu.commit.COM:loads 1185 # Number of loads committed -system.cpu.commit.COM:membars 0 # Number of memory barriers committed -system.cpu.commit.COM:refs 2050 # Number of memory references committed -system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed system.cpu.commit.branchMispredicts 369 # The number of times a branch was mispredicted +system.cpu.commit.branches 1051 # Number of branches committed +system.cpu.commit.bw_lim_events 127 # number cycles where commit BW limit reached +system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.commitCommittedInsts 6403 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.commitSquashedInsts 4249 # The number of squashed insts skipped by commit +system.cpu.commit.committed_per_cycle::samples 12090 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.529611 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.331978 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 9222 76.28% 76.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1613 13.34% 89.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 453 3.75% 93.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 264 2.18% 95.55% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 157 1.30% 96.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 121 1.00% 97.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 88 0.73% 98.58% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 45 0.37% 98.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 127 1.05% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 12090 # Number of insts commited each cycle +system.cpu.commit.count 6403 # Number of instructions committed +system.cpu.commit.fp_insts 10 # Number of committed floating point instructions. +system.cpu.commit.function_calls 127 # Number of function calls committed. +system.cpu.commit.int_insts 6321 # Number of committed integer instructions. +system.cpu.commit.loads 1185 # Number of loads committed +system.cpu.commit.membars 0 # Number of memory barriers committed +system.cpu.commit.refs 2050 # Number of memory references committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.committedInsts 6386 # Number of Instructions Simulated system.cpu.committedInsts_total 6386 # Number of Instructions Simulated system.cpu.cpi 3.870341 # CPI: Cycles Per Instruction @@ -96,8 +96,8 @@ system.cpu.dcache.demand_mshr_misses 174 # nu system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.026841 # Average percentage of cache occupancy system.cpu.dcache.occ_blocks::0 109.940770 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.026841 # Average percentage of cache occupancy system.cpu.dcache.overall_accesses 2570 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 35355.731225 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 36083.333333 # average overall mshr miss latency @@ -119,15 +119,15 @@ system.cpu.dcache.tagsinuse 109.940770 # Cy system.cpu.dcache.total_refs 2064 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 1035 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 75 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 181 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 12021 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 8780 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 2228 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 825 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 209 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 47 # Number of cycles decode is unblocking +system.cpu.decode.BlockedCycles 1035 # Number of cycles decode is blocked +system.cpu.decode.BranchMispred 75 # Number of times decode detected a branch misprediction +system.cpu.decode.BranchResolved 181 # Number of times decode resolved a branch +system.cpu.decode.DecodedInsts 12021 # Number of instructions handled by decode +system.cpu.decode.IdleCycles 8780 # Number of cycles decode is idle +system.cpu.decode.RunCycles 2228 # Number of cycles decode is running +system.cpu.decode.SquashCycles 825 # Number of cycles decode is squashing +system.cpu.decode.SquashedInsts 209 # Number of squashed instructions handled by decode +system.cpu.decode.UnblockCycles 47 # Number of cycles decode is unblocking system.cpu.dtb.data_accesses 2822 # DTB accesses system.cpu.dtb.data_acv 0 # DTB access violations system.cpu.dtb.data_hits 2761 # DTB hits @@ -207,8 +207,8 @@ system.cpu.icache.demand_mshr_misses 307 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.076986 # Average percentage of cache occupancy system.cpu.icache.occ_blocks::0 157.666490 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.076986 # Average percentage of cache occupancy system.cpu.icache.overall_accesses 1711 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 35919.512195 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 35283.387622 # average overall mshr miss latency @@ -231,21 +231,13 @@ system.cpu.icache.total_refs 1301 # To system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idleCycles 11801 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 1424 # Number of branches executed -system.cpu.iew.EXEC:nop 82 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.357542 # Inst execution rate -system.cpu.iew.EXEC:refs 2832 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 1038 # Number of stores executed -system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 5952 # num instructions consuming a value -system.cpu.iew.WB:count 8559 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.744120 # average fanout of values written-back -system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 4429 # num instructions producing a value -system.cpu.iew.WB:rate 0.346294 # insts written-back per cycle -system.cpu.iew.WB:sent 8658 # cumulative count of insts sent to commit system.cpu.iew.branchMispredicts 429 # Number of branch mispredicts detected at execute +system.cpu.iew.exec_branches 1424 # Number of branches executed +system.cpu.iew.exec_nop 82 # number of nop insts executed +system.cpu.iew.exec_rate 0.357542 # Inst execution rate +system.cpu.iew.exec_refs 2832 # number of memory reference insts executed +system.cpu.iew.exec_stores 1038 # Number of stores executed +system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.iewBlockCycles 67 # Number of cycles IEW is blocking system.cpu.iew.iewDispLoadInsts 2144 # Number of dispatched load instructions system.cpu.iew.iewDispNonSpecInsts 25 # Number of dispatched non-speculative instructions @@ -273,103 +265,93 @@ system.cpu.iew.lsq.thread.0.squashedStores 330 # system.cpu.iew.memOrderViolationEvents 16 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 304 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 125 # Number of branches that were predicted taken incorrectly +system.cpu.iew.wb_consumers 5952 # num instructions consuming a value +system.cpu.iew.wb_count 8559 # cumulative count of insts written-back +system.cpu.iew.wb_fanout 0.744120 # average fanout of values written-back +system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ +system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu.iew.wb_producers 4429 # num instructions producing a value +system.cpu.iew.wb_rate 0.346294 # insts written-back per cycle +system.cpu.iew.wb_sent 8658 # cumulative count of insts sent to commit system.cpu.int_regfile_reads 11291 # number of integer regfile reads system.cpu.int_regfile_writes 6385 # number of integer regfile writes system.cpu.ipc 0.258375 # IPC: Instructions Per Cycle system.cpu.ipc_total 0.258375 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 6174 67.79% 67.81% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 1 0.01% 67.82% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatAdd 2 0.02% 67.84% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 67.84% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 67.84% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 67.84% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 67.84% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 67.84% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 67.84% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 67.84% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 67.84% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 67.84% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 67.84% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 67.84% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 67.84% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 67.84% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 67.84% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 67.84% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 67.84% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 67.84% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 67.84% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 67.84% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 67.84% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 67.84% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 67.84% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 67.84% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 67.84% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 67.84% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 1875 20.59% 88.43% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 1054 11.57% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 9108 # Type of FU issued -system.cpu.iq.ISSUE:fu_busy_cnt 88 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.009662 # FU busy rate (busy events/executed inst) -system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntAlu 1 1.14% 1.14% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemRead 52 59.09% 60.23% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemWrite 35 39.77% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 12915 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 0.705226 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.305176 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0 8840 68.45% 68.45% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1 1652 12.79% 81.24% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2 1039 8.04% 89.28% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3 684 5.30% 94.58% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4 367 2.84% 97.42% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5 198 1.53% 98.95% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6 88 0.68% 99.64% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7 36 0.28% 99.91% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::8 11 0.09% 100.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 12915 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 0.368506 # Inst issue rate +system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 6174 67.79% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 1 0.01% 67.82% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.84% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 1875 20.59% 88.43% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1054 11.57% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 9108 # Type of FU issued system.cpu.iq.fp_alu_accesses 11 # Number of floating point alu accesses system.cpu.iq.fp_inst_queue_reads 21 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_wakeup_accesses 10 # Number of floating instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_writes 10 # Number of floating instruction queue writes +system.cpu.iq.fu_busy_cnt 88 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.009662 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 1 1.14% 1.14% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 1.14% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 1.14% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.14% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.14% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.14% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 1.14% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.14% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 1.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 1.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.14% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 52 59.09% 60.23% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 35 39.77% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.int_alu_accesses 9183 # Number of integer alu accesses system.cpu.iq.int_inst_queue_reads 31223 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_wakeup_accesses 8549 # Number of integer instruction queue wakeup accesses @@ -381,6 +363,24 @@ system.cpu.iq.iqSquashedInstsExamined 3797 # Nu system.cpu.iq.iqSquashedInstsIssued 25 # Number of squashed instructions issued system.cpu.iq.iqSquashedNonSpecRemoved 8 # Number of squashed non-spec instructions that were removed system.cpu.iq.iqSquashedOperandsExamined 2286 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.issued_per_cycle::samples 12915 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.705226 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.305176 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 8840 68.45% 68.45% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1652 12.79% 81.24% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 1039 8.04% 89.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 684 5.30% 94.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 367 2.84% 97.42% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 198 1.53% 98.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 88 0.68% 99.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 36 0.28% 99.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 11 0.09% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 12915 # Number of insts issued each cycle +system.cpu.iq.rate 0.368506 # Inst issue rate system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_hits 0 # DTB hits @@ -438,8 +438,8 @@ system.cpu.l2cache.demand_mshr_misses 480 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.006698 # Average percentage of cache occupancy system.cpu.l2cache.occ_blocks::0 219.485914 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.006698 # Average percentage of cache occupancy system.cpu.l2cache.overall_accesses 481 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 34421.875000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 31252.083333 # average overall mshr miss latency @@ -470,27 +470,27 @@ system.cpu.misc_regfile_writes 1 # nu system.cpu.numCycles 24716 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.rename.RENAME:BlockCycles 337 # Number of cycles rename is blocking -system.cpu.rename.RENAME:CommittedMaps 4583 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 8 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 8928 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 260 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 14615 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 11616 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 8669 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 2118 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 825 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 301 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 4086 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:fp_rename_lookups 17 # Number of floating rename lookups -system.cpu.rename.RENAME:int_rename_lookups 14598 # Number of integer rename lookups -system.cpu.rename.RENAME:serializeStallCycles 406 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 28 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 754 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 22 # count of temporary serializing insts renamed +system.cpu.rename.BlockCycles 337 # Number of cycles rename is blocking +system.cpu.rename.CommittedMaps 4583 # Number of HB maps that are committed +system.cpu.rename.IQFullEvents 8 # Number of times rename has blocked due to IQ full +system.cpu.rename.IdleCycles 8928 # Number of cycles rename is idle +system.cpu.rename.LSQFullEvents 260 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenameLookups 14615 # Number of register rename lookups that rename has made +system.cpu.rename.RenamedInsts 11616 # Number of instructions processed by rename +system.cpu.rename.RenamedOperands 8669 # Number of destination operands rename has renamed +system.cpu.rename.RunCycles 2118 # Number of cycles rename is running +system.cpu.rename.SquashCycles 825 # Number of cycles rename is squashing +system.cpu.rename.UnblockCycles 301 # Number of cycles rename is unblocking +system.cpu.rename.UndoneMaps 4086 # Number of HB maps that are undone due to squashing +system.cpu.rename.fp_rename_lookups 17 # Number of floating rename lookups +system.cpu.rename.int_rename_lookups 14598 # Number of integer rename lookups +system.cpu.rename.serializeStallCycles 406 # count of cycles rename stalled for serializing inst +system.cpu.rename.serializingInsts 28 # count of serializing insts renamed +system.cpu.rename.skidInsts 754 # count of insts added to the skid buffer +system.cpu.rename.tempSerializingInsts 22 # count of temporary serializing insts renamed system.cpu.rob.rob_reads 22264 # The number of ROB reads system.cpu.rob.rob_writes 22135 # The number of ROB writes system.cpu.timesIdled 240 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.workload.PROG:num_syscalls 17 # Number of system calls +system.cpu.workload.num_syscalls 17 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/simout b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/simout index b6cabe98f..e68d877ae 100755 --- a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/simout +++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/simout @@ -5,10 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 7 2011 01:47:18 -M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip -M5 started Feb 7 2011 01:47:39 -M5 executing on burrito +M5 compiled Apr 19 2011 11:52:53 +M5 started Apr 19 2011 12:03:52 +M5 executing on maize command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stats.txt index 29c354685..16e0bb854 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 474100 # Simulator instruction rate (inst/s) -host_mem_usage 215244 # Number of bytes of host memory used +host_inst_rate 863821 # Simulator instruction rate (inst/s) +host_mem_usage 195076 # Number of bytes of host memory used host_seconds 0.01 # Real time elapsed on the host -host_tick_rate 233713954 # Simulator tick rate (ticks/s) +host_tick_rate 424966568 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 6404 # Number of instructions simulated sim_seconds 0.000003 # Number of seconds simulated @@ -61,6 +61,6 @@ system.cpu.num_int_register_writes 4581 # nu system.cpu.num_load_insts 1192 # Number of load instructions system.cpu.num_mem_refs 2060 # number of memory refs system.cpu.num_store_insts 868 # Number of store instructions -system.cpu.workload.PROG:num_syscalls 17 # Number of system calls +system.cpu.workload.num_syscalls 17 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/config.ini b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/config.ini index c905c3ec3..97adc30bc 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/config.ini +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/config.ini @@ -63,7 +63,7 @@ egid=100 env= errout=cerr euid=100 -executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/linux/hello +executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello gid=100 input=cin max_stack_size=67108864 @@ -201,6 +201,7 @@ deadlock_threshold=500000 icache=system.l1_cntrl0.L1IcacheMemory max_outstanding_requests=16 physmem=system.physmem +using_network_tester=false using_ruby_tester=false version=0 physMemPort=system.physmem.port[0] diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/ruby.stats b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/ruby.stats index 50b357793..61a1f65c1 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/ruby.stats +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/ruby.stats @@ -34,27 +34,27 @@ periodic_stats_period: 1000000 ================ End RubySystem Configuration Print ================ -Real time: Feb/08/2011 17:31:55 +Real time: Apr/19/2011 12:12:41 Profiler Stats -------------- -Elapsed_time_in_seconds: 0 -Elapsed_time_in_minutes: 0 -Elapsed_time_in_hours: 0 -Elapsed_time_in_days: 0 +Elapsed_time_in_seconds: 1 +Elapsed_time_in_minutes: 0.0166667 +Elapsed_time_in_hours: 0.000277778 +Elapsed_time_in_days: 1.15741e-05 -Virtual_time_in_seconds: 0.51 -Virtual_time_in_minutes: 0.0085 -Virtual_time_in_hours: 0.000141667 -Virtual_time_in_days: 5.90278e-06 +Virtual_time_in_seconds: 0.22 +Virtual_time_in_minutes: 0.00366667 +Virtual_time_in_hours: 6.11111e-05 +Virtual_time_in_days: 2.5463e-06 Ruby_current_time: 275313 Ruby_start_time: 0 Ruby_cycles: 275313 -mbytes_resident: 37.0469 -mbytes_total: 210.465 -resident_ratio: 0.176098 +mbytes_resident: 39.0156 +mbytes_total: 208.391 +resident_ratio: 0.187242 ruby_cycles_executed: [ 275314 ] @@ -71,9 +71,9 @@ sequencer_requests_outstanding: [binsize: 1 max: 1 count: 8465 average: 1 | All Non-Zero Cycle Demand Cache Accesses ---------------------------------------- miss_latency: [binsize: 2 max: 281 count: 8464 average: 31.5275 | standard deviation: 62.4195 | 0 6974 0 0 0 0 0 0 0 30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 156 439 246 330 220 8 7 9 11 3 2 9 4 5 1 0 0 1 1 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 1 0 0 0 0 1 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_IFETCH: [binsize: 2 max: 269 count: 6414 average: 20.6784 | standard deviation: 51.1007 | 0 5723 0 0 0 0 0 0 0 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 59 203 95 191 106 4 5 4 6 2 1 1 1 4 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] miss_latency_LD: [binsize: 2 max: 281 count: 1185 average: 82.5848 | standard deviation: 82.5677 | 0 602 0 0 0 0 0 0 0 13 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 64 191 73 123 92 4 2 3 3 1 1 7 2 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] miss_latency_ST: [binsize: 2 max: 215 count: 865 average: 42.0289 | standard deviation: 69.8546 | 0 649 0 0 0 0 0 0 0 12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 33 45 78 16 22 0 0 2 2 0 0 1 1 1 0 0 0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_IFETCH: [binsize: 2 max: 269 count: 6414 average: 20.6784 | standard deviation: 51.1007 | 0 5723 0 0 0 0 0 0 0 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 59 203 95 191 106 4 5 4 6 2 1 1 1 4 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] miss_latency_NULL: [binsize: 2 max: 281 count: 8464 average: 31.5275 | standard deviation: 62.4195 | 0 6974 0 0 0 0 0 0 0 30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 156 439 246 330 220 8 7 9 11 3 2 9 4 5 1 0 0 1 1 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 1 0 0 0 0 1 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] @@ -85,9 +85,9 @@ miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 0 average: N miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] miss_latency_dir_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] imcomplete_dir_Times: 0 -miss_latency_IFETCH_NULL: [binsize: 2 max: 269 count: 6414 average: 20.6784 | standard deviation: 51.1007 | 0 5723 0 0 0 0 0 0 0 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 59 203 95 191 106 4 5 4 6 2 1 1 1 4 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] miss_latency_LD_NULL: [binsize: 2 max: 281 count: 1185 average: 82.5848 | standard deviation: 82.5677 | 0 602 0 0 0 0 0 0 0 13 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 64 191 73 123 92 4 2 3 3 1 1 7 2 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] miss_latency_ST_NULL: [binsize: 2 max: 215 count: 865 average: 42.0289 | standard deviation: 69.8546 | 0 649 0 0 0 0 0 0 0 12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 33 45 78 16 22 0 0 2 2 0 0 1 1 1 0 0 0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_IFETCH_NULL: [binsize: 2 max: 269 count: 6414 average: 20.6784 | standard deviation: 51.1007 | 0 5723 0 0 0 0 0 0 0 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 59 203 95 191 106 4 5 4 6 2 1 1 1 4 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] All Non-Zero Cycle SW Prefetch Requests ------------------------------------ @@ -119,11 +119,11 @@ Resource Usage page_size: 4096 user_time: 0 system_time: 0 -page_reclaims: 10681 +page_reclaims: 10280 page_faults: 0 swaps: 0 block_inputs: 0 -block_outputs: 0 +block_outputs: 64 Network Stats ------------- diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simout b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simout index 8e7f8bf86..87aa40602 100755 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simout +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simout @@ -5,10 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 8 2011 17:31:51 -M5 revision 685719afafe6 7938 default tip brad/increase_ruby_mem_test_threshold qtip -M5 started Feb 8 2011 17:31:55 -M5 executing on SC2B0617 +M5 compiled Apr 19 2011 12:12:36 +M5 started Apr 19 2011 12:12:40 +M5 executing on maize command line: build/ALPHA_SE_MESI_CMP_directory/m5.fast -d build/ALPHA_SE_MESI_CMP_directory/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MESI_CMP_directory -re tests/run.py build/ALPHA_SE_MESI_CMP_directory/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MESI_CMP_directory Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/stats.txt index d0f6b1167..752b7fee0 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 30108 # Simulator instruction rate (inst/s) -host_mem_usage 215520 # Number of bytes of host memory used -host_seconds 0.21 # Real time elapsed on the host -host_tick_rate 1293296 # Simulator tick rate (ticks/s) +host_inst_rate 53768 # Simulator instruction rate (inst/s) +host_mem_usage 213396 # Number of bytes of host memory used +host_seconds 0.12 # Real time elapsed on the host +host_tick_rate 2308748 # Simulator tick rate (ticks/s) sim_freq 1000000000 # Frequency of simulated ticks sim_insts 6404 # Number of instructions simulated sim_seconds 0.000275 # Number of seconds simulated @@ -61,6 +61,6 @@ system.cpu.num_int_register_writes 4581 # nu system.cpu.num_load_insts 1192 # Number of load instructions system.cpu.num_mem_refs 2060 # number of memory refs system.cpu.num_store_insts 868 # Number of store instructions -system.cpu.workload.PROG:num_syscalls 17 # Number of system calls +system.cpu.workload.num_syscalls 17 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini index cb765942a..f21fa2c0d 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini @@ -63,7 +63,7 @@ egid=100 env= errout=cerr euid=100 -executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/linux/hello +executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello gid=100 input=cin max_stack_size=67108864 @@ -197,6 +197,7 @@ deadlock_threshold=500000 icache=system.l1_cntrl0.L1IcacheMemory max_outstanding_requests=16 physmem=system.physmem +using_network_tester=false using_ruby_tester=false version=0 physMemPort=system.physmem.port[0] diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/ruby.stats b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/ruby.stats index 9154f09df..4ab7d1237 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/ruby.stats +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/ruby.stats @@ -34,27 +34,27 @@ periodic_stats_period: 1000000 ================ End RubySystem Configuration Print ================ -Real time: Feb/08/2011 17:41:43 +Real time: Apr/19/2011 12:14:53 Profiler Stats -------------- -Elapsed_time_in_seconds: 1 -Elapsed_time_in_minutes: 0.0166667 -Elapsed_time_in_hours: 0.000277778 -Elapsed_time_in_days: 1.15741e-05 +Elapsed_time_in_seconds: 0 +Elapsed_time_in_minutes: 0 +Elapsed_time_in_hours: 0 +Elapsed_time_in_days: 0 -Virtual_time_in_seconds: 0.52 -Virtual_time_in_minutes: 0.00866667 -Virtual_time_in_hours: 0.000144444 -Virtual_time_in_days: 6.01852e-06 +Virtual_time_in_seconds: 0.24 +Virtual_time_in_minutes: 0.004 +Virtual_time_in_hours: 6.66667e-05 +Virtual_time_in_days: 2.77778e-06 Ruby_current_time: 223854 Ruby_start_time: 0 Ruby_cycles: 223854 -mbytes_resident: 37.1562 -mbytes_total: 210.609 -resident_ratio: 0.176478 +mbytes_resident: 39.1172 +mbytes_total: 208.504 +resident_ratio: 0.187628 ruby_cycles_executed: [ 223855 ] @@ -71,9 +71,9 @@ sequencer_requests_outstanding: [binsize: 1 max: 1 count: 8465 average: 1 | All Non-Zero Cycle Demand Cache Accesses ---------------------------------------- miss_latency: [binsize: 2 max: 276 count: 8464 average: 25.4478 | standard deviation: 56.39 | 0 7102 0 0 0 0 0 0 0 188 60 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 251 197 238 187 165 13 4 20 3 7 5 4 3 3 1 0 1 1 1 0 0 1 0 1 0 0 0 3 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_IFETCH: [binsize: 2 max: 276 count: 6414 average: 17.9724 | standard deviation: 47.359 | 0 5768 0 0 0 0 0 0 0 76 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 153 110 113 93 66 5 3 16 1 3 0 1 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 2 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] miss_latency_LD: [binsize: 2 max: 259 count: 1185 average: 62.838 | standard deviation: 78.9565 | 0 660 0 0 0 0 0 0 0 112 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 98 55 84 84 63 2 1 3 2 3 5 3 2 2 0 0 1 0 1 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] miss_latency_ST: [binsize: 2 max: 227 count: 865 average: 29.6555 | standard deviation: 60.051 | 0 674 0 0 0 0 0 0 0 0 60 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 32 41 10 36 6 0 1 0 1 0 0 1 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_IFETCH: [binsize: 2 max: 276 count: 6414 average: 17.9724 | standard deviation: 47.359 | 0 5768 0 0 0 0 0 0 0 76 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 153 110 113 93 66 5 3 16 1 3 0 1 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 2 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] miss_latency_NULL: [binsize: 2 max: 276 count: 8464 average: 25.4478 | standard deviation: 56.39 | 0 7102 0 0 0 0 0 0 0 188 60 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 251 197 238 187 165 13 4 20 3 7 5 4 3 3 1 0 1 1 1 0 0 1 0 1 0 0 0 3 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] @@ -85,9 +85,9 @@ miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 0 average: N miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] miss_latency_dir_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] imcomplete_dir_Times: 0 -miss_latency_IFETCH_NULL: [binsize: 2 max: 276 count: 6414 average: 17.9724 | standard deviation: 47.359 | 0 5768 0 0 0 0 0 0 0 76 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 153 110 113 93 66 5 3 16 1 3 0 1 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 2 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] miss_latency_LD_NULL: [binsize: 2 max: 259 count: 1185 average: 62.838 | standard deviation: 78.9565 | 0 660 0 0 0 0 0 0 0 112 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 98 55 84 84 63 2 1 3 2 3 5 3 2 2 0 0 1 0 1 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] miss_latency_ST_NULL: [binsize: 2 max: 227 count: 865 average: 29.6555 | standard deviation: 60.051 | 0 674 0 0 0 0 0 0 0 0 60 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 32 41 10 36 6 0 1 0 1 0 0 1 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_IFETCH_NULL: [binsize: 2 max: 276 count: 6414 average: 17.9724 | standard deviation: 47.359 | 0 5768 0 0 0 0 0 0 0 76 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 153 110 113 93 66 5 3 16 1 3 0 1 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 2 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] All Non-Zero Cycle SW Prefetch Requests ------------------------------------ @@ -119,11 +119,11 @@ Resource Usage page_size: 4096 user_time: 0 system_time: 0 -page_reclaims: 10696 +page_reclaims: 10307 page_faults: 0 swaps: 0 block_inputs: 0 -block_outputs: 0 +block_outputs: 64 Network Stats ------------- @@ -411,6 +411,7 @@ Writeback_Ack [1098 ] 1098 Writeback_Nack [0 ] 0 Unblock [0 ] 0 Exclusive_Unblock [1362 ] 1362 +DmaAck [0 ] 0 L2_Replacement [1098 ] 1098 - Transitions - @@ -1160,6 +1161,76 @@ ILSI All_Acks [0 ] 0 ILSI Writeback_Ack [0 ] 0 ILSI L2_Replacement [0 ] 0 +ILOSD L1_GETS [0 ] 0 +ILOSD L1_GETX [0 ] 0 +ILOSD L1_PUTO [0 ] 0 +ILOSD L1_PUTX [0 ] 0 +ILOSD L1_PUTS_only [0 ] 0 +ILOSD L1_PUTS [0 ] 0 +ILOSD Fwd_GETX [0 ] 0 +ILOSD Fwd_GETS [0 ] 0 +ILOSD Fwd_DMA [0 ] 0 +ILOSD Own_GETX [0 ] 0 +ILOSD Inv [0 ] 0 +ILOSD DmaAck [0 ] 0 +ILOSD L2_Replacement [0 ] 0 + +ILOSXD L1_GETS [0 ] 0 +ILOSXD L1_GETX [0 ] 0 +ILOSXD L1_PUTO [0 ] 0 +ILOSXD L1_PUTX [0 ] 0 +ILOSXD L1_PUTS_only [0 ] 0 +ILOSXD L1_PUTS [0 ] 0 +ILOSXD Fwd_GETX [0 ] 0 +ILOSXD Fwd_GETS [0 ] 0 +ILOSXD Fwd_DMA [0 ] 0 +ILOSXD Own_GETX [0 ] 0 +ILOSXD Inv [0 ] 0 +ILOSXD DmaAck [0 ] 0 +ILOSXD L2_Replacement [0 ] 0 + +ILOD L1_GETS [0 ] 0 +ILOD L1_GETX [0 ] 0 +ILOD L1_PUTO [0 ] 0 +ILOD L1_PUTX [0 ] 0 +ILOD L1_PUTS_only [0 ] 0 +ILOD L1_PUTS [0 ] 0 +ILOD Fwd_GETX [0 ] 0 +ILOD Fwd_GETS [0 ] 0 +ILOD Fwd_DMA [0 ] 0 +ILOD Own_GETX [0 ] 0 +ILOD Inv [0 ] 0 +ILOD DmaAck [0 ] 0 +ILOD L2_Replacement [0 ] 0 + +ILXD L1_GETS [0 ] 0 +ILXD L1_GETX [0 ] 0 +ILXD L1_PUTO [0 ] 0 +ILXD L1_PUTX [0 ] 0 +ILXD L1_PUTS_only [0 ] 0 +ILXD L1_PUTS [0 ] 0 +ILXD Fwd_GETX [0 ] 0 +ILXD Fwd_GETS [0 ] 0 +ILXD Fwd_DMA [0 ] 0 +ILXD Own_GETX [0 ] 0 +ILXD Inv [0 ] 0 +ILXD DmaAck [0 ] 0 +ILXD L2_Replacement [0 ] 0 + +ILOXD L1_GETS [0 ] 0 +ILOXD L1_GETX [0 ] 0 +ILOXD L1_PUTO [0 ] 0 +ILOXD L1_PUTX [0 ] 0 +ILOXD L1_PUTS_only [0 ] 0 +ILOXD L1_PUTS [0 ] 0 +ILOXD Fwd_GETX [0 ] 0 +ILOXD Fwd_GETS [0 ] 0 +ILOXD Fwd_DMA [0 ] 0 +ILOXD Own_GETX [0 ] 0 +ILOXD Inv [0 ] 0 +ILOXD DmaAck [0 ] 0 +ILOXD L2_Replacement [0 ] 0 + Memory controller: system.dir_cntrl0.memBuffer: memory_total_requests: 1308 memory_reads: 1114 @@ -1196,6 +1267,7 @@ Memory_Data [1114 ] 1114 Memory_Ack [194 ] 194 DMA_READ [0 ] 0 DMA_WRITE [0 ] 0 +DMA_ACK [0 ] 0 Data [0 ] 0 - Transitions - @@ -1376,4 +1448,22 @@ OI_D PUTO [0 ] 0 OI_D PUTO_SHARERS [0 ] 0 OI_D DMA_READ [0 ] 0 OI_D DMA_WRITE [0 ] 0 -OI_D Data
\ No newline at end of file +OI_D Data [0 ] 0 + +OD GETX [0 ] 0 +OD GETS [0 ] 0 +OD PUTX [0 ] 0 +OD PUTO [0 ] 0 +OD PUTO_SHARERS [0 ] 0 +OD DMA_READ [0 ] 0 +OD DMA_WRITE [0 ] 0 +OD DMA_ACK [0 ] 0 + +MD GETX [0 ] 0 +MD GETS [0 ] 0 +MD PUTX [0 ] 0 +MD PUTO [0 ] 0 +MD PUTO_SHARERS [0 ] 0 +MD DMA_READ [0 ] 0 +MD DMA_WRITE [0 ] 0 +MD DMA_ACK
\ No newline at end of file diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout index c4db03463..e906774aa 100755 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout @@ -5,10 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 8 2011 17:41:34 -M5 revision 685719afafe6+ 7938+ default tip brad/increase_ruby_mem_test_threshold qtip -M5 started Feb 8 2011 17:41:42 -M5 executing on SC2B0617 +M5 compiled Apr 19 2011 12:14:48 +M5 started Apr 19 2011 12:14:53 +M5 executing on maize command line: build/ALPHA_SE_MOESI_CMP_directory/m5.fast -d build/ALPHA_SE_MOESI_CMP_directory/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory -re tests/run.py build/ALPHA_SE_MOESI_CMP_directory/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt index e92c6159b..03c5a78bf 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 26297 # Simulator instruction rate (inst/s) -host_mem_usage 215668 # Number of bytes of host memory used -host_seconds 0.24 # Real time elapsed on the host -host_tick_rate 918519 # Simulator tick rate (ticks/s) +host_inst_rate 44214 # Simulator instruction rate (inst/s) +host_mem_usage 213512 # Number of bytes of host memory used +host_seconds 0.14 # Real time elapsed on the host +host_tick_rate 1544058 # Simulator tick rate (ticks/s) sim_freq 1000000000 # Frequency of simulated ticks sim_insts 6404 # Number of instructions simulated sim_seconds 0.000224 # Number of seconds simulated @@ -61,6 +61,6 @@ system.cpu.num_int_register_writes 4581 # nu system.cpu.num_load_insts 1192 # Number of load instructions system.cpu.num_mem_refs 2060 # number of memory refs system.cpu.num_store_insts 868 # Number of store instructions -system.cpu.workload.PROG:num_syscalls 17 # Number of system calls +system.cpu.workload.num_syscalls 17 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini index 2f2bf304c..f1fd9e728 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini @@ -63,7 +63,7 @@ egid=100 env= errout=cerr euid=100 -executable=tests/test-progs/hello/bin/alpha/linux/hello +executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/ruby.stats b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/ruby.stats index 0fc931dc4..6e05a4449 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/ruby.stats +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/ruby.stats @@ -34,7 +34,7 @@ periodic_stats_period: 1000000 ================ End RubySystem Configuration Print ================ -Real time: Mar/26/2011 22:00:44 +Real time: Apr/19/2011 12:17:16 Profiler Stats -------------- @@ -43,18 +43,18 @@ Elapsed_time_in_minutes: 0 Elapsed_time_in_hours: 0 Elapsed_time_in_days: 0 -Virtual_time_in_seconds: 0.23 -Virtual_time_in_minutes: 0.00383333 -Virtual_time_in_hours: 6.38889e-05 -Virtual_time_in_days: 2.66204e-06 +Virtual_time_in_seconds: 0.18 +Virtual_time_in_minutes: 0.003 +Virtual_time_in_hours: 5e-05 +Virtual_time_in_days: 2.08333e-06 Ruby_current_time: 217591 Ruby_start_time: 0 Ruby_cycles: 217591 -mbytes_resident: 38.1094 -mbytes_total: 199.473 -resident_ratio: 0.19107 +mbytes_resident: 38.9258 +mbytes_total: 208.391 +resident_ratio: 0.186811 ruby_cycles_executed: [ 217592 ] @@ -127,7 +127,7 @@ Resource Usage page_size: 4096 user_time: 0 system_time: 0 -page_reclaims: 10053 +page_reclaims: 10260 page_faults: 0 swaps: 0 block_inputs: 0 diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout index 97520046b..b93a9ba34 100755 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout @@ -5,9 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Mar 26 2011 14:06:20 -M5 started Mar 26 2011 22:00:43 -M5 executing on phenom +M5 compiled Apr 19 2011 12:17:10 +M5 started Apr 19 2011 12:17:16 +M5 executing on maize command line: build/ALPHA_SE_MOESI_CMP_token/m5.fast -d build/ALPHA_SE_MOESI_CMP_token/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token -re tests/run.py build/ALPHA_SE_MOESI_CMP_token/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt index fd6cdb90f..a40ed048f 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 21360 # Simulator instruction rate (inst/s) -host_mem_usage 204264 # Number of bytes of host memory used -host_seconds 0.30 # Real time elapsed on the host -host_tick_rate 725351 # Simulator tick rate (ticks/s) +host_inst_rate 82829 # Simulator instruction rate (inst/s) +host_mem_usage 213396 # Number of bytes of host memory used +host_seconds 0.08 # Real time elapsed on the host +host_tick_rate 2809629 # Simulator tick rate (ticks/s) sim_freq 1000000000 # Frequency of simulated ticks sim_insts 6404 # Number of instructions simulated sim_seconds 0.000218 # Number of seconds simulated @@ -61,6 +61,6 @@ system.cpu.num_int_register_writes 4581 # nu system.cpu.num_load_insts 1192 # Number of load instructions system.cpu.num_mem_refs 2060 # number of memory refs system.cpu.num_store_insts 868 # Number of store instructions -system.cpu.workload.PROG:num_syscalls 17 # Number of system calls +system.cpu.workload.num_syscalls 17 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini index b25662a67..2dfe81c60 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini @@ -63,7 +63,7 @@ egid=100 env= errout=cerr euid=100 -executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/linux/hello +executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello gid=100 input=cin max_stack_size=67108864 @@ -184,6 +184,7 @@ deadlock_threshold=500000 icache=system.ruby.cpu_ruby_ports.icache max_outstanding_requests=16 physmem=system.physmem +using_network_tester=false using_ruby_tester=false version=0 physMemPort=system.physmem.port[0] diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/ruby.stats b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/ruby.stats index afe766dd7..e78377434 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/ruby.stats +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/ruby.stats @@ -34,7 +34,7 @@ periodic_stats_period: 1000000 ================ End RubySystem Configuration Print ================ -Real time: Feb/08/2011 17:57:03 +Real time: Apr/19/2011 12:10:00 Profiler Stats -------------- @@ -43,18 +43,18 @@ Elapsed_time_in_minutes: 0 Elapsed_time_in_hours: 0 Elapsed_time_in_days: 0 -Virtual_time_in_seconds: 0.42 -Virtual_time_in_minutes: 0.007 -Virtual_time_in_hours: 0.000116667 -Virtual_time_in_days: 4.86111e-06 +Virtual_time_in_seconds: 0.18 +Virtual_time_in_minutes: 0.003 +Virtual_time_in_hours: 5e-05 +Virtual_time_in_days: 2.08333e-06 Ruby_current_time: 208400 Ruby_start_time: 0 Ruby_cycles: 208400 -mbytes_resident: 36.6641 -mbytes_total: 209.902 -resident_ratio: 0.174709 +mbytes_resident: 38.6719 +mbytes_total: 208.031 +resident_ratio: 0.185913 ruby_cycles_executed: [ 208401 ] @@ -70,9 +70,9 @@ sequencer_requests_outstanding: [binsize: 1 max: 1 count: 8465 average: 1 | All Non-Zero Cycle Demand Cache Accesses ---------------------------------------- miss_latency: [binsize: 2 max: 340 count: 8464 average: 23.6219 | standard deviation: 54.4451 | 0 7102 0 0 0 0 203 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 81 188 166 188 149 272 6 5 3 5 20 2 4 9 1 15 3 1 0 0 1 1 0 3 2 1 0 1 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 2 3 18 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 ] -miss_latency_IFETCH: [binsize: 2 max: 206 count: 6414 average: 15.8564 | standard deviation: 43.57 | 0 5768 0 0 0 0 65 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 43 102 56 91 98 150 4 2 2 2 14 0 0 5 1 7 2 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] miss_latency_LD: [binsize: 2 max: 327 count: 1185 average: 57.3924 | standard deviation: 73.6654 | 0 660 0 0 0 0 105 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 37 78 73 59 44 91 2 3 1 3 5 2 2 3 0 6 1 0 0 0 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 ] miss_latency_ST: [binsize: 2 max: 340 count: 865 average: 34.9399 | standard deviation: 73.2706 | 0 674 0 0 0 0 33 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 8 37 38 7 31 0 0 0 0 1 0 2 1 0 2 0 1 0 0 0 1 0 2 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 3 17 0 0 0 0 0 0 0 0 0 1 ] +miss_latency_IFETCH: [binsize: 2 max: 206 count: 6414 average: 15.8564 | standard deviation: 43.57 | 0 5768 0 0 0 0 65 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 43 102 56 91 98 150 4 2 2 2 14 0 0 5 1 7 2 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] miss_latency_L1Cache: [binsize: 1 max: 2 count: 7102 average: 2 | standard deviation: 0 | 0 0 7102 ] miss_latency_L2Cache: [binsize: 1 max: 13 count: 203 average: 13 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 203 ] miss_latency_Directory: [binsize: 2 max: 340 count: 1159 average: 157.975 | standard deviation: 26.6537 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 81 188 166 188 149 272 6 5 3 5 20 2 4 9 1 15 3 1 0 0 1 1 0 3 2 1 0 1 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 2 3 18 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 ] @@ -86,15 +86,15 @@ miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 1 average: miss_latency_dir_forward_to_first_response: [binsize: 1 max: 158 count: 1 average: 158 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] miss_latency_dir_first_response_to_completion: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ] imcomplete_dir_Times: 1158 -miss_latency_IFETCH_L1Cache: [binsize: 1 max: 2 count: 5768 average: 2 | standard deviation: 0 | 0 0 5768 ] -miss_latency_IFETCH_L2Cache: [binsize: 1 max: 13 count: 65 average: 13 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 65 ] -miss_latency_IFETCH_Directory: [binsize: 2 max: 206 count: 581 average: 153.738 | standard deviation: 5.93543 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 43 102 56 91 98 150 4 2 2 2 14 0 0 5 1 7 2 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] miss_latency_LD_L1Cache: [binsize: 1 max: 2 count: 660 average: 2 | standard deviation: 0 | 0 0 660 ] miss_latency_LD_L2Cache: [binsize: 1 max: 13 count: 105 average: 13 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 105 ] miss_latency_LD_Directory: [binsize: 2 max: 327 count: 420 average: 155.536 | standard deviation: 18.768 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 37 78 73 59 44 91 2 3 1 3 5 2 2 3 0 6 1 0 0 0 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 ] miss_latency_ST_L1Cache: [binsize: 1 max: 2 count: 674 average: 2 | standard deviation: 0 | 0 0 674 ] miss_latency_ST_L2Cache: [binsize: 1 max: 13 count: 33 average: 13 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 33 ] miss_latency_ST_Directory: [binsize: 2 max: 340 count: 158 average: 180.038 | standard deviation: 59.9794 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 8 37 38 7 31 0 0 0 0 1 0 2 1 0 2 0 1 0 0 0 1 0 2 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 3 17 0 0 0 0 0 0 0 0 0 1 ] +miss_latency_IFETCH_L1Cache: [binsize: 1 max: 2 count: 5768 average: 2 | standard deviation: 0 | 0 0 5768 ] +miss_latency_IFETCH_L2Cache: [binsize: 1 max: 13 count: 65 average: 13 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 65 ] +miss_latency_IFETCH_Directory: [binsize: 2 max: 206 count: 581 average: 153.738 | standard deviation: 5.93543 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 43 102 56 91 98 150 4 2 2 2 14 0 0 5 1 7 2 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] All Non-Zero Cycle SW Prefetch Requests ------------------------------------ @@ -126,11 +126,11 @@ Resource Usage page_size: 4096 user_time: 0 system_time: 0 -page_reclaims: 10608 +page_reclaims: 10195 page_faults: 0 swaps: 0 block_inputs: 0 -block_outputs: 0 +block_outputs: 64 Network Stats ------------- @@ -190,7 +190,7 @@ Cache Stats: system.ruby.cpu_ruby_ports.icache system.ruby.cpu_ruby_ports.icache_request_type_IFETCH: 100% - system.ruby.cpu_ruby_ports.icache_access_mode_type_SupervisorMode: 646 100% + system.ruby.cpu_ruby_ports.icache_access_mode_type_Supervisor: 646 100% Cache Stats: system.ruby.cpu_ruby_ports.dcache system.ruby.cpu_ruby_ports.dcache_total_misses: 716 @@ -202,7 +202,7 @@ Cache Stats: system.ruby.cpu_ruby_ports.dcache system.ruby.cpu_ruby_ports.dcache_request_type_LD: 73.324% system.ruby.cpu_ruby_ports.dcache_request_type_ST: 26.676% - system.ruby.cpu_ruby_ports.dcache_access_mode_type_SupervisorMode: 716 100% + system.ruby.cpu_ruby_ports.dcache_access_mode_type_Supervisor: 716 100% Cache Stats: system.l1_cntrl0.L2cacheMemory system.l1_cntrl0.L2cacheMemory_total_misses: 1362 @@ -215,7 +215,7 @@ Cache Stats: system.l1_cntrl0.L2cacheMemory system.l1_cntrl0.L2cacheMemory_request_type_ST: 14.0235% system.l1_cntrl0.L2cacheMemory_request_type_IFETCH: 47.4302% - system.l1_cntrl0.L2cacheMemory_access_mode_type_SupervisorMode: 1362 100% + system.l1_cntrl0.L2cacheMemory_access_mode_type_Supervisor: 1362 100% --- L1Cache --- - Event Counts - @@ -242,6 +242,8 @@ Writeback_Ack [1143 ] 1143 Writeback_Nack [0 ] 0 All_acks [0 ] 0 All_acks_no_sharers [1159 ] 1159 +Flush_line [0 ] 0 +Block_Ack [0 ] 0 - Transitions - I Load [420 ] 420 @@ -256,6 +258,7 @@ I Other_GETS [0 ] 0 I Other_GETS_No_Mig [0 ] 0 I NC_DMA_GETS [0 ] 0 I Invalidate [0 ] 0 +I Flush_line [0 ] 0 S Load [0 ] 0 S Ifetch [0 ] 0 @@ -269,6 +272,7 @@ S Other_GETS [0 ] 0 S Other_GETS_No_Mig [0 ] 0 S NC_DMA_GETS [0 ] 0 S Invalidate [0 ] 0 +S Flush_line [0 ] 0 O Load [0 ] 0 O Ifetch [0 ] 0 @@ -283,6 +287,7 @@ O Merged_GETS [0 ] 0 O Other_GETS_No_Mig [0 ] 0 O NC_DMA_GETS [0 ] 0 O Invalidate [0 ] 0 +O Flush_line [0 ] 0 M Load [368 ] 368 M Ifetch [5833 ] 5833 @@ -297,6 +302,7 @@ M Merged_GETS [0 ] 0 M Other_GETS_No_Mig [0 ] 0 M NC_DMA_GETS [0 ] 0 M Invalidate [0 ] 0 +M Flush_line [0 ] 0 MM Load [397 ] 397 MM Ifetch [0 ] 0 @@ -311,6 +317,7 @@ MM Merged_GETS [0 ] 0 MM Other_GETS_No_Mig [0 ] 0 MM NC_DMA_GETS [0 ] 0 MM Invalidate [0 ] 0 +MM Flush_line [0 ] 0 IM Load [0 ] 0 IM Ifetch [0 ] 0 @@ -325,6 +332,7 @@ IM Invalidate [0 ] 0 IM Ack [0 ] 0 IM Data [0 ] 0 IM Exclusive_Data [158 ] 158 +IM Flush_line [0 ] 0 SM Load [0 ] 0 SM Ifetch [0 ] 0 @@ -339,6 +347,7 @@ SM Invalidate [0 ] 0 SM Ack [0 ] 0 SM Data [0 ] 0 SM Exclusive_Data [0 ] 0 +SM Flush_line [0 ] 0 OM Load [0 ] 0 OM Ifetch [0 ] 0 @@ -354,6 +363,7 @@ OM Invalidate [0 ] 0 OM Ack [0 ] 0 OM All_acks [0 ] 0 OM All_acks_no_sharers [0 ] 0 +OM Flush_line [0 ] 0 ISM Load [0 ] 0 ISM Ifetch [0 ] 0 @@ -362,6 +372,7 @@ ISM L2_Replacement [0 ] 0 ISM L1_to_L2 [0 ] 0 ISM Ack [0 ] 0 ISM All_acks_no_sharers [0 ] 0 +ISM Flush_line [0 ] 0 M_W Load [0 ] 0 M_W Ifetch [0 ] 0 @@ -370,6 +381,7 @@ M_W L2_Replacement [0 ] 0 M_W L1_to_L2 [0 ] 0 M_W Ack [0 ] 0 M_W All_acks_no_sharers [1001 ] 1001 +M_W Flush_line [0 ] 0 MM_W Load [0 ] 0 MM_W Ifetch [0 ] 0 @@ -378,6 +390,7 @@ MM_W L2_Replacement [0 ] 0 MM_W L1_to_L2 [0 ] 0 MM_W Ack [0 ] 0 MM_W All_acks_no_sharers [158 ] 158 +MM_W Flush_line [0 ] 0 IS Load [0 ] 0 IS Ifetch [0 ] 0 @@ -394,6 +407,7 @@ IS Shared_Ack [0 ] 0 IS Data [0 ] 0 IS Shared_Data [0 ] 0 IS Exclusive_Data [1001 ] 1001 +IS Flush_line [0 ] 0 SS Load [0 ] 0 SS Ifetch [0 ] 0 @@ -404,6 +418,7 @@ SS Ack [0 ] 0 SS Shared_Ack [0 ] 0 SS All_acks [0 ] 0 SS All_acks_no_sharers [0 ] 0 +SS Flush_line [0 ] 0 OI Load [0 ] 0 OI Ifetch [0 ] 0 @@ -417,6 +432,7 @@ OI Other_GETS_No_Mig [0 ] 0 OI NC_DMA_GETS [0 ] 0 OI Invalidate [0 ] 0 OI Writeback_Ack [0 ] 0 +OI Flush_line [0 ] 0 MI Load [8 ] 8 MI Ifetch [11 ] 11 @@ -430,6 +446,7 @@ MI Other_GETS_No_Mig [0 ] 0 MI NC_DMA_GETS [0 ] 0 MI Invalidate [0 ] 0 MI Writeback_Ack [1143 ] 1143 +MI Flush_line [0 ] 0 II Load [0 ] 0 II Ifetch [0 ] 0 @@ -443,6 +460,7 @@ II NC_DMA_GETS [0 ] 0 II Invalidate [0 ] 0 II Writeback_Ack [0 ] 0 II Writeback_Nack [0 ] 0 +II Flush_line [0 ] 0 IT Load [0 ] 0 IT Ifetch [0 ] 0 @@ -456,6 +474,7 @@ IT Merged_GETS [0 ] 0 IT Other_GETS_No_Mig [0 ] 0 IT NC_DMA_GETS [0 ] 0 IT Invalidate [0 ] 0 +IT Flush_line [0 ] 0 ST Load [0 ] 0 ST Ifetch [0 ] 0 @@ -469,6 +488,7 @@ ST Merged_GETS [0 ] 0 ST Other_GETS_No_Mig [0 ] 0 ST NC_DMA_GETS [0 ] 0 ST Invalidate [0 ] 0 +ST Flush_line [0 ] 0 OT Load [0 ] 0 OT Ifetch [0 ] 0 @@ -482,6 +502,7 @@ OT Merged_GETS [0 ] 0 OT Other_GETS_No_Mig [0 ] 0 OT NC_DMA_GETS [0 ] 0 OT Invalidate [0 ] 0 +OT Flush_line [0 ] 0 MT Load [0 ] 0 MT Ifetch [0 ] 0 @@ -495,6 +516,7 @@ MT Merged_GETS [0 ] 0 MT Other_GETS_No_Mig [0 ] 0 MT NC_DMA_GETS [0 ] 0 MT Invalidate [0 ] 0 +MT Flush_line [0 ] 0 MMT Load [0 ] 0 MMT Ifetch [0 ] 0 @@ -508,6 +530,94 @@ MMT Merged_GETS [0 ] 0 MMT Other_GETS_No_Mig [0 ] 0 MMT NC_DMA_GETS [0 ] 0 MMT Invalidate [0 ] 0 +MMT Flush_line [0 ] 0 + +MI_F Load [0 ] 0 +MI_F Ifetch [0 ] 0 +MI_F Store [0 ] 0 +MI_F L1_to_L2 [0 ] 0 +MI_F Writeback_Ack [0 ] 0 +MI_F Flush_line [0 ] 0 + +MM_F Load [0 ] 0 +MM_F Ifetch [0 ] 0 +MM_F Store [0 ] 0 +MM_F L1_to_L2 [0 ] 0 +MM_F Other_GETX [0 ] 0 +MM_F Other_GETS [0 ] 0 +MM_F Merged_GETS [0 ] 0 +MM_F Other_GETS_No_Mig [0 ] 0 +MM_F NC_DMA_GETS [0 ] 0 +MM_F Invalidate [0 ] 0 +MM_F Ack [0 ] 0 +MM_F All_acks [0 ] 0 +MM_F All_acks_no_sharers [0 ] 0 +MM_F Flush_line [0 ] 0 +MM_F Block_Ack [0 ] 0 + +IM_F Load [0 ] 0 +IM_F Ifetch [0 ] 0 +IM_F Store [0 ] 0 +IM_F L2_Replacement [0 ] 0 +IM_F L1_to_L2 [0 ] 0 +IM_F Other_GETX [0 ] 0 +IM_F Other_GETS [0 ] 0 +IM_F Other_GETS_No_Mig [0 ] 0 +IM_F NC_DMA_GETS [0 ] 0 +IM_F Invalidate [0 ] 0 +IM_F Ack [0 ] 0 +IM_F Data [0 ] 0 +IM_F Exclusive_Data [0 ] 0 +IM_F Flush_line [0 ] 0 + +ISM_F Load [0 ] 0 +ISM_F Ifetch [0 ] 0 +ISM_F Store [0 ] 0 +ISM_F L2_Replacement [0 ] 0 +ISM_F L1_to_L2 [0 ] 0 +ISM_F Ack [0 ] 0 +ISM_F All_acks_no_sharers [0 ] 0 +ISM_F Flush_line [0 ] 0 + +SM_F Load [0 ] 0 +SM_F Ifetch [0 ] 0 +SM_F Store [0 ] 0 +SM_F L2_Replacement [0 ] 0 +SM_F L1_to_L2 [0 ] 0 +SM_F Other_GETX [0 ] 0 +SM_F Other_GETS [0 ] 0 +SM_F Other_GETS_No_Mig [0 ] 0 +SM_F NC_DMA_GETS [0 ] 0 +SM_F Invalidate [0 ] 0 +SM_F Ack [0 ] 0 +SM_F Data [0 ] 0 +SM_F Exclusive_Data [0 ] 0 +SM_F Flush_line [0 ] 0 + +OM_F Load [0 ] 0 +OM_F Ifetch [0 ] 0 +OM_F Store [0 ] 0 +OM_F L2_Replacement [0 ] 0 +OM_F L1_to_L2 [0 ] 0 +OM_F Other_GETX [0 ] 0 +OM_F Other_GETS [0 ] 0 +OM_F Merged_GETS [0 ] 0 +OM_F Other_GETS_No_Mig [0 ] 0 +OM_F NC_DMA_GETS [0 ] 0 +OM_F Invalidate [0 ] 0 +OM_F Ack [0 ] 0 +OM_F All_acks [0 ] 0 +OM_F All_acks_no_sharers [0 ] 0 +OM_F Flush_line [0 ] 0 + +MM_WF Load [0 ] 0 +MM_WF Ifetch [0 ] 0 +MM_WF Store [0 ] 0 +MM_WF L2_Replacement [0 ] 0 +MM_WF L1_to_L2 [0 ] 0 +MM_WF Ack [0 ] 0 +MM_WF All_acks_no_sharers [0 ] 0 +MM_WF Flush_line [0 ] 0 Cache Stats: system.dir_cntrl0.probeFilter system.dir_cntrl0.probeFilter_total_misses: 0 @@ -563,6 +673,8 @@ All_acks_and_shared_data [0 ] 0 All_acks_and_owner_data [0 ] 0 All_acks_and_data_no_sharers [0 ] 0 All_Unblocks [0 ] 0 +GETF [0 ] 0 +PUTF [0 ] 0 - Transitions - NX GETX [0 ] 0 @@ -571,6 +683,7 @@ NX PUT [0 ] 0 NX Pf_Replacement [0 ] 0 NX DMA_READ [0 ] 0 NX DMA_WRITE [0 ] 0 +NX GETF [0 ] 0 NO GETX [0 ] 0 NO GETS [0 ] 0 @@ -578,6 +691,7 @@ NO PUT [1143 ] 1143 NO Pf_Replacement [0 ] 0 NO DMA_READ [0 ] 0 NO DMA_WRITE [0 ] 0 +NO GETF [0 ] 0 S GETX [0 ] 0 S GETS [0 ] 0 @@ -585,6 +699,7 @@ S PUT [0 ] 0 S Pf_Replacement [0 ] 0 S DMA_READ [0 ] 0 S DMA_WRITE [0 ] 0 +S GETF [0 ] 0 O GETX [0 ] 0 O GETS [0 ] 0 @@ -592,12 +707,14 @@ O PUT [0 ] 0 O Pf_Replacement [0 ] 0 O DMA_READ [0 ] 0 O DMA_WRITE [0 ] 0 +O GETF [0 ] 0 E GETX [158 ] 158 E GETS [1001 ] 1001 E PUT [0 ] 0 E DMA_READ [0 ] 0 E DMA_WRITE [0 ] 0 +E GETF [0 ] 0 O_R GETX [0 ] 0 O_R GETS [0 ] 0 @@ -607,6 +724,7 @@ O_R DMA_READ [0 ] 0 O_R DMA_WRITE [0 ] 0 O_R Ack [0 ] 0 O_R All_acks_and_data_no_sharers [0 ] 0 +O_R GETF [0 ] 0 S_R GETX [0 ] 0 S_R GETS [0 ] 0 @@ -617,6 +735,7 @@ S_R DMA_WRITE [0 ] 0 S_R Ack [0 ] 0 S_R Data [0 ] 0 S_R All_acks_and_data_no_sharers [0 ] 0 +S_R GETF [0 ] 0 NO_R GETX [0 ] 0 NO_R GETS [0 ] 0 @@ -628,6 +747,7 @@ NO_R Ack [0 ] 0 NO_R Data [0 ] 0 NO_R Exclusive_Data [0 ] 0 NO_R All_acks_and_data_no_sharers [0 ] 0 +NO_R GETF [0 ] 0 NO_B GETX [0 ] 0 NO_B GETS [0 ] 0 @@ -637,6 +757,7 @@ NO_B UnblockM [1159 ] 1159 NO_B Pf_Replacement [0 ] 0 NO_B DMA_READ [0 ] 0 NO_B DMA_WRITE [0 ] 0 +NO_B GETF [0 ] 0 NO_B_X GETX [0 ] 0 NO_B_X GETS [0 ] 0 @@ -646,6 +767,7 @@ NO_B_X UnblockM [0 ] 0 NO_B_X Pf_Replacement [0 ] 0 NO_B_X DMA_READ [0 ] 0 NO_B_X DMA_WRITE [0 ] 0 +NO_B_X GETF [0 ] 0 NO_B_S GETX [0 ] 0 NO_B_S GETS [0 ] 0 @@ -655,6 +777,7 @@ NO_B_S UnblockM [0 ] 0 NO_B_S Pf_Replacement [0 ] 0 NO_B_S DMA_READ [0 ] 0 NO_B_S DMA_WRITE [0 ] 0 +NO_B_S GETF [0 ] 0 NO_B_S_W GETX [0 ] 0 NO_B_S_W GETS [0 ] 0 @@ -664,6 +787,7 @@ NO_B_S_W Pf_Replacement [0 ] 0 NO_B_S_W DMA_READ [0 ] 0 NO_B_S_W DMA_WRITE [0 ] 0 NO_B_S_W All_Unblocks [0 ] 0 +NO_B_S_W GETF [0 ] 0 O_B GETX [0 ] 0 O_B GETS [0 ] 0 @@ -673,6 +797,7 @@ O_B UnblockM [0 ] 0 O_B Pf_Replacement [0 ] 0 O_B DMA_READ [0 ] 0 O_B DMA_WRITE [0 ] 0 +O_B GETF [0 ] 0 NO_B_W GETX [0 ] 0 NO_B_W GETS [0 ] 0 @@ -683,6 +808,7 @@ NO_B_W Pf_Replacement [0 ] 0 NO_B_W DMA_READ [0 ] 0 NO_B_W DMA_WRITE [0 ] 0 NO_B_W Memory_Data [1159 ] 1159 +NO_B_W GETF [0 ] 0 O_B_W GETX [0 ] 0 O_B_W GETS [0 ] 0 @@ -692,6 +818,7 @@ O_B_W Pf_Replacement [0 ] 0 O_B_W DMA_READ [0 ] 0 O_B_W DMA_WRITE [0 ] 0 O_B_W Memory_Data [0 ] 0 +O_B_W GETF [0 ] 0 NO_W GETX [0 ] 0 NO_W GETS [0 ] 0 @@ -700,6 +827,7 @@ NO_W Pf_Replacement [0 ] 0 NO_W DMA_READ [0 ] 0 NO_W DMA_WRITE [0 ] 0 NO_W Memory_Data [0 ] 0 +NO_W GETF [0 ] 0 O_W GETX [0 ] 0 O_W GETS [0 ] 0 @@ -708,6 +836,7 @@ O_W Pf_Replacement [0 ] 0 O_W DMA_READ [0 ] 0 O_W DMA_WRITE [0 ] 0 O_W Memory_Data [0 ] 0 +O_W GETF [0 ] 0 NO_DW_B_W GETX [0 ] 0 NO_DW_B_W GETS [0 ] 0 @@ -719,6 +848,7 @@ NO_DW_B_W Ack [0 ] 0 NO_DW_B_W Data [0 ] 0 NO_DW_B_W Exclusive_Data [0 ] 0 NO_DW_B_W All_acks_and_data_no_sharers [0 ] 0 +NO_DW_B_W GETF [0 ] 0 NO_DR_B_W GETX [0 ] 0 NO_DR_B_W GETS [0 ] 0 @@ -732,6 +862,7 @@ NO_DR_B_W Shared_Ack [0 ] 0 NO_DR_B_W Shared_Data [0 ] 0 NO_DR_B_W Data [0 ] 0 NO_DR_B_W Exclusive_Data [0 ] 0 +NO_DR_B_W GETF [0 ] 0 NO_DR_B_D GETX [0 ] 0 NO_DR_B_D GETS [0 ] 0 @@ -747,6 +878,7 @@ NO_DR_B_D Exclusive_Data [0 ] 0 NO_DR_B_D All_acks_and_shared_data [0 ] 0 NO_DR_B_D All_acks_and_owner_data [0 ] 0 NO_DR_B_D All_acks_and_data_no_sharers [0 ] 0 +NO_DR_B_D GETF [0 ] 0 NO_DR_B GETX [0 ] 0 NO_DR_B GETS [0 ] 0 @@ -762,6 +894,7 @@ NO_DR_B Exclusive_Data [0 ] 0 NO_DR_B All_acks_and_shared_data [0 ] 0 NO_DR_B All_acks_and_owner_data [0 ] 0 NO_DR_B All_acks_and_data_no_sharers [0 ] 0 +NO_DR_B GETF [0 ] 0 NO_DW_W GETX [0 ] 0 NO_DW_W GETS [0 ] 0 @@ -770,6 +903,7 @@ NO_DW_W Pf_Replacement [0 ] 0 NO_DW_W DMA_READ [0 ] 0 NO_DW_W DMA_WRITE [0 ] 0 NO_DW_W Memory_Ack [0 ] 0 +NO_DW_W GETF [0 ] 0 O_DR_B_W GETX [0 ] 0 O_DR_B_W GETS [0 ] 0 @@ -780,6 +914,7 @@ O_DR_B_W DMA_WRITE [0 ] 0 O_DR_B_W Memory_Data [0 ] 0 O_DR_B_W Ack [0 ] 0 O_DR_B_W Shared_Ack [0 ] 0 +O_DR_B_W GETF [0 ] 0 O_DR_B GETX [0 ] 0 O_DR_B GETS [0 ] 0 @@ -791,6 +926,7 @@ O_DR_B Ack [0 ] 0 O_DR_B Shared_Ack [0 ] 0 O_DR_B All_acks_and_owner_data [0 ] 0 O_DR_B All_acks_and_data_no_sharers [0 ] 0 +O_DR_B GETF [0 ] 0 WB GETX [27 ] 27 WB GETS [19 ] 19 @@ -803,6 +939,7 @@ WB Writeback_Exclusive_Dirty [220 ] 220 WB Pf_Replacement [0 ] 0 WB DMA_READ [0 ] 0 WB DMA_WRITE [0 ] 0 +WB GETF [0 ] 0 WB_O_W GETX [0 ] 0 WB_O_W GETS [0 ] 0 @@ -811,6 +948,7 @@ WB_O_W Pf_Replacement [0 ] 0 WB_O_W DMA_READ [0 ] 0 WB_O_W DMA_WRITE [0 ] 0 WB_O_W Memory_Ack [0 ] 0 +WB_O_W GETF [0 ] 0 WB_E_W GETX [4 ] 4 WB_E_W GETS [7 ] 7 @@ -818,4 +956,22 @@ WB_E_W PUT [0 ] 0 WB_E_W Pf_Replacement [0 ] 0 WB_E_W DMA_READ [0 ] 0 WB_E_W DMA_WRITE [0 ] 0 -WB_E_W Memory_Ack
\ No newline at end of file +WB_E_W Memory_Ack [220 ] 220 +WB_E_W GETF [0 ] 0 + +NO_F GETX [0 ] 0 +NO_F GETS [0 ] 0 +NO_F PUT [0 ] 0 +NO_F UnblockM [0 ] 0 +NO_F Pf_Replacement [0 ] 0 +NO_F GETF [0 ] 0 +NO_F PUTF [0 ] 0 + +NO_F_W GETX [0 ] 0 +NO_F_W GETS [0 ] 0 +NO_F_W PUT [0 ] 0 +NO_F_W Pf_Replacement [0 ] 0 +NO_F_W DMA_READ [0 ] 0 +NO_F_W DMA_WRITE [0 ] 0 +NO_F_W Memory_Data [0 ] 0 +NO_F_W GETF
\ No newline at end of file diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout index 968d521e0..8cd875f7c 100755 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout @@ -5,10 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 8 2011 17:56:59 -M5 revision 685719afafe6+ 7938+ default tip brad/increase_ruby_mem_test_threshold qtip -M5 started Feb 8 2011 17:57:03 -M5 executing on SC2B0617 +M5 compiled Apr 19 2011 12:09:47 +M5 started Apr 19 2011 12:10:00 +M5 executing on maize command line: build/ALPHA_SE_MOESI_hammer/m5.fast -d build/ALPHA_SE_MOESI_hammer/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer -re tests/run.py build/ALPHA_SE_MOESI_hammer/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt index 5f06bc32c..bbdd232d4 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 50833 # Simulator instruction rate (inst/s) -host_mem_usage 214944 # Number of bytes of host memory used -host_seconds 0.13 # Real time elapsed on the host -host_tick_rate 1651975 # Simulator tick rate (ticks/s) +host_inst_rate 81916 # Simulator instruction rate (inst/s) +host_mem_usage 213028 # Number of bytes of host memory used +host_seconds 0.08 # Real time elapsed on the host +host_tick_rate 2661098 # Simulator tick rate (ticks/s) sim_freq 1000000000 # Frequency of simulated ticks sim_insts 6404 # Number of instructions simulated sim_seconds 0.000208 # Number of seconds simulated @@ -61,6 +61,6 @@ system.cpu.num_int_register_writes 4581 # nu system.cpu.num_load_insts 1192 # Number of load instructions system.cpu.num_mem_refs 2060 # number of memory refs system.cpu.num_store_insts 868 # Number of store instructions -system.cpu.workload.PROG:num_syscalls 17 # Number of system calls +system.cpu.workload.num_syscalls 17 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini index 5053e806a..dd1e9cef6 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini @@ -160,6 +160,7 @@ deadlock_threshold=500000 icache=system.ruby.cpu_ruby_ports.dcache max_outstanding_requests=16 physmem=system.physmem +using_network_tester=false using_ruby_tester=false version=0 physMemPort=system.physmem.port[0] diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/ruby.stats b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/ruby.stats index a6219b7a9..4874f85a0 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/ruby.stats +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/ruby.stats @@ -34,27 +34,27 @@ periodic_stats_period: 1000000 ================ End RubySystem Configuration Print ================ -Real time: Feb/07/2011 01:47:49 +Real time: Apr/19/2011 11:58:50 Profiler Stats -------------- -Elapsed_time_in_seconds: 1 -Elapsed_time_in_minutes: 0.0166667 -Elapsed_time_in_hours: 0.000277778 -Elapsed_time_in_days: 1.15741e-05 +Elapsed_time_in_seconds: 0 +Elapsed_time_in_minutes: 0 +Elapsed_time_in_hours: 0 +Elapsed_time_in_days: 0 -Virtual_time_in_seconds: 0.35 -Virtual_time_in_minutes: 0.00583333 -Virtual_time_in_hours: 9.72222e-05 -Virtual_time_in_days: 4.05093e-06 +Virtual_time_in_seconds: 0.17 +Virtual_time_in_minutes: 0.00283333 +Virtual_time_in_hours: 4.72222e-05 +Virtual_time_in_days: 1.96759e-06 Ruby_current_time: 342698 Ruby_start_time: 0 Ruby_cycles: 342698 -mbytes_resident: 37.7383 -mbytes_total: 227.77 -resident_ratio: 0.165703 +mbytes_resident: 38.5859 +mbytes_total: 208.09 +resident_ratio: 0.185448 ruby_cycles_executed: [ 342699 ] @@ -70,9 +70,9 @@ sequencer_requests_outstanding: [binsize: 1 max: 1 count: 8465 average: 1 | All Non-Zero Cycle Demand Cache Accesses ---------------------------------------- miss_latency: [binsize: 2 max: 377 count: 8464 average: 39.4889 | standard deviation: 72.9776 | 0 6734 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 6 1 3 6 0 334 211 182 529 243 4 4 0 5 2 15 9 4 14 10 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 30 18 15 24 37 2 3 0 0 2 2 1 1 3 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 ] -miss_latency_IFETCH: [binsize: 2 max: 285 count: 6414 average: 23.2806 | standard deviation: 57.2661 | 0 5684 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 3 1 2 4 0 155 91 77 220 92 2 3 0 1 2 2 6 1 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 20 9 5 10 12 2 1 0 0 1 2 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] miss_latency_LD: [binsize: 2 max: 375 count: 1185 average: 110.608 | standard deviation: 87.0282 | 0 458 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 3 0 1 2 0 147 90 74 255 81 2 1 0 3 0 12 3 1 9 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 4 2 11 4 0 2 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 ] miss_latency_ST: [binsize: 2 max: 377 count: 865 average: 62.2439 | standard deviation: 89.6671 | 0 592 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 32 30 31 54 70 0 0 0 1 0 1 0 2 2 4 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 5 8 3 21 0 0 0 0 0 0 0 1 2 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 ] +miss_latency_IFETCH: [binsize: 2 max: 285 count: 6414 average: 23.2806 | standard deviation: 57.2661 | 0 5684 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 3 1 2 4 0 155 91 77 220 92 2 3 0 1 2 2 6 1 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 20 9 5 10 12 2 1 0 0 1 2 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] miss_latency_L1Cache: [binsize: 1 max: 3 count: 6734 average: 3 | standard deviation: 0 | 0 0 0 6734 ] miss_latency_Directory: [binsize: 2 max: 377 count: 1730 average: 181.521 | standard deviation: 26.4115 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 6 1 3 6 0 334 211 182 529 243 4 4 0 5 2 15 9 4 14 10 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 30 18 15 24 37 2 3 0 0 2 2 1 1 3 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 ] miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] @@ -85,12 +85,12 @@ miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 1 average: miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ] miss_latency_dir_first_response_to_completion: [binsize: 1 max: 159 count: 1 average: 159 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] imcomplete_dir_Times: 1729 -miss_latency_IFETCH_L1Cache: [binsize: 1 max: 3 count: 5684 average: 3 | standard deviation: 0 | 0 0 0 5684 ] -miss_latency_IFETCH_Directory: [binsize: 2 max: 285 count: 730 average: 181.192 | standard deviation: 25.9199 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 3 1 2 4 0 155 91 77 220 92 2 3 0 1 2 2 6 1 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 20 9 5 10 12 2 1 0 0 1 2 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] miss_latency_LD_L1Cache: [binsize: 1 max: 3 count: 458 average: 3 | standard deviation: 0 | 0 0 0 458 ] miss_latency_LD_Directory: [binsize: 2 max: 375 count: 727 average: 178.4 | standard deviation: 21.0913 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 3 0 1 2 0 147 90 74 255 81 2 1 0 3 0 12 3 1 9 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 4 2 11 4 0 2 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 ] miss_latency_ST_L1Cache: [binsize: 1 max: 3 count: 592 average: 3 | standard deviation: 0 | 0 0 0 592 ] miss_latency_ST_Directory: [binsize: 2 max: 377 count: 273 average: 190.714 | standard deviation: 36.5384 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 32 30 31 54 70 0 0 0 1 0 1 0 2 2 4 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 5 8 3 21 0 0 0 0 0 0 0 1 2 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 ] +miss_latency_IFETCH_L1Cache: [binsize: 1 max: 3 count: 5684 average: 3 | standard deviation: 0 | 0 0 0 5684 ] +miss_latency_IFETCH_Directory: [binsize: 2 max: 285 count: 730 average: 181.192 | standard deviation: 25.9199 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 3 1 2 4 0 155 91 77 220 92 2 3 0 1 2 2 6 1 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 20 9 5 10 12 2 1 0 0 1 2 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] All Non-Zero Cycle SW Prefetch Requests ------------------------------------ @@ -122,7 +122,7 @@ Resource Usage page_size: 4096 user_time: 0 system_time: 0 -page_reclaims: 10742 +page_reclaims: 10179 page_faults: 0 swaps: 0 block_inputs: 0 @@ -181,7 +181,7 @@ Cache Stats: system.ruby.cpu_ruby_ports.dcache system.ruby.cpu_ruby_ports.dcache_request_type_ST: 15.7803% system.ruby.cpu_ruby_ports.dcache_request_type_IFETCH: 42.1965% - system.ruby.cpu_ruby_ports.dcache_access_mode_type_SupervisorMode: 1730 100% + system.ruby.cpu_ruby_ports.dcache_access_mode_type_Supervisor: 1730 100% --- L1Cache --- - Event Counts - diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/simout b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/simout index 6867d8c8b..06d5157d3 100755 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/simout +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/simout @@ -5,10 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 7 2011 01:47:18 -M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip -M5 started Feb 7 2011 01:47:48 -M5 executing on burrito +M5 compiled Apr 19 2011 11:52:53 +M5 started Apr 19 2011 11:58:50 +M5 executing on maize command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt index a6f61bb79..546fc87e2 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 16267 # Simulator instruction rate (inst/s) -host_mem_usage 233240 # Number of bytes of host memory used -host_seconds 0.39 # Real time elapsed on the host -host_tick_rate 870027 # Simulator tick rate (ticks/s) +host_inst_rate 85595 # Simulator instruction rate (inst/s) +host_mem_usage 213088 # Number of bytes of host memory used +host_seconds 0.07 # Real time elapsed on the host +host_tick_rate 4571649 # Simulator tick rate (ticks/s) sim_freq 1000000000 # Frequency of simulated ticks sim_insts 6404 # Number of instructions simulated sim_seconds 0.000343 # Number of seconds simulated @@ -61,6 +61,6 @@ system.cpu.num_int_register_writes 4581 # nu system.cpu.num_load_insts 1192 # Number of load instructions system.cpu.num_mem_refs 2060 # number of memory refs system.cpu.num_store_insts 868 # Number of store instructions -system.cpu.workload.PROG:num_syscalls 17 # Number of system calls +system.cpu.workload.num_syscalls 17 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini index 8ac220e1e..49928ea02 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini @@ -51,6 +51,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=true latency=1000 max_miss_count=0 mshrs=10 @@ -86,6 +87,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=true latency=1000 max_miss_count=0 mshrs=10 @@ -121,6 +123,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=false latency=10000 max_miss_count=0 mshrs=10 diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/simout b/tests/quick/00.hello/ref/alpha/linux/simple-timing/simout index 6e929844e..ece1fd443 100755 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/simout +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/simout @@ -5,10 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 7 2011 01:47:18 -M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip -M5 started Feb 7 2011 01:47:37 -M5 executing on burrito +M5 compiled Apr 19 2011 11:52:53 +M5 started Apr 19 2011 12:04:47 +M5 executing on maize command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-timing/stats.txt index 710a7cdd2..fdf9b36d5 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 267933 # Simulator instruction rate (inst/s) -host_mem_usage 222956 # Number of bytes of host memory used -host_seconds 0.02 # Real time elapsed on the host -host_tick_rate 1366456557 # Simulator tick rate (ticks/s) +host_inst_rate 19269 # Simulator instruction rate (inst/s) +host_mem_usage 202736 # Number of bytes of host memory used +host_seconds 0.33 # Real time elapsed on the host +host_tick_rate 99261557 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 6404 # Number of instructions simulated sim_seconds 0.000033 # Number of seconds simulated @@ -50,8 +50,8 @@ system.cpu.dcache.demand_mshr_misses 168 # nu system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.025313 # Average percentage of cache occupancy system.cpu.dcache.occ_blocks::0 103.680615 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.025313 # Average percentage of cache occupancy system.cpu.dcache.overall_accesses 2050 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency @@ -121,8 +121,8 @@ system.cpu.icache.demand_mshr_misses 279 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.062443 # Average percentage of cache occupancy system.cpu.icache.occ_blocks::0 127.883393 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.062443 # Average percentage of cache occupancy system.cpu.icache.overall_accesses 6415 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 55849.462366 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 52849.462366 # average overall mshr miss latency @@ -202,8 +202,8 @@ system.cpu.l2cache.demand_mshr_misses 446 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.005626 # Average percentage of cache occupancy system.cpu.l2cache.occ_blocks::0 184.342479 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.005626 # Average percentage of cache occupancy system.cpu.l2cache.overall_accesses 447 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency @@ -245,6 +245,6 @@ system.cpu.num_int_register_writes 4581 # nu system.cpu.num_load_insts 1192 # Number of load instructions system.cpu.num_mem_refs 2060 # number of memory refs system.cpu.num_store_insts 868 # Number of store instructions -system.cpu.workload.PROG:num_syscalls 17 # Number of system calls +system.cpu.workload.num_syscalls 17 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini index e2033d8c4..838834423 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini @@ -25,6 +25,8 @@ BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 LQEntries=32 +LSQCheckLoads=true +LSQDepCheckShift=4 RASSize=16 SQEntries=32 SSITSize=1024 diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout index 6c13eb8f5..fc9118372 100755 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout @@ -5,9 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Mar 17 2011 21:44:37 -M5 started Mar 17 2011 21:45:02 -M5 executing on zizzer +M5 compiled Apr 19 2011 11:52:53 +M5 started Apr 19 2011 12:04:56 +M5 executing on maize command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt index 3fca93af7..e80a12bfa 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 58135 # Simulator instruction rate (inst/s) -host_mem_usage 204672 # Number of bytes of host memory used -host_seconds 0.04 # Real time elapsed on the host -host_tick_rate 176416397 # Simulator tick rate (ticks/s) +host_inst_rate 106844 # Simulator instruction rate (inst/s) +host_mem_usage 202600 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host +host_tick_rate 323591910 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 2387 # Number of instructions simulated sim_seconds 0.000007 # Number of seconds simulated @@ -16,38 +16,38 @@ system.cpu.BPredUnit.condIncorrect 223 # Nu system.cpu.BPredUnit.condPredicted 485 # Number of conditional branches predicted system.cpu.BPredUnit.lookups 931 # Number of BP lookups system.cpu.BPredUnit.usedRAS 174 # Number of times the RAS was used to get a target. -system.cpu.commit.COM:branches 396 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 41 # number cycles where commit BW limit reached -system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 6308 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 0.408370 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 1.199072 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0 5350 84.81% 84.81% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1 259 4.11% 88.92% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2 343 5.44% 94.36% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3 133 2.11% 96.46% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4 72 1.14% 97.61% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5 64 1.01% 98.62% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6 26 0.41% 99.03% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7 20 0.32% 99.35% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 41 0.65% 100.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 6308 # Number of insts commited each cycle -system.cpu.commit.COM:count 2576 # Number of instructions committed -system.cpu.commit.COM:fp_insts 6 # Number of committed floating point instructions. -system.cpu.commit.COM:function_calls 71 # Number of function calls committed. -system.cpu.commit.COM:int_insts 2367 # Number of committed integer instructions. -system.cpu.commit.COM:loads 415 # Number of loads committed -system.cpu.commit.COM:membars 0 # Number of memory barriers committed -system.cpu.commit.COM:refs 709 # Number of memory references committed -system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed system.cpu.commit.branchMispredicts 146 # The number of times a branch was mispredicted +system.cpu.commit.branches 396 # Number of branches committed +system.cpu.commit.bw_lim_events 41 # number cycles where commit BW limit reached +system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.commitCommittedInsts 2576 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 4 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.commitSquashedInsts 1995 # The number of squashed insts skipped by commit +system.cpu.commit.committed_per_cycle::samples 6308 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.408370 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.199072 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 5350 84.81% 84.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 259 4.11% 88.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 343 5.44% 94.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 133 2.11% 96.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 72 1.14% 97.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 64 1.01% 98.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 26 0.41% 99.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 20 0.32% 99.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 41 0.65% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 6308 # Number of insts commited each cycle +system.cpu.commit.count 2576 # Number of instructions committed +system.cpu.commit.fp_insts 6 # Number of committed floating point instructions. +system.cpu.commit.function_calls 71 # Number of function calls committed. +system.cpu.commit.int_insts 2367 # Number of committed integer instructions. +system.cpu.commit.loads 415 # Number of loads committed +system.cpu.commit.membars 0 # Number of memory barriers committed +system.cpu.commit.refs 709 # Number of memory references committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.committedInsts 2387 # Number of Instructions Simulated system.cpu.committedInsts_total 2387 # Number of Instructions Simulated system.cpu.cpi 6.107667 # CPI: Cycles Per Instruction @@ -96,8 +96,8 @@ system.cpu.dcache.demand_mshr_misses 85 # nu system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.011366 # Average percentage of cache occupancy system.cpu.dcache.occ_blocks::0 46.556735 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.011366 # Average percentage of cache occupancy system.cpu.dcache.overall_accesses 883 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 35891.666667 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 35829.411765 # average overall mshr miss latency @@ -119,15 +119,15 @@ system.cpu.dcache.tagsinuse 46.556735 # Cy system.cpu.dcache.total_refs 703 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 217 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 79 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 136 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 5047 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 5111 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 977 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 374 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 284 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 3 # Number of cycles decode is unblocking +system.cpu.decode.BlockedCycles 217 # Number of cycles decode is blocked +system.cpu.decode.BranchMispred 79 # Number of times decode detected a branch misprediction +system.cpu.decode.BranchResolved 136 # Number of times decode resolved a branch +system.cpu.decode.DecodedInsts 5047 # Number of instructions handled by decode +system.cpu.decode.IdleCycles 5111 # Number of cycles decode is idle +system.cpu.decode.RunCycles 977 # Number of cycles decode is running +system.cpu.decode.SquashCycles 374 # Number of cycles decode is squashing +system.cpu.decode.SquashedInsts 284 # Number of squashed instructions handled by decode +system.cpu.decode.UnblockCycles 3 # Number of cycles decode is unblocking system.cpu.dtb.data_accesses 1010 # DTB accesses system.cpu.dtb.data_acv 1 # DTB access violations system.cpu.dtb.data_hits 964 # DTB hits @@ -206,8 +206,8 @@ system.cpu.icache.demand_mshr_misses 181 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.044195 # Average percentage of cache occupancy system.cpu.icache.occ_blocks::0 90.511194 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.044195 # Average percentage of cache occupancy system.cpu.icache.overall_accesses 777 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 36200.431034 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 35306.629834 # average overall mshr miss latency @@ -230,21 +230,13 @@ system.cpu.icache.total_refs 545 # To system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idleCycles 7897 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 600 # Number of branches executed -system.cpu.iew.EXEC:nop 311 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.241855 # Inst execution rate -system.cpu.iew.EXEC:refs 1011 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 366 # Number of stores executed -system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 1995 # num instructions consuming a value -system.cpu.iew.WB:count 3404 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.790977 # average fanout of values written-back -system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 1578 # num instructions producing a value -system.cpu.iew.WB:rate 0.233487 # insts written-back per cycle -system.cpu.iew.WB:sent 3463 # cumulative count of insts sent to commit system.cpu.iew.branchMispredicts 171 # Number of branch mispredicts detected at execute +system.cpu.iew.exec_branches 600 # Number of branches executed +system.cpu.iew.exec_nop 311 # number of nop insts executed +system.cpu.iew.exec_rate 0.241855 # Inst execution rate +system.cpu.iew.exec_refs 1011 # number of memory reference insts executed +system.cpu.iew.exec_stores 366 # Number of stores executed +system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.iewBlockCycles 48 # Number of cycles IEW is blocking system.cpu.iew.iewDispLoadInsts 779 # Number of dispatched load instructions system.cpu.iew.iewDispNonSpecInsts 6 # Number of dispatched non-speculative instructions @@ -272,103 +264,93 @@ system.cpu.iew.lsq.thread.0.squashedStores 134 # system.cpu.iew.memOrderViolationEvents 4 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 118 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 53 # Number of branches that were predicted taken incorrectly +system.cpu.iew.wb_consumers 1995 # num instructions consuming a value +system.cpu.iew.wb_count 3404 # cumulative count of insts written-back +system.cpu.iew.wb_fanout 0.790977 # average fanout of values written-back +system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ +system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu.iew.wb_producers 1578 # num instructions producing a value +system.cpu.iew.wb_rate 0.233487 # insts written-back per cycle +system.cpu.iew.wb_sent 3463 # cumulative count of insts sent to commit system.cpu.int_regfile_reads 4291 # number of integer regfile reads system.cpu.int_regfile_writes 2610 # number of integer regfile writes system.cpu.ipc 0.163729 # IPC: Instructions Per Cycle system.cpu.ipc_total 0.163729 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 2594 71.36% 71.36% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 1 0.03% 71.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 71.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 71.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 71.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 71.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 71.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 71.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 71.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 71.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 71.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 71.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 71.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 71.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 71.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 71.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 71.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 71.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 71.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 71.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 71.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 71.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 71.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 71.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 71.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 71.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 71.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 71.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 71.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 669 18.40% 89.79% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 371 10.21% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 3635 # Type of FU issued -system.cpu.iq.ISSUE:fu_busy_cnt 32 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.008803 # FU busy rate (busy events/executed inst) -system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntAlu 1 3.12% 3.12% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemRead 9 28.12% 31.25% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemWrite 22 68.75% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 6682 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 0.543999 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.232060 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0 5130 76.77% 76.77% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1 639 9.56% 86.34% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2 335 5.01% 91.35% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3 242 3.62% 94.97% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4 178 2.66% 97.64% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5 94 1.41% 99.04% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6 39 0.58% 99.63% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7 16 0.24% 99.87% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::8 9 0.13% 100.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 6682 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 0.249331 # Inst issue rate +system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 2594 71.36% 71.36% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 1 0.03% 71.39% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 71.39% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 71.39% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 71.39% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 71.39% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 71.39% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 71.39% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 71.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 71.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 71.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 71.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 71.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 71.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 71.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 71.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 71.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 71.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 71.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 71.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 71.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 71.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 71.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 71.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 71.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 71.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 71.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 71.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 71.39% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 669 18.40% 89.79% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 371 10.21% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 3635 # Type of FU issued system.cpu.iq.fp_alu_accesses 7 # Number of floating point alu accesses system.cpu.iq.fp_inst_queue_reads 13 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_wakeup_accesses 6 # Number of floating instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_writes 6 # Number of floating instruction queue writes +system.cpu.iq.fu_busy_cnt 32 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.008803 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 1 3.12% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 9 28.12% 31.25% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 22 68.75% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.int_alu_accesses 3660 # Number of integer alu accesses system.cpu.iq.int_inst_queue_reads 14000 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_wakeup_accesses 3398 # Number of integer instruction queue wakeup accesses @@ -380,6 +362,24 @@ system.cpu.iq.iqSquashedInstsExamined 1704 # Nu system.cpu.iq.iqSquashedInstsIssued 29 # Number of squashed instructions issued system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed system.cpu.iq.iqSquashedOperandsExamined 959 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.issued_per_cycle::samples 6682 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.543999 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.232060 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 5130 76.77% 76.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 639 9.56% 86.34% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 335 5.01% 91.35% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 242 3.62% 94.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 178 2.66% 97.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 94 1.41% 99.04% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 39 0.58% 99.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 16 0.24% 99.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 9 0.13% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 6682 # Number of insts issued each cycle +system.cpu.iq.rate 0.249331 # Inst issue rate system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_hits 0 # DTB hits @@ -436,8 +436,8 @@ system.cpu.l2cache.demand_mshr_misses 266 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.003658 # Average percentage of cache occupancy system.cpu.l2cache.occ_blocks::0 119.871330 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.003658 # Average percentage of cache occupancy system.cpu.l2cache.overall_accesses 266 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 34351.503759 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 31176.691729 # average overall mshr miss latency @@ -468,27 +468,27 @@ system.cpu.misc_regfile_writes 1 # nu system.cpu.numCycles 14579 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.rename.RENAME:BlockCycles 55 # Number of cycles rename is blocking -system.cpu.rename.RENAME:CommittedMaps 1768 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 6 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 5189 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 2 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 5515 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 4879 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 3490 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 901 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 374 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 17 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 1722 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:fp_rename_lookups 12 # Number of floating rename lookups -system.cpu.rename.RENAME:int_rename_lookups 5503 # Number of integer rename lookups -system.cpu.rename.RENAME:serializeStallCycles 146 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 8 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 74 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 6 # count of temporary serializing insts renamed +system.cpu.rename.BlockCycles 55 # Number of cycles rename is blocking +system.cpu.rename.CommittedMaps 1768 # Number of HB maps that are committed +system.cpu.rename.IQFullEvents 6 # Number of times rename has blocked due to IQ full +system.cpu.rename.IdleCycles 5189 # Number of cycles rename is idle +system.cpu.rename.LSQFullEvents 2 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenameLookups 5515 # Number of register rename lookups that rename has made +system.cpu.rename.RenamedInsts 4879 # Number of instructions processed by rename +system.cpu.rename.RenamedOperands 3490 # Number of destination operands rename has renamed +system.cpu.rename.RunCycles 901 # Number of cycles rename is running +system.cpu.rename.SquashCycles 374 # Number of cycles rename is squashing +system.cpu.rename.UnblockCycles 17 # Number of cycles rename is unblocking +system.cpu.rename.UndoneMaps 1722 # Number of HB maps that are undone due to squashing +system.cpu.rename.fp_rename_lookups 12 # Number of floating rename lookups +system.cpu.rename.int_rename_lookups 5503 # Number of integer rename lookups +system.cpu.rename.serializeStallCycles 146 # count of cycles rename stalled for serializing inst +system.cpu.rename.serializingInsts 8 # count of serializing insts renamed +system.cpu.rename.skidInsts 74 # count of insts added to the skid buffer +system.cpu.rename.tempSerializingInsts 6 # count of temporary serializing insts renamed system.cpu.rob.rob_reads 10591 # The number of ROB reads system.cpu.rob.rob_writes 9519 # The number of ROB writes system.cpu.timesIdled 151 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.workload.PROG:num_syscalls 4 # Number of system calls +system.cpu.workload.num_syscalls 4 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simout b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simout index 800e2e284..534040190 100755 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simout +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simout @@ -5,10 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 7 2011 01:47:18 -M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip -M5 started Feb 7 2011 01:47:37 -M5 executing on burrito +M5 compiled Apr 19 2011 11:52:53 +M5 started Apr 19 2011 12:00:19 +M5 executing on maize command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stats.txt index 835697644..50ec4667d 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 290762 # Simulator instruction rate (inst/s) -host_mem_usage 214352 # Number of bytes of host memory used +host_inst_rate 343171 # Simulator instruction rate (inst/s) +host_mem_usage 194176 # Number of bytes of host memory used host_seconds 0.01 # Real time elapsed on the host -host_tick_rate 142079814 # Simulator tick rate (ticks/s) +host_tick_rate 169102503 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 2577 # Number of instructions simulated sim_seconds 0.000001 # Number of seconds simulated @@ -61,6 +61,6 @@ system.cpu.num_int_register_writes 1768 # nu system.cpu.num_load_insts 419 # Number of load instructions system.cpu.num_mem_refs 717 # number of memory refs system.cpu.num_store_insts 298 # Number of store instructions -system.cpu.workload.PROG:num_syscalls 4 # Number of system calls +system.cpu.workload.num_syscalls 4 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/config.ini b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/config.ini index b7bfb0aae..2236053ad 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/config.ini +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/config.ini @@ -63,7 +63,7 @@ egid=100 env= errout=cerr euid=100 -executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/tru64/hello +executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello gid=100 input=cin max_stack_size=67108864 @@ -201,6 +201,7 @@ deadlock_threshold=500000 icache=system.l1_cntrl0.L1IcacheMemory max_outstanding_requests=16 physmem=system.physmem +using_network_tester=false using_ruby_tester=false version=0 physMemPort=system.physmem.port[0] diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/ruby.stats b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/ruby.stats index 594f80de9..5ce289e6f 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/ruby.stats +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/ruby.stats @@ -34,7 +34,7 @@ periodic_stats_period: 1000000 ================ End RubySystem Configuration Print ================ -Real time: Feb/08/2011 17:31:55 +Real time: Apr/19/2011 12:12:40 Profiler Stats -------------- @@ -43,18 +43,18 @@ Elapsed_time_in_minutes: 0 Elapsed_time_in_hours: 0 Elapsed_time_in_days: 0 -Virtual_time_in_seconds: 0.39 -Virtual_time_in_minutes: 0.0065 -Virtual_time_in_hours: 0.000108333 -Virtual_time_in_days: 4.51389e-06 +Virtual_time_in_seconds: 0.16 +Virtual_time_in_minutes: 0.00266667 +Virtual_time_in_hours: 4.44444e-05 +Virtual_time_in_days: 1.85185e-06 Ruby_current_time: 103637 Ruby_start_time: 0 Ruby_cycles: 103637 -mbytes_resident: 35.7188 -mbytes_total: 209.473 -resident_ratio: 0.170592 +mbytes_resident: 37.7031 +mbytes_total: 207.426 +resident_ratio: 0.181786 ruby_cycles_executed: [ 103638 ] @@ -71,9 +71,9 @@ sequencer_requests_outstanding: [binsize: 1 max: 1 count: 3295 average: 1 | All Non-Zero Cycle Demand Cache Accesses ---------------------------------------- miss_latency: [binsize: 2 max: 223 count: 3294 average: 30.4624 | standard deviation: 61.2716 | 0 2722 0 0 0 0 0 0 0 25 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 68 156 96 122 80 3 4 5 3 3 0 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_IFETCH: [binsize: 1 max: 181 count: 2585 average: 21.5791 | standard deviation: 52.0174 | 0 0 0 2285 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 32 0 70 0 67 0 59 0 54 0 1 1 1 0 3 0 0 0 3 ] miss_latency_LD: [binsize: 2 max: 217 count: 415 average: 79.6169 | standard deviation: 81.8661 | 0 211 0 0 0 0 0 0 0 12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 30 58 25 52 15 1 2 2 2 0 0 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] miss_latency_ST: [binsize: 2 max: 223 count: 294 average: 39.1837 | standard deviation: 68.3072 | 0 226 0 0 0 0 0 0 0 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 28 4 11 11 1 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_IFETCH: [binsize: 1 max: 181 count: 2585 average: 21.5791 | standard deviation: 52.0174 | 0 0 0 2285 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 32 0 70 0 67 0 59 0 54 0 1 1 1 0 3 0 0 0 3 ] miss_latency_NULL: [binsize: 2 max: 223 count: 3294 average: 30.4624 | standard deviation: 61.2716 | 0 2722 0 0 0 0 0 0 0 25 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 68 156 96 122 80 3 4 5 3 3 0 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] @@ -85,9 +85,9 @@ miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 0 average: N miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] miss_latency_dir_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] imcomplete_dir_Times: 0 -miss_latency_IFETCH_NULL: [binsize: 1 max: 181 count: 2585 average: 21.5791 | standard deviation: 52.0174 | 0 0 0 2285 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 32 0 70 0 67 0 59 0 54 0 1 1 1 0 3 0 0 0 3 ] miss_latency_LD_NULL: [binsize: 2 max: 217 count: 415 average: 79.6169 | standard deviation: 81.8661 | 0 211 0 0 0 0 0 0 0 12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 30 58 25 52 15 1 2 2 2 0 0 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] miss_latency_ST_NULL: [binsize: 2 max: 223 count: 294 average: 39.1837 | standard deviation: 68.3072 | 0 226 0 0 0 0 0 0 0 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 28 4 11 11 1 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_IFETCH_NULL: [binsize: 1 max: 181 count: 2585 average: 21.5791 | standard deviation: 52.0174 | 0 0 0 2285 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 32 0 70 0 67 0 59 0 54 0 1 1 1 0 3 0 0 0 3 ] All Non-Zero Cycle SW Prefetch Requests ------------------------------------ @@ -119,11 +119,11 @@ Resource Usage page_size: 4096 user_time: 0 system_time: 0 -page_reclaims: 10341 +page_reclaims: 9943 page_faults: 0 swaps: 0 block_inputs: 0 -block_outputs: 0 +block_outputs: 64 Network Stats ------------- diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simout b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simout index 38e786bad..f2d20d5dd 100755 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simout +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simout @@ -5,10 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 8 2011 17:31:51 -M5 revision 685719afafe6 7938 default tip brad/increase_ruby_mem_test_threshold qtip -M5 started Feb 8 2011 17:31:55 -M5 executing on SC2B0617 +M5 compiled Apr 19 2011 12:12:36 +M5 started Apr 19 2011 12:12:40 +M5 executing on maize command line: build/ALPHA_SE_MESI_CMP_directory/m5.fast -d build/ALPHA_SE_MESI_CMP_directory/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MESI_CMP_directory -re tests/run.py build/ALPHA_SE_MESI_CMP_directory/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MESI_CMP_directory Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/stats.txt index 591cdf9bb..b8af50b9b 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/stats.txt +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 31237 # Simulator instruction rate (inst/s) -host_mem_usage 214504 # Number of bytes of host memory used -host_seconds 0.08 # Real time elapsed on the host -host_tick_rate 1253532 # Simulator tick rate (ticks/s) +host_inst_rate 46920 # Simulator instruction rate (inst/s) +host_mem_usage 212408 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host +host_tick_rate 1882342 # Simulator tick rate (ticks/s) sim_freq 1000000000 # Frequency of simulated ticks sim_insts 2577 # Number of instructions simulated sim_seconds 0.000104 # Number of seconds simulated @@ -61,6 +61,6 @@ system.cpu.num_int_register_writes 1768 # nu system.cpu.num_load_insts 419 # Number of load instructions system.cpu.num_mem_refs 717 # number of memory refs system.cpu.num_store_insts 298 # Number of store instructions -system.cpu.workload.PROG:num_syscalls 4 # Number of system calls +system.cpu.workload.num_syscalls 4 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini index dae855509..412f71fac 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini @@ -63,7 +63,7 @@ egid=100 env= errout=cerr euid=100 -executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/tru64/hello +executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello gid=100 input=cin max_stack_size=67108864 @@ -197,6 +197,7 @@ deadlock_threshold=500000 icache=system.l1_cntrl0.L1IcacheMemory max_outstanding_requests=16 physmem=system.physmem +using_network_tester=false using_ruby_tester=false version=0 physMemPort=system.physmem.port[0] diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/ruby.stats b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/ruby.stats index b0eff5788..18c0ded27 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/ruby.stats +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/ruby.stats @@ -34,27 +34,27 @@ periodic_stats_period: 1000000 ================ End RubySystem Configuration Print ================ -Real time: Feb/08/2011 17:41:43 +Real time: Apr/19/2011 12:14:52 Profiler Stats -------------- -Elapsed_time_in_seconds: 1 -Elapsed_time_in_minutes: 0.0166667 -Elapsed_time_in_hours: 0.000277778 -Elapsed_time_in_days: 1.15741e-05 +Elapsed_time_in_seconds: 0 +Elapsed_time_in_minutes: 0 +Elapsed_time_in_hours: 0 +Elapsed_time_in_days: 0 -Virtual_time_in_seconds: 0.4 -Virtual_time_in_minutes: 0.00666667 -Virtual_time_in_hours: 0.000111111 -Virtual_time_in_days: 4.62963e-06 +Virtual_time_in_seconds: 0.16 +Virtual_time_in_minutes: 0.00266667 +Virtual_time_in_hours: 4.44444e-05 +Virtual_time_in_days: 1.85185e-06 Ruby_current_time: 85988 Ruby_start_time: 0 Ruby_cycles: 85988 -mbytes_resident: 35.8359 -mbytes_total: 209.617 -resident_ratio: 0.171015 +mbytes_resident: 37.793 +mbytes_total: 207.531 +resident_ratio: 0.182126 ruby_cycles_executed: [ 85989 ] @@ -71,9 +71,9 @@ sequencer_requests_outstanding: [binsize: 1 max: 1 count: 3295 average: 1 | All Non-Zero Cycle Demand Cache Accesses ---------------------------------------- miss_latency: [binsize: 2 max: 269 count: 3294 average: 25.1044 | standard deviation: 56.2234 | 0 2784 0 0 0 0 0 0 0 69 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 80 86 86 80 64 7 5 1 2 0 2 4 2 1 2 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_IFETCH: [binsize: 2 max: 227 count: 2585 average: 18.8561 | standard deviation: 48.7313 | 0 2315 0 0 0 0 0 0 0 27 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 48 53 42 50 34 2 4 1 1 0 2 2 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] miss_latency_LD: [binsize: 2 max: 267 count: 415 average: 61.0506 | standard deviation: 78.3756 | 0 233 0 0 0 0 0 0 0 42 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 32 18 42 18 23 1 0 0 1 0 0 1 0 0 2 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] miss_latency_ST: [binsize: 2 max: 269 count: 294 average: 29.3027 | standard deviation: 60.9274 | 0 236 0 0 0 0 0 0 0 0 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 2 12 7 4 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_IFETCH: [binsize: 2 max: 227 count: 2585 average: 18.8561 | standard deviation: 48.7313 | 0 2315 0 0 0 0 0 0 0 27 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 48 53 42 50 34 2 4 1 1 0 2 2 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] miss_latency_NULL: [binsize: 2 max: 269 count: 3294 average: 25.1044 | standard deviation: 56.2234 | 0 2784 0 0 0 0 0 0 0 69 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 80 86 86 80 64 7 5 1 2 0 2 4 2 1 2 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] @@ -85,9 +85,9 @@ miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 0 average: N miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] miss_latency_dir_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] imcomplete_dir_Times: 0 -miss_latency_IFETCH_NULL: [binsize: 2 max: 227 count: 2585 average: 18.8561 | standard deviation: 48.7313 | 0 2315 0 0 0 0 0 0 0 27 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 48 53 42 50 34 2 4 1 1 0 2 2 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] miss_latency_LD_NULL: [binsize: 2 max: 267 count: 415 average: 61.0506 | standard deviation: 78.3756 | 0 233 0 0 0 0 0 0 0 42 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 32 18 42 18 23 1 0 0 1 0 0 1 0 0 2 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] miss_latency_ST_NULL: [binsize: 2 max: 269 count: 294 average: 29.3027 | standard deviation: 60.9274 | 0 236 0 0 0 0 0 0 0 0 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 2 12 7 4 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_IFETCH_NULL: [binsize: 2 max: 227 count: 2585 average: 18.8561 | standard deviation: 48.7313 | 0 2315 0 0 0 0 0 0 0 27 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 48 53 42 50 34 2 4 1 1 0 2 2 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] All Non-Zero Cycle SW Prefetch Requests ------------------------------------ @@ -119,11 +119,11 @@ Resource Usage page_size: 4096 user_time: 0 system_time: 0 -page_reclaims: 10362 +page_reclaims: 9966 page_faults: 0 swaps: 0 block_inputs: 0 -block_outputs: 0 +block_outputs: 64 Network Stats ------------- @@ -411,6 +411,7 @@ Writeback_Ack [411 ] 411 Writeback_Nack [0 ] 0 Unblock [0 ] 0 Exclusive_Unblock [510 ] 510 +DmaAck [0 ] 0 L2_Replacement [411 ] 411 - Transitions - @@ -1160,6 +1161,76 @@ ILSI All_Acks [0 ] 0 ILSI Writeback_Ack [0 ] 0 ILSI L2_Replacement [0 ] 0 +ILOSD L1_GETS [0 ] 0 +ILOSD L1_GETX [0 ] 0 +ILOSD L1_PUTO [0 ] 0 +ILOSD L1_PUTX [0 ] 0 +ILOSD L1_PUTS_only [0 ] 0 +ILOSD L1_PUTS [0 ] 0 +ILOSD Fwd_GETX [0 ] 0 +ILOSD Fwd_GETS [0 ] 0 +ILOSD Fwd_DMA [0 ] 0 +ILOSD Own_GETX [0 ] 0 +ILOSD Inv [0 ] 0 +ILOSD DmaAck [0 ] 0 +ILOSD L2_Replacement [0 ] 0 + +ILOSXD L1_GETS [0 ] 0 +ILOSXD L1_GETX [0 ] 0 +ILOSXD L1_PUTO [0 ] 0 +ILOSXD L1_PUTX [0 ] 0 +ILOSXD L1_PUTS_only [0 ] 0 +ILOSXD L1_PUTS [0 ] 0 +ILOSXD Fwd_GETX [0 ] 0 +ILOSXD Fwd_GETS [0 ] 0 +ILOSXD Fwd_DMA [0 ] 0 +ILOSXD Own_GETX [0 ] 0 +ILOSXD Inv [0 ] 0 +ILOSXD DmaAck [0 ] 0 +ILOSXD L2_Replacement [0 ] 0 + +ILOD L1_GETS [0 ] 0 +ILOD L1_GETX [0 ] 0 +ILOD L1_PUTO [0 ] 0 +ILOD L1_PUTX [0 ] 0 +ILOD L1_PUTS_only [0 ] 0 +ILOD L1_PUTS [0 ] 0 +ILOD Fwd_GETX [0 ] 0 +ILOD Fwd_GETS [0 ] 0 +ILOD Fwd_DMA [0 ] 0 +ILOD Own_GETX [0 ] 0 +ILOD Inv [0 ] 0 +ILOD DmaAck [0 ] 0 +ILOD L2_Replacement [0 ] 0 + +ILXD L1_GETS [0 ] 0 +ILXD L1_GETX [0 ] 0 +ILXD L1_PUTO [0 ] 0 +ILXD L1_PUTX [0 ] 0 +ILXD L1_PUTS_only [0 ] 0 +ILXD L1_PUTS [0 ] 0 +ILXD Fwd_GETX [0 ] 0 +ILXD Fwd_GETS [0 ] 0 +ILXD Fwd_DMA [0 ] 0 +ILXD Own_GETX [0 ] 0 +ILXD Inv [0 ] 0 +ILXD DmaAck [0 ] 0 +ILXD L2_Replacement [0 ] 0 + +ILOXD L1_GETS [0 ] 0 +ILOXD L1_GETX [0 ] 0 +ILOXD L1_PUTO [0 ] 0 +ILOXD L1_PUTX [0 ] 0 +ILOXD L1_PUTS_only [0 ] 0 +ILOXD L1_PUTS [0 ] 0 +ILOXD Fwd_GETX [0 ] 0 +ILOXD Fwd_GETS [0 ] 0 +ILOXD Fwd_DMA [0 ] 0 +ILOXD Own_GETX [0 ] 0 +ILOXD Inv [0 ] 0 +ILOXD DmaAck [0 ] 0 +ILOXD L2_Replacement [0 ] 0 + Memory controller: system.dir_cntrl0.memBuffer: memory_total_requests: 504 memory_reads: 427 @@ -1196,6 +1267,7 @@ Memory_Data [427 ] 427 Memory_Ack [77 ] 77 DMA_READ [0 ] 0 DMA_WRITE [0 ] 0 +DMA_ACK [0 ] 0 Data [0 ] 0 - Transitions - @@ -1376,4 +1448,22 @@ OI_D PUTO [0 ] 0 OI_D PUTO_SHARERS [0 ] 0 OI_D DMA_READ [0 ] 0 OI_D DMA_WRITE [0 ] 0 -OI_D Data
\ No newline at end of file +OI_D Data [0 ] 0 + +OD GETX [0 ] 0 +OD GETS [0 ] 0 +OD PUTX [0 ] 0 +OD PUTO [0 ] 0 +OD PUTO_SHARERS [0 ] 0 +OD DMA_READ [0 ] 0 +OD DMA_WRITE [0 ] 0 +OD DMA_ACK [0 ] 0 + +MD GETX [0 ] 0 +MD GETS [0 ] 0 +MD PUTX [0 ] 0 +MD PUTO [0 ] 0 +MD PUTO_SHARERS [0 ] 0 +MD DMA_READ [0 ] 0 +MD DMA_WRITE [0 ] 0 +MD DMA_ACK
\ No newline at end of file diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout index 2588731f1..26db17bca 100755 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout @@ -5,10 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 8 2011 17:41:34 -M5 revision 685719afafe6+ 7938+ default tip brad/increase_ruby_mem_test_threshold qtip -M5 started Feb 8 2011 17:41:42 -M5 executing on SC2B0617 +M5 compiled Apr 19 2011 12:14:48 +M5 started Apr 19 2011 12:14:52 +M5 executing on maize command line: build/ALPHA_SE_MOESI_CMP_directory/m5.fast -d build/ALPHA_SE_MOESI_CMP_directory/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory -re tests/run.py build/ALPHA_SE_MOESI_CMP_directory/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt index dd02fbf60..274f15f77 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 26760 # Simulator instruction rate (inst/s) -host_mem_usage 214652 # Number of bytes of host memory used -host_seconds 0.10 # Real time elapsed on the host -host_tick_rate 891261 # Simulator tick rate (ticks/s) +host_inst_rate 38282 # Simulator instruction rate (inst/s) +host_mem_usage 212516 # Number of bytes of host memory used +host_seconds 0.07 # Real time elapsed on the host +host_tick_rate 1274831 # Simulator tick rate (ticks/s) sim_freq 1000000000 # Frequency of simulated ticks sim_insts 2577 # Number of instructions simulated sim_seconds 0.000086 # Number of seconds simulated @@ -61,6 +61,6 @@ system.cpu.num_int_register_writes 1768 # nu system.cpu.num_load_insts 419 # Number of load instructions system.cpu.num_mem_refs 717 # number of memory refs system.cpu.num_store_insts 298 # Number of store instructions -system.cpu.workload.PROG:num_syscalls 4 # Number of system calls +system.cpu.workload.num_syscalls 4 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini index 0c0cc2e1c..d99bf3102 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini @@ -63,7 +63,7 @@ egid=100 env= errout=cerr euid=100 -executable=tests/test-progs/hello/bin/alpha/tru64/hello +executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/ruby.stats b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/ruby.stats index 54abfd298..9fa414f7b 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/ruby.stats +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/ruby.stats @@ -34,27 +34,27 @@ periodic_stats_period: 1000000 ================ End RubySystem Configuration Print ================ -Real time: Mar/26/2011 22:00:44 +Real time: Apr/19/2011 12:17:16 Profiler Stats -------------- -Elapsed_time_in_seconds: 1 -Elapsed_time_in_minutes: 0.0166667 -Elapsed_time_in_hours: 0.000277778 -Elapsed_time_in_days: 1.15741e-05 +Elapsed_time_in_seconds: 0 +Elapsed_time_in_minutes: 0 +Elapsed_time_in_hours: 0 +Elapsed_time_in_days: 0 -Virtual_time_in_seconds: 0.19 -Virtual_time_in_minutes: 0.00316667 -Virtual_time_in_hours: 5.27778e-05 -Virtual_time_in_days: 2.19907e-06 +Virtual_time_in_seconds: 0.14 +Virtual_time_in_minutes: 0.00233333 +Virtual_time_in_hours: 3.88889e-05 +Virtual_time_in_days: 1.62037e-06 Ruby_current_time: 84059 Ruby_start_time: 0 Ruby_cycles: 84059 -mbytes_resident: 36.8242 -mbytes_total: 198.527 -resident_ratio: 0.185507 +mbytes_resident: 37.6562 +mbytes_total: 207.355 +resident_ratio: 0.181621 ruby_cycles_executed: [ 84060 ] @@ -127,7 +127,7 @@ Resource Usage page_size: 4096 user_time: 0 system_time: 0 -page_reclaims: 9723 +page_reclaims: 9934 page_faults: 0 swaps: 0 block_inputs: 0 diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout index f5c0cf433..978cef283 100755 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout @@ -5,9 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Mar 26 2011 14:06:20 -M5 started Mar 26 2011 22:00:43 -M5 executing on phenom +M5 compiled Apr 19 2011 12:17:10 +M5 started Apr 19 2011 12:17:16 +M5 executing on maize command line: build/ALPHA_SE_MOESI_CMP_token/m5.fast -d build/ALPHA_SE_MOESI_CMP_token/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_token -re tests/run.py build/ALPHA_SE_MOESI_CMP_token/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_token Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt index ab4470f42..ef789547c 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 8652 # Simulator instruction rate (inst/s) -host_mem_usage 203296 # Number of bytes of host memory used -host_seconds 0.30 # Real time elapsed on the host -host_tick_rate 282076 # Simulator tick rate (ticks/s) +host_inst_rate 40575 # Simulator instruction rate (inst/s) +host_mem_usage 212336 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host +host_tick_rate 1320785 # Simulator tick rate (ticks/s) sim_freq 1000000000 # Frequency of simulated ticks sim_insts 2577 # Number of instructions simulated sim_seconds 0.000084 # Number of seconds simulated @@ -61,6 +61,6 @@ system.cpu.num_int_register_writes 1768 # nu system.cpu.num_load_insts 419 # Number of load instructions system.cpu.num_mem_refs 717 # number of memory refs system.cpu.num_store_insts 298 # Number of store instructions -system.cpu.workload.PROG:num_syscalls 4 # Number of system calls +system.cpu.workload.num_syscalls 4 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini index 08f882272..b810f5467 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini @@ -63,7 +63,7 @@ egid=100 env= errout=cerr euid=100 -executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/tru64/hello +executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello gid=100 input=cin max_stack_size=67108864 @@ -184,6 +184,7 @@ deadlock_threshold=500000 icache=system.ruby.cpu_ruby_ports.icache max_outstanding_requests=16 physmem=system.physmem +using_network_tester=false using_ruby_tester=false version=0 physMemPort=system.physmem.port[0] diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/ruby.stats b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/ruby.stats index 3e0d391db..4245fbc90 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/ruby.stats +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/ruby.stats @@ -34,7 +34,7 @@ periodic_stats_period: 1000000 ================ End RubySystem Configuration Print ================ -Real time: Feb/08/2011 17:57:03 +Real time: Apr/19/2011 12:09:50 Profiler Stats -------------- @@ -43,18 +43,18 @@ Elapsed_time_in_minutes: 0 Elapsed_time_in_hours: 0 Elapsed_time_in_days: 0 -Virtual_time_in_seconds: 0.34 -Virtual_time_in_minutes: 0.00566667 -Virtual_time_in_hours: 9.44444e-05 -Virtual_time_in_days: 3.93519e-06 +Virtual_time_in_seconds: 0.13 +Virtual_time_in_minutes: 0.00216667 +Virtual_time_in_hours: 3.61111e-05 +Virtual_time_in_days: 1.50463e-06 Ruby_current_time: 78448 Ruby_start_time: 0 Ruby_cycles: 78448 -mbytes_resident: 35.3906 -mbytes_total: 208.879 -resident_ratio: 0.169469 +mbytes_resident: 37.4102 +mbytes_total: 207.098 +resident_ratio: 0.180659 ruby_cycles_executed: [ 78449 ] @@ -70,9 +70,9 @@ sequencer_requests_outstanding: [binsize: 1 max: 1 count: 3295 average: 1 | All Non-Zero Cycle Demand Cache Accesses ---------------------------------------- miss_latency: [binsize: 2 max: 320 count: 3294 average: 22.8154 | standard deviation: 52.8821 | 0 2784 0 0 0 0 69 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 35 77 95 66 57 76 2 2 1 4 2 0 1 2 2 5 1 4 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 3 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_IFETCH: [binsize: 1 max: 181 count: 2585 average: 16.5636 | standard deviation: 44.4401 | 0 0 2315 0 0 0 0 0 0 0 0 0 0 22 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 47 18 11 32 22 14 39 1 1 1 1 0 0 0 2 1 0 0 0 0 0 0 0 1 0 0 0 2 1 0 2 1 ] miss_latency_LD: [binsize: 2 max: 319 count: 415 average: 57.3952 | standard deviation: 74.7751 | 0 233 0 0 0 0 36 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 35 24 16 16 26 0 1 1 0 1 0 0 1 2 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] miss_latency_ST: [binsize: 2 max: 320 count: 294 average: 28.9728 | standard deviation: 63.5282 | 0 236 0 0 0 0 11 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 7 6 7 5 10 0 0 0 1 1 0 1 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 2 0 1 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_IFETCH: [binsize: 1 max: 181 count: 2585 average: 16.5636 | standard deviation: 44.4401 | 0 0 2315 0 0 0 0 0 0 0 0 0 0 22 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 47 18 11 32 22 14 39 1 1 1 1 0 0 0 2 1 0 0 0 0 0 0 0 1 0 0 0 2 1 0 2 1 ] miss_latency_L1Cache: [binsize: 1 max: 2 count: 2784 average: 2 | standard deviation: 0 | 0 0 2784 ] miss_latency_L2Cache: [binsize: 1 max: 13 count: 69 average: 13 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 69 ] miss_latency_Directory: [binsize: 2 max: 320 count: 441 average: 155.757 | standard deviation: 21.4255 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 35 77 95 66 57 76 2 2 1 4 2 0 1 2 2 5 1 4 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 3 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] @@ -86,15 +86,15 @@ miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 1 average: miss_latency_dir_forward_to_first_response: [binsize: 1 max: 158 count: 1 average: 158 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] miss_latency_dir_first_response_to_completion: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ] imcomplete_dir_Times: 440 -miss_latency_IFETCH_L1Cache: [binsize: 1 max: 2 count: 2315 average: 2 | standard deviation: 0 | 0 0 2315 ] -miss_latency_IFETCH_L2Cache: [binsize: 1 max: 13 count: 22 average: 13 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 22 ] -miss_latency_IFETCH_Directory: [binsize: 1 max: 181 count: 248 average: 152.827 | standard deviation: 5.37952 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 47 18 11 32 22 14 39 1 1 1 1 0 0 0 2 1 0 0 0 0 0 0 0 1 0 0 0 2 1 0 2 1 ] miss_latency_LD_L1Cache: [binsize: 1 max: 2 count: 233 average: 2 | standard deviation: 0 | 0 0 233 ] miss_latency_LD_L2Cache: [binsize: 1 max: 13 count: 36 average: 13 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 36 ] miss_latency_LD_Directory: [binsize: 2 max: 319 count: 146 average: 156.747 | standard deviation: 24.5989 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 35 24 16 16 26 0 1 1 0 1 0 0 1 2 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] miss_latency_ST_L1Cache: [binsize: 1 max: 2 count: 236 average: 2 | standard deviation: 0 | 0 0 236 ] miss_latency_ST_L2Cache: [binsize: 1 max: 13 count: 11 average: 13 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 11 ] miss_latency_ST_Directory: [binsize: 2 max: 320 count: 47 average: 168.149 | standard deviation: 46.0633 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 7 6 7 5 10 0 0 0 1 1 0 1 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 2 0 1 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_IFETCH_L1Cache: [binsize: 1 max: 2 count: 2315 average: 2 | standard deviation: 0 | 0 0 2315 ] +miss_latency_IFETCH_L2Cache: [binsize: 1 max: 13 count: 22 average: 13 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 22 ] +miss_latency_IFETCH_Directory: [binsize: 1 max: 181 count: 248 average: 152.827 | standard deviation: 5.37952 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 47 18 11 32 22 14 39 1 1 1 1 0 0 0 2 1 0 0 0 0 0 0 0 1 0 0 0 2 1 0 2 1 ] All Non-Zero Cycle SW Prefetch Requests ------------------------------------ @@ -126,11 +126,11 @@ Resource Usage page_size: 4096 user_time: 0 system_time: 0 -page_reclaims: 10290 +page_reclaims: 9871 page_faults: 0 swaps: 0 block_inputs: 0 -block_outputs: 0 +block_outputs: 64 Network Stats ------------- @@ -190,7 +190,7 @@ Cache Stats: system.ruby.cpu_ruby_ports.icache system.ruby.cpu_ruby_ports.icache_request_type_IFETCH: 100% - system.ruby.cpu_ruby_ports.icache_access_mode_type_SupervisorMode: 270 100% + system.ruby.cpu_ruby_ports.icache_access_mode_type_Supervisor: 270 100% Cache Stats: system.ruby.cpu_ruby_ports.dcache system.ruby.cpu_ruby_ports.dcache_total_misses: 240 @@ -202,7 +202,7 @@ Cache Stats: system.ruby.cpu_ruby_ports.dcache system.ruby.cpu_ruby_ports.dcache_request_type_LD: 75.8333% system.ruby.cpu_ruby_ports.dcache_request_type_ST: 24.1667% - system.ruby.cpu_ruby_ports.dcache_access_mode_type_SupervisorMode: 240 100% + system.ruby.cpu_ruby_ports.dcache_access_mode_type_Supervisor: 240 100% Cache Stats: system.l1_cntrl0.L2cacheMemory system.l1_cntrl0.L2cacheMemory_total_misses: 510 @@ -215,7 +215,7 @@ Cache Stats: system.l1_cntrl0.L2cacheMemory system.l1_cntrl0.L2cacheMemory_request_type_ST: 11.3725% system.l1_cntrl0.L2cacheMemory_request_type_IFETCH: 52.9412% - system.l1_cntrl0.L2cacheMemory_access_mode_type_SupervisorMode: 510 100% + system.l1_cntrl0.L2cacheMemory_access_mode_type_Supervisor: 510 100% --- L1Cache --- - Event Counts - @@ -242,6 +242,8 @@ Writeback_Ack [425 ] 425 Writeback_Nack [0 ] 0 All_acks [0 ] 0 All_acks_no_sharers [441 ] 441 +Flush_line [0 ] 0 +Block_Ack [0 ] 0 - Transitions - I Load [146 ] 146 @@ -256,6 +258,7 @@ I Other_GETS [0 ] 0 I Other_GETS_No_Mig [0 ] 0 I NC_DMA_GETS [0 ] 0 I Invalidate [0 ] 0 +I Flush_line [0 ] 0 S Load [0 ] 0 S Ifetch [0 ] 0 @@ -269,6 +272,7 @@ S Other_GETS [0 ] 0 S Other_GETS_No_Mig [0 ] 0 S NC_DMA_GETS [0 ] 0 S Invalidate [0 ] 0 +S Flush_line [0 ] 0 O Load [0 ] 0 O Ifetch [0 ] 0 @@ -283,6 +287,7 @@ O Merged_GETS [0 ] 0 O Other_GETS_No_Mig [0 ] 0 O NC_DMA_GETS [0 ] 0 O Invalidate [0 ] 0 +O Flush_line [0 ] 0 M Load [131 ] 131 M Ifetch [2337 ] 2337 @@ -297,6 +302,7 @@ M Merged_GETS [0 ] 0 M Other_GETS_No_Mig [0 ] 0 M NC_DMA_GETS [0 ] 0 M Invalidate [0 ] 0 +M Flush_line [0 ] 0 MM Load [138 ] 138 MM Ifetch [0 ] 0 @@ -311,6 +317,7 @@ MM Merged_GETS [0 ] 0 MM Other_GETS_No_Mig [0 ] 0 MM NC_DMA_GETS [0 ] 0 MM Invalidate [0 ] 0 +MM Flush_line [0 ] 0 IM Load [0 ] 0 IM Ifetch [0 ] 0 @@ -325,6 +332,7 @@ IM Invalidate [0 ] 0 IM Ack [0 ] 0 IM Data [0 ] 0 IM Exclusive_Data [47 ] 47 +IM Flush_line [0 ] 0 SM Load [0 ] 0 SM Ifetch [0 ] 0 @@ -339,6 +347,7 @@ SM Invalidate [0 ] 0 SM Ack [0 ] 0 SM Data [0 ] 0 SM Exclusive_Data [0 ] 0 +SM Flush_line [0 ] 0 OM Load [0 ] 0 OM Ifetch [0 ] 0 @@ -354,6 +363,7 @@ OM Invalidate [0 ] 0 OM Ack [0 ] 0 OM All_acks [0 ] 0 OM All_acks_no_sharers [0 ] 0 +OM Flush_line [0 ] 0 ISM Load [0 ] 0 ISM Ifetch [0 ] 0 @@ -362,6 +372,7 @@ ISM L2_Replacement [0 ] 0 ISM L1_to_L2 [0 ] 0 ISM Ack [0 ] 0 ISM All_acks_no_sharers [0 ] 0 +ISM Flush_line [0 ] 0 M_W Load [0 ] 0 M_W Ifetch [0 ] 0 @@ -370,6 +381,7 @@ M_W L2_Replacement [0 ] 0 M_W L1_to_L2 [0 ] 0 M_W Ack [0 ] 0 M_W All_acks_no_sharers [394 ] 394 +M_W Flush_line [0 ] 0 MM_W Load [0 ] 0 MM_W Ifetch [0 ] 0 @@ -378,6 +390,7 @@ MM_W L2_Replacement [0 ] 0 MM_W L1_to_L2 [0 ] 0 MM_W Ack [0 ] 0 MM_W All_acks_no_sharers [47 ] 47 +MM_W Flush_line [0 ] 0 IS Load [0 ] 0 IS Ifetch [0 ] 0 @@ -394,6 +407,7 @@ IS Shared_Ack [0 ] 0 IS Data [0 ] 0 IS Shared_Data [0 ] 0 IS Exclusive_Data [394 ] 394 +IS Flush_line [0 ] 0 SS Load [0 ] 0 SS Ifetch [0 ] 0 @@ -404,6 +418,7 @@ SS Ack [0 ] 0 SS Shared_Ack [0 ] 0 SS All_acks [0 ] 0 SS All_acks_no_sharers [0 ] 0 +SS Flush_line [0 ] 0 OI Load [0 ] 0 OI Ifetch [0 ] 0 @@ -417,6 +432,7 @@ OI Other_GETS_No_Mig [0 ] 0 OI NC_DMA_GETS [0 ] 0 OI Invalidate [0 ] 0 OI Writeback_Ack [0 ] 0 +OI Flush_line [0 ] 0 MI Load [7 ] 7 MI Ifetch [6 ] 6 @@ -430,6 +446,7 @@ MI Other_GETS_No_Mig [0 ] 0 MI NC_DMA_GETS [0 ] 0 MI Invalidate [0 ] 0 MI Writeback_Ack [425 ] 425 +MI Flush_line [0 ] 0 II Load [0 ] 0 II Ifetch [0 ] 0 @@ -443,6 +460,7 @@ II NC_DMA_GETS [0 ] 0 II Invalidate [0 ] 0 II Writeback_Ack [0 ] 0 II Writeback_Nack [0 ] 0 +II Flush_line [0 ] 0 IT Load [0 ] 0 IT Ifetch [0 ] 0 @@ -456,6 +474,7 @@ IT Merged_GETS [0 ] 0 IT Other_GETS_No_Mig [0 ] 0 IT NC_DMA_GETS [0 ] 0 IT Invalidate [0 ] 0 +IT Flush_line [0 ] 0 ST Load [0 ] 0 ST Ifetch [0 ] 0 @@ -469,6 +488,7 @@ ST Merged_GETS [0 ] 0 ST Other_GETS_No_Mig [0 ] 0 ST NC_DMA_GETS [0 ] 0 ST Invalidate [0 ] 0 +ST Flush_line [0 ] 0 OT Load [0 ] 0 OT Ifetch [0 ] 0 @@ -482,6 +502,7 @@ OT Merged_GETS [0 ] 0 OT Other_GETS_No_Mig [0 ] 0 OT NC_DMA_GETS [0 ] 0 OT Invalidate [0 ] 0 +OT Flush_line [0 ] 0 MT Load [0 ] 0 MT Ifetch [0 ] 0 @@ -495,6 +516,7 @@ MT Merged_GETS [0 ] 0 MT Other_GETS_No_Mig [0 ] 0 MT NC_DMA_GETS [0 ] 0 MT Invalidate [0 ] 0 +MT Flush_line [0 ] 0 MMT Load [0 ] 0 MMT Ifetch [0 ] 0 @@ -508,6 +530,94 @@ MMT Merged_GETS [0 ] 0 MMT Other_GETS_No_Mig [0 ] 0 MMT NC_DMA_GETS [0 ] 0 MMT Invalidate [0 ] 0 +MMT Flush_line [0 ] 0 + +MI_F Load [0 ] 0 +MI_F Ifetch [0 ] 0 +MI_F Store [0 ] 0 +MI_F L1_to_L2 [0 ] 0 +MI_F Writeback_Ack [0 ] 0 +MI_F Flush_line [0 ] 0 + +MM_F Load [0 ] 0 +MM_F Ifetch [0 ] 0 +MM_F Store [0 ] 0 +MM_F L1_to_L2 [0 ] 0 +MM_F Other_GETX [0 ] 0 +MM_F Other_GETS [0 ] 0 +MM_F Merged_GETS [0 ] 0 +MM_F Other_GETS_No_Mig [0 ] 0 +MM_F NC_DMA_GETS [0 ] 0 +MM_F Invalidate [0 ] 0 +MM_F Ack [0 ] 0 +MM_F All_acks [0 ] 0 +MM_F All_acks_no_sharers [0 ] 0 +MM_F Flush_line [0 ] 0 +MM_F Block_Ack [0 ] 0 + +IM_F Load [0 ] 0 +IM_F Ifetch [0 ] 0 +IM_F Store [0 ] 0 +IM_F L2_Replacement [0 ] 0 +IM_F L1_to_L2 [0 ] 0 +IM_F Other_GETX [0 ] 0 +IM_F Other_GETS [0 ] 0 +IM_F Other_GETS_No_Mig [0 ] 0 +IM_F NC_DMA_GETS [0 ] 0 +IM_F Invalidate [0 ] 0 +IM_F Ack [0 ] 0 +IM_F Data [0 ] 0 +IM_F Exclusive_Data [0 ] 0 +IM_F Flush_line [0 ] 0 + +ISM_F Load [0 ] 0 +ISM_F Ifetch [0 ] 0 +ISM_F Store [0 ] 0 +ISM_F L2_Replacement [0 ] 0 +ISM_F L1_to_L2 [0 ] 0 +ISM_F Ack [0 ] 0 +ISM_F All_acks_no_sharers [0 ] 0 +ISM_F Flush_line [0 ] 0 + +SM_F Load [0 ] 0 +SM_F Ifetch [0 ] 0 +SM_F Store [0 ] 0 +SM_F L2_Replacement [0 ] 0 +SM_F L1_to_L2 [0 ] 0 +SM_F Other_GETX [0 ] 0 +SM_F Other_GETS [0 ] 0 +SM_F Other_GETS_No_Mig [0 ] 0 +SM_F NC_DMA_GETS [0 ] 0 +SM_F Invalidate [0 ] 0 +SM_F Ack [0 ] 0 +SM_F Data [0 ] 0 +SM_F Exclusive_Data [0 ] 0 +SM_F Flush_line [0 ] 0 + +OM_F Load [0 ] 0 +OM_F Ifetch [0 ] 0 +OM_F Store [0 ] 0 +OM_F L2_Replacement [0 ] 0 +OM_F L1_to_L2 [0 ] 0 +OM_F Other_GETX [0 ] 0 +OM_F Other_GETS [0 ] 0 +OM_F Merged_GETS [0 ] 0 +OM_F Other_GETS_No_Mig [0 ] 0 +OM_F NC_DMA_GETS [0 ] 0 +OM_F Invalidate [0 ] 0 +OM_F Ack [0 ] 0 +OM_F All_acks [0 ] 0 +OM_F All_acks_no_sharers [0 ] 0 +OM_F Flush_line [0 ] 0 + +MM_WF Load [0 ] 0 +MM_WF Ifetch [0 ] 0 +MM_WF Store [0 ] 0 +MM_WF L2_Replacement [0 ] 0 +MM_WF L1_to_L2 [0 ] 0 +MM_WF Ack [0 ] 0 +MM_WF All_acks_no_sharers [0 ] 0 +MM_WF Flush_line [0 ] 0 Cache Stats: system.dir_cntrl0.probeFilter system.dir_cntrl0.probeFilter_total_misses: 0 @@ -563,6 +673,8 @@ All_acks_and_shared_data [0 ] 0 All_acks_and_owner_data [0 ] 0 All_acks_and_data_no_sharers [0 ] 0 All_Unblocks [0 ] 0 +GETF [0 ] 0 +PUTF [0 ] 0 - Transitions - NX GETX [0 ] 0 @@ -571,6 +683,7 @@ NX PUT [0 ] 0 NX Pf_Replacement [0 ] 0 NX DMA_READ [0 ] 0 NX DMA_WRITE [0 ] 0 +NX GETF [0 ] 0 NO GETX [0 ] 0 NO GETS [0 ] 0 @@ -578,6 +691,7 @@ NO PUT [425 ] 425 NO Pf_Replacement [0 ] 0 NO DMA_READ [0 ] 0 NO DMA_WRITE [0 ] 0 +NO GETF [0 ] 0 S GETX [0 ] 0 S GETS [0 ] 0 @@ -585,6 +699,7 @@ S PUT [0 ] 0 S Pf_Replacement [0 ] 0 S DMA_READ [0 ] 0 S DMA_WRITE [0 ] 0 +S GETF [0 ] 0 O GETX [0 ] 0 O GETS [0 ] 0 @@ -592,12 +707,14 @@ O PUT [0 ] 0 O Pf_Replacement [0 ] 0 O DMA_READ [0 ] 0 O DMA_WRITE [0 ] 0 +O GETF [0 ] 0 E GETX [47 ] 47 E GETS [394 ] 394 E PUT [0 ] 0 E DMA_READ [0 ] 0 E DMA_WRITE [0 ] 0 +E GETF [0 ] 0 O_R GETX [0 ] 0 O_R GETS [0 ] 0 @@ -607,6 +724,7 @@ O_R DMA_READ [0 ] 0 O_R DMA_WRITE [0 ] 0 O_R Ack [0 ] 0 O_R All_acks_and_data_no_sharers [0 ] 0 +O_R GETF [0 ] 0 S_R GETX [0 ] 0 S_R GETS [0 ] 0 @@ -617,6 +735,7 @@ S_R DMA_WRITE [0 ] 0 S_R Ack [0 ] 0 S_R Data [0 ] 0 S_R All_acks_and_data_no_sharers [0 ] 0 +S_R GETF [0 ] 0 NO_R GETX [0 ] 0 NO_R GETS [0 ] 0 @@ -628,6 +747,7 @@ NO_R Ack [0 ] 0 NO_R Data [0 ] 0 NO_R Exclusive_Data [0 ] 0 NO_R All_acks_and_data_no_sharers [0 ] 0 +NO_R GETF [0 ] 0 NO_B GETX [0 ] 0 NO_B GETS [0 ] 0 @@ -637,6 +757,7 @@ NO_B UnblockM [440 ] 440 NO_B Pf_Replacement [0 ] 0 NO_B DMA_READ [0 ] 0 NO_B DMA_WRITE [0 ] 0 +NO_B GETF [0 ] 0 NO_B_X GETX [0 ] 0 NO_B_X GETS [0 ] 0 @@ -646,6 +767,7 @@ NO_B_X UnblockM [0 ] 0 NO_B_X Pf_Replacement [0 ] 0 NO_B_X DMA_READ [0 ] 0 NO_B_X DMA_WRITE [0 ] 0 +NO_B_X GETF [0 ] 0 NO_B_S GETX [0 ] 0 NO_B_S GETS [0 ] 0 @@ -655,6 +777,7 @@ NO_B_S UnblockM [0 ] 0 NO_B_S Pf_Replacement [0 ] 0 NO_B_S DMA_READ [0 ] 0 NO_B_S DMA_WRITE [0 ] 0 +NO_B_S GETF [0 ] 0 NO_B_S_W GETX [0 ] 0 NO_B_S_W GETS [0 ] 0 @@ -664,6 +787,7 @@ NO_B_S_W Pf_Replacement [0 ] 0 NO_B_S_W DMA_READ [0 ] 0 NO_B_S_W DMA_WRITE [0 ] 0 NO_B_S_W All_Unblocks [0 ] 0 +NO_B_S_W GETF [0 ] 0 O_B GETX [0 ] 0 O_B GETS [0 ] 0 @@ -673,6 +797,7 @@ O_B UnblockM [0 ] 0 O_B Pf_Replacement [0 ] 0 O_B DMA_READ [0 ] 0 O_B DMA_WRITE [0 ] 0 +O_B GETF [0 ] 0 NO_B_W GETX [0 ] 0 NO_B_W GETS [0 ] 0 @@ -683,6 +808,7 @@ NO_B_W Pf_Replacement [0 ] 0 NO_B_W DMA_READ [0 ] 0 NO_B_W DMA_WRITE [0 ] 0 NO_B_W Memory_Data [441 ] 441 +NO_B_W GETF [0 ] 0 O_B_W GETX [0 ] 0 O_B_W GETS [0 ] 0 @@ -692,6 +818,7 @@ O_B_W Pf_Replacement [0 ] 0 O_B_W DMA_READ [0 ] 0 O_B_W DMA_WRITE [0 ] 0 O_B_W Memory_Data [0 ] 0 +O_B_W GETF [0 ] 0 NO_W GETX [0 ] 0 NO_W GETS [0 ] 0 @@ -700,6 +827,7 @@ NO_W Pf_Replacement [0 ] 0 NO_W DMA_READ [0 ] 0 NO_W DMA_WRITE [0 ] 0 NO_W Memory_Data [0 ] 0 +NO_W GETF [0 ] 0 O_W GETX [0 ] 0 O_W GETS [0 ] 0 @@ -708,6 +836,7 @@ O_W Pf_Replacement [0 ] 0 O_W DMA_READ [0 ] 0 O_W DMA_WRITE [0 ] 0 O_W Memory_Data [0 ] 0 +O_W GETF [0 ] 0 NO_DW_B_W GETX [0 ] 0 NO_DW_B_W GETS [0 ] 0 @@ -719,6 +848,7 @@ NO_DW_B_W Ack [0 ] 0 NO_DW_B_W Data [0 ] 0 NO_DW_B_W Exclusive_Data [0 ] 0 NO_DW_B_W All_acks_and_data_no_sharers [0 ] 0 +NO_DW_B_W GETF [0 ] 0 NO_DR_B_W GETX [0 ] 0 NO_DR_B_W GETS [0 ] 0 @@ -732,6 +862,7 @@ NO_DR_B_W Shared_Ack [0 ] 0 NO_DR_B_W Shared_Data [0 ] 0 NO_DR_B_W Data [0 ] 0 NO_DR_B_W Exclusive_Data [0 ] 0 +NO_DR_B_W GETF [0 ] 0 NO_DR_B_D GETX [0 ] 0 NO_DR_B_D GETS [0 ] 0 @@ -747,6 +878,7 @@ NO_DR_B_D Exclusive_Data [0 ] 0 NO_DR_B_D All_acks_and_shared_data [0 ] 0 NO_DR_B_D All_acks_and_owner_data [0 ] 0 NO_DR_B_D All_acks_and_data_no_sharers [0 ] 0 +NO_DR_B_D GETF [0 ] 0 NO_DR_B GETX [0 ] 0 NO_DR_B GETS [0 ] 0 @@ -762,6 +894,7 @@ NO_DR_B Exclusive_Data [0 ] 0 NO_DR_B All_acks_and_shared_data [0 ] 0 NO_DR_B All_acks_and_owner_data [0 ] 0 NO_DR_B All_acks_and_data_no_sharers [0 ] 0 +NO_DR_B GETF [0 ] 0 NO_DW_W GETX [0 ] 0 NO_DW_W GETS [0 ] 0 @@ -770,6 +903,7 @@ NO_DW_W Pf_Replacement [0 ] 0 NO_DW_W DMA_READ [0 ] 0 NO_DW_W DMA_WRITE [0 ] 0 NO_DW_W Memory_Ack [0 ] 0 +NO_DW_W GETF [0 ] 0 O_DR_B_W GETX [0 ] 0 O_DR_B_W GETS [0 ] 0 @@ -780,6 +914,7 @@ O_DR_B_W DMA_WRITE [0 ] 0 O_DR_B_W Memory_Data [0 ] 0 O_DR_B_W Ack [0 ] 0 O_DR_B_W Shared_Ack [0 ] 0 +O_DR_B_W GETF [0 ] 0 O_DR_B GETX [0 ] 0 O_DR_B GETS [0 ] 0 @@ -791,6 +926,7 @@ O_DR_B Ack [0 ] 0 O_DR_B Shared_Ack [0 ] 0 O_DR_B All_acks_and_owner_data [0 ] 0 O_DR_B All_acks_and_data_no_sharers [0 ] 0 +O_DR_B GETF [0 ] 0 WB GETX [4 ] 4 WB GETS [14 ] 14 @@ -803,6 +939,7 @@ WB Writeback_Exclusive_Dirty [81 ] 81 WB Pf_Replacement [0 ] 0 WB DMA_READ [0 ] 0 WB DMA_WRITE [0 ] 0 +WB GETF [0 ] 0 WB_O_W GETX [0 ] 0 WB_O_W GETS [0 ] 0 @@ -811,6 +948,7 @@ WB_O_W Pf_Replacement [0 ] 0 WB_O_W DMA_READ [0 ] 0 WB_O_W DMA_WRITE [0 ] 0 WB_O_W Memory_Ack [0 ] 0 +WB_O_W GETF [0 ] 0 WB_E_W GETX [2 ] 2 WB_E_W GETS [2 ] 2 @@ -818,4 +956,22 @@ WB_E_W PUT [0 ] 0 WB_E_W Pf_Replacement [0 ] 0 WB_E_W DMA_READ [0 ] 0 WB_E_W DMA_WRITE [0 ] 0 -WB_E_W Memory_Ack
\ No newline at end of file +WB_E_W Memory_Ack [81 ] 81 +WB_E_W GETF [0 ] 0 + +NO_F GETX [0 ] 0 +NO_F GETS [0 ] 0 +NO_F PUT [0 ] 0 +NO_F UnblockM [0 ] 0 +NO_F Pf_Replacement [0 ] 0 +NO_F GETF [0 ] 0 +NO_F PUTF [0 ] 0 + +NO_F_W GETX [0 ] 0 +NO_F_W GETS [0 ] 0 +NO_F_W PUT [0 ] 0 +NO_F_W Pf_Replacement [0 ] 0 +NO_F_W DMA_READ [0 ] 0 +NO_F_W DMA_WRITE [0 ] 0 +NO_F_W Memory_Data [0 ] 0 +NO_F_W GETF
\ No newline at end of file diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout index 06957aba3..256657039 100755 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout @@ -5,10 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 8 2011 17:56:59 -M5 revision 685719afafe6+ 7938+ default tip brad/increase_ruby_mem_test_threshold qtip -M5 started Feb 8 2011 17:57:03 -M5 executing on SC2B0617 +M5 compiled Apr 19 2011 12:09:47 +M5 started Apr 19 2011 12:09:50 +M5 executing on maize command line: build/ALPHA_SE_MOESI_hammer/m5.fast -d build/ALPHA_SE_MOESI_hammer/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer -re tests/run.py build/ALPHA_SE_MOESI_hammer/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt index 73743c0c5..6446a9edb 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 49095 # Simulator instruction rate (inst/s) -host_mem_usage 213896 # Number of bytes of host memory used -host_seconds 0.05 # Real time elapsed on the host -host_tick_rate 1489708 # Simulator tick rate (ticks/s) +host_inst_rate 62557 # Simulator instruction rate (inst/s) +host_mem_usage 212072 # Number of bytes of host memory used +host_seconds 0.04 # Real time elapsed on the host +host_tick_rate 1897992 # Simulator tick rate (ticks/s) sim_freq 1000000000 # Frequency of simulated ticks sim_insts 2577 # Number of instructions simulated sim_seconds 0.000078 # Number of seconds simulated @@ -61,6 +61,6 @@ system.cpu.num_int_register_writes 1768 # nu system.cpu.num_load_insts 419 # Number of load instructions system.cpu.num_mem_refs 717 # number of memory refs system.cpu.num_store_insts 298 # Number of store instructions -system.cpu.workload.PROG:num_syscalls 4 # Number of system calls +system.cpu.workload.num_syscalls 4 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini index 71495ec84..a38ab1515 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini @@ -160,6 +160,7 @@ deadlock_threshold=500000 icache=system.ruby.cpu_ruby_ports.dcache max_outstanding_requests=16 physmem=system.physmem +using_network_tester=false using_ruby_tester=false version=0 physMemPort=system.physmem.port[0] diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/ruby.stats b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/ruby.stats index c43ead0e8..986bc42a5 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/ruby.stats +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/ruby.stats @@ -34,27 +34,27 @@ periodic_stats_period: 1000000 ================ End RubySystem Configuration Print ================ -Real time: Feb/07/2011 01:47:37 +Real time: Apr/19/2011 12:00:50 Profiler Stats -------------- -Elapsed_time_in_seconds: 1 -Elapsed_time_in_minutes: 0.0166667 -Elapsed_time_in_hours: 0.000277778 -Elapsed_time_in_days: 1.15741e-05 +Elapsed_time_in_seconds: 0 +Elapsed_time_in_minutes: 0 +Elapsed_time_in_hours: 0 +Elapsed_time_in_days: 0 -Virtual_time_in_seconds: 0.26 -Virtual_time_in_minutes: 0.00433333 -Virtual_time_in_hours: 7.22222e-05 -Virtual_time_in_days: 3.00926e-06 +Virtual_time_in_seconds: 0.13 +Virtual_time_in_minutes: 0.00216667 +Virtual_time_in_hours: 3.61111e-05 +Virtual_time_in_days: 1.50463e-06 Ruby_current_time: 123378 Ruby_start_time: 0 Ruby_cycles: 123378 -mbytes_resident: 36.4062 -mbytes_total: 226.781 -resident_ratio: 0.160552 +mbytes_resident: 37.2734 +mbytes_total: 207.098 +resident_ratio: 0.179999 ruby_cycles_executed: [ 123379 ] @@ -70,9 +70,9 @@ sequencer_requests_outstanding: [binsize: 1 max: 1 count: 3295 average: 1 | All Non-Zero Cycle Demand Cache Accesses ---------------------------------------- miss_latency: [binsize: 2 max: 375 count: 3294 average: 36.4554 | standard deviation: 69.7725 | 0 2668 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 0 0 0 3 1 1 4 2 101 88 63 177 126 0 1 1 8 0 2 1 1 4 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7 4 5 13 2 0 0 0 1 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 ] -miss_latency_IFETCH: [binsize: 2 max: 375 count: 2585 average: 23.1702 | standard deviation: 56.4841 | 0 2288 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 2 0 0 2 2 31 53 29 71 82 0 1 0 5 0 1 1 1 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 2 1 3 2 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] miss_latency_LD: [binsize: 2 max: 281 count: 415 average: 107.304 | standard deviation: 88.8453 | 0 170 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 0 2 0 56 24 27 75 32 0 0 1 3 0 1 0 0 2 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 0 4 7 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] miss_latency_ST: [binsize: 2 max: 265 count: 294 average: 53.2585 | standard deviation: 80.456 | 0 210 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 14 11 7 31 12 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_IFETCH: [binsize: 2 max: 375 count: 2585 average: 23.1702 | standard deviation: 56.4841 | 0 2288 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 2 0 0 2 2 31 53 29 71 82 0 1 0 5 0 1 1 1 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 2 1 3 2 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] miss_latency_L1Cache: [binsize: 1 max: 3 count: 2668 average: 3 | standard deviation: 0 | 0 0 0 2668 ] miss_latency_Directory: [binsize: 2 max: 375 count: 626 average: 179.042 | standard deviation: 22.5462 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 0 0 0 3 1 1 4 2 101 88 63 177 126 0 1 1 8 0 2 1 1 4 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7 4 5 13 2 0 0 0 1 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 ] miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] @@ -85,12 +85,12 @@ miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 1 average: miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ] miss_latency_dir_first_response_to_completion: [binsize: 1 max: 159 count: 1 average: 159 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] imcomplete_dir_Times: 625 -miss_latency_IFETCH_L1Cache: [binsize: 1 max: 3 count: 2288 average: 3 | standard deviation: 0 | 0 0 0 2288 ] -miss_latency_IFETCH_Directory: [binsize: 2 max: 375 count: 297 average: 178.556 | standard deviation: 21.9279 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 2 0 0 2 2 31 53 29 71 82 0 1 0 5 0 1 1 1 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 2 1 3 2 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] miss_latency_LD_L1Cache: [binsize: 1 max: 3 count: 170 average: 3 | standard deviation: 0 | 0 0 0 170 ] miss_latency_LD_Directory: [binsize: 2 max: 281 count: 245 average: 179.678 | standard deviation: 23.5327 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 0 2 0 56 24 27 75 32 0 0 1 3 0 1 0 0 2 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 0 4 7 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] miss_latency_ST_L1Cache: [binsize: 1 max: 3 count: 210 average: 3 | standard deviation: 0 | 0 0 0 210 ] miss_latency_ST_Directory: [binsize: 2 max: 265 count: 84 average: 178.905 | standard deviation: 21.977 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 14 11 7 31 12 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_IFETCH_L1Cache: [binsize: 1 max: 3 count: 2288 average: 3 | standard deviation: 0 | 0 0 0 2288 ] +miss_latency_IFETCH_Directory: [binsize: 2 max: 375 count: 297 average: 178.556 | standard deviation: 21.9279 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 2 0 0 2 2 31 53 29 71 82 0 1 0 5 0 1 1 1 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 2 1 3 2 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] All Non-Zero Cycle SW Prefetch Requests ------------------------------------ @@ -122,7 +122,7 @@ Resource Usage page_size: 4096 user_time: 0 system_time: 0 -page_reclaims: 10395 +page_reclaims: 9841 page_faults: 0 swaps: 0 block_inputs: 0 @@ -181,7 +181,7 @@ Cache Stats: system.ruby.cpu_ruby_ports.dcache system.ruby.cpu_ruby_ports.dcache_request_type_ST: 13.4185% system.ruby.cpu_ruby_ports.dcache_request_type_IFETCH: 47.4441% - system.ruby.cpu_ruby_ports.dcache_access_mode_type_SupervisorMode: 626 100% + system.ruby.cpu_ruby_ports.dcache_access_mode_type_Supervisor: 626 100% --- L1Cache --- - Event Counts - diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/simout b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/simout index 5f04faac1..69d07c3aa 100755 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/simout +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/simout @@ -5,10 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 7 2011 01:47:18 -M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip -M5 started Feb 7 2011 01:47:36 -M5 executing on burrito +M5 compiled Apr 19 2011 11:52:53 +M5 started Apr 19 2011 12:00:50 +M5 executing on maize command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt index 8d615ceb9..a05c1b96e 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 17883 # Simulator instruction rate (inst/s) -host_mem_usage 232228 # Number of bytes of host memory used -host_seconds 0.14 # Real time elapsed on the host -host_tick_rate 854675 # Simulator tick rate (ticks/s) +host_inst_rate 79660 # Simulator instruction rate (inst/s) +host_mem_usage 212072 # Number of bytes of host memory used +host_seconds 0.03 # Real time elapsed on the host +host_tick_rate 3797301 # Simulator tick rate (ticks/s) sim_freq 1000000000 # Frequency of simulated ticks sim_insts 2577 # Number of instructions simulated sim_seconds 0.000123 # Number of seconds simulated @@ -61,6 +61,6 @@ system.cpu.num_int_register_writes 1768 # nu system.cpu.num_load_insts 419 # Number of load instructions system.cpu.num_mem_refs 717 # number of memory refs system.cpu.num_store_insts 298 # Number of store instructions -system.cpu.workload.PROG:num_syscalls 4 # Number of system calls +system.cpu.workload.num_syscalls 4 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini index 6019fe73e..965487eb2 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini @@ -51,6 +51,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=true latency=1000 max_miss_count=0 mshrs=10 @@ -86,6 +87,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=true latency=1000 max_miss_count=0 mshrs=10 @@ -121,6 +123,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=false latency=10000 max_miss_count=0 mshrs=10 diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/simout b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/simout index 37ac69d98..363499d94 100755 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/simout +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/simout @@ -5,10 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 7 2011 01:47:18 -M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip -M5 started Feb 7 2011 01:47:36 -M5 executing on burrito +M5 compiled Apr 19 2011 11:52:53 +M5 started Apr 19 2011 11:58:24 +M5 executing on maize command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stats.txt index aa9ef9160..a8a5eaa16 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 236465 # Simulator instruction rate (inst/s) -host_mem_usage 222144 # Number of bytes of host memory used +host_inst_rate 195987 # Simulator instruction rate (inst/s) +host_mem_usage 201848 # Number of bytes of host memory used host_seconds 0.01 # Real time elapsed on the host -host_tick_rate 1500776387 # Simulator tick rate (ticks/s) +host_tick_rate 1258278911 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 2577 # Number of instructions simulated sim_seconds 0.000017 # Number of seconds simulated @@ -50,8 +50,8 @@ system.cpu.dcache.demand_mshr_misses 82 # nu system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.011577 # Average percentage of cache occupancy system.cpu.dcache.occ_blocks::0 47.418751 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.011577 # Average percentage of cache occupancy system.cpu.dcache.overall_accesses 709 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency @@ -121,8 +121,8 @@ system.cpu.icache.demand_mshr_misses 163 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.039064 # Average percentage of cache occupancy system.cpu.icache.occ_blocks::0 80.003762 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.039064 # Average percentage of cache occupancy system.cpu.icache.overall_accesses 2586 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency @@ -201,8 +201,8 @@ system.cpu.l2cache.demand_mshr_misses 245 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.003268 # Average percentage of cache occupancy system.cpu.l2cache.occ_blocks::0 107.101205 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.003268 # Average percentage of cache occupancy system.cpu.l2cache.overall_accesses 245 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency @@ -244,6 +244,6 @@ system.cpu.num_int_register_writes 1768 # nu system.cpu.num_load_insts 419 # Number of load instructions system.cpu.num_mem_refs 717 # number of memory refs system.cpu.num_store_insts 298 # Number of store instructions -system.cpu.workload.PROG:num_syscalls 4 # Number of system calls +system.cpu.workload.num_syscalls 4 # Number of system calls ---------- End Simulation Statistics ---------- |