diff options
| author | Gabe Black <gblack@eecs.umich.edu> | 2007-06-22 15:06:10 -0400 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2007-06-22 15:06:10 -0400 |
| commit | 8e6abaed797d567b4ce009abac63ba19f87efa28 (patch) | |
| tree | 9e906217ff701f768e7c5e0fc7477c7c72cb2df9 /tests/quick/00.hello/ref/alpha | |
| parent | 49490b334af3bc145071a9a81f37012e7693af59 (diff) | |
| download | gem5-8e6abaed797d567b4ce009abac63ba19f87efa28.tar.xz | |
Update of reference outputs. SPARC_SE o3 gzip didn't have reference outputs, mcf has a reduced input size, and most of the other changes are for a change in how branch mispredicts work which makes things more accurate.
--HG--
extra : convert_revision : 33ad6a220945b344d2fc5c6abef8e67467e0c0ec
Diffstat (limited to 'tests/quick/00.hello/ref/alpha')
6 files changed, 289 insertions, 261 deletions
diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini b/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini index f2617931a..f112ef506 100644 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini @@ -21,6 +21,7 @@ SQEntries=32 SSITSize=1024 activity=0 backComSize=5 +cachePorts=200 choiceCtrBits=2 choicePredictorSize=8192 clock=500 @@ -74,6 +75,15 @@ renameToFetchDelay=1 renameToIEWDelay=2 renameToROBDelay=1 renameWidth=8 +smtCommitPolicy=RoundRobin +smtFetchPolicy=SingleThread +smtIQPolicy=Partitioned +smtIQThreshold=100 +smtLSQPolicy=Partitioned +smtLSQThreshold=100 +smtNumFetchingThreads=1 +smtROBPolicy=Partitioned +smtROBThreshold=100 squashWidth=8 system=system trapLatency=13 @@ -86,6 +96,7 @@ icache_port=system.cpu.icache.cpu_side [system.cpu.dcache] type=BaseCache adaptive_compression=false +addr_range=0:18446744073709551615 assoc=2 block_size=64 compressed_bus=false @@ -261,6 +272,7 @@ opLat=3 [system.cpu.icache] type=BaseCache adaptive_compression=false +addr_range=0:18446744073709551615 assoc=2 block_size=64 compressed_bus=false @@ -299,6 +311,7 @@ mem_side=system.cpu.toL2Bus.port[0] [system.cpu.l2cache] type=BaseCache adaptive_compression=false +addr_range=0:18446744073709551615 assoc=2 block_size=64 compressed_bus=false diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt index e1bed0c51..2ac86dd84 100644 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt @@ -1,39 +1,40 @@ ---------- Begin Simulation Statistics ---------- global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 524 # Number of BTB hits -global.BPredUnit.BTBLookups 1590 # Number of BTB lookups +global.BPredUnit.BTBHits 522 # Number of BTB hits +global.BPredUnit.BTBLookups 1584 # Number of BTB lookups global.BPredUnit.RASInCorrect 57 # Number of incorrect RAS predictions. global.BPredUnit.condIncorrect 422 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 1093 # Number of conditional branches predicted -global.BPredUnit.lookups 1843 # Number of BP lookups +global.BPredUnit.condPredicted 1088 # Number of conditional branches predicted +global.BPredUnit.lookups 1837 # Number of BP lookups global.BPredUnit.usedRAS 241 # Number of times the RAS was used to get a target. -host_inst_rate 7145 # Simulator instruction rate (inst/s) -host_seconds 0.79 # Real time elapsed on the host -host_tick_rate 5828052 # Simulator tick rate (ticks/s) +host_inst_rate 39303 # Simulator instruction rate (inst/s) +host_mem_usage 153768 # Number of bytes of host memory used +host_seconds 0.14 # Real time elapsed on the host +host_tick_rate 32016268 # Simulator tick rate (ticks/s) memdepunit.memDep.conflictingLoads 17 # Number of conflicting loads. memdepunit.memDep.conflictingStores 127 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 1876 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 1144 # Number of stores inserted to the mem dependence unit. +memdepunit.memDep.insertedLoads 1874 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 1142 # Number of stores inserted to the mem dependence unit. sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5623 # Number of instructions simulated sim_seconds 0.000005 # Number of seconds simulated -sim_ticks 4588000 # Number of ticks simulated +sim_ticks 4589500 # Number of ticks simulated system.cpu.commit.COM:branches 862 # Number of branches committed system.cpu.commit.COM:bw_lim_events 104 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 8514 +system.cpu.commit.COM:committed_per_cycle.samples 8521 system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 6195 7276.25% - 1 1158 1360.11% - 2 469 550.86% - 3 176 206.72% - 4 131 153.86% - 5 99 116.28% - 6 109 128.02% - 7 73 85.74% - 8 104 122.15% + 0 6200 7276.14% + 1 1160 1361.34% + 2 469 550.40% + 3 177 207.72% + 4 131 153.74% + 5 98 115.01% + 6 109 127.92% + 7 73 85.67% + 8 104 122.05% system.cpu.commit.COM:committed_per_cycle.max_value 8 system.cpu.commit.COM:committed_per_cycle.end_dist @@ -45,27 +46,27 @@ system.cpu.commit.COM:swp_count 0 # Nu system.cpu.commit.branchMispredicts 350 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 5640 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 3588 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 3571 # The number of squashed insts skipped by commit system.cpu.committedInsts 5623 # Number of Instructions Simulated system.cpu.committedInsts_total 5623 # Number of Instructions Simulated -system.cpu.cpi 1.635604 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.635604 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 1475 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 5928.571429 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 5385 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 1342 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 788500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.090169 # miss rate for ReadReq accesses +system.cpu.cpi 1.636315 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.636315 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 1470 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 5932.330827 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 5380 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 1337 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 789000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.090476 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 133 # number of ReadReq misses system.cpu.dcache.ReadReq_mshr_hits 33 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 538500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.067797 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency 538000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.068027 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 100 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 812 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 4501.457726 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 4504.373178 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency 5116.438356 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 469 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 1544000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 1545000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.422414 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 343 # number of WriteReq misses system.cpu.dcache.WriteReq_mshr_hits 270 # number of WriteReq MSHR hits @@ -74,37 +75,37 @@ system.cpu.dcache.WriteReq_mshr_miss_rate 0.089901 # m system.cpu.dcache.WriteReq_mshr_misses 73 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 10.468208 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 10.439306 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 2287 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 4900.210084 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 5271.676301 # average overall mshr miss latency -system.cpu.dcache.demand_hits 1811 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 2332500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.208133 # miss rate for demand accesses +system.cpu.dcache.demand_accesses 2282 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 4903.361345 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 5268.786127 # average overall mshr miss latency +system.cpu.dcache.demand_hits 1806 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 2334000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.208589 # miss rate for demand accesses system.cpu.dcache.demand_misses 476 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 303 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 912000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.075645 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_latency 911500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.075811 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 173 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 2287 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 4900.210084 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 5271.676301 # average overall mshr miss latency +system.cpu.dcache.overall_accesses 2282 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 4903.361345 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 5268.786127 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 1811 # number of overall hits -system.cpu.dcache.overall_miss_latency 2332500 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.208133 # miss rate for overall accesses +system.cpu.dcache.overall_hits 1806 # number of overall hits +system.cpu.dcache.overall_miss_latency 2334000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.208589 # miss rate for overall accesses system.cpu.dcache.overall_misses 476 # number of overall misses system.cpu.dcache.overall_mshr_hits 303 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 912000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.075645 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_latency 911500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.075811 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 173 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses @@ -120,88 +121,88 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 173 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 112.670676 # Cycle average of tags in use -system.cpu.dcache.total_refs 1811 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 112.669258 # Cycle average of tags in use +system.cpu.dcache.total_refs 1806 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks system.cpu.decode.DECODE:BlockedCycles 389 # Number of cycles decode is blocked system.cpu.decode.DECODE:BranchMispred 75 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 144 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 10499 # Number of instructions handled by decode +system.cpu.decode.DECODE:BranchResolved 143 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 10466 # Number of instructions handled by decode system.cpu.decode.DECODE:IdleCycles 6230 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 1848 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 682 # Number of cycles decode is squashing +system.cpu.decode.DECODE:RunCycles 1855 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 679 # Number of cycles decode is squashing system.cpu.decode.DECODE:SquashedInsts 228 # Number of squashed instructions handled by decode system.cpu.decode.DECODE:UnblockCycles 48 # Number of cycles decode is unblocking -system.cpu.fetch.Branches 1843 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 1471 # Number of cache lines fetched -system.cpu.fetch.Cycles 3451 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 269 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 11450 # Number of instructions fetch has processed +system.cpu.fetch.Branches 1837 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 1469 # Number of cache lines fetched +system.cpu.fetch.Cycles 3456 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 267 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 11417 # Number of instructions fetch has processed system.cpu.fetch.SquashCycles 455 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.200391 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 1471 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 765 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 1.244971 # Number of inst fetches per cycle +system.cpu.fetch.branchRate 0.199652 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 1469 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 763 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.240843 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 9197 +system.cpu.fetch.rateDist.samples 9201 system.cpu.fetch.rateDist.min_value 0 - 0 7219 7849.30% - 1 167 181.58% - 2 147 159.83% - 3 129 140.26% - 4 200 217.46% - 5 139 151.14% - 6 181 196.80% - 7 99 107.64% - 8 916 995.98% + 0 7216 7842.63% + 1 168 182.59% + 2 148 160.85% + 3 136 147.81% + 4 214 232.58% + 5 138 149.98% + 6 177 192.37% + 7 95 103.25% + 8 909 987.94% system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.end_dist -system.cpu.icache.ReadReq_accesses 1471 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 5375.757576 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 4524.038462 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 1141 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 1774000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.224337 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_accesses 1469 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 5381.818182 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 4530.448718 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 1139 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 1776000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.224643 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 330 # number of ReadReq misses system.cpu.icache.ReadReq_mshr_hits 18 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 1411500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.212101 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_latency 1413500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.212389 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 312 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_refs 3.657051 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 3.650641 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 1471 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 5375.757576 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 4524.038462 # average overall mshr miss latency -system.cpu.icache.demand_hits 1141 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 1774000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.224337 # miss rate for demand accesses +system.cpu.icache.demand_accesses 1469 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 5381.818182 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 4530.448718 # average overall mshr miss latency +system.cpu.icache.demand_hits 1139 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 1776000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.224643 # miss rate for demand accesses system.cpu.icache.demand_misses 330 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 18 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 1411500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.212101 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_latency 1413500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.212389 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 312 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 1471 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 5375.757576 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 4524.038462 # average overall mshr miss latency +system.cpu.icache.overall_accesses 1469 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 5381.818182 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 4530.448718 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 1141 # number of overall hits -system.cpu.icache.overall_miss_latency 1774000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.224337 # miss rate for overall accesses +system.cpu.icache.overall_hits 1139 # number of overall hits +system.cpu.icache.overall_miss_latency 1776000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.224643 # miss rate for overall accesses system.cpu.icache.overall_misses 330 # number of overall misses system.cpu.icache.overall_mshr_hits 18 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 1411500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.212101 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_latency 1413500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.212389 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 312 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses @@ -217,39 +218,39 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 0 # number of replacements system.cpu.icache.sampled_refs 312 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 165.938349 # Cycle average of tags in use -system.cpu.icache.total_refs 1141 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 165.921810 # Cycle average of tags in use +system.cpu.icache.total_refs 1139 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 2475 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 1148 # Number of branches executed +system.cpu.idleCycles 2474 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 1144 # Number of branches executed system.cpu.iew.EXEC:nop 40 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.837338 # Inst execution rate -system.cpu.iew.EXEC:refs 2524 # number of memory reference insts executed +system.cpu.iew.EXEC:rate 0.835018 # Inst execution rate +system.cpu.iew.EXEC:refs 2519 # number of memory reference insts executed system.cpu.iew.EXEC:stores 977 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 5205 # num instructions consuming a value -system.cpu.iew.WB:count 7402 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.742747 # average fanout of values written-back +system.cpu.iew.WB:consumers 5193 # num instructions consuming a value +system.cpu.iew.WB:count 7387 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.742923 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 3866 # num instructions producing a value -system.cpu.iew.WB:rate 0.804828 # insts written-back per cycle -system.cpu.iew.WB:sent 7467 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 374 # Number of branch mispredicts detected at execute +system.cpu.iew.WB:producers 3858 # num instructions producing a value +system.cpu.iew.WB:rate 0.802848 # insts written-back per cycle +system.cpu.iew.WB:sent 7452 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 373 # Number of branch mispredicts detected at execute system.cpu.iew.iewBlockCycles 4 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 1876 # Number of dispatched load instructions +system.cpu.iew.iewDispLoadInsts 1874 # Number of dispatched load instructions system.cpu.iew.iewDispNonSpecInsts 22 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 315 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 1144 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 9245 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 1547 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 280 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 7701 # Number of executed instructions +system.cpu.iew.iewDispSquashedInsts 302 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 1142 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 9228 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 1542 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 285 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 7683 # Number of executed instructions system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 682 # Number of cycles IEW is squashing +system.cpu.iew.iewSquashCycles 679 # Number of cycles IEW is squashing system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked @@ -259,17 +260,17 @@ system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Nu system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread.0.memOrderViolation 63 # Number of memory ordering violations system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 897 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 332 # Number of stores squashed +system.cpu.iew.lsq.thread.0.squashedLoads 895 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 330 # Number of stores squashed system.cpu.iew.memOrderViolationEvents 63 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 263 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 262 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 111 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 0.611395 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.611395 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 7981 # Type of FU issued +system.cpu.ipc 0.611129 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.611129 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 7968 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist No_OpClass 2 0.03% # Type of FU issued - IntAlu 5322 66.68% # Type of FU issued + IntAlu 5314 66.69% # Type of FU issued IntMult 1 0.01% # Type of FU issued IntDiv 0 0.00% # Type of FU issued FloatAdd 2 0.03% # Type of FU issued @@ -278,13 +279,13 @@ system.cpu.iq.ISSUE:FU_type_0.start_dist FloatMult 0 0.00% # Type of FU issued FloatDiv 0 0.00% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 1662 20.82% # Type of FU issued - MemWrite 992 12.43% # Type of FU issued + MemRead 1659 20.82% # Type of FU issued + MemWrite 990 12.42% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 106 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.013282 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_cnt 105 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.013178 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full.start_dist No_OpClass 0 0.00% # attempts to use FU when none available IntAlu 0 0.00% # attempts to use FU when none available @@ -296,41 +297,41 @@ system.cpu.iq.ISSUE:fu_full.start_dist FloatMult 0 0.00% # attempts to use FU when none available FloatDiv 0 0.00% # attempts to use FU when none available FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 71 66.98% # attempts to use FU when none available - MemWrite 35 33.02% # attempts to use FU when none available + MemRead 70 66.67% # attempts to use FU when none available + MemWrite 35 33.33% # attempts to use FU when none available IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 9197 +system.cpu.iq.ISSUE:issued_per_cycle.samples 9201 system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 5952 6471.68% - 1 1107 1203.65% - 2 919 999.24% - 3 442 480.59% - 4 375 407.74% - 5 250 271.83% - 6 115 125.04% - 7 26 28.27% - 8 11 11.96% + 0 5952 6468.86% + 1 1111 1207.48% + 2 928 1008.59% + 3 433 470.60% + 4 378 410.82% + 5 251 272.80% + 6 111 120.64% + 7 27 29.34% + 8 10 10.87% system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.end_dist -system.cpu.iq.ISSUE:rate 0.867783 # Inst issue rate -system.cpu.iq.iqInstsAdded 9183 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 7981 # Number of instructions issued +system.cpu.iq.ISSUE:rate 0.865993 # Inst issue rate +system.cpu.iq.iqInstsAdded 9166 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 7968 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 22 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 3171 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsExamined 3154 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iq.iqSquashedInstsIssued 22 # Number of squashed instructions issued system.cpu.iq.iqSquashedNonSpecRemoved 5 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 2045 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedOperandsExamined 2035 # Number of squashed operands that are examined and possibly removed from graph system.cpu.l2cache.ReadReq_accesses 483 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 4639.751553 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2463.768116 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_miss_latency 2241000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_avg_miss_latency 4644.927536 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2467.908903 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_miss_latency 2243500 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 483 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1190000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 1192000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 483 # number of ReadReq MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -342,29 +343,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 # system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 483 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 4639.751553 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 2463.768116 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_miss_latency 4644.927536 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 2467.908903 # average overall mshr miss latency system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 2241000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 2243500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses system.cpu.l2cache.demand_misses 483 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 1190000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 1192000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 483 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.overall_accesses 483 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 4639.751553 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 2463.768116 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_miss_latency 4644.927536 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 2467.908903 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 0 # number of overall hits -system.cpu.l2cache.overall_miss_latency 2241000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 2243500 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses system.cpu.l2cache.overall_misses 483 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 1190000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 1192000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 483 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -381,27 +382,27 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.sampled_refs 483 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 278.222582 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 278.204751 # Cycle average of tags in use system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.numCycles 9197 # number of cpu cycles simulated +system.cpu.numCycles 9201 # number of cpu cycles simulated system.cpu.rename.RENAME:BlockCycles 15 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 4051 # Number of HB maps that are committed -system.cpu.rename.RENAME:IdleCycles 6383 # Number of cycles rename is idle +system.cpu.rename.RENAME:IdleCycles 6382 # Number of cycles rename is idle system.cpu.rename.RENAME:LSQFullEvents 70 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 12854 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 10031 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 7485 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 1746 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 682 # Number of cycles rename is squashing +system.cpu.rename.RENAME:RenameLookups 12837 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 10018 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 7477 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 1754 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 679 # Number of cycles rename is squashing system.cpu.rename.RENAME:UnblockCycles 101 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 3434 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:UndoneMaps 3426 # Number of HB maps that are undone due to squashing system.cpu.rename.RENAME:serializeStallCycles 270 # count of cycles rename stalled for serializing inst system.cpu.rename.RENAME:serializingInsts 26 # count of serializing insts renamed system.cpu.rename.RENAME:skidInsts 380 # count of insts added to the skid buffer system.cpu.rename.RENAME:tempSerializingInsts 20 # count of temporary serializing insts renamed -system.cpu.timesIdled 25 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.timesIdled 26 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 17 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout index d935401d2..142cb9695 100644 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout @@ -6,9 +6,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jun 10 2007 14:06:20 -M5 started Sun Jun 10 14:22:32 2007 -M5 executing on iceaxe -command line: /Users/nate/build/outgoing/build/ALPHA_SE/m5.debug -d /Users/nate/build/outgoing/build/ALPHA_SE/tests/debug/quick/00.hello/alpha/linux/o3-timing tests/run.py quick/00.hello/alpha/linux/o3-timing +M5 compiled Jun 21 2007 21:25:27 +M5 started Fri Jun 22 00:04:38 2007 +M5 executing on zizzer.eecs.umich.edu +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing tests/run.py quick/00.hello/alpha/linux/o3-timing Global frequency set at 1000000000000 ticks per second -Exiting @ tick 4588000 because target called exit() +Exiting @ tick 4589500 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini index e3080f9e5..36a50c983 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini @@ -21,6 +21,7 @@ SQEntries=32 SSITSize=1024 activity=0 backComSize=5 +cachePorts=200 choiceCtrBits=2 choicePredictorSize=8192 clock=500 @@ -74,6 +75,15 @@ renameToFetchDelay=1 renameToIEWDelay=2 renameToROBDelay=1 renameWidth=8 +smtCommitPolicy=RoundRobin +smtFetchPolicy=SingleThread +smtIQPolicy=Partitioned +smtIQThreshold=100 +smtLSQPolicy=Partitioned +smtLSQThreshold=100 +smtNumFetchingThreads=1 +smtROBPolicy=Partitioned +smtROBThreshold=100 squashWidth=8 system=system trapLatency=13 @@ -86,6 +96,7 @@ icache_port=system.cpu.icache.cpu_side [system.cpu.dcache] type=BaseCache adaptive_compression=false +addr_range=0:18446744073709551615 assoc=2 block_size=64 compressed_bus=false @@ -261,6 +272,7 @@ opLat=3 [system.cpu.icache] type=BaseCache adaptive_compression=false +addr_range=0:18446744073709551615 assoc=2 block_size=64 compressed_bus=false @@ -299,6 +311,7 @@ mem_side=system.cpu.toL2Bus.port[0] [system.cpu.l2cache] type=BaseCache adaptive_compression=false +addr_range=0:18446744073709551615 assoc=2 block_size=64 compressed_bus=false diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt index 6dd4c291d..d400dcd22 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt @@ -8,9 +8,10 @@ global.BPredUnit.condIncorrect 208 # Nu global.BPredUnit.condPredicted 376 # Number of conditional branches predicted global.BPredUnit.lookups 738 # Number of BP lookups global.BPredUnit.usedRAS 140 # Number of times the RAS was used to get a target. -host_inst_rate 8881 # Simulator instruction rate (inst/s) -host_seconds 0.27 # Real time elapsed on the host -host_tick_rate 7632084 # Simulator tick rate (ticks/s) +host_inst_rate 39805 # Simulator instruction rate (inst/s) +host_mem_usage 153128 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host +host_tick_rate 34110715 # Simulator tick rate (ticks/s) memdepunit.memDep.conflictingLoads 8 # Number of conflicting loads. memdepunit.memDep.conflictingStores 7 # Number of conflicting stores. memdepunit.memDep.insertedLoads 608 # Number of loads inserted to the mem dependence unit. @@ -18,22 +19,22 @@ memdepunit.memDep.insertedStores 357 # Nu sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 2387 # Number of instructions simulated sim_seconds 0.000002 # Number of seconds simulated -sim_ticks 2053000 # Number of ticks simulated +sim_ticks 2055000 # Number of ticks simulated system.cpu.commit.COM:branches 396 # Number of branches committed system.cpu.commit.COM:bw_lim_events 41 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 3906 +system.cpu.commit.COM:committed_per_cycle.samples 3910 system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 2949 7549.92% - 1 266 681.00% - 2 333 852.53% - 3 131 335.38% - 4 74 189.45% - 5 64 163.85% - 6 29 74.24% - 7 19 48.64% - 8 41 104.97% + 0 2950 7544.76% + 1 266 680.31% + 2 336 859.34% + 3 131 335.04% + 4 76 194.37% + 5 65 166.24% + 6 27 69.05% + 7 18 46.04% + 8 41 104.86% system.cpu.commit.COM:committed_per_cycle.max_value 8 system.cpu.commit.COM:committed_per_cycle.end_dist @@ -48,17 +49,17 @@ system.cpu.commit.commitNonSpecStalls 4 # Th system.cpu.commit.commitSquashedInsts 978 # The number of squashed insts skipped by commit system.cpu.committedInsts 2387 # Number of Instructions Simulated system.cpu.committedInsts_total 2387 # Number of Instructions Simulated -system.cpu.cpi 1.721408 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.721408 # CPI: Total CPI of All Threads +system.cpu.cpi 1.723083 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.723083 # CPI: Total CPI of All Threads system.cpu.dcache.ReadReq_accesses 514 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 5456.521739 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 4737.288136 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 5391.304348 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 4669.491525 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 445 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 376500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 372000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.134241 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 69 # number of ReadReq misses system.cpu.dcache.ReadReq_mshr_hits 10 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 279500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 275500 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.114786 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 59 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 294 # number of WriteReq accesses(hits+misses) @@ -81,29 +82,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 808 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 5564.285714 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 4821.428571 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency 5532.142857 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 4773.809524 # average overall mshr miss latency system.cpu.dcache.demand_hits 668 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 779000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 774500 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.173267 # miss rate for demand accesses system.cpu.dcache.demand_misses 140 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 56 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 405000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 401000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.103960 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 84 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 808 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 5564.285714 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 4821.428571 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 5532.142857 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 4773.809524 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 668 # number of overall hits -system.cpu.dcache.overall_miss_latency 779000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 774500 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.173267 # miss rate for overall accesses system.cpu.dcache.overall_misses 140 # number of overall misses system.cpu.dcache.overall_mshr_hits 56 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 405000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 401000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.103960 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 84 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -120,7 +121,7 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 84 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 51.851940 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 51.873008 # Cycle average of tags in use system.cpu.dcache.total_refs 668 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks @@ -129,43 +130,43 @@ system.cpu.decode.DECODE:BranchMispred 81 # Nu system.cpu.decode.DECODE:BranchResolved 123 # Number of times decode resolved a branch system.cpu.decode.DECODE:DecodedInsts 4033 # Number of instructions handled by decode system.cpu.decode.DECODE:IdleCycles 3045 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 767 # Number of cycles decode is running +system.cpu.decode.DECODE:RunCycles 771 # Number of cycles decode is running system.cpu.decode.DECODE:SquashCycles 202 # Number of cycles decode is squashing system.cpu.decode.DECODE:SquashedInsts 298 # Number of squashed instructions handled by decode system.cpu.fetch.Branches 738 # Number of branches that fetch encountered system.cpu.fetch.CacheLines 654 # Number of cache lines fetched -system.cpu.fetch.Cycles 1440 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.Cycles 1444 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.IcacheSquashes 120 # Number of outstanding Icache misses that were squashed system.cpu.fetch.Insts 4685 # Number of instructions fetch has processed system.cpu.fetch.SquashCycles 218 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.179606 # Number of branch fetches per cycle +system.cpu.fetch.branchRate 0.179431 # Number of branch fetches per cycle system.cpu.fetch.icacheStallCycles 654 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.predictedBranches 272 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 1.140180 # Number of inst fetches per cycle +system.cpu.fetch.rate 1.139071 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 4109 +system.cpu.fetch.rateDist.samples 4113 system.cpu.fetch.rateDist.min_value 0 - 0 3325 8091.99% - 1 32 77.88% - 2 74 180.09% - 3 53 128.99% - 4 99 240.93% - 5 49 119.25% - 6 38 92.48% - 7 35 85.18% - 8 404 983.21% + 0 3325 8084.12% + 1 32 77.80% + 2 80 194.51% + 3 50 121.57% + 4 99 240.70% + 5 52 126.43% + 6 39 94.82% + 7 35 85.10% + 8 401 974.96% system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.end_dist system.cpu.icache.ReadReq_accesses 654 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 5296.019900 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 4553.763441 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_miss_latency 5298.507463 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 4556.451613 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 453 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 1064500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency 1065000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.307339 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 201 # number of ReadReq misses system.cpu.icache.ReadReq_mshr_hits 15 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 847000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 847500 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.284404 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 186 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -177,29 +178,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 654 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 5296.019900 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 4553.763441 # average overall mshr miss latency +system.cpu.icache.demand_avg_miss_latency 5298.507463 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 4556.451613 # average overall mshr miss latency system.cpu.icache.demand_hits 453 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 1064500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 1065000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.307339 # miss rate for demand accesses system.cpu.icache.demand_misses 201 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 15 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 847000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 847500 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.284404 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 186 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.overall_accesses 654 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 5296.019900 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 4553.763441 # average overall mshr miss latency +system.cpu.icache.overall_avg_miss_latency 5298.507463 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 4556.451613 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.icache.overall_hits 453 # number of overall hits -system.cpu.icache.overall_miss_latency 1064500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 1065000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.307339 # miss rate for overall accesses system.cpu.icache.overall_misses 201 # number of overall misses system.cpu.icache.overall_mshr_hits 15 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 847000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 847500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.284404 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 186 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -216,14 +217,14 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 0 # number of replacements system.cpu.icache.sampled_refs 186 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 106.237740 # Cycle average of tags in use +system.cpu.icache.tagsinuse 106.293956 # Cycle average of tags in use system.cpu.icache.total_refs 453 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idleCycles 2992 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.iew.EXEC:branches 501 # Number of branches executed system.cpu.iew.EXEC:nop 234 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.727184 # Inst execution rate +system.cpu.iew.EXEC:rate 0.726477 # Inst execution rate system.cpu.iew.EXEC:refs 878 # number of memory reference insts executed system.cpu.iew.EXEC:stores 333 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed @@ -233,7 +234,7 @@ system.cpu.iew.WB:fanout 0.799637 # av system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.iew.WB:producers 1321 # num instructions producing a value -system.cpu.iew.WB:rate 0.709175 # insts written-back per cycle +system.cpu.iew.WB:rate 0.708485 # insts written-back per cycle system.cpu.iew.WB:sent 2931 # cumulative count of insts sent to commit system.cpu.iew.branchMispredicts 135 # Number of branch mispredicts detected at execute system.cpu.iew.iewBlockCycles 0 # Number of cycles IEW is blocking @@ -263,8 +264,8 @@ system.cpu.iew.lsq.thread.0.squashedStores 63 # system.cpu.iew.memOrderViolationEvents 10 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 98 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 37 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 0.580920 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.580920 # IPC: Total IPC of All Threads +system.cpu.ipc 0.580355 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.580355 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0 3075 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist No_OpClass 0 0.00% # Type of FU issued @@ -301,21 +302,21 @@ system.cpu.iq.ISSUE:fu_full.start_dist InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 4109 +system.cpu.iq.ISSUE:issued_per_cycle.samples 4113 system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 2849 6933.56% - 1 475 1156.00% - 2 270 657.09% - 3 217 528.11% - 4 159 386.96% - 5 86 209.30% - 6 34 82.75% - 7 13 31.64% - 8 6 14.60% + 0 2848 6924.39% + 1 479 1164.60% + 2 276 671.04% + 3 213 517.87% + 4 158 384.15% + 5 86 209.09% + 6 34 82.66% + 7 13 31.61% + 8 6 14.59% system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.end_dist -system.cpu.iq.ISSUE:rate 0.748357 # Inst issue rate +system.cpu.iq.ISSUE:rate 0.747629 # Inst issue rate system.cpu.iq.iqInstsAdded 3330 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqInstsIssued 3075 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 7 # Number of non-speculative instructions added to the IQ @@ -323,9 +324,9 @@ system.cpu.iq.iqSquashedInstsExamined 790 # Nu system.cpu.iq.iqSquashedNonSpecRemoved 3 # Number of squashed non-spec instructions that were removed system.cpu.iq.iqSquashedOperandsExamined 409 # Number of squashed operands that are examined and possibly removed from graph system.cpu.l2cache.ReadReq_accesses 270 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 4522.222222 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency 4509.259259 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2388.888889 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_miss_latency 1221000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency 1217500 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 270 # number of ReadReq misses system.cpu.l2cache.ReadReq_mshr_miss_latency 645000 # number of ReadReq MSHR miss cycles @@ -340,10 +341,10 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 # system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 270 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 4522.222222 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency 4509.259259 # average overall miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 2388.888889 # average overall mshr miss latency system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 1221000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 1217500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses system.cpu.l2cache.demand_misses 270 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits @@ -354,11 +355,11 @@ system.cpu.l2cache.fast_writes 0 # nu system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.overall_accesses 270 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 4522.222222 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 4509.259259 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 2388.888889 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 0 # number of overall hits -system.cpu.l2cache.overall_miss_latency 1221000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 1217500 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses system.cpu.l2cache.overall_misses 270 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits @@ -379,18 +380,18 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.sampled_refs 270 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 158.236294 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 158.313436 # Cycle average of tags in use system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.numCycles 4109 # number of cpu cycles simulated +system.cpu.numCycles 4113 # number of cpu cycles simulated system.cpu.rename.RENAME:CommittedMaps 1768 # Number of HB maps that are committed system.cpu.rename.RENAME:IdleCycles 3116 # Number of cycles rename is idle system.cpu.rename.RENAME:LSQFullEvents 1 # Number of times rename has blocked due to LSQ full system.cpu.rename.RENAME:RenameLookups 4416 # Number of register rename lookups that rename has made system.cpu.rename.RENAME:RenamedInsts 3886 # Number of instructions processed by rename system.cpu.rename.RENAME:RenamedOperands 2777 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 696 # Number of cycles rename is running +system.cpu.rename.RENAME:RunCycles 700 # Number of cycles rename is running system.cpu.rename.RENAME:SquashCycles 202 # Number of cycles rename is squashing system.cpu.rename.RENAME:UnblockCycles 6 # Number of cycles rename is unblocking system.cpu.rename.RENAME:UndoneMaps 1009 # Number of HB maps that are undone due to squashing diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout index 60520dc0c..c276fcaea 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout @@ -6,9 +6,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jun 10 2007 14:06:20 -M5 started Sun Jun 10 14:22:36 2007 -M5 executing on iceaxe -command line: /Users/nate/build/outgoing/build/ALPHA_SE/m5.debug -d /Users/nate/build/outgoing/build/ALPHA_SE/tests/debug/quick/00.hello/alpha/tru64/o3-timing tests/run.py quick/00.hello/alpha/tru64/o3-timing +M5 compiled Jun 21 2007 21:25:27 +M5 started Fri Jun 22 00:04:44 2007 +M5 executing on zizzer.eecs.umich.edu +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/o3-timing tests/run.py quick/00.hello/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second -Exiting @ tick 2053000 because target called exit() +Exiting @ tick 2055000 because target called exit() |