diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2011-07-10 12:56:09 -0500 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2011-07-10 12:56:09 -0500 |
| commit | 3ebfe2eb0124b0524952c59f04580a55eb36edff (patch) | |
| tree | 3d48c5d7bddaa51413b4504b7bc17635e67e14a7 /tests/quick/00.hello/ref/alpha | |
| parent | 3396fd9e84358346b60437a7635c9cc5f331017f (diff) | |
| download | gem5-3ebfe2eb0124b0524952c59f04580a55eb36edff.tar.xz | |
O3: Update stats for fetch and bp changes.
Diffstat (limited to 'tests/quick/00.hello/ref/alpha')
10 files changed, 927 insertions, 927 deletions
diff --git a/tests/quick/00.hello/ref/alpha/linux/inorder-timing/config.ini b/tests/quick/00.hello/ref/alpha/linux/inorder-timing/config.ini index 258f4e533..56fbbd75c 100644 --- a/tests/quick/00.hello/ref/alpha/linux/inorder-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/linux/inorder-timing/config.ini @@ -9,6 +9,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem mem_mode=atomic +memories=system.physmem physmem=system.physmem work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 @@ -204,7 +205,7 @@ egid=100 env= errout=cerr euid=100 -executable=tests/test-progs/hello/bin/alpha/linux/hello +executable=/chips/pd/randd/dist/test-progs/hello/bin/alpha/linux/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/00.hello/ref/alpha/linux/inorder-timing/simout b/tests/quick/00.hello/ref/alpha/linux/inorder-timing/simout index cdb09d17e..d51796d4d 100755 --- a/tests/quick/00.hello/ref/alpha/linux/inorder-timing/simout +++ b/tests/quick/00.hello/ref/alpha/linux/inorder-timing/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 19 2011 23:40:02 -gem5 started Jun 20 2011 08:26:33 -gem5 executing on zooks +gem5 compiled Jul 8 2011 15:00:53 +gem5 started Jul 8 2011 15:20:58 +gem5 executing on u200439-lin.austin.arm.com command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/inorder-timing -re tests/run.py build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello world! -Exiting @ tick 21228000 because target called exit() +Exiting @ tick 21216000 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/linux/inorder-timing/stats.txt b/tests/quick/00.hello/ref/alpha/linux/inorder-timing/stats.txt index 3184d80aa..118e4e630 100644 --- a/tests/quick/00.hello/ref/alpha/linux/inorder-timing/stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/inorder-timing/stats.txt @@ -1,12 +1,12 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000021 # Number of seconds simulated -sim_ticks 21228000 # Number of ticks simulated +sim_ticks 21216000 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 45998 # Simulator instruction rate (inst/s) -host_tick_rate 152436103 # Simulator tick rate (ticks/s) -host_mem_usage 157012 # Number of bytes of host memory used -host_seconds 0.14 # Real time elapsed on the host +host_inst_rate 29106 # Simulator instruction rate (inst/s) +host_tick_rate 96412699 # Simulator tick rate (ticks/s) +host_mem_usage 242900 # Number of bytes of host memory used +host_seconds 0.22 # Real time elapsed on the host sim_insts 6404 # Number of instructions simulated system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses @@ -24,10 +24,10 @@ system.cpu.dtb.data_hits 2084 # DT system.cpu.dtb.data_misses 10 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations system.cpu.dtb.data_accesses 2094 # DTB accesses -system.cpu.itb.fetch_hits 932 # ITB hits +system.cpu.itb.fetch_hits 929 # ITB hits system.cpu.itb.fetch_misses 17 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 949 # ITB accesses +system.cpu.itb.fetch_accesses 946 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -41,16 +41,16 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 42457 # number of cpu cycles simulated +system.cpu.numCycles 42433 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 11420 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 11397 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode system.cpu.timesIdled 442 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 35048 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 7409 # Number of cycles cpu stages are processed. -system.cpu.activity 17.450597 # Percentage of cycles cpu is active +system.cpu.idleCycles 35050 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 7383 # Number of cycles cpu stages are processed. +system.cpu.activity 17.399194 # Percentage of cycles cpu is active system.cpu.comLoads 1185 # Number of Load instructions committed system.cpu.comStores 865 # Number of Store instructions committed system.cpu.comBranches 1051 # Number of Branches instructions committed @@ -61,79 +61,79 @@ system.cpu.comFloats 2 # Nu system.cpu.committedInsts 6404 # Number of Instructions Simulated (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread) system.cpu.committedInsts_total 6404 # Number of Instructions Simulated (Total) -system.cpu.cpi 6.629763 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 6.626015 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi no_value # CPI: Total SMT-CPI -system.cpu.cpi_total 6.629763 # CPI: Total CPI of All Threads -system.cpu.ipc 0.150835 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 6.626015 # CPI: Total CPI of All Threads +system.cpu.ipc 0.150920 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc no_value # IPC: Total SMT-IPC -system.cpu.ipc_total 0.150835 # IPC: Total IPC of All Threads -system.cpu.branch_predictor.lookups 1674 # Number of BP lookups -system.cpu.branch_predictor.condPredicted 1207 # Number of conditional branches predicted -system.cpu.branch_predictor.condIncorrect 720 # Number of conditional branches incorrect -system.cpu.branch_predictor.BTBLookups 1422 # Number of BTB lookups -system.cpu.branch_predictor.BTBHits 419 # Number of BTB hits +system.cpu.ipc_total 0.150920 # IPC: Total IPC of All Threads +system.cpu.branch_predictor.lookups 1670 # Number of BP lookups +system.cpu.branch_predictor.condPredicted 1199 # Number of conditional branches predicted +system.cpu.branch_predictor.condIncorrect 712 # Number of conditional branches incorrect +system.cpu.branch_predictor.BTBLookups 1410 # Number of BTB lookups +system.cpu.branch_predictor.BTBHits 414 # Number of BTB hits system.cpu.branch_predictor.usedRAS 126 # Number of times the RAS was used to get a target. system.cpu.branch_predictor.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.branch_predictor.BTBHitPct 29.465541 # BTB Hit Percentage -system.cpu.branch_predictor.predictedTaken 570 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 1104 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 5167 # Number of Reads from Int. Register File +system.cpu.branch_predictor.BTBHitPct 29.361702 # BTB Hit Percentage +system.cpu.branch_predictor.predictedTaken 565 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 1105 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 5165 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 4580 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 9747 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.intRegFileAccesses 9745 # Total Accesses (Read+Write) to the Int. Register File system.cpu.regfile_manager.floatRegFileReads 8 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 2 # Number of Writes to FP Register File system.cpu.regfile_manager.floatRegFileAccesses 10 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 3004 # Number of Registers Read Through Forwarding Logic -system.cpu.agen_unit.agens 2137 # Number of Address Generations -system.cpu.execution_unit.predictedTakenIncorrect 369 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.execution_unit.predictedNotTakenIncorrect 290 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.execution_unit.mispredicted 659 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.predicted 393 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.mispredictPct 62.642586 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.executions 4444 # Number of Instructions Executed. +system.cpu.regfile_manager.regForwards 3002 # Number of Registers Read Through Forwarding Logic +system.cpu.agen_unit.agens 2138 # Number of Address Generations +system.cpu.execution_unit.predictedTakenIncorrect 357 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.execution_unit.predictedNotTakenIncorrect 294 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.execution_unit.mispredicted 651 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.predicted 401 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.mispredictPct 61.882129 # Percentage of Incorrect Branches Predicts +system.cpu.execution_unit.executions 4447 # Number of Instructions Executed. system.cpu.mult_div_unit.multiplies 1 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed -system.cpu.stage0.idleCycles 37460 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 4997 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 11.769555 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 38535 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 3922 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 9.237582 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 38269 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 4188 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 9.864098 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 41117 # Number of cycles 0 instructions are processed. +system.cpu.stage0.idleCycles 37465 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 4968 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 11.707869 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 38516 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 3917 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 9.231023 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 38252 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 4181 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 9.853180 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 41093 # Number of cycles 0 instructions are processed. system.cpu.stage3.runCycles 1340 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 3.156134 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 37979 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 4478 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 10.547142 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.utilization 3.157920 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 37964 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 4469 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 10.531897 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 138.808044 # Cycle average of tags in use -system.cpu.icache.total_refs 584 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 138.882502 # Cycle average of tags in use +system.cpu.icache.total_refs 581 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 301 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 1.940199 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 1.930233 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 138.808044 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.067777 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 584 # number of ReadReq hits -system.cpu.icache.demand_hits 584 # number of demand (read+write) hits -system.cpu.icache.overall_hits 584 # number of overall hits +system.cpu.icache.occ_blocks::0 138.882502 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.067814 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 581 # number of ReadReq hits +system.cpu.icache.demand_hits 581 # number of demand (read+write) hits +system.cpu.icache.overall_hits 581 # number of overall hits system.cpu.icache.ReadReq_misses 348 # number of ReadReq misses system.cpu.icache.demand_misses 348 # number of demand (read+write) misses system.cpu.icache.overall_misses 348 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 19242000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 19242000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 19242000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 932 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 932 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 932 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.373391 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.373391 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.373391 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 55293.103448 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 55293.103448 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 55293.103448 # average overall miss latency +system.cpu.icache.ReadReq_miss_latency 19241000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 19241000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 19241000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 929 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 929 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 929 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.374596 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.374596 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.374596 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 55290.229885 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 55290.229885 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 55290.229885 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -150,28 +150,28 @@ system.cpu.icache.ReadReq_mshr_misses 302 # nu system.cpu.icache.demand_mshr_misses 302 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses 302 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 16050000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 16050000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 16050000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 16049000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 16049000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 16049000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.324034 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.324034 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.324034 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 53145.695364 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 53145.695364 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 53145.695364 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate 0.325081 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate 0.325081 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate 0.325081 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 53142.384106 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 53142.384106 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 53142.384106 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 102.626911 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 102.671807 # Cycle average of tags in use system.cpu.dcache.total_refs 1703 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 168 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 10.136905 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 102.626911 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.025055 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 102.671807 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.025066 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits 1088 # number of ReadReq hits system.cpu.dcache.WriteReq_hits 615 # number of WriteReq hits system.cpu.dcache.demand_hits 1703 # number of demand (read+write) hits @@ -181,9 +181,9 @@ system.cpu.dcache.WriteReq_misses 250 # nu system.cpu.dcache.demand_misses 347 # number of demand (read+write) misses system.cpu.dcache.overall_misses 347 # number of overall misses system.cpu.dcache.ReadReq_miss_latency 5508500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 13555000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 19063500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 19063500 # number of overall miss cycles +system.cpu.dcache.WriteReq_miss_latency 13555500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency 19064000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 19064000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses 1185 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 865 # number of WriteReq accesses(hits+misses) system.cpu.dcache.demand_accesses 2050 # number of demand (read+write) accesses @@ -193,9 +193,9 @@ system.cpu.dcache.WriteReq_miss_rate 0.289017 # mi system.cpu.dcache.demand_miss_rate 0.169268 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate 0.169268 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency 56788.659794 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 54220 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 54938.040346 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 54938.040346 # average overall miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 54222 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency 54939.481268 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 54939.481268 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 1656000 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -215,30 +215,30 @@ system.cpu.dcache.demand_mshr_misses 168 # nu system.cpu.dcache.overall_mshr_misses 168 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.ReadReq_mshr_miss_latency 5114000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 3909500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 9023500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 9023500 # number of overall MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 3910000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 9024000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 9024000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.080169 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate 0.084393 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate 0.081951 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate 0.081951 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53831.578947 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53554.794521 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 53711.309524 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 53711.309524 # average overall mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53561.643836 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 53714.285714 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 53714.285714 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 195.111607 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 195.209568 # Cycle average of tags in use system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 395 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.002532 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 195.111607 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.005954 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 195.209568 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.005957 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits 1 # number of ReadReq hits system.cpu.l2cache.demand_hits 1 # number of demand (read+write) hits system.cpu.l2cache.overall_hits 1 # number of overall hits @@ -246,8 +246,8 @@ system.cpu.l2cache.ReadReq_misses 396 # nu system.cpu.l2cache.ReadExReq_misses 73 # number of ReadExReq misses system.cpu.l2cache.demand_misses 469 # number of demand (read+write) misses system.cpu.l2cache.overall_misses 469 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 20702500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 3821500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency 20702000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 3822000 # number of ReadExReq miss cycles system.cpu.l2cache.demand_miss_latency 24524000 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency 24524000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses 397 # number of ReadReq accesses(hits+misses) @@ -258,8 +258,8 @@ system.cpu.l2cache.ReadReq_miss_rate 0.997481 # mi system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate 0.997872 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate 0.997872 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 52279.040404 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 52349.315068 # average ReadExReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency 52277.777778 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 52356.164384 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency 52289.978678 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency 52289.978678 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked @@ -278,19 +278,19 @@ system.cpu.l2cache.ReadExReq_mshr_misses 73 # nu system.cpu.l2cache.demand_mshr_misses 469 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses 469 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 15876500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 15877000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency 2942500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 18819000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 18819000 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 18819500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 18819500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.997481 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate 0.997872 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate 0.997872 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40092.171717 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40093.434343 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40308.219178 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 40125.799574 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 40125.799574 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 40126.865672 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 40126.865672 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini b/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini index 08baf7c22..03a16a5ea 100644 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini @@ -9,6 +9,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem mem_mode=atomic +memories=system.physmem physmem=system.physmem work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 @@ -498,7 +499,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello +executable=/chips/pd/randd/dist/test-progs/hello/bin/alpha/linux/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout b/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout index 6caee1c6f..f022a446d 100755 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 19 2011 06:59:13 -gem5 started Jun 19 2011 07:04:58 -gem5 executing on m60-009.pool -command line: build/ALPHA_SE/gem5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing +gem5 compiled Jul 8 2011 15:00:53 +gem5 started Jul 8 2011 15:20:58 +gem5 executing on u200439-lin.austin.arm.com +command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello world! -Exiting @ tick 12357500 because target called exit() +Exiting @ tick 12002500 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt index 42ab89f68..50d6ec22a 100644 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt @@ -1,33 +1,33 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000012 # Number of seconds simulated -sim_ticks 12357500 # Number of ticks simulated +sim_ticks 12002500 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 108363 # Simulator instruction rate (inst/s) -host_tick_rate 209619317 # Simulator tick rate (ticks/s) -host_mem_usage 192840 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host +host_inst_rate 25819 # Simulator instruction rate (inst/s) +host_tick_rate 48521023 # Simulator tick rate (ticks/s) +host_mem_usage 243716 # Number of bytes of host memory used +host_seconds 0.25 # Real time elapsed on the host sim_insts 6386 # Number of instructions simulated system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 1750 # DTB read hits -system.cpu.dtb.read_misses 36 # DTB read misses +system.cpu.dtb.read_hits 1863 # DTB read hits +system.cpu.dtb.read_misses 45 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 1786 # DTB read accesses -system.cpu.dtb.write_hits 1011 # DTB write hits -system.cpu.dtb.write_misses 25 # DTB write misses +system.cpu.dtb.read_accesses 1908 # DTB read accesses +system.cpu.dtb.write_hits 1047 # DTB write hits +system.cpu.dtb.write_misses 28 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 1036 # DTB write accesses -system.cpu.dtb.data_hits 2761 # DTB hits -system.cpu.dtb.data_misses 61 # DTB misses +system.cpu.dtb.write_accesses 1075 # DTB write accesses +system.cpu.dtb.data_hits 2910 # DTB hits +system.cpu.dtb.data_misses 73 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 2822 # DTB accesses -system.cpu.itb.fetch_hits 1711 # ITB hits -system.cpu.itb.fetch_misses 33 # ITB misses +system.cpu.dtb.data_accesses 2983 # DTB accesses +system.cpu.itb.fetch_hits 2044 # ITB hits +system.cpu.itb.fetch_misses 29 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 1744 # ITB accesses +system.cpu.itb.fetch_accesses 2073 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -41,243 +41,245 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 24716 # number of cpu cycles simulated +system.cpu.numCycles 24006 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 2180 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 1297 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 443 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 1765 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 670 # Number of BTB hits +system.cpu.BPredUnit.lookups 2516 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 1462 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 458 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 1947 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 723 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 306 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 65 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 1711 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 12863 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2180 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 976 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 2325 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 482 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 33 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.CacheLines 1711 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 248 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 12915 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.995974 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.389736 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 372 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 67 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 7155 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 14481 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2516 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 1095 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 2626 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1554 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 1112 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 24 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 631 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 2044 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 318 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 12602 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.149103 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.531397 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 10590 82.00% 82.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 233 1.80% 83.80% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 211 1.63% 85.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 179 1.39% 86.82% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 229 1.77% 88.59% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 156 1.21% 89.80% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 218 1.69% 91.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 125 0.97% 92.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 974 7.54% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 9976 79.16% 79.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 274 2.17% 81.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 231 1.83% 83.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 220 1.75% 84.92% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 235 1.86% 86.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 176 1.40% 88.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 257 2.04% 90.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 141 1.12% 91.33% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1092 8.67% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 12915 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.088202 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.520432 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 8780 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 1035 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2228 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 47 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 825 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 181 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 75 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 12021 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 209 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 825 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 8928 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 337 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 406 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2118 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 301 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 11616 # Number of instructions processed by rename -system.cpu.rename.IQFullEvents 8 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 260 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 8669 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 14615 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 14598 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 12602 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.104807 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.603224 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 7976 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 1126 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2455 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 69 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 976 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 216 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 85 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 13403 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 215 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 976 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 8164 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 432 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 358 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2326 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 346 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 12866 # Number of instructions processed by rename +system.cpu.rename.IQFullEvents 11 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 291 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 9599 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 16086 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 16069 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 17 # Number of floating rename lookups system.cpu.rename.CommittedMaps 4583 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 4086 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 5016 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 28 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 22 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 754 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2144 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1195 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 0 # Number of conflicting loads. +system.cpu.rename.skidInsts 881 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2397 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1265 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 4 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 10562 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 25 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 9108 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 25 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 3797 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 2286 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 8 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 12915 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.705226 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.305176 # Number of insts issued each cycle +system.cpu.iq.iqInstsAdded 11578 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 27 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 9768 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 45 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 4900 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 2850 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 10 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 12602 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.775115 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.397410 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 8840 68.45% 68.45% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1652 12.79% 81.24% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 1039 8.04% 89.28% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 684 5.30% 94.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 367 2.84% 97.42% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 198 1.53% 98.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 88 0.68% 99.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 36 0.28% 99.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 11 0.09% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 8516 67.58% 67.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1470 11.66% 79.24% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 1066 8.46% 87.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 684 5.43% 93.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 441 3.50% 96.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 254 2.02% 98.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 129 1.02% 99.67% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 30 0.24% 99.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 12 0.10% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 12915 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 12602 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 1 1.14% 1.14% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 52 59.09% 60.23% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 35 39.77% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 13 12.38% 12.38% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 12.38% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 12.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 12.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 12.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 12.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 12.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 12.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 12.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 12.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 12.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 12.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 12.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 12.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 12.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 12.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 12.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 12.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 12.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 12.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 12.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 12.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 12.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 12.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 12.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 12.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 12.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 12.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 12.38% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 54 51.43% 63.81% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 38 36.19% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 6174 67.79% 67.81% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 1 0.01% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.84% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 1875 20.59% 88.43% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1054 11.57% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 6583 67.39% 67.41% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 1 0.01% 67.42% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.42% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.44% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.44% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.44% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.44% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.44% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.44% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2078 21.27% 88.72% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1102 11.28% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 9108 # Type of FU issued -system.cpu.iq.rate 0.368506 # Inst issue rate -system.cpu.iq.fu_busy_cnt 88 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.009662 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 31223 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 14386 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 8549 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 9768 # Type of FU issued +system.cpu.iq.rate 0.406898 # Inst issue rate +system.cpu.iq.fu_busy_cnt 105 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.010749 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 32267 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 16511 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 8987 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 21 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 10 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 10 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 9183 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 9860 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 11 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 44 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 61 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 959 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 6 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 16 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 330 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1212 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 21 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 400 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 825 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 67 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 9 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 10669 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 193 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2144 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1195 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 25 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 7 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 976 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 150 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 8 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 11685 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 148 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2397 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1265 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 27 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 5 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 16 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 125 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 304 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 429 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 8837 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 1794 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 271 # Number of squashed instructions skipped in execute +system.cpu.iew.memOrderViolationEvents 21 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 118 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 327 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 445 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 9324 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 1918 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 444 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 82 # number of nop insts executed -system.cpu.iew.exec_refs 2832 # number of memory reference insts executed -system.cpu.iew.exec_branches 1424 # Number of branches executed -system.cpu.iew.exec_stores 1038 # Number of stores executed -system.cpu.iew.exec_rate 0.357542 # Inst execution rate -system.cpu.iew.wb_sent 8658 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 8559 # cumulative count of insts written-back -system.cpu.iew.wb_producers 4429 # num instructions producing a value -system.cpu.iew.wb_consumers 5952 # num instructions consuming a value +system.cpu.iew.exec_nop 80 # number of nop insts executed +system.cpu.iew.exec_refs 2995 # number of memory reference insts executed +system.cpu.iew.exec_branches 1503 # Number of branches executed +system.cpu.iew.exec_stores 1077 # Number of stores executed +system.cpu.iew.exec_rate 0.388403 # Inst execution rate +system.cpu.iew.wb_sent 9127 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 8997 # cumulative count of insts written-back +system.cpu.iew.wb_producers 4717 # num instructions producing a value +system.cpu.iew.wb_consumers 6401 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.346294 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.744120 # average fanout of values written-back +system.cpu.iew.wb_rate 0.374781 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.736916 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 6403 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 4249 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 5279 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 369 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 12090 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.529611 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.331978 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 380 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 11626 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.550748 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.411308 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 9222 76.28% 76.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1613 13.34% 89.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 453 3.75% 93.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 264 2.18% 95.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 157 1.30% 96.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 121 1.00% 97.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 88 0.73% 98.58% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 45 0.37% 98.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 127 1.05% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 8945 76.94% 76.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1414 12.16% 89.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 463 3.98% 93.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 244 2.10% 95.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 156 1.34% 96.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 87 0.75% 97.27% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 110 0.95% 98.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 44 0.38% 98.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 163 1.40% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 12090 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 11626 # Number of insts commited each cycle system.cpu.commit.count 6403 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 2050 # Number of memory references committed @@ -287,50 +289,50 @@ system.cpu.commit.branches 1051 # Nu system.cpu.commit.fp_insts 10 # Number of committed floating point instructions. system.cpu.commit.int_insts 6321 # Number of committed integer instructions. system.cpu.commit.function_calls 127 # Number of function calls committed. -system.cpu.commit.bw_lim_events 127 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 163 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 22264 # The number of ROB reads -system.cpu.rob.rob_writes 22135 # The number of ROB writes -system.cpu.timesIdled 240 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 11801 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 22794 # The number of ROB reads +system.cpu.rob.rob_writes 24351 # The number of ROB writes +system.cpu.timesIdled 230 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 11404 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 6386 # Number of Instructions Simulated system.cpu.committedInsts_total 6386 # Number of Instructions Simulated -system.cpu.cpi 3.870341 # CPI: Cycles Per Instruction -system.cpu.cpi_total 3.870341 # CPI: Total CPI of All Threads -system.cpu.ipc 0.258375 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.258375 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 11291 # number of integer regfile reads -system.cpu.int_regfile_writes 6385 # number of integer regfile writes +system.cpu.cpi 3.759161 # CPI: Cycles Per Instruction +system.cpu.cpi_total 3.759161 # CPI: Total CPI of All Threads +system.cpu.ipc 0.266017 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.266017 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 11850 # number of integer regfile reads +system.cpu.int_regfile_writes 6735 # number of integer regfile writes system.cpu.fp_regfile_reads 8 # number of floating regfile reads system.cpu.fp_regfile_writes 2 # number of floating regfile writes system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 157.666490 # Cycle average of tags in use -system.cpu.icache.total_refs 1301 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 307 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 4.237785 # Average number of references to valid blocks. +system.cpu.icache.tagsinuse 159.654959 # Cycle average of tags in use +system.cpu.icache.total_refs 1612 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 311 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 5.183280 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 157.666490 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.076986 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 1301 # number of ReadReq hits -system.cpu.icache.demand_hits 1301 # number of demand (read+write) hits -system.cpu.icache.overall_hits 1301 # number of overall hits -system.cpu.icache.ReadReq_misses 410 # number of ReadReq misses -system.cpu.icache.demand_misses 410 # number of demand (read+write) misses -system.cpu.icache.overall_misses 410 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 14727000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 14727000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 14727000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 1711 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 1711 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 1711 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.239626 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.239626 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.239626 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 35919.512195 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 35919.512195 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 35919.512195 # average overall miss latency +system.cpu.icache.occ_blocks::0 159.654959 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.077957 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 1612 # number of ReadReq hits +system.cpu.icache.demand_hits 1612 # number of demand (read+write) hits +system.cpu.icache.overall_hits 1612 # number of overall hits +system.cpu.icache.ReadReq_misses 432 # number of ReadReq misses +system.cpu.icache.demand_misses 432 # number of demand (read+write) misses +system.cpu.icache.overall_misses 432 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 15402000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 15402000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 15402000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 2044 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 2044 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 2044 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.211350 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.211350 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.211350 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 35652.777778 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 35652.777778 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 35652.777778 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -340,59 +342,59 @@ system.cpu.icache.avg_blocked_cycles::no_targets no_value system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 103 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 103 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 103 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 307 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 307 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 307 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_hits 121 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 121 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 121 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 311 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 311 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 311 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 10832000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 10832000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 10832000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 10985500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 10985500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 10985500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.179427 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.179427 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.179427 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 35283.387622 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 35283.387622 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 35283.387622 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate 0.152153 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate 0.152153 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate 0.152153 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 35323.151125 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 35323.151125 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 35323.151125 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 109.940770 # Cycle average of tags in use -system.cpu.dcache.total_refs 2064 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 109.289403 # Cycle average of tags in use +system.cpu.dcache.total_refs 2155 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 174 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 11.862069 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 12.385057 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 109.940770 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.026841 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 1555 # number of ReadReq hits +system.cpu.dcache.occ_blocks::0 109.289403 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.026682 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 1646 # number of ReadReq hits system.cpu.dcache.WriteReq_hits 509 # number of WriteReq hits -system.cpu.dcache.demand_hits 2064 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 2064 # number of overall hits -system.cpu.dcache.ReadReq_misses 150 # number of ReadReq misses +system.cpu.dcache.demand_hits 2155 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 2155 # number of overall hits +system.cpu.dcache.ReadReq_misses 155 # number of ReadReq misses system.cpu.dcache.WriteReq_misses 356 # number of WriteReq misses -system.cpu.dcache.demand_misses 506 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 506 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 5422000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 12468000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 17890000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 17890000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 1705 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses 511 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 511 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 5502500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 12467500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency 17970000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 17970000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 1801 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 865 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 2570 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 2570 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.087977 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses 2666 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 2666 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.086063 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate 0.411561 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.196887 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.196887 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 36146.666667 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 35022.471910 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 35355.731225 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 35355.731225 # average overall miss latency +system.cpu.dcache.demand_miss_rate 0.191673 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.191673 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 35500 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 35021.067416 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency 35166.340509 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 35166.340509 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -402,63 +404,63 @@ system.cpu.dcache.avg_blocked_cycles::no_targets no_value system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 49 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits 54 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits 283 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 332 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 332 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits 337 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 337 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses 101 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses 73 # number of WriteReq MSHR misses system.cpu.dcache.demand_mshr_misses 174 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses 174 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 3659000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 2619500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 6278500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 6278500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 3654000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 2611500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 6265500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 6265500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.059238 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate 0.056080 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate 0.084393 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.067704 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.067704 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 36227.722772 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35883.561644 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 36083.333333 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 36083.333333 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate 0.065266 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate 0.065266 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 36178.217822 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35773.972603 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 36008.620690 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 36008.620690 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 219.485914 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 221.186144 # Cycle average of tags in use system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 407 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.002457 # Average number of references to valid blocks. +system.cpu.l2cache.sampled_refs 411 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.002433 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 219.485914 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.006698 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 221.186144 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.006750 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits 1 # number of ReadReq hits system.cpu.l2cache.demand_hits 1 # number of demand (read+write) hits system.cpu.l2cache.overall_hits 1 # number of overall hits -system.cpu.l2cache.ReadReq_misses 407 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses 411 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses 73 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 480 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 480 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 14004500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 2518000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 16522500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 16522500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 408 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.demand_misses 484 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 484 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 14128000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 2513500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 16641500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 16641500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 412 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses 73 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 481 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 481 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.997549 # miss rate for ReadReq accesses +system.cpu.l2cache.demand_accesses 485 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 485 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.997573 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.997921 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.997921 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34409.090909 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34493.150685 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34421.875000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34421.875000 # average overall miss latency +system.cpu.l2cache.demand_miss_rate 0.997938 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.997938 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 34374.695864 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34431.506849 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34383.264463 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34383.264463 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -470,24 +472,24 @@ system.cpu.l2cache.cache_copies 0 # nu system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 407 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses 411 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses 73 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 480 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 480 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses 484 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 484 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 12710000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 2291000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 15001000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 15001000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 12819000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 2286000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 15105000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 15105000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.997549 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.997573 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.997921 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.997921 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31228.501229 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31383.561644 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31252.083333 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31252.083333 # average overall mshr miss latency +system.cpu.l2cache.demand_mshr_miss_rate 0.997938 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.997938 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31189.781022 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31315.068493 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31208.677686 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31208.677686 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini index 838834423..1c3640f5b 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini @@ -9,6 +9,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem mem_mode=atomic +memories=system.physmem physmem=system.physmem work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 @@ -498,7 +499,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello +executable=/chips/pd/randd/dist/test-progs/hello/bin/alpha/tru64/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simerr b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simerr index 0659d557a..27f858d8f 100755 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simerr +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simerr @@ -1,7 +1,4 @@ warn: Sockets disabled, not accepting gdb connections -For more information see: http://www.m5sim.org/warn/d946bea6 -warn: Prefetch instrutions is Alpha do not do anything -For more information see: http://www.m5sim.org/warn/3e0eccba +warn: Prefetch instructions in Alpha do not do anything warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...) -For more information see: http://www.m5sim.org/warn/5c5b547f hack: be nice to actually delete the event here diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout index 8a87312b4..74424d63b 100755 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout @@ -1,16 +1,12 @@ -M5 Simulator System +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Apr 21 2011 12:29:56 -M5 started Apr 21 2011 13:15:23 -M5 executing on maize -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/o3-timing +gem5 compiled Jul 8 2011 15:00:53 +gem5 started Jul 8 2011 15:21:09 +gem5 executing on u200439-lin.austin.arm.com +command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello world! -Exiting @ tick 7289000 because target called exit() +Exiting @ tick 6921000 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt index b8b5c99cd..5e52ef944 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt @@ -1,494 +1,496 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 66320 # Simulator instruction rate (inst/s) -host_mem_usage 205872 # Number of bytes of host memory used -host_seconds 0.04 # Real time elapsed on the host -host_tick_rate 201598879 # Simulator tick rate (ticks/s) +sim_seconds 0.000007 # Number of seconds simulated +sim_ticks 6921000 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 33894 # Simulator instruction rate (inst/s) +host_tick_rate 98227338 # Simulator tick rate (ticks/s) +host_mem_usage 242788 # Number of bytes of host memory used +host_seconds 0.07 # Real time elapsed on the host sim_insts 2387 # Number of instructions simulated -sim_seconds 0.000007 # Number of seconds simulated -sim_ticks 7289000 # Number of ticks simulated +system.cpu.dtb.fetch_hits 0 # ITB hits +system.cpu.dtb.fetch_misses 0 # ITB misses +system.cpu.dtb.fetch_acv 0 # ITB acv +system.cpu.dtb.fetch_accesses 0 # ITB accesses +system.cpu.dtb.read_hits 720 # DTB read hits +system.cpu.dtb.read_misses 34 # DTB read misses +system.cpu.dtb.read_acv 1 # DTB read access violations +system.cpu.dtb.read_accesses 754 # DTB read accesses +system.cpu.dtb.write_hits 354 # DTB write hits +system.cpu.dtb.write_misses 22 # DTB write misses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_accesses 376 # DTB write accesses +system.cpu.dtb.data_hits 1074 # DTB hits +system.cpu.dtb.data_misses 56 # DTB misses +system.cpu.dtb.data_acv 1 # DTB access violations +system.cpu.dtb.data_accesses 1130 # DTB accesses +system.cpu.itb.fetch_hits 976 # ITB hits +system.cpu.itb.fetch_misses 30 # ITB misses +system.cpu.itb.fetch_acv 0 # ITB acv +system.cpu.itb.fetch_accesses 1006 # ITB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_acv 0 # DTB read access violations +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_acv 0 # DTB write access violations +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.data_hits 0 # DTB hits +system.cpu.itb.data_misses 0 # DTB misses +system.cpu.itb.data_acv 0 # DTB access violations +system.cpu.itb.data_accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 4 # Number of system calls +system.cpu.numCycles 13843 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.BPredUnit.lookups 1112 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 583 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 236 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 781 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 240 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 197 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 687 # Number of BTB lookups -system.cpu.BPredUnit.RASInCorrect 35 # Number of incorrect RAS predictions. -system.cpu.BPredUnit.condIncorrect 223 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 485 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 931 # Number of BP lookups -system.cpu.BPredUnit.usedRAS 174 # Number of times the RAS was used to get a target. -system.cpu.commit.branchMispredicts 146 # The number of times a branch was mispredicted -system.cpu.commit.branches 396 # Number of branches committed -system.cpu.commit.bw_lim_events 41 # number cycles where commit BW limit reached -system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits +system.cpu.BPredUnit.usedRAS 215 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 34 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 3787 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 6697 # Number of instructions fetch has processed +system.cpu.fetch.Branches 1112 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 455 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 1166 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 814 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 253 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 17 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 781 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 976 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 159 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 6557 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.021351 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.437035 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 5391 82.22% 82.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 67 1.02% 83.24% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 123 1.88% 85.12% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 97 1.48% 86.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 146 2.23% 88.82% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 50 0.76% 89.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 61 0.93% 90.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 83 1.27% 91.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 539 8.22% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 6557 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.080329 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.483782 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 4673 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 269 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 1132 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 7 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 476 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 152 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 80 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 6020 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 284 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 476 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 4772 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 89 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 147 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 1039 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 34 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 5743 # Number of instructions processed by rename +system.cpu.rename.IQFullEvents 15 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 11 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 4153 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 6495 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 6483 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 12 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 1768 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 2385 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 8 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 6 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 117 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 961 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 458 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 5 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 3 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 4907 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 6 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 3996 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 90 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 2355 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1385 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 6557 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.609425 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.316967 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 4952 75.52% 75.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 578 8.82% 84.34% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 360 5.49% 89.83% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 270 4.12% 93.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 209 3.19% 97.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 109 1.66% 98.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 54 0.82% 99.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 17 0.26% 99.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 8 0.12% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 6557 # Number of insts issued each cycle +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 1 2.27% 2.27% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 2.27% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 2.27% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.27% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.27% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.27% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 2.27% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.27% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 2.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 2.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.27% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 20 45.45% 47.73% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 23 52.27% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 2819 70.55% 70.55% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 1 0.03% 70.57% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.57% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.57% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.57% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.57% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.57% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.57% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 70.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 70.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 70.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 70.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.57% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 794 19.87% 90.44% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 382 9.56% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 3996 # Type of FU issued +system.cpu.iq.rate 0.288666 # Inst issue rate +system.cpu.iq.fu_busy_cnt 44 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.011011 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 14670 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 7267 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 3636 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 13 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 6 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 6 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 4033 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 7 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 32 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.squashedLoads 546 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 6 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 164 # Number of stores squashed +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewSquashCycles 476 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 79 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 7 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 5242 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 68 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 961 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 458 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 6 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 4 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 6 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 52 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 137 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 189 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 3843 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 755 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 153 # Number of squashed instructions skipped in execute +system.cpu.iew.exec_swp 0 # number of swp insts executed +system.cpu.iew.exec_nop 329 # number of nop insts executed +system.cpu.iew.exec_refs 1131 # number of memory reference insts executed +system.cpu.iew.exec_branches 644 # Number of branches executed +system.cpu.iew.exec_stores 376 # Number of stores executed +system.cpu.iew.exec_rate 0.277613 # Inst execution rate +system.cpu.iew.wb_sent 3725 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 3642 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1733 # num instructions producing a value +system.cpu.iew.wb_consumers 2231 # num instructions consuming a value +system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ +system.cpu.iew.wb_rate 0.263093 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.776782 # average fanout of values written-back +system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 2576 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 2657 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 4 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 1995 # The number of squashed insts skipped by commit -system.cpu.commit.committed_per_cycle::samples 6308 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.408370 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.199072 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 159 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 6081 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.423615 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.271187 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 5350 84.81% 84.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 259 4.11% 88.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 343 5.44% 94.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 133 2.11% 96.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 72 1.14% 97.61% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 64 1.01% 98.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 26 0.41% 99.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 20 0.32% 99.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 41 0.65% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 5177 85.13% 85.13% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 230 3.78% 88.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 323 5.31% 94.23% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 118 1.94% 96.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 67 1.10% 97.27% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 52 0.86% 98.13% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 37 0.61% 98.73% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 20 0.33% 99.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 57 0.94% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 6308 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 6081 # Number of insts commited each cycle system.cpu.commit.count 2576 # Number of instructions committed -system.cpu.commit.fp_insts 6 # Number of committed floating point instructions. -system.cpu.commit.function_calls 71 # Number of function calls committed. -system.cpu.commit.int_insts 2367 # Number of committed integer instructions. +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.refs 709 # Number of memory references committed system.cpu.commit.loads 415 # Number of loads committed system.cpu.commit.membars 0 # Number of memory barriers committed -system.cpu.commit.refs 709 # Number of memory references committed -system.cpu.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.branches 396 # Number of branches committed +system.cpu.commit.fp_insts 6 # Number of committed floating point instructions. +system.cpu.commit.int_insts 2367 # Number of committed integer instructions. +system.cpu.commit.function_calls 71 # Number of function calls committed. +system.cpu.commit.bw_lim_events 57 # number cycles where commit BW limit reached +system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits +system.cpu.rob.rob_reads 11010 # The number of ROB reads +system.cpu.rob.rob_writes 10947 # The number of ROB writes +system.cpu.timesIdled 139 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 7286 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 2387 # Number of Instructions Simulated system.cpu.committedInsts_total 2387 # Number of Instructions Simulated -system.cpu.cpi 6.107667 # CPI: Cycles Per Instruction -system.cpu.cpi_total 6.107667 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 589 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 33939.814815 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35704.918033 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 481 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 3665500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.183362 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 108 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 47 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 2178000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.103565 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 61 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 294 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 38819.444444 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36145.833333 # average WriteReq mshr miss latency +system.cpu.cpi 5.799330 # CPI: Cycles Per Instruction +system.cpu.cpi_total 5.799330 # CPI: Total CPI of All Threads +system.cpu.ipc 0.172434 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.172434 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 4649 # number of integer regfile reads +system.cpu.int_regfile_writes 2817 # number of integer regfile writes +system.cpu.fp_regfile_reads 6 # number of floating regfile reads +system.cpu.misc_regfile_reads 1 # number of misc regfile reads +system.cpu.misc_regfile_writes 1 # number of misc regfile writes +system.cpu.icache.replacements 0 # number of replacements +system.cpu.icache.tagsinuse 92.452549 # Cycle average of tags in use +system.cpu.icache.total_refs 735 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 185 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 3.972973 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::0 92.452549 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.045143 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 735 # number of ReadReq hits +system.cpu.icache.demand_hits 735 # number of demand (read+write) hits +system.cpu.icache.overall_hits 735 # number of overall hits +system.cpu.icache.ReadReq_misses 241 # number of ReadReq misses +system.cpu.icache.demand_misses 241 # number of demand (read+write) misses +system.cpu.icache.overall_misses 241 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 8775500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 8775500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 8775500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 976 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 976 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 976 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.246926 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.246926 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.246926 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 36412.863071 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 36412.863071 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 36412.863071 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.writebacks 0 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits 56 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 56 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 56 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 185 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 185 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 185 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.ReadReq_mshr_miss_latency 6554000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 6554000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 6554000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.189549 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate 0.189549 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate 0.189549 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 35427.027027 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 35427.027027 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 35427.027027 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.replacements 0 # number of replacements +system.cpu.dcache.tagsinuse 45.779373 # Cycle average of tags in use +system.cpu.dcache.total_refs 794 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 85 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 9.341176 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::0 45.779373 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.011177 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 572 # number of ReadReq hits system.cpu.dcache.WriteReq_hits 222 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 2795000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.244898 # miss rate for WriteReq accesses +system.cpu.dcache.demand_hits 794 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 794 # number of overall hits +system.cpu.dcache.ReadReq_misses 116 # number of ReadReq misses system.cpu.dcache.WriteReq_misses 72 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 48 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 867500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.081633 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 24 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 8.270588 # Average number of references to valid blocks. -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.demand_misses 188 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 188 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 3872000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 2816500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency 6688500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 6688500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 688 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses 294 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses 982 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 982 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.168605 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate 0.244898 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate 0.191446 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.191446 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 33379.310345 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 39118.055556 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency 35577.127660 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 35577.127660 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 883 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 35891.666667 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 35829.411765 # average overall mshr miss latency -system.cpu.dcache.demand_hits 703 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 6460500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.203851 # miss rate for demand accesses -system.cpu.dcache.demand_misses 180 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 95 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 3045500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.096263 # mshr miss rate for demand accesses +system.cpu.dcache.writebacks 0 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 55 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 48 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits 103 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 103 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 61 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 24 # number of WriteReq MSHR misses system.cpu.dcache.demand_mshr_misses 85 # number of demand (read+write) MSHR misses -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_blocks::0 46.556735 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.011366 # Average percentage of cache occupancy -system.cpu.dcache.overall_accesses 883 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 35891.666667 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 35829.411765 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 703 # number of overall hits -system.cpu.dcache.overall_miss_latency 6460500 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.203851 # miss rate for overall accesses -system.cpu.dcache.overall_misses 180 # number of overall misses -system.cpu.dcache.overall_mshr_hits 95 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 3045500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.096263 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 85 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.sampled_refs 85 # Sample count of references to valid blocks. +system.cpu.dcache.ReadReq_mshr_miss_latency 2165500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 872000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 3037500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 3037500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.088663 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate 0.081633 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate 0.086558 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate 0.086558 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35500 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36333.333333 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 35735.294118 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 35735.294118 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 46.556735 # Cycle average of tags in use -system.cpu.dcache.total_refs 703 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.decode.BlockedCycles 217 # Number of cycles decode is blocked -system.cpu.decode.BranchMispred 79 # Number of times decode detected a branch misprediction -system.cpu.decode.BranchResolved 136 # Number of times decode resolved a branch -system.cpu.decode.DecodedInsts 5047 # Number of instructions handled by decode -system.cpu.decode.IdleCycles 5111 # Number of cycles decode is idle -system.cpu.decode.RunCycles 977 # Number of cycles decode is running -system.cpu.decode.SquashCycles 374 # Number of cycles decode is squashing -system.cpu.decode.SquashedInsts 284 # Number of squashed instructions handled by decode -system.cpu.decode.UnblockCycles 3 # Number of cycles decode is unblocking -system.cpu.dtb.data_accesses 1010 # DTB accesses -system.cpu.dtb.data_acv 1 # DTB access violations -system.cpu.dtb.data_hits 964 # DTB hits -system.cpu.dtb.data_misses 46 # DTB misses -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.read_accesses 644 # DTB read accesses -system.cpu.dtb.read_acv 1 # DTB read access violations -system.cpu.dtb.read_hits 617 # DTB read hits -system.cpu.dtb.read_misses 27 # DTB read misses -system.cpu.dtb.write_accesses 366 # DTB write accesses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_hits 347 # DTB write hits -system.cpu.dtb.write_misses 19 # DTB write misses -system.cpu.fetch.Branches 931 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 777 # Number of cache lines fetched -system.cpu.fetch.Cycles 986 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 113 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 5745 # Number of instructions fetch has processed -system.cpu.fetch.MiscStallCycles 29 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.SquashCycles 246 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.063859 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 777 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 371 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 0.394060 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 6682 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.859773 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.273067 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 5696 85.24% 85.24% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 43 0.64% 85.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 112 1.68% 87.56% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 72 1.08% 88.64% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 123 1.84% 90.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 53 0.79% 91.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 50 0.75% 92.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 59 0.88% 92.91% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 474 7.09% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 6682 # Number of instructions fetched each cycle (Total) -system.cpu.fp_regfile_reads 6 # number of floating regfile reads -system.cpu.icache.ReadReq_accesses 777 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 36200.431034 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 35306.629834 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 545 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 8398500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.298584 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 232 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 51 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 6390500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.232947 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 181 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 3.011050 # Average number of references to valid blocks. -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 777 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 36200.431034 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 35306.629834 # average overall mshr miss latency -system.cpu.icache.demand_hits 545 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 8398500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.298584 # miss rate for demand accesses -system.cpu.icache.demand_misses 232 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 51 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 6390500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.232947 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 181 # number of demand (read+write) MSHR misses -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_blocks::0 90.511194 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.044195 # Average percentage of cache occupancy -system.cpu.icache.overall_accesses 777 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 36200.431034 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 35306.629834 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 545 # number of overall hits -system.cpu.icache.overall_miss_latency 8398500 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.298584 # miss rate for overall accesses -system.cpu.icache.overall_misses 232 # number of overall misses -system.cpu.icache.overall_mshr_hits 51 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 6390500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.232947 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 181 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.sampled_refs 181 # Sample count of references to valid blocks. -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 90.511194 # Cycle average of tags in use -system.cpu.icache.total_refs 545 # Total number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 7897 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.branchMispredicts 171 # Number of branch mispredicts detected at execute -system.cpu.iew.exec_branches 600 # Number of branches executed -system.cpu.iew.exec_nop 311 # number of nop insts executed -system.cpu.iew.exec_rate 0.241855 # Inst execution rate -system.cpu.iew.exec_refs 1011 # number of memory reference insts executed -system.cpu.iew.exec_stores 366 # Number of stores executed -system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.iewBlockCycles 48 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 779 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 6 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 58 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 428 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 4585 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 645 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 109 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 3526 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 374 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 3 # Number of cycles IEW is unblocking -system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread0.forwLoads 28 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread0.memOrderViolation 4 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.squashedLoads 364 # Number of loads squashed -system.cpu.iew.lsq.thread0.squashedStores 134 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 4 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 118 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 53 # Number of branches that were predicted taken incorrectly -system.cpu.iew.wb_consumers 1995 # num instructions consuming a value -system.cpu.iew.wb_count 3404 # cumulative count of insts written-back -system.cpu.iew.wb_fanout 0.790977 # average fanout of values written-back -system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.wb_producers 1578 # num instructions producing a value -system.cpu.iew.wb_rate 0.233487 # insts written-back per cycle -system.cpu.iew.wb_sent 3463 # cumulative count of insts sent to commit -system.cpu.int_regfile_reads 4291 # number of integer regfile reads -system.cpu.int_regfile_writes 2610 # number of integer regfile writes -system.cpu.ipc 0.163729 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.163729 # IPC: Total IPC of All Threads -system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 2594 71.36% 71.36% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 1 0.03% 71.39% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 71.39% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 71.39% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 71.39% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 71.39% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 71.39% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 71.39% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 71.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 71.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 71.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 71.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 71.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 71.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 71.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 71.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 71.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 71.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 71.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 71.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 71.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 71.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 71.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 71.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 71.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 71.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 71.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 71.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 71.39% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 669 18.40% 89.79% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 371 10.21% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 3635 # Type of FU issued -system.cpu.iq.fp_alu_accesses 7 # Number of floating point alu accesses -system.cpu.iq.fp_inst_queue_reads 13 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_wakeup_accesses 6 # Number of floating instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_writes 6 # Number of floating instruction queue writes -system.cpu.iq.fu_busy_cnt 32 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.008803 # FU busy rate (busy events/executed inst) -system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 1 3.12% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 9 28.12% 31.25% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 22 68.75% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.int_alu_accesses 3660 # Number of integer alu accesses -system.cpu.iq.int_inst_queue_reads 14000 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_wakeup_accesses 3398 # Number of integer instruction queue wakeup accesses -system.cpu.iq.int_inst_queue_writes 5975 # Number of integer instruction queue writes -system.cpu.iq.iqInstsAdded 4268 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 3635 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 6 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 1704 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 29 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 959 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.issued_per_cycle::samples 6682 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.543999 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.232060 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 5130 76.77% 76.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 639 9.56% 86.34% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 335 5.01% 91.35% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 242 3.62% 94.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 178 2.66% 97.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 94 1.41% 99.04% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 39 0.58% 99.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 16 0.24% 99.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 9 0.13% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 6682 # Number of insts issued each cycle -system.cpu.iq.rate 0.249331 # Inst issue rate -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.fetch_accesses 806 # ITB accesses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_hits 777 # ITB hits -system.cpu.itb.fetch_misses 29 # ITB misses -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.l2cache.ReadExReq_accesses 24 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 34604.166667 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 830500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.replacements 0 # number of replacements +system.cpu.l2cache.tagsinuse 121.331762 # Cycle average of tags in use +system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 246 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::0 121.331762 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.003703 # Average percentage of cache occupancy +system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 0 # number of overall hits +system.cpu.l2cache.ReadReq_misses 246 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses 24 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 756000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 24 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 242 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 34326.446281 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31144.628099 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_miss_latency 8307000 # number of ReadReq miss cycles +system.cpu.l2cache.demand_misses 270 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 270 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 8443500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 831000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 9274500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 9274500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 246 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses 24 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 270 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 270 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 242 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 7537000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 242 # number of ReadReq MSHR misses -system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks. -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 34323.170732 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34625 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34350 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34350 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 266 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 34351.503759 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31176.691729 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 9137500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 266 # number of demand (read+write) misses +system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 8293000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 266 # number of demand (read+write) MSHR misses -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_blocks::0 119.871330 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.003658 # Average percentage of cache occupancy -system.cpu.l2cache.overall_accesses 266 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 34351.503759 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31176.691729 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 0 # number of overall hits -system.cpu.l2cache.overall_miss_latency 9137500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 266 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 8293000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 266 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_misses 246 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 24 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses 270 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 270 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 242 # Sample count of references to valid blocks. +system.cpu.l2cache.ReadReq_mshr_miss_latency 7659500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 756000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 8415500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 8415500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31136.178862 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31500 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31168.518519 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31168.518519 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 119.871330 # Cycle average of tags in use -system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.memDep0.conflictingLoads 4 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 779 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 428 # Number of stores inserted to the mem dependence unit. -system.cpu.misc_regfile_reads 1 # number of misc regfile reads -system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.numCycles 14579 # number of cpu cycles simulated -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.rename.BlockCycles 55 # Number of cycles rename is blocking -system.cpu.rename.CommittedMaps 1768 # Number of HB maps that are committed -system.cpu.rename.IQFullEvents 6 # Number of times rename has blocked due to IQ full -system.cpu.rename.IdleCycles 5189 # Number of cycles rename is idle -system.cpu.rename.LSQFullEvents 2 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenameLookups 5515 # Number of register rename lookups that rename has made -system.cpu.rename.RenamedInsts 4879 # Number of instructions processed by rename -system.cpu.rename.RenamedOperands 3490 # Number of destination operands rename has renamed -system.cpu.rename.RunCycles 901 # Number of cycles rename is running -system.cpu.rename.SquashCycles 374 # Number of cycles rename is squashing -system.cpu.rename.UnblockCycles 17 # Number of cycles rename is unblocking -system.cpu.rename.UndoneMaps 1722 # Number of HB maps that are undone due to squashing -system.cpu.rename.fp_rename_lookups 12 # Number of floating rename lookups -system.cpu.rename.int_rename_lookups 5503 # Number of integer rename lookups -system.cpu.rename.serializeStallCycles 146 # count of cycles rename stalled for serializing inst -system.cpu.rename.serializingInsts 8 # count of serializing insts renamed -system.cpu.rename.skidInsts 74 # count of insts added to the skid buffer -system.cpu.rename.tempSerializingInsts 6 # count of temporary serializing insts renamed -system.cpu.rob.rob_reads 10591 # The number of ROB reads -system.cpu.rob.rob_writes 9519 # The number of ROB writes -system.cpu.timesIdled 151 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.workload.num_syscalls 4 # Number of system calls +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |