regress: Regression Tester output updates

3 files changed, 41 insertions, 10 deletions

diff --git a/tests/quick/00.hello/ref/arm/linux/o3-timing/config.ini b/tests/quick/00.hello/ref/arm/linux/o3-timing/config.ini
index 9981924d0..63d0e5c85 100644
--- a/tests/quick/00.hello/ref/arm/linux/o3-timing/config.ini
+++ b/tests/quick/00.hello/ref/arm/linux/o3-timing/config.ini
@@ -1,13 +1,22 @@
 [root]
 type=Root
 children=system
-dummy=0
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
 
 [system]
 type=System
 children=cpu membus physmem
 mem_mode=atomic
 physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
 
 [system.cpu]
 type=DerivO3CPU
@@ -484,7 +493,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/chips/pd/randd/dist/test-progs/hello/bin/arm/linux/hello
+executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/arm/linux/hello
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/quick/00.hello/ref/arm/linux/o3-timing/simout b/tests/quick/00.hello/ref/arm/linux/o3-timing/simout
index 898cae0a1..55c02fbce 100755
--- a/tests/quick/00.hello/ref/arm/linux/o3-timing/simout
+++ b/tests/quick/00.hello/ref/arm/linux/o3-timing/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Jan 11 2011 18:16:01
-M5 revision b39a8457b332 7816 default ext/o3_regressions.patch qtip tip
-M5 started Jan 12 2011 04:32:17
-M5 executing on u200439-lin.austin.arm.com
+M5 compiled Feb  6 2011 15:30:08
+M5 revision b885adc82ab4+ 7924+ default tip qtip brad/regress_updates
+M5 started Feb  6 2011 20:48:42
+M5 executing on SC2B0617
 command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/quick/00.hello/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/quick/00.hello/arm/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/00.hello/ref/arm/linux/o3-timing/stats.txt b/tests/quick/00.hello/ref/arm/linux/o3-timing/stats.txt
index dbec33d6c..eae82995f 100644
--- a/tests/quick/00.hello/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/quick/00.hello/ref/arm/linux/o3-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                  59213                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 247916                       # Number of bytes of host memory used
-host_seconds                                     0.10                       # Real time elapsed on the host
-host_tick_rate                              108401013                       # Simulator tick rate (ticks/s)
+host_inst_rate                                  76010                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 216532                       # Number of bytes of host memory used
+host_seconds                                     0.07                       # Real time elapsed on the host
+host_tick_rate                              138961844                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                        5620                       # Number of instructions simulated
 sim_seconds                                  0.000010                       # Number of seconds simulated
@@ -37,6 +37,9 @@ system.cpu.commit.COM:committed_per_cycle::min_value            0
 system.cpu.commit.COM:committed_per_cycle::max_value            8                       # Number of insts commited each cycle
 system.cpu.commit.COM:committed_per_cycle::total        10656                       # Number of insts commited each cycle
 system.cpu.commit.COM:count                      5620                       # Number of instructions committed
+system.cpu.commit.COM:fp_insts                     16                       # Number of committed floating point instructions.
+system.cpu.commit.COM:function_calls                0                       # Number of function calls committed.
+system.cpu.commit.COM:int_insts                  4889                       # Number of committed integer instructions.
 system.cpu.commit.COM:loads                      1207                       # Number of loads committed
 system.cpu.commit.COM:membars                       0                       # Number of memory barriers committed
 system.cpu.commit.COM:refs                       2145                       # Number of memory references committed
@@ -171,6 +174,7 @@ system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Nu
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::total                11818                       # Number of instructions fetched each cycle (Total)
+system.cpu.fp_regfile_reads                        16                       # number of floating regfile reads
 system.cpu.icache.ReadReq_accesses               1675                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_avg_miss_latency 34635.549872                       # average ReadReq miss latency
 system.cpu.icache.ReadReq_avg_mshr_miss_latency 33596.573209                       # average ReadReq mshr miss latency
@@ -270,6 +274,8 @@ system.cpu.iew.lsq.thread.0.squashedStores          708                       #
 system.cpu.iew.memOrderViolationEvents             34                       # Number of memory order violations
 system.cpu.iew.predictedNotTakenIncorrect          609                       # Number of branches that were predicted not taken incorrectly
 system.cpu.iew.predictedTakenIncorrect             33                       # Number of branches that were predicted taken incorrectly
+system.cpu.int_regfile_reads                    19236                       # number of integer regfile reads
+system.cpu.int_regfile_writes                    5710                       # number of integer regfile writes
 system.cpu.ipc                               0.272340                       # IPC: Instructions Per Cycle
 system.cpu.ipc_total                         0.272340                       # IPC: Total IPC of All Threads
 system.cpu.iq.ISSUE:FU_type_0::No_OpClass            0      0.00%      0.00% # Type of FU issued
@@ -361,6 +367,14 @@ system.cpu.iq.ISSUE:issued_per_cycle::min_value            0
 system.cpu.iq.ISSUE:issued_per_cycle::max_value            8                       # Number of insts issued each cycle
 system.cpu.iq.ISSUE:issued_per_cycle::total        11818                       # Number of insts issued each cycle
 system.cpu.iq.ISSUE:rate                     0.440202                       # Inst issue rate
+system.cpu.iq.fp_alu_accesses                      22                       # Number of floating point alu accesses
+system.cpu.iq.fp_inst_queue_reads                  54                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_wakeup_accesses           16                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_writes                 58                       # Number of floating instruction queue writes
+system.cpu.iq.int_alu_accesses                   9243                       # Number of integer alu accesses
+system.cpu.iq.int_inst_queue_reads              30172                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_wakeup_accesses         7972                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.int_inst_queue_writes             17831                       # Number of integer instruction queue writes
 system.cpu.iq.iqInstsAdded                      11904                       # Number of instructions added to the IQ (excludes non-spec)
 system.cpu.iq.iqInstsIssued                      9084                       # Number of instructions issued
 system.cpu.iq.iqNonSpecInstsAdded                   2                       # Number of non-speculative instructions added to the IQ
@@ -458,7 +472,11 @@ system.cpu.memDep0.conflictingLoads                12                       # Nu
 system.cpu.memDep0.conflictingStores               11                       # Number of conflicting stores.
 system.cpu.memDep0.insertedLoads                 2545                       # Number of loads inserted to the mem dependence unit.
 system.cpu.memDep0.insertedStores                1646                       # Number of stores inserted to the mem dependence unit.
+system.cpu.misc_regfile_reads                   15396                       # number of misc regfile reads
+system.cpu.misc_regfile_writes                      3                       # number of misc regfile writes
 system.cpu.numCycles                            20636                       # number of cpu cycles simulated
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.rename.RENAME:BlockCycles              346                       # Number of cycles rename is blocking
 system.cpu.rename.RENAME:CommittedMaps           4006                       # Number of HB maps that are committed
 system.cpu.rename.RENAME:IQFullEvents              46                       # Number of times rename has blocked due to IQ full
@@ -471,10 +489,14 @@ system.cpu.rename.RENAME:RunCycles               2314                       # Nu
 system.cpu.rename.RENAME:SquashCycles            1162                       # Number of cycles rename is squashing
 system.cpu.rename.RENAME:UnblockCycles            187                       # Number of cycles rename is unblocking
 system.cpu.rename.RENAME:UndoneMaps              6085                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.RENAME:fp_rename_lookups          744                       # Number of floating rename lookups
+system.cpu.rename.RENAME:int_rename_lookups        36764                       # Number of integer rename lookups
 system.cpu.rename.RENAME:serializeStallCycles          271                       # count of cycles rename stalled for serializing inst
 system.cpu.rename.RENAME:serializingInsts            4                       # count of serializing insts renamed
 system.cpu.rename.RENAME:skidInsts                537                       # count of insts added to the skid buffer
 system.cpu.rename.RENAME:tempSerializingInsts            1                       # count of temporary serializing insts renamed
+system.cpu.rob.rob_reads                        22070                       # The number of ROB reads
+system.cpu.rob.rob_writes                       24470                       # The number of ROB writes
 system.cpu.timesIdled                             180                       # Number of times that the entire CPU went into an idle state and unscheduled itself
 system.cpu.workload.PROG:num_syscalls              13                       # Number of system calls