diff options
author | Ali Saidi <Ali.Saidi@ARM.com> | 2012-01-25 17:19:50 +0000 |
---|---|---|
committer | Ali Saidi <Ali.Saidi@ARM.com> | 2012-01-25 17:19:50 +0000 |
commit | a17dbdf8834b84f05a8f5154a74ac819fe8adc7c (patch) | |
tree | 8761136c790b84e20d6df2e84207eca3c553984b /tests/quick/00.hello/ref/arm/linux/o3-timing | |
parent | bd55c9e2af7fd6c06af48a020c29cb33ba1ca3fc (diff) | |
download | gem5-a17dbdf8834b84f05a8f5154a74ac819fe8adc7c.tar.xz |
stats: Update stats for final tick and memory bandwidth patches
Diffstat (limited to 'tests/quick/00.hello/ref/arm/linux/o3-timing')
-rw-r--r-- | tests/quick/00.hello/ref/arm/linux/o3-timing/config.ini | 10 | ||||
-rwxr-xr-x | tests/quick/00.hello/ref/arm/linux/o3-timing/simout | 6 | ||||
-rw-r--r-- | tests/quick/00.hello/ref/arm/linux/o3-timing/stats.txt | 18 |
3 files changed, 23 insertions, 11 deletions
diff --git a/tests/quick/00.hello/ref/arm/linux/o3-timing/config.ini b/tests/quick/00.hello/ref/arm/linux/o3-timing/config.ini index 35f7f2ba7..21dc694d7 100644 --- a/tests/quick/00.hello/ref/arm/linux/o3-timing/config.ini +++ b/tests/quick/00.hello/ref/arm/linux/o3-timing/config.ini @@ -10,6 +10,7 @@ type=System children=cpu membus physmem mem_mode=atomic memories=system.physmem +num_work_ids=16 physmem=system.physmem work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 @@ -18,6 +19,7 @@ work_cpus_ckpt_count=0 work_end_ckpt_count=0 work_end_exit_count=0 work_item_id=-1 +system_port=system.membus.port[0] [system.cpu] type=DerivO3CPU @@ -477,7 +479,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.toL2Bus.port[2] -mem_side=system.membus.port[1] +mem_side=system.membus.port[2] [system.cpu.toL2Bus] type=Bus @@ -500,7 +502,7 @@ egid=100 env= errout=cerr euid=100 -executable=/projects/pd/randd/dist/test-progs/hello/bin/arm/linux/hello +executable=/dist/m5/regression/test-progs/hello/bin/arm/linux/hello gid=100 input=cin max_stack_size=67108864 @@ -519,7 +521,7 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.physmem.port[0] system.cpu.l2cache.mem_side +port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side [system.physmem] type=PhysicalMemory @@ -529,5 +531,5 @@ latency_var=0 null=false range=0:134217727 zero=false -port=system.membus.port[0] +port=system.membus.port[1] diff --git a/tests/quick/00.hello/ref/arm/linux/o3-timing/simout b/tests/quick/00.hello/ref/arm/linux/o3-timing/simout index 2cb4f1a9c..f402d7e9e 100755 --- a/tests/quick/00.hello/ref/arm/linux/o3-timing/simout +++ b/tests/quick/00.hello/ref/arm/linux/o3-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Nov 21 2011 16:28:02 -gem5 started Nov 22 2011 19:01:51 -gem5 executing on u200540-lin +gem5 compiled Jan 23 2012 04:16:21 +gem5 started Jan 23 2012 04:24:50 +gem5 executing on zizzer command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/quick/00.hello/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/quick/00.hello/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/00.hello/ref/arm/linux/o3-timing/stats.txt b/tests/quick/00.hello/ref/arm/linux/o3-timing/stats.txt index 3aaa40ec4..19b87b225 100644 --- a/tests/quick/00.hello/ref/arm/linux/o3-timing/stats.txt +++ b/tests/quick/00.hello/ref/arm/linux/o3-timing/stats.txt @@ -2,12 +2,22 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000010 # Number of seconds simulated sim_ticks 10001500 # Number of ticks simulated +final_tick 10001500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 48143 # Simulator instruction rate (inst/s) -host_tick_rate 83889434 # Simulator tick rate (ticks/s) -host_mem_usage 212568 # Number of bytes of host memory used -host_seconds 0.12 # Real time elapsed on the host +host_inst_rate 15723 # Simulator instruction rate (inst/s) +host_tick_rate 27400304 # Simulator tick rate (ticks/s) +host_mem_usage 218472 # Number of bytes of host memory used +host_seconds 0.37 # Real time elapsed on the host sim_insts 5739 # Number of instructions simulated +system.physmem.bytes_read 25856 # Number of bytes read from this memory +system.physmem.bytes_inst_read 17856 # Number of instructions bytes read from this memory +system.physmem.bytes_written 0 # Number of bytes written to this memory +system.physmem.num_reads 404 # Number of read requests responded to by this memory +system.physmem.num_writes 0 # Number of write requests responded to by this memory +system.physmem.num_other 0 # Number of other requests responded to by this memory +system.physmem.bw_read 2585212218 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 1785332200 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total 2585212218 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits |