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author | Gabe Black <gblack@eecs.umich.edu> | 2009-06-09 23:55:53 -0700 |
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committer | Gabe Black <gblack@eecs.umich.edu> | 2009-06-09 23:55:53 -0700 |
commit | 85ca50261101287c33539adeb703b21a3783a703 (patch) | |
tree | 823b2fc9bb43d9c5cabdce23aa147e511755a35e /tests/quick/00.hello/ref/arm/linux/simple-atomic/stats.txt | |
parent | d91a3cf53d7077aa70e5bf101aab68e7b1ebd579 (diff) | |
download | gem5-85ca50261101287c33539adeb703b21a3783a703.tar.xz |
ARM: Add a hello world regression.
Diffstat (limited to 'tests/quick/00.hello/ref/arm/linux/simple-atomic/stats.txt')
-rw-r--r-- | tests/quick/00.hello/ref/arm/linux/simple-atomic/stats.txt | 36 |
1 files changed, 36 insertions, 0 deletions
diff --git a/tests/quick/00.hello/ref/arm/linux/simple-atomic/stats.txt b/tests/quick/00.hello/ref/arm/linux/simple-atomic/stats.txt new file mode 100644 index 000000000..5a17d118e --- /dev/null +++ b/tests/quick/00.hello/ref/arm/linux/simple-atomic/stats.txt @@ -0,0 +1,36 @@ + +---------- Begin Simulation Statistics ---------- +host_inst_rate 79163 # Simulator instruction rate (inst/s) +host_mem_usage 189980 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host +host_tick_rate 39442081 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 4598 # Number of instructions simulated +sim_seconds 0.000002 # Number of seconds simulated +sim_ticks 2299000 # Number of ticks simulated +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.numCycles 4599 # number of cpu cycles simulated +system.cpu.num_insts 4598 # Number of instructions executed +system.cpu.num_refs 1851 # Number of memory references +system.cpu.workload.PROG:num_syscalls 14 # Number of system calls + +---------- End Simulation Statistics ---------- |