diff options
author | Ali Saidi <Ali.Saidi@ARM.com> | 2011-03-17 19:20:22 -0500 |
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committer | Ali Saidi <Ali.Saidi@ARM.com> | 2011-03-17 19:20:22 -0500 |
commit | 63eb337b3b93ab71ab3157ec6487901d4fc6cda6 (patch) | |
tree | f3dada322d407488b3081a6b9139948b42a610b3 /tests/quick/00.hello/ref/arm/linux/simple-atomic | |
parent | ccaaa98b4916f730e5eee0cb1d206dca21cb802d (diff) | |
download | gem5-63eb337b3b93ab71ab3157ec6487901d4fc6cda6.tar.xz |
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
Diffstat (limited to 'tests/quick/00.hello/ref/arm/linux/simple-atomic')
3 files changed, 23 insertions, 23 deletions
diff --git a/tests/quick/00.hello/ref/arm/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/arm/linux/simple-atomic/config.ini index 327106c53..e51c73913 100644 --- a/tests/quick/00.hello/ref/arm/linux/simple-atomic/config.ini +++ b/tests/quick/00.hello/ref/arm/linux/simple-atomic/config.ini @@ -66,7 +66,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/hello/bin/arm/linux/hello +executable=/chips/pd/randd/dist/test-progs/hello/bin/arm/linux/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/00.hello/ref/arm/linux/simple-atomic/simout b/tests/quick/00.hello/ref/arm/linux/simple-atomic/simout index 301661eda..9914f72a8 100755 --- a/tests/quick/00.hello/ref/arm/linux/simple-atomic/simout +++ b/tests/quick/00.hello/ref/arm/linux/simple-atomic/simout @@ -5,12 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 7 2011 01:56:16 -M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip -M5 started Feb 7 2011 01:56:25 -M5 executing on burrito +M5 compiled Mar 11 2011 20:10:09 +M5 revision 4decc284606a 8095 default qtip tip ext/update_add_stats.patch +M5 started Mar 11 2011 21:03:49 +M5 executing on u200439-lin.austin.arm.com command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/quick/00.hello/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/fast/quick/00.hello/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 2816000 because target called exit() +Exiting @ tick 2875500 because target called exit() diff --git a/tests/quick/00.hello/ref/arm/linux/simple-atomic/stats.txt b/tests/quick/00.hello/ref/arm/linux/simple-atomic/stats.txt index 25bd032b8..95e8b4e85 100644 --- a/tests/quick/00.hello/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/quick/00.hello/ref/arm/linux/simple-atomic/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 100802 # Simulator instruction rate (inst/s) -host_mem_usage 225720 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host -host_tick_rate 50271986 # Simulator tick rate (ticks/s) +host_inst_rate 642377 # Simulator instruction rate (inst/s) +host_mem_usage 242352 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host +host_tick_rate 312928501 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 5620 # Number of instructions simulated +sim_insts 5739 # Number of instructions simulated sim_seconds 0.000003 # Number of seconds simulated -sim_ticks 2816000 # Number of ticks simulated +sim_ticks 2875500 # Number of ticks simulated system.cpu.dtb.accesses 0 # DTB accesses system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -52,24 +52,24 @@ system.cpu.itb.write_accesses 0 # DT system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 5633 # number of cpu cycles simulated +system.cpu.numCycles 5752 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.num_busy_cycles 5633 # Number of busy cycles -system.cpu.num_conditional_control_insts 0 # number of instructions that are conditional controls +system.cpu.num_busy_cycles 5752 # Number of busy cycles +system.cpu.num_conditional_control_insts 775 # number of instructions that are conditional controls system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses system.cpu.num_fp_insts 16 # number of float instructions system.cpu.num_fp_register_reads 16 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_func_calls 0 # number of times a function call or return occured +system.cpu.num_func_calls 185 # number of times a function call or return occured system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_insts 5620 # Number of instructions executed -system.cpu.num_int_alu_accesses 4889 # Number of integer alu accesses -system.cpu.num_int_insts 4889 # number of integer instructions -system.cpu.num_int_register_reads 14091 # number of times the integer registers were read -system.cpu.num_int_register_writes 3689 # number of times the integer registers were written -system.cpu.num_load_insts 1207 # Number of load instructions -system.cpu.num_mem_refs 2145 # number of memory refs +system.cpu.num_insts 5739 # Number of instructions executed +system.cpu.num_int_alu_accesses 4985 # Number of integer alu accesses +system.cpu.num_int_insts 4985 # number of integer instructions +system.cpu.num_int_register_reads 14295 # number of times the integer registers were read +system.cpu.num_int_register_writes 3802 # number of times the integer registers were written +system.cpu.num_load_insts 1201 # Number of load instructions +system.cpu.num_mem_refs 2139 # number of memory refs system.cpu.num_store_insts 938 # Number of store instructions system.cpu.workload.PROG:num_syscalls 13 # Number of system calls |