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| author | Brad Beckmann <Brad.Beckmann@amd.com> | 2011-02-06 22:14:23 -0800 |
|---|---|---|
| committer | Brad Beckmann <Brad.Beckmann@amd.com> | 2011-02-06 22:14:23 -0800 |
| commit | 45f881919fc9c4d2b2d4ea9f165fb567aad9849a (patch) | |
| tree | 2a6ebbec93e62ef5279ec35e27e06f86577372fd /tests/quick/00.hello/ref/arm/linux/simple-timing | |
| parent | f5aa75fdc528aca122ac1369fa4ac3df8a915027 (diff) | |
| download | gem5-45f881919fc9c4d2b2d4ea9f165fb567aad9849a.tar.xz | |
regress: Regression Tester output updates
Diffstat (limited to 'tests/quick/00.hello/ref/arm/linux/simple-timing')
3 files changed, 36 insertions, 11 deletions
diff --git a/tests/quick/00.hello/ref/arm/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/arm/linux/simple-timing/config.ini index d4111deef..e20209bea 100644 --- a/tests/quick/00.hello/ref/arm/linux/simple-timing/config.ini +++ b/tests/quick/00.hello/ref/arm/linux/simple-timing/config.ini @@ -1,13 +1,22 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=TimingSimpleCPU @@ -157,7 +166,7 @@ egid=100 env= errout=cerr euid=100 -executable=/chips/pd/randd/dist/test-progs/hello/bin/arm/linux/hello +executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/arm/linux/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/00.hello/ref/arm/linux/simple-timing/simout b/tests/quick/00.hello/ref/arm/linux/simple-timing/simout index a1f858063..7a871d396 100755 --- a/tests/quick/00.hello/ref/arm/linux/simple-timing/simout +++ b/tests/quick/00.hello/ref/arm/linux/simple-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Dec 7 2010 18:51:32 -M5 revision 331c8c76d885 7806 default qtip tip ext/mismatched_new_delete.patch -M5 started Dec 7 2010 18:51:46 -M5 executing on u200439-lin.austin.arm.com +M5 compiled Feb 6 2011 15:30:08 +M5 revision b885adc82ab4+ 7924+ default tip qtip brad/regress_updates +M5 started Feb 6 2011 20:48:42 +M5 executing on SC2B0617 command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/quick/00.hello/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/fast/quick/00.hello/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/00.hello/ref/arm/linux/simple-timing/stats.txt b/tests/quick/00.hello/ref/arm/linux/simple-timing/stats.txt index 3c0d4e2a6..59d8fd1e1 100644 --- a/tests/quick/00.hello/ref/arm/linux/simple-timing/stats.txt +++ b/tests/quick/00.hello/ref/arm/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 315416 # Simulator instruction rate (inst/s) -host_mem_usage 248988 # Number of bytes of host memory used -host_seconds 0.02 # Real time elapsed on the host -host_tick_rate 1472008046 # Simulator tick rate (ticks/s) +host_inst_rate 437377 # Simulator instruction rate (inst/s) +host_mem_usage 215508 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host +host_tick_rate 2028175520 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5563 # Number of instructions simulated sim_seconds 0.000026 # Number of seconds simulated @@ -237,8 +237,24 @@ system.cpu.l2cache.warmup_cycle 0 # Cy system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 52692 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.num_busy_cycles 52692 # Number of busy cycles +system.cpu.num_conditional_control_insts 0 # number of instructions that are conditional controls +system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses +system.cpu.num_fp_insts 16 # number of float instructions +system.cpu.num_fp_register_reads 16 # number of times the floating registers were read +system.cpu.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu.num_func_calls 0 # number of times a function call or return occured +system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 5563 # Number of instructions executed -system.cpu.num_refs 2145 # Number of memory references +system.cpu.num_int_alu_accesses 4889 # Number of integer alu accesses +system.cpu.num_int_insts 4889 # number of integer instructions +system.cpu.num_int_register_reads 15212 # number of times the integer registers were read +system.cpu.num_int_register_writes 3689 # number of times the integer registers were written +system.cpu.num_load_insts 1207 # Number of load instructions +system.cpu.num_mem_refs 2145 # number of memory refs +system.cpu.num_store_insts 938 # Number of store instructions system.cpu.workload.PROG:num_syscalls 13 # Number of system calls ---------- End Simulation Statistics ---------- |