diff options
author | Nathan Binkert <nate@binkert.org> | 2011-04-22 10:18:51 -0700 |
---|---|---|
committer | Nathan Binkert <nate@binkert.org> | 2011-04-22 10:18:51 -0700 |
commit | a7e27f9a82300f213b268264e1dede222d26bd4d (patch) | |
tree | 905f84d6e06111d4a243c18a1899e932646bdced /tests/quick/00.hello/ref/arm/linux | |
parent | 2342aa2ebbb9dfe232eafcd20f01a8dd95ebfcc0 (diff) | |
download | gem5-a7e27f9a82300f213b268264e1dede222d26bd4d.tar.xz |
tests: updates for stat name change
Diffstat (limited to 'tests/quick/00.hello/ref/arm/linux')
-rwxr-xr-x | tests/quick/00.hello/ref/arm/linux/o3-timing/simout | 4 | ||||
-rw-r--r-- | tests/quick/00.hello/ref/arm/linux/o3-timing/stats.txt | 28 |
2 files changed, 16 insertions, 16 deletions
diff --git a/tests/quick/00.hello/ref/arm/linux/o3-timing/simout b/tests/quick/00.hello/ref/arm/linux/o3-timing/simout index ca0b775a3..f5ea06dc5 100755 --- a/tests/quick/00.hello/ref/arm/linux/o3-timing/simout +++ b/tests/quick/00.hello/ref/arm/linux/o3-timing/simout @@ -5,8 +5,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 19 2011 12:47:10 -M5 started Apr 19 2011 13:32:41 +M5 compiled Apr 21 2011 12:05:01 +M5 started Apr 21 2011 15:18:29 M5 executing on maize command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/quick/00.hello/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/quick/00.hello/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/quick/00.hello/ref/arm/linux/o3-timing/stats.txt b/tests/quick/00.hello/ref/arm/linux/o3-timing/stats.txt index d620e2c6d..1ac2ece63 100644 --- a/tests/quick/00.hello/ref/arm/linux/o3-timing/stats.txt +++ b/tests/quick/00.hello/ref/arm/linux/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 117635 # Simulator instruction rate (inst/s) -host_mem_usage 212912 # Number of bytes of host memory used -host_seconds 0.05 # Real time elapsed on the host -host_tick_rate 220680920 # Simulator tick rate (ticks/s) +host_inst_rate 81044 # Simulator instruction rate (inst/s) +host_mem_usage 215360 # Number of bytes of host memory used +host_seconds 0.07 # Real time elapsed on the host +host_tick_rate 152195453 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5739 # Number of instructions simulated sim_seconds 0.000011 # Number of seconds simulated @@ -265,16 +265,16 @@ system.cpu.iew.iewIdleCycles 0 # Nu system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu.iew.iewSquashCycles 770 # Number of cycles IEW is squashing system.cpu.iew.iewUnblockCycles 26 # Number of cycles IEW is unblocking -system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 52 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 12 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 1171 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 560 # Number of stores squashed +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.forwLoads 52 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.memOrderViolation 12 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.squashedLoads 1171 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedStores 560 # Number of stores squashed system.cpu.iew.memOrderViolationEvents 12 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 246 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 119 # Number of branches that were predicted taken incorrectly |