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authorGabe Black <gblack@eecs.umich.edu>2012-01-28 07:24:45 -0800
committerGabe Black <gblack@eecs.umich.edu>2012-01-28 07:24:45 -0800
commit57e07ac2d2daaa7469241372510395e43ebe14c0 (patch)
treedc338f4fbe8b26f7d7d3532ea0abe324846ca33d /tests/quick/00.hello/ref/arm
parentec20ee2f7cdaff22e63a5ae492f925d0d4839849 (diff)
downloadgem5-57e07ac2d2daaa7469241372510395e43ebe14c0.tar.xz
SE/FS: Make both SE and FS tests available all the time.
--HG-- rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simerr => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simerr rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/system.terminal => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/system.terminal rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simerr => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simerr rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/system.terminal => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/system.terminal rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/simout => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/status => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/status rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/system.terminal => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/system.terminal rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3/config.ini => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3/simerr => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simerr rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3/simout => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3/stats.txt => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3/system.terminal => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/system.terminal rename : tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini => tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini rename : tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/simerr => tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simerr rename : tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/simout => tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout rename : tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt => tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt rename : tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/system.pc.com_1.terminal => tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/system.pc.com_1.terminal rename : tests/long/10.linux-boot/test.py => tests/long/fs/10.linux-boot/test.py rename : tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini => tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini rename : tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simerr => tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simerr rename : tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simout => tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simout rename : tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt => tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt rename : tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/system.t1000.hterm => tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/system.t1000.hterm rename : tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/system.t1000.pterm => tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/system.t1000.pterm rename : tests/long/80.solaris-boot/test.py => tests/long/fs/80.solaris-boot/test.py rename : tests/long/00.gzip/ref/alpha/tru64/inorder-timing/config.ini => tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/config.ini rename : tests/long/00.gzip/ref/alpha/tru64/inorder-timing/simerr => tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/simerr rename : tests/long/00.gzip/ref/alpha/tru64/inorder-timing/simout => tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/simout rename : tests/long/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt => tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt rename : tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini => tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/config.ini rename : tests/long/00.gzip/ref/alpha/tru64/o3-timing/simerr => tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/simerr rename : tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout => tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/simout rename : tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt => tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt rename : tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.ini => tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/config.ini rename : tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simerr => tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/simerr rename : tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simout => tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/simout rename : tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt => tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt rename : tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini => tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/config.ini rename : tests/long/00.gzip/ref/alpha/tru64/simple-timing/simerr => tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/simerr rename : tests/long/00.gzip/ref/alpha/tru64/simple-timing/simout => tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/simout rename : tests/long/00.gzip/ref/alpha/tru64/simple-timing/stats.txt => tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/stats.txt rename : tests/long/00.gzip/ref/arm/linux/o3-timing/config.ini => tests/long/se/00.gzip/ref/arm/linux/o3-timing/config.ini rename : tests/long/00.gzip/ref/arm/linux/o3-timing/simerr => tests/long/se/00.gzip/ref/arm/linux/o3-timing/simerr rename : tests/long/00.gzip/ref/arm/linux/o3-timing/simout => tests/long/se/00.gzip/ref/arm/linux/o3-timing/simout rename : tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt => tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt rename : tests/long/00.gzip/ref/arm/linux/simple-atomic/config.ini => tests/long/se/00.gzip/ref/arm/linux/simple-atomic/config.ini rename : tests/long/00.gzip/ref/arm/linux/simple-atomic/simerr => tests/long/se/00.gzip/ref/arm/linux/simple-atomic/simerr rename : tests/long/00.gzip/ref/arm/linux/simple-atomic/simout => tests/long/se/00.gzip/ref/arm/linux/simple-atomic/simout rename : tests/long/00.gzip/ref/arm/linux/simple-atomic/stats.txt => tests/long/se/00.gzip/ref/arm/linux/simple-atomic/stats.txt rename : tests/long/00.gzip/ref/arm/linux/simple-timing/config.ini => tests/long/se/00.gzip/ref/arm/linux/simple-timing/config.ini rename : tests/long/00.gzip/ref/arm/linux/simple-timing/simerr => tests/long/se/00.gzip/ref/arm/linux/simple-timing/simerr rename : tests/long/00.gzip/ref/arm/linux/simple-timing/simout => tests/long/se/00.gzip/ref/arm/linux/simple-timing/simout rename : tests/long/00.gzip/ref/arm/linux/simple-timing/stats.txt => tests/long/se/00.gzip/ref/arm/linux/simple-timing/stats.txt rename : tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini => tests/long/se/00.gzip/ref/sparc/linux/o3-timing/config.ini rename : tests/long/00.gzip/ref/sparc/linux/o3-timing/simerr => tests/long/se/00.gzip/ref/sparc/linux/o3-timing/simerr rename : tests/long/00.gzip/ref/sparc/linux/o3-timing/simout => tests/long/se/00.gzip/ref/sparc/linux/o3-timing/simout rename : tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt => tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt rename : tests/long/00.gzip/ref/sparc/linux/simple-atomic/config.ini => tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/config.ini rename : tests/long/00.gzip/ref/sparc/linux/simple-atomic/simerr => tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/simerr rename : tests/long/00.gzip/ref/sparc/linux/simple-atomic/simout => tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/simout rename : tests/long/00.gzip/ref/sparc/linux/simple-atomic/stats.txt => tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/stats.txt rename : tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini => tests/long/se/00.gzip/ref/sparc/linux/simple-timing/config.ini rename : tests/long/00.gzip/ref/sparc/linux/simple-timing/simerr => tests/long/se/00.gzip/ref/sparc/linux/simple-timing/simerr rename : tests/long/00.gzip/ref/sparc/linux/simple-timing/simout => tests/long/se/00.gzip/ref/sparc/linux/simple-timing/simout rename : tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt => tests/long/se/00.gzip/ref/sparc/linux/simple-timing/stats.txt rename : tests/long/00.gzip/ref/x86/linux/o3-timing/config.ini => tests/long/se/00.gzip/ref/x86/linux/o3-timing/config.ini rename : tests/long/00.gzip/ref/x86/linux/o3-timing/simerr => tests/long/se/00.gzip/ref/x86/linux/o3-timing/simerr rename : tests/long/00.gzip/ref/x86/linux/o3-timing/simout => tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout rename : tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt => tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt rename : tests/long/00.gzip/ref/x86/linux/simple-atomic/config.ini => tests/long/se/00.gzip/ref/x86/linux/simple-atomic/config.ini rename : tests/long/00.gzip/ref/x86/linux/simple-atomic/simerr => tests/long/se/00.gzip/ref/x86/linux/simple-atomic/simerr rename : tests/long/00.gzip/ref/x86/linux/simple-atomic/simout => tests/long/se/00.gzip/ref/x86/linux/simple-atomic/simout rename : tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt => tests/long/se/00.gzip/ref/x86/linux/simple-atomic/stats.txt rename : tests/long/00.gzip/ref/x86/linux/simple-timing/config.ini => tests/long/se/00.gzip/ref/x86/linux/simple-timing/config.ini rename : tests/long/00.gzip/ref/x86/linux/simple-timing/simerr => tests/long/se/00.gzip/ref/x86/linux/simple-timing/simerr rename : tests/long/00.gzip/ref/x86/linux/simple-timing/simout => tests/long/se/00.gzip/ref/x86/linux/simple-timing/simout rename : tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt => tests/long/se/00.gzip/ref/x86/linux/simple-timing/stats.txt rename : tests/long/00.gzip/test.py => tests/long/se/00.gzip/test.py rename : tests/long/10.mcf/ref/arm/linux/o3-timing/chair.cook.ppm => tests/long/se/10.mcf/ref/arm/linux/o3-timing/chair.cook.ppm rename : tests/long/10.mcf/ref/arm/linux/o3-timing/config.ini => tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini rename : tests/long/10.mcf/ref/arm/linux/o3-timing/mcf.out => tests/long/se/10.mcf/ref/arm/linux/o3-timing/mcf.out rename : tests/long/10.mcf/ref/arm/linux/o3-timing/simerr => tests/long/se/10.mcf/ref/arm/linux/o3-timing/simerr rename : tests/long/10.mcf/ref/arm/linux/o3-timing/simout => tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout rename : tests/long/10.mcf/ref/arm/linux/o3-timing/stats.txt => tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt rename : tests/long/10.mcf/ref/arm/linux/simple-atomic/chair.cook.ppm => tests/long/se/10.mcf/ref/arm/linux/simple-atomic/chair.cook.ppm rename : tests/long/10.mcf/ref/arm/linux/simple-atomic/config.ini => tests/long/se/10.mcf/ref/arm/linux/simple-atomic/config.ini rename : tests/long/10.mcf/ref/arm/linux/simple-atomic/mcf.out => tests/long/se/10.mcf/ref/arm/linux/simple-atomic/mcf.out rename : tests/long/10.mcf/ref/arm/linux/simple-atomic/simerr => tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simerr rename : tests/long/10.mcf/ref/arm/linux/simple-atomic/simout => tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simout rename : tests/long/10.mcf/ref/arm/linux/simple-atomic/stats.txt => tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt rename : tests/long/10.mcf/ref/arm/linux/simple-timing/chair.cook.ppm => tests/long/se/10.mcf/ref/arm/linux/simple-timing/chair.cook.ppm rename : tests/long/10.mcf/ref/arm/linux/simple-timing/config.ini => tests/long/se/10.mcf/ref/arm/linux/simple-timing/config.ini rename : tests/long/10.mcf/ref/arm/linux/simple-timing/mcf.out => tests/long/se/10.mcf/ref/arm/linux/simple-timing/mcf.out rename : tests/long/10.mcf/ref/arm/linux/simple-timing/simerr => tests/long/se/10.mcf/ref/arm/linux/simple-timing/simerr rename : tests/long/10.mcf/ref/arm/linux/simple-timing/simout => tests/long/se/10.mcf/ref/arm/linux/simple-timing/simout rename : tests/long/10.mcf/ref/arm/linux/simple-timing/stats.txt => tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt rename : tests/long/10.mcf/ref/sparc/linux/simple-atomic/config.ini => tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/config.ini rename : tests/long/10.mcf/ref/sparc/linux/simple-atomic/mcf.out => tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/mcf.out rename : tests/long/10.mcf/ref/sparc/linux/simple-atomic/simerr => tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/simerr rename : tests/long/10.mcf/ref/sparc/linux/simple-atomic/simout => tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/simout rename : tests/long/10.mcf/ref/sparc/linux/simple-atomic/stats.txt => tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt rename : tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini => tests/long/se/10.mcf/ref/sparc/linux/simple-timing/config.ini rename : tests/long/10.mcf/ref/sparc/linux/simple-timing/mcf.out => tests/long/se/10.mcf/ref/sparc/linux/simple-timing/mcf.out rename : tests/long/10.mcf/ref/sparc/linux/simple-timing/simerr => tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simerr rename : tests/long/10.mcf/ref/sparc/linux/simple-timing/simout => tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simout rename : tests/long/10.mcf/ref/sparc/linux/simple-timing/stats.txt => tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt rename : tests/long/10.mcf/ref/x86/linux/o3-timing/config.ini => tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini rename : tests/long/10.mcf/ref/x86/linux/o3-timing/mcf.out => tests/long/se/10.mcf/ref/x86/linux/o3-timing/mcf.out rename : tests/long/10.mcf/ref/x86/linux/o3-timing/simerr => tests/long/se/10.mcf/ref/x86/linux/o3-timing/simerr rename : tests/long/10.mcf/ref/x86/linux/o3-timing/simout => tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout rename : tests/long/10.mcf/ref/x86/linux/o3-timing/stats.txt => tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt rename : tests/long/10.mcf/ref/x86/linux/simple-atomic/config.ini => tests/long/se/10.mcf/ref/x86/linux/simple-atomic/config.ini rename : tests/long/10.mcf/ref/x86/linux/simple-atomic/mcf.out => tests/long/se/10.mcf/ref/x86/linux/simple-atomic/mcf.out rename : tests/long/10.mcf/ref/x86/linux/simple-atomic/simerr => tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simerr rename : tests/long/10.mcf/ref/x86/linux/simple-atomic/simout => tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simout rename : tests/long/10.mcf/ref/x86/linux/simple-atomic/stats.txt => tests/long/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt rename : tests/long/10.mcf/ref/x86/linux/simple-timing/config.ini => tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini rename : tests/long/10.mcf/ref/x86/linux/simple-timing/mcf.out => tests/long/se/10.mcf/ref/x86/linux/simple-timing/mcf.out rename : tests/long/10.mcf/ref/x86/linux/simple-timing/simerr => tests/long/se/10.mcf/ref/x86/linux/simple-timing/simerr rename : tests/long/10.mcf/ref/x86/linux/simple-timing/simout => tests/long/se/10.mcf/ref/x86/linux/simple-timing/simout rename : tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt => tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt rename : tests/long/10.mcf/test.py => tests/long/se/10.mcf/test.py rename : tests/long/20.parser/ref/alpha/tru64/NOTE => tests/long/se/20.parser/ref/alpha/tru64/NOTE rename : tests/long/20.parser/ref/arm/linux/o3-timing/config.ini => tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini rename : tests/long/20.parser/ref/arm/linux/o3-timing/simerr => tests/long/se/20.parser/ref/arm/linux/o3-timing/simerr rename : tests/long/20.parser/ref/arm/linux/o3-timing/simout => tests/long/se/20.parser/ref/arm/linux/o3-timing/simout rename : tests/long/20.parser/ref/arm/linux/o3-timing/stats.txt => tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt rename : tests/long/20.parser/ref/arm/linux/simple-atomic/config.ini => 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tests/long/50.vortex/ref/arm/linux/simple-atomic/smred.out => tests/long/se/50.vortex/ref/arm/linux/simple-atomic/smred.out rename : tests/long/50.vortex/ref/arm/linux/simple-atomic/stats.txt => tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt rename : tests/long/50.vortex/ref/arm/linux/simple-timing/config.ini => tests/long/se/50.vortex/ref/arm/linux/simple-timing/config.ini rename : tests/long/50.vortex/ref/arm/linux/simple-timing/simerr => tests/long/se/50.vortex/ref/arm/linux/simple-timing/simerr rename : tests/long/50.vortex/ref/arm/linux/simple-timing/simout => tests/long/se/50.vortex/ref/arm/linux/simple-timing/simout rename : tests/long/50.vortex/ref/arm/linux/simple-timing/smred.out => tests/long/se/50.vortex/ref/arm/linux/simple-timing/smred.out rename : tests/long/50.vortex/ref/arm/linux/simple-timing/stats.txt => tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt rename : tests/long/50.vortex/ref/sparc/linux/simple-atomic/config.ini => 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tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/stats.txt => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/stats.txt rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/ruby.stats => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/ruby.stats rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simerr => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simerr rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/ruby.stats => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/ruby.stats rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simerr => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simerr rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/ruby.stats => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/ruby.stats rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simerr => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simerr rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/ruby.stats => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/ruby.stats rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/simerr => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simerr rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/simout => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simout rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/config.ini rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing/simerr => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/simerr rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing/simout => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/simout rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing/stats.txt => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt rename : tests/quick/00.hello/ref/arm/linux/o3-timing/config.ini => tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini rename : tests/quick/00.hello/ref/arm/linux/o3-timing/simerr => tests/quick/se/00.hello/ref/arm/linux/o3-timing/simerr rename : tests/quick/00.hello/ref/arm/linux/o3-timing/simout => tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout rename : tests/quick/00.hello/ref/arm/linux/o3-timing/stats.txt => tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt rename : tests/quick/00.hello/ref/arm/linux/simple-atomic/config.ini => tests/quick/se/00.hello/ref/arm/linux/simple-atomic/config.ini rename : tests/quick/00.hello/ref/arm/linux/simple-atomic/simerr => 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tests/quick/00.hello/ref/mips/linux/inorder-timing/simerr => tests/quick/se/00.hello/ref/mips/linux/inorder-timing/simerr rename : tests/quick/00.hello/ref/mips/linux/inorder-timing/simout => tests/quick/se/00.hello/ref/mips/linux/inorder-timing/simout rename : tests/quick/00.hello/ref/mips/linux/inorder-timing/stats.txt => tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt rename : tests/quick/00.hello/ref/mips/linux/o3-timing/config.ini => tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini rename : tests/quick/00.hello/ref/mips/linux/o3-timing/simerr => tests/quick/se/00.hello/ref/mips/linux/o3-timing/simerr rename : tests/quick/00.hello/ref/mips/linux/o3-timing/simout => tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout rename : tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt => tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt rename : tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini => tests/quick/se/00.hello/ref/mips/linux/simple-atomic/config.ini rename : tests/quick/00.hello/ref/mips/linux/simple-atomic/simerr => tests/quick/se/00.hello/ref/mips/linux/simple-atomic/simerr rename : tests/quick/00.hello/ref/mips/linux/simple-atomic/simout => tests/quick/se/00.hello/ref/mips/linux/simple-atomic/simout rename : tests/quick/00.hello/ref/mips/linux/simple-atomic/stats.txt => tests/quick/se/00.hello/ref/mips/linux/simple-atomic/stats.txt rename : tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/config.ini => tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/config.ini rename : tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/simerr => tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/simerr rename : tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/simout => tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/simout rename : tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt => tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt rename : tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini => tests/quick/se/00.hello/ref/mips/linux/simple-timing/config.ini rename : tests/quick/00.hello/ref/mips/linux/simple-timing/simerr => tests/quick/se/00.hello/ref/mips/linux/simple-timing/simerr rename : tests/quick/00.hello/ref/mips/linux/simple-timing/simout => tests/quick/se/00.hello/ref/mips/linux/simple-timing/simout rename : tests/quick/00.hello/ref/mips/linux/simple-timing/stats.txt => tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt rename : tests/quick/00.hello/ref/power/linux/o3-timing/config.ini => tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini rename : tests/quick/00.hello/ref/power/linux/o3-timing/simerr => tests/quick/se/00.hello/ref/power/linux/o3-timing/simerr rename : tests/quick/00.hello/ref/power/linux/o3-timing/simout => tests/quick/se/00.hello/ref/power/linux/o3-timing/simout rename : tests/quick/00.hello/ref/power/linux/o3-timing/stats.txt => tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt rename : tests/quick/00.hello/ref/power/linux/simple-atomic/config.ini => tests/quick/se/00.hello/ref/power/linux/simple-atomic/config.ini rename : tests/quick/00.hello/ref/power/linux/simple-atomic/simerr => tests/quick/se/00.hello/ref/power/linux/simple-atomic/simerr rename : tests/quick/00.hello/ref/power/linux/simple-atomic/simout => tests/quick/se/00.hello/ref/power/linux/simple-atomic/simout rename : tests/quick/00.hello/ref/power/linux/simple-atomic/stats.txt => tests/quick/se/00.hello/ref/power/linux/simple-atomic/stats.txt rename : tests/quick/00.hello/ref/sparc/linux/inorder-timing/config.ini => tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/config.ini rename : tests/quick/00.hello/ref/sparc/linux/inorder-timing/simerr => tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/simerr rename : tests/quick/00.hello/ref/sparc/linux/inorder-timing/simout => tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/simout rename : tests/quick/00.hello/ref/sparc/linux/inorder-timing/stats.txt => tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt rename : tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.ini => tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/config.ini rename : tests/quick/00.hello/ref/sparc/linux/simple-atomic/simerr => tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/simerr rename : tests/quick/00.hello/ref/sparc/linux/simple-atomic/simout => tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/simout rename : tests/quick/00.hello/ref/sparc/linux/simple-atomic/stats.txt => tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/stats.txt rename : tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini => tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini rename : tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/ruby.stats => tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/ruby.stats rename : tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/simerr => tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simerr rename : tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/simout => tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simout rename : tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt => tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt rename : tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini => tests/quick/se/00.hello/ref/sparc/linux/simple-timing/config.ini rename : tests/quick/00.hello/ref/sparc/linux/simple-timing/simerr => tests/quick/se/00.hello/ref/sparc/linux/simple-timing/simerr rename : tests/quick/00.hello/ref/sparc/linux/simple-timing/simout => tests/quick/se/00.hello/ref/sparc/linux/simple-timing/simout rename : tests/quick/00.hello/ref/sparc/linux/simple-timing/stats.txt => tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt rename : tests/quick/00.hello/ref/x86/linux/o3-timing/config.ini => tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini rename : tests/quick/00.hello/ref/x86/linux/o3-timing/simerr => tests/quick/se/00.hello/ref/x86/linux/o3-timing/simerr rename : tests/quick/00.hello/ref/x86/linux/o3-timing/simout => tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout rename : tests/quick/00.hello/ref/x86/linux/o3-timing/stats.txt => tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt rename : tests/quick/00.hello/ref/x86/linux/simple-atomic/config.ini => tests/quick/se/00.hello/ref/x86/linux/simple-atomic/config.ini rename : tests/quick/00.hello/ref/x86/linux/simple-atomic/simerr => tests/quick/se/00.hello/ref/x86/linux/simple-atomic/simerr rename : tests/quick/00.hello/ref/x86/linux/simple-atomic/simout => tests/quick/se/00.hello/ref/x86/linux/simple-atomic/simout rename : tests/quick/00.hello/ref/x86/linux/simple-atomic/stats.txt => tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt rename : tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/config.ini => tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/config.ini rename : tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats => tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats rename : tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/simerr => tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simerr rename : tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/simout => tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simout rename : tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt => tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt rename : tests/quick/00.hello/ref/x86/linux/simple-timing/config.ini => tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini rename : tests/quick/00.hello/ref/x86/linux/simple-timing/simerr => tests/quick/se/00.hello/ref/x86/linux/simple-timing/simerr rename : tests/quick/00.hello/ref/x86/linux/simple-timing/simout => tests/quick/se/00.hello/ref/x86/linux/simple-timing/simout rename : tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt => tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt rename : tests/quick/00.hello/test.py => tests/quick/se/00.hello/test.py rename : tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini => tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini rename : tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simerr => tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simerr rename : tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout => tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout rename : tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt => tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt rename : tests/quick/01.hello-2T-smt/test.py => tests/quick/se/01.hello-2T-smt/test.py rename : tests/quick/02.insttest/ref/sparc/linux/inorder-timing/config.ini => tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/config.ini rename : tests/quick/02.insttest/ref/sparc/linux/inorder-timing/simerr => tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/simerr rename : tests/quick/02.insttest/ref/sparc/linux/inorder-timing/simout => tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/simout rename : tests/quick/02.insttest/ref/sparc/linux/inorder-timing/stats.txt => tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt rename : tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini => tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini rename : tests/quick/02.insttest/ref/sparc/linux/o3-timing/simerr => tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simerr rename : tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout => tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout rename : tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt => tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt rename : tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.ini => tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/config.ini rename : tests/quick/02.insttest/ref/sparc/linux/simple-atomic/simerr => tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simerr rename : tests/quick/02.insttest/ref/sparc/linux/simple-atomic/simout => tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simout rename : tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stats.txt => tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/stats.txt rename : tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.ini => tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/config.ini rename : tests/quick/02.insttest/ref/sparc/linux/simple-timing/simerr => tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/simerr rename : tests/quick/02.insttest/ref/sparc/linux/simple-timing/simout => tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/simout rename : tests/quick/02.insttest/ref/sparc/linux/simple-timing/stats.txt => tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt rename : tests/quick/02.insttest/test.py => tests/quick/se/02.insttest/test.py rename : tests/quick/20.eio-short/ref/alpha/eio/detailed/config.ini => tests/quick/se/20.eio-short/ref/alpha/eio/detailed/config.ini rename : tests/quick/20.eio-short/ref/alpha/eio/detailed/simerr => tests/quick/se/20.eio-short/ref/alpha/eio/detailed/simerr rename : tests/quick/20.eio-short/ref/alpha/eio/detailed/simout => tests/quick/se/20.eio-short/ref/alpha/eio/detailed/simout rename : tests/quick/20.eio-short/ref/alpha/eio/detailed/stats.txt => tests/quick/se/20.eio-short/ref/alpha/eio/detailed/stats.txt rename : tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini => tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/config.ini rename : tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/simerr => tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/simerr rename : tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/simout => tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/simout rename : tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt => tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt rename : tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini => tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/config.ini rename : tests/quick/20.eio-short/ref/alpha/eio/simple-timing/simerr => tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/simerr rename : tests/quick/20.eio-short/ref/alpha/eio/simple-timing/simout => tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/simout rename : tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stats.txt => tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/stats.txt rename : tests/quick/20.eio-short/test.py => tests/quick/se/20.eio-short/test.py rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.ini => tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.ini rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simerr => tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simerr rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout => tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt => tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini => tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr => tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout => tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt => tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt rename : tests/quick/30.eio-mp/test.py => tests/quick/se/30.eio-mp/test.py rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simerr => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simerr rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simerr => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simerr rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/config.ini => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/config.ini rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/ruby.stats => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/ruby.stats rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/simerr => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/simerr rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/simout => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/simout rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/skip => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/skip rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/stats.txt => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/stats.txt rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simerr => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simerr rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt rename : tests/quick/40.m5threads-test-atomic/test.py => tests/quick/se/40.m5threads-test-atomic/test.py rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/config.ini => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/config.ini rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/ruby.stats => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/ruby.stats rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simerr => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simerr rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simout => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simout rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/stats.txt => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/stats.txt rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/config.ini => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/config.ini rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/ruby.stats => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/ruby.stats rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simerr => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simerr rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simout => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simout rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/config.ini => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/config.ini rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/ruby.stats => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/ruby.stats rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simerr => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simerr rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simout => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simout rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/config.ini => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/config.ini rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/ruby.stats => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/ruby.stats rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simerr => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simerr rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simout => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simout rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/config.ini => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/config.ini rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/ruby.stats => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/ruby.stats rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/simerr => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/simerr rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/simout => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/simout rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt rename : tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini => tests/quick/se/50.memtest/ref/alpha/linux/memtest/config.ini rename : tests/quick/50.memtest/ref/alpha/linux/memtest/simerr => tests/quick/se/50.memtest/ref/alpha/linux/memtest/simerr rename : tests/quick/50.memtest/ref/alpha/linux/memtest/simout => tests/quick/se/50.memtest/ref/alpha/linux/memtest/simout rename : tests/quick/50.memtest/ref/alpha/linux/memtest/stats.txt => tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt rename : tests/quick/50.memtest/test.py => tests/quick/se/50.memtest/test.py rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/config.ini => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/config.ini rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/ruby.stats => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/ruby.stats rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simerr => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simerr rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simout => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simout rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/stats.txt => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/stats.txt rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/config.ini => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/config.ini rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/ruby.stats => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/ruby.stats rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simerr => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simerr rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simout => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simout rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/config.ini => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/config.ini rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/ruby.stats => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/ruby.stats rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simerr => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simerr rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simout => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simout rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/stats.txt => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/stats.txt rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/config.ini => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/config.ini rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/ruby.stats => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/ruby.stats rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simerr => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simerr rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simout => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simout rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/config.ini => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/config.ini rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/ruby.stats => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/ruby.stats rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/simerr => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/simerr rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/simout => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/simout rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt rename : tests/quick/60.rubytest/test.py => tests/quick/se/60.rubytest/test.py
Diffstat (limited to 'tests/quick/00.hello/ref/arm')
-rw-r--r--tests/quick/00.hello/ref/arm/linux/o3-timing/config.ini535
-rwxr-xr-xtests/quick/00.hello/ref/arm/linux/o3-timing/simerr2
-rwxr-xr-xtests/quick/00.hello/ref/arm/linux/o3-timing/simout11
-rw-r--r--tests/quick/00.hello/ref/arm/linux/o3-timing/stats.txt526
-rw-r--r--tests/quick/00.hello/ref/arm/linux/simple-atomic/config.ini102
-rwxr-xr-xtests/quick/00.hello/ref/arm/linux/simple-atomic/simerr2
-rwxr-xr-xtests/quick/00.hello/ref/arm/linux/simple-atomic/simout11
-rw-r--r--tests/quick/00.hello/ref/arm/linux/simple-atomic/stats.txt87
-rw-r--r--tests/quick/00.hello/ref/arm/linux/simple-timing/config.ini205
-rwxr-xr-xtests/quick/00.hello/ref/arm/linux/simple-timing/simerr2
-rwxr-xr-xtests/quick/00.hello/ref/arm/linux/simple-timing/simout11
-rw-r--r--tests/quick/00.hello/ref/arm/linux/simple-timing/stats.txt274
12 files changed, 0 insertions, 1768 deletions
diff --git a/tests/quick/00.hello/ref/arm/linux/o3-timing/config.ini b/tests/quick/00.hello/ref/arm/linux/o3-timing/config.ini
deleted file mode 100644
index 21dc694d7..000000000
--- a/tests/quick/00.hello/ref/arm/linux/o3-timing/config.ini
+++ /dev/null
@@ -1,535 +0,0 @@
-[root]
-type=Root
-children=system
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
-
-[system]
-type=System
-children=cpu membus physmem
-mem_mode=atomic
-memories=system.physmem
-num_work_ids=16
-physmem=system.physmem
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
-system_port=system.membus.port[0]
-
-[system.cpu]
-type=DerivO3CPU
-children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload
-BTBEntries=4096
-BTBTagSize=16
-LFSTSize=1024
-LQEntries=32
-LSQCheckLoads=true
-LSQDepCheckShift=4
-RASSize=16
-SQEntries=32
-SSITSize=1024
-activity=0
-backComSize=5
-cachePorts=200
-checker=Null
-choiceCtrBits=2
-choicePredictorSize=8192
-clock=500
-commitToDecodeDelay=1
-commitToFetchDelay=1
-commitToIEWDelay=1
-commitToRenameDelay=1
-commitWidth=8
-cpu_id=0
-decodeToFetchDelay=1
-decodeToRenameDelay=1
-decodeWidth=8
-defer_registration=false
-dispatchWidth=8
-do_checkpoint_insts=true
-do_statistics_insts=true
-dtb=system.cpu.dtb
-fetchToDecodeDelay=1
-fetchTrapLatency=1
-fetchWidth=8
-forwardComSize=5
-fuPool=system.cpu.fuPool
-function_trace=false
-function_trace_start=0
-globalCtrBits=2
-globalHistoryBits=13
-globalPredictorSize=8192
-iewToCommitDelay=1
-iewToDecodeDelay=1
-iewToFetchDelay=1
-iewToRenameDelay=1
-instShiftAmt=2
-issueToExecuteDelay=1
-issueWidth=8
-itb=system.cpu.itb
-localCtrBits=2
-localHistoryBits=11
-localHistoryTableSize=2048
-localPredictorSize=2048
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-numIQEntries=64
-numPhysFloatRegs=256
-numPhysIntRegs=256
-numROBEntries=192
-numRobs=1
-numThreads=1
-phase=0
-predType=tournament
-progress_interval=0
-renameToDecodeDelay=1
-renameToFetchDelay=1
-renameToIEWDelay=2
-renameToROBDelay=1
-renameWidth=8
-smtCommitPolicy=RoundRobin
-smtFetchPolicy=SingleThread
-smtIQPolicy=Partitioned
-smtIQThreshold=100
-smtLSQPolicy=Partitioned
-smtLSQThreshold=100
-smtNumFetchingThreads=1
-smtROBPolicy=Partitioned
-smtROBThreshold=100
-squashWidth=8
-store_set_clear_period=250000
-system=system
-tracer=system.cpu.tracer
-trapLatency=13
-wbDepth=1
-wbWidth=8
-workload=system.cpu.workload
-dcache_port=system.cpu.dcache.cpu_side
-icache_port=system.cpu.icache.cpu_side
-
-[system.cpu.dcache]
-type=BaseCache
-addr_range=0:18446744073709551615
-assoc=2
-block_size=64
-forward_snoops=true
-hash_delay=1
-is_top_level=true
-latency=1000
-max_miss_count=0
-mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
-prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-repl=Null
-size=262144
-subblock_size=0
-tgts_per_mshr=20
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.dcache_port
-mem_side=system.cpu.toL2Bus.port[1]
-
-[system.cpu.dtb]
-type=ArmTLB
-size=64
-
-[system.cpu.fuPool]
-type=FUPool
-children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
-FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
-
-[system.cpu.fuPool.FUList0]
-type=FUDesc
-children=opList
-count=6
-opList=system.cpu.fuPool.FUList0.opList
-
-[system.cpu.fuPool.FUList0.opList]
-type=OpDesc
-issueLat=1
-opClass=IntAlu
-opLat=1
-
-[system.cpu.fuPool.FUList1]
-type=FUDesc
-children=opList0 opList1
-count=2
-opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
-
-[system.cpu.fuPool.FUList1.opList0]
-type=OpDesc
-issueLat=1
-opClass=IntMult
-opLat=3
-
-[system.cpu.fuPool.FUList1.opList1]
-type=OpDesc
-issueLat=19
-opClass=IntDiv
-opLat=20
-
-[system.cpu.fuPool.FUList2]
-type=FUDesc
-children=opList0 opList1 opList2
-count=4
-opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
-
-[system.cpu.fuPool.FUList2.opList0]
-type=OpDesc
-issueLat=1
-opClass=FloatAdd
-opLat=2
-
-[system.cpu.fuPool.FUList2.opList1]
-type=OpDesc
-issueLat=1
-opClass=FloatCmp
-opLat=2
-
-[system.cpu.fuPool.FUList2.opList2]
-type=OpDesc
-issueLat=1
-opClass=FloatCvt
-opLat=2
-
-[system.cpu.fuPool.FUList3]
-type=FUDesc
-children=opList0 opList1 opList2
-count=2
-opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
-
-[system.cpu.fuPool.FUList3.opList0]
-type=OpDesc
-issueLat=1
-opClass=FloatMult
-opLat=4
-
-[system.cpu.fuPool.FUList3.opList1]
-type=OpDesc
-issueLat=12
-opClass=FloatDiv
-opLat=12
-
-[system.cpu.fuPool.FUList3.opList2]
-type=OpDesc
-issueLat=24
-opClass=FloatSqrt
-opLat=24
-
-[system.cpu.fuPool.FUList4]
-type=FUDesc
-children=opList
-count=0
-opList=system.cpu.fuPool.FUList4.opList
-
-[system.cpu.fuPool.FUList4.opList]
-type=OpDesc
-issueLat=1
-opClass=MemRead
-opLat=1
-
-[system.cpu.fuPool.FUList5]
-type=FUDesc
-children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
-count=4
-opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
-
-[system.cpu.fuPool.FUList5.opList00]
-type=OpDesc
-issueLat=1
-opClass=SimdAdd
-opLat=1
-
-[system.cpu.fuPool.FUList5.opList01]
-type=OpDesc
-issueLat=1
-opClass=SimdAddAcc
-opLat=1
-
-[system.cpu.fuPool.FUList5.opList02]
-type=OpDesc
-issueLat=1
-opClass=SimdAlu
-opLat=1
-
-[system.cpu.fuPool.FUList5.opList03]
-type=OpDesc
-issueLat=1
-opClass=SimdCmp
-opLat=1
-
-[system.cpu.fuPool.FUList5.opList04]
-type=OpDesc
-issueLat=1
-opClass=SimdCvt
-opLat=1
-
-[system.cpu.fuPool.FUList5.opList05]
-type=OpDesc
-issueLat=1
-opClass=SimdMisc
-opLat=1
-
-[system.cpu.fuPool.FUList5.opList06]
-type=OpDesc
-issueLat=1
-opClass=SimdMult
-opLat=1
-
-[system.cpu.fuPool.FUList5.opList07]
-type=OpDesc
-issueLat=1
-opClass=SimdMultAcc
-opLat=1
-
-[system.cpu.fuPool.FUList5.opList08]
-type=OpDesc
-issueLat=1
-opClass=SimdShift
-opLat=1
-
-[system.cpu.fuPool.FUList5.opList09]
-type=OpDesc
-issueLat=1
-opClass=SimdShiftAcc
-opLat=1
-
-[system.cpu.fuPool.FUList5.opList10]
-type=OpDesc
-issueLat=1
-opClass=SimdSqrt
-opLat=1
-
-[system.cpu.fuPool.FUList5.opList11]
-type=OpDesc
-issueLat=1
-opClass=SimdFloatAdd
-opLat=1
-
-[system.cpu.fuPool.FUList5.opList12]
-type=OpDesc
-issueLat=1
-opClass=SimdFloatAlu
-opLat=1
-
-[system.cpu.fuPool.FUList5.opList13]
-type=OpDesc
-issueLat=1
-opClass=SimdFloatCmp
-opLat=1
-
-[system.cpu.fuPool.FUList5.opList14]
-type=OpDesc
-issueLat=1
-opClass=SimdFloatCvt
-opLat=1
-
-[system.cpu.fuPool.FUList5.opList15]
-type=OpDesc
-issueLat=1
-opClass=SimdFloatDiv
-opLat=1
-
-[system.cpu.fuPool.FUList5.opList16]
-type=OpDesc
-issueLat=1
-opClass=SimdFloatMisc
-opLat=1
-
-[system.cpu.fuPool.FUList5.opList17]
-type=OpDesc
-issueLat=1
-opClass=SimdFloatMult
-opLat=1
-
-[system.cpu.fuPool.FUList5.opList18]
-type=OpDesc
-issueLat=1
-opClass=SimdFloatMultAcc
-opLat=1
-
-[system.cpu.fuPool.FUList5.opList19]
-type=OpDesc
-issueLat=1
-opClass=SimdFloatSqrt
-opLat=1
-
-[system.cpu.fuPool.FUList6]
-type=FUDesc
-children=opList
-count=0
-opList=system.cpu.fuPool.FUList6.opList
-
-[system.cpu.fuPool.FUList6.opList]
-type=OpDesc
-issueLat=1
-opClass=MemWrite
-opLat=1
-
-[system.cpu.fuPool.FUList7]
-type=FUDesc
-children=opList0 opList1
-count=4
-opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
-
-[system.cpu.fuPool.FUList7.opList0]
-type=OpDesc
-issueLat=1
-opClass=MemRead
-opLat=1
-
-[system.cpu.fuPool.FUList7.opList1]
-type=OpDesc
-issueLat=1
-opClass=MemWrite
-opLat=1
-
-[system.cpu.fuPool.FUList8]
-type=FUDesc
-children=opList
-count=1
-opList=system.cpu.fuPool.FUList8.opList
-
-[system.cpu.fuPool.FUList8.opList]
-type=OpDesc
-issueLat=3
-opClass=IprAccess
-opLat=3
-
-[system.cpu.icache]
-type=BaseCache
-addr_range=0:18446744073709551615
-assoc=2
-block_size=64
-forward_snoops=true
-hash_delay=1
-is_top_level=true
-latency=1000
-max_miss_count=0
-mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
-prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-repl=Null
-size=131072
-subblock_size=0
-tgts_per_mshr=20
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.icache_port
-mem_side=system.cpu.toL2Bus.port[0]
-
-[system.cpu.itb]
-type=ArmTLB
-size=64
-
-[system.cpu.l2cache]
-type=BaseCache
-addr_range=0:18446744073709551615
-assoc=2
-block_size=64
-forward_snoops=true
-hash_delay=1
-is_top_level=false
-latency=1000
-max_miss_count=0
-mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
-prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-repl=Null
-size=2097152
-subblock_size=0
-tgts_per_mshr=5
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[2]
-
-[system.cpu.toL2Bus]
-type=Bus
-block_size=64
-bus_id=0
-clock=1000
-header_cycles=1
-use_default_range=false
-width=64
-port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
-
-[system.cpu.tracer]
-type=ExeTracer
-
-[system.cpu.workload]
-type=LiveProcess
-cmd=hello
-cwd=
-egid=100
-env=
-errout=cerr
-euid=100
-executable=/dist/m5/regression/test-progs/hello/bin/arm/linux/hello
-gid=100
-input=cin
-max_stack_size=67108864
-output=cout
-pid=100
-ppid=99
-simpoint=0
-system=system
-uid=100
-
-[system.membus]
-type=Bus
-block_size=64
-bus_id=0
-clock=1000
-header_cycles=1
-use_default_range=false
-width=64
-port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
-
-[system.physmem]
-type=PhysicalMemory
-file=
-latency=30000
-latency_var=0
-null=false
-range=0:134217727
-zero=false
-port=system.membus.port[1]
-
diff --git a/tests/quick/00.hello/ref/arm/linux/o3-timing/simerr b/tests/quick/00.hello/ref/arm/linux/o3-timing/simerr
deleted file mode 100755
index e45cd058f..000000000
--- a/tests/quick/00.hello/ref/arm/linux/o3-timing/simerr
+++ /dev/null
@@ -1,2 +0,0 @@
-warn: Sockets disabled, not accepting gdb connections
-hack: be nice to actually delete the event here
diff --git a/tests/quick/00.hello/ref/arm/linux/o3-timing/simout b/tests/quick/00.hello/ref/arm/linux/o3-timing/simout
deleted file mode 100755
index f402d7e9e..000000000
--- a/tests/quick/00.hello/ref/arm/linux/o3-timing/simout
+++ /dev/null
@@ -1,11 +0,0 @@
-gem5 Simulator System. http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-gem5 compiled Jan 23 2012 04:16:21
-gem5 started Jan 23 2012 04:24:50
-gem5 executing on zizzer
-command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/quick/00.hello/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/quick/00.hello/arm/linux/o3-timing
-Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0. Starting simulation...
-Hello world!
-Exiting @ tick 10001500 because target called exit()
diff --git a/tests/quick/00.hello/ref/arm/linux/o3-timing/stats.txt b/tests/quick/00.hello/ref/arm/linux/o3-timing/stats.txt
deleted file mode 100644
index 19b87b225..000000000
--- a/tests/quick/00.hello/ref/arm/linux/o3-timing/stats.txt
+++ /dev/null
@@ -1,526 +0,0 @@
-
----------- Begin Simulation Statistics ----------
-sim_seconds 0.000010 # Number of seconds simulated
-sim_ticks 10001500 # Number of ticks simulated
-final_tick 10001500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 15723 # Simulator instruction rate (inst/s)
-host_tick_rate 27400304 # Simulator tick rate (ticks/s)
-host_mem_usage 218472 # Number of bytes of host memory used
-host_seconds 0.37 # Real time elapsed on the host
-sim_insts 5739 # Number of instructions simulated
-system.physmem.bytes_read 25856 # Number of bytes read from this memory
-system.physmem.bytes_inst_read 17856 # Number of instructions bytes read from this memory
-system.physmem.bytes_written 0 # Number of bytes written to this memory
-system.physmem.num_reads 404 # Number of read requests responded to by this memory
-system.physmem.num_writes 0 # Number of write requests responded to by this memory
-system.physmem.num_other 0 # Number of other requests responded to by this memory
-system.physmem.bw_read 2585212218 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read 1785332200 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total 2585212218 # Total bandwidth to/from this memory (bytes/s)
-system.cpu.dtb.inst_hits 0 # ITB inst hits
-system.cpu.dtb.inst_misses 0 # ITB inst misses
-system.cpu.dtb.read_hits 0 # DTB read hits
-system.cpu.dtb.read_misses 0 # DTB read misses
-system.cpu.dtb.write_hits 0 # DTB write hits
-system.cpu.dtb.write_misses 0 # DTB write misses
-system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses 0 # DTB read accesses
-system.cpu.dtb.write_accesses 0 # DTB write accesses
-system.cpu.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu.dtb.hits 0 # DTB hits
-system.cpu.dtb.misses 0 # DTB misses
-system.cpu.dtb.accesses 0 # DTB accesses
-system.cpu.itb.inst_hits 0 # ITB inst hits
-system.cpu.itb.inst_misses 0 # ITB inst misses
-system.cpu.itb.read_hits 0 # DTB read hits
-system.cpu.itb.read_misses 0 # DTB read misses
-system.cpu.itb.write_hits 0 # DTB write hits
-system.cpu.itb.write_misses 0 # DTB write misses
-system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.itb.read_accesses 0 # DTB read accesses
-system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.inst_accesses 0 # ITB inst accesses
-system.cpu.itb.hits 0 # DTB hits
-system.cpu.itb.misses 0 # DTB misses
-system.cpu.itb.accesses 0 # DTB accesses
-system.cpu.workload.num_syscalls 13 # Number of system calls
-system.cpu.numCycles 20004 # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 2398 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 1771 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 436 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 1789 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 703 # Number of BTB hits
-system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS 246 # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect 51 # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles 6120 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 12134 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 2398 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 949 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 2694 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 1578 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 1626 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 2 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 19 # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines 1920 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 303 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 11510 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 1.338054 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.716635 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 8816 76.59% 76.59% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 262 2.28% 78.87% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 169 1.47% 80.34% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 225 1.95% 82.29% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 227 1.97% 84.27% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 313 2.72% 86.99% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 109 0.95% 87.93% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 113 0.98% 88.91% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 1276 11.09% 100.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 11510 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.119876 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.606579 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 6265 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 1809 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 2491 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 58 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 887 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 401 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 168 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 13387 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 587 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 887 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 6541 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 230 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 1411 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 2270 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 171 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 12504 # Number of instructions processed by rename
-system.cpu.rename.LSQFullEvents 153 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands 12063 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 57218 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 56026 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 1192 # Number of floating rename lookups
-system.cpu.rename.CommittedMaps 5684 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 6379 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 41 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 39 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 478 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 2574 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 1703 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 9 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 8 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 10784 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 49 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 8706 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 95 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 4802 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 13397 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 12 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 11510 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 0.756386 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.438063 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 8025 69.72% 69.72% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 1281 11.13% 80.85% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 772 6.71% 87.56% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 541 4.70% 92.26% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 447 3.88% 96.14% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 256 2.22% 98.37% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 137 1.19% 99.56% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 40 0.35% 99.90% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 11 0.10% 100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 11510 # Number of insts issued each cycle
-system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 2 0.99% 0.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 0.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 0.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 0.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 0.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 0.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 137 67.49% 68.47% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 64 31.53% 100.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 5272 60.56% 60.56% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 6 0.07% 60.62% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.62% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.62% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.62% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.62% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.62% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.62% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.62% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.62% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.62% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.62% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.62% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.62% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.62% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.62% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.62% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.62% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.62% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.62% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.62% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.62% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.62% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.62% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.62% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.66% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.66% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.66% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.66% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 2203 25.30% 85.96% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 1222 14.04% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 8706 # Type of FU issued
-system.cpu.iq.rate 0.435213 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 203 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.023317 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 29184 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 15632 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 7824 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 8889 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 51 # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 1373 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 14 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 765 # Number of stores squashed
-system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 887 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 121 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 8 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 10834 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 179 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 2574 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 1703 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 37 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 14 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 90 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 295 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 385 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 8282 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 2009 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 424 # Number of squashed instructions skipped in execute
-system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 1 # number of nop insts executed
-system.cpu.iew.exec_refs 3178 # number of memory reference insts executed
-system.cpu.iew.exec_branches 1354 # Number of branches executed
-system.cpu.iew.exec_stores 1169 # Number of stores executed
-system.cpu.iew.exec_rate 0.414017 # Inst execution rate
-system.cpu.iew.wb_sent 7957 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 7840 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 3690 # num instructions producing a value
-system.cpu.iew.wb_consumers 7291 # num instructions consuming a value
-system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 0.391922 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.506103 # average fanout of values written-back
-system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitCommittedInsts 5739 # The number of committed instructions
-system.cpu.commit.commitSquashedInsts 5094 # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 345 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 10624 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 0.540192 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 1.352731 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 8288 78.01% 78.01% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 1088 10.24% 88.25% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 420 3.95% 92.21% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 282 2.65% 94.86% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 183 1.72% 96.58% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 168 1.58% 98.16% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 65 0.61% 98.78% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 37 0.35% 99.12% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 93 0.88% 100.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 10624 # Number of insts commited each cycle
-system.cpu.commit.count 5739 # Number of instructions committed
-system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.refs 2139 # Number of memory references committed
-system.cpu.commit.loads 1201 # Number of loads committed
-system.cpu.commit.membars 12 # Number of memory barriers committed
-system.cpu.commit.branches 945 # Number of branches committed
-system.cpu.commit.fp_insts 16 # Number of committed floating point instructions.
-system.cpu.commit.int_insts 4985 # Number of committed integer instructions.
-system.cpu.commit.function_calls 82 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 93 # number cycles where commit BW limit reached
-system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 21207 # The number of ROB reads
-system.cpu.rob.rob_writes 22566 # The number of ROB writes
-system.cpu.timesIdled 180 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 8494 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.committedInsts 5739 # Number of Instructions Simulated
-system.cpu.committedInsts_total 5739 # Number of Instructions Simulated
-system.cpu.cpi 3.485625 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 3.485625 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.286893 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.286893 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 37816 # number of integer regfile reads
-system.cpu.int_regfile_writes 7658 # number of integer regfile writes
-system.cpu.fp_regfile_reads 16 # number of floating regfile reads
-system.cpu.misc_regfile_reads 14993 # number of misc regfile reads
-system.cpu.misc_regfile_writes 24 # number of misc regfile writes
-system.cpu.icache.replacements 2 # number of replacements
-system.cpu.icache.tagsinuse 148.864335 # Cycle average of tags in use
-system.cpu.icache.total_refs 1560 # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs 297 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 5.252525 # Average number of references to valid blocks.
-system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0 148.864335 # Average occupied blocks per context
-system.cpu.icache.occ_percent::0 0.072688 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits 1560 # number of ReadReq hits
-system.cpu.icache.demand_hits 1560 # number of demand (read+write) hits
-system.cpu.icache.overall_hits 1560 # number of overall hits
-system.cpu.icache.ReadReq_misses 360 # number of ReadReq misses
-system.cpu.icache.demand_misses 360 # number of demand (read+write) misses
-system.cpu.icache.overall_misses 360 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency 12552000 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency 12552000 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency 12552000 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses 1920 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses 1920 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses 1920 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate 0.187500 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate 0.187500 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate 0.187500 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency 34866.666667 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency 34866.666667 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency 34866.666667 # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.icache.fast_writes 0 # number of fast writes performed
-system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits 63 # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits 63 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits 63 # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses 297 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses 297 # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses 297 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency 9945000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency 9945000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency 9945000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.154688 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate 0.154688 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate 0.154688 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 33484.848485 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 33484.848485 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 33484.848485 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.replacements 0 # number of replacements
-system.cpu.dcache.tagsinuse 89.089443 # Cycle average of tags in use
-system.cpu.dcache.total_refs 2331 # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs 154 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 15.136364 # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::0 89.089443 # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0 0.021750 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits 1702 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits 609 # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits 9 # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits 11 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits 2311 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits 2311 # number of overall hits
-system.cpu.dcache.ReadReq_misses 169 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses 304 # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses 2 # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses 473 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses 473 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency 5350500 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency 10725000 # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency 76500 # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency 16075500 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency 16075500 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses 1871 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses 913 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses 11 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses 11 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses 2784 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses 2784 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate 0.090326 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate 0.332968 # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate 0.181818 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate 0.169899 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate 0.169899 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency 31659.763314 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency 35279.605263 # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency 38250 # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency 33986.257928 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency 33986.257928 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks 0 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits 57 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits 262 # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits 2 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits 319 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits 319 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses 112 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses 42 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses 154 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses 154 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency 3230000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency 1505000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency 4735000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency 4735000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.059861 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.046002 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate 0.055316 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate 0.055316 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 28839.285714 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35833.333333 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 30746.753247 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 30746.753247 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.replacements 0 # number of replacements
-system.cpu.l2cache.tagsinuse 188.120549 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 42 # Total number of references to valid blocks.
-system.cpu.l2cache.sampled_refs 362 # Sample count of references to valid blocks.
-system.cpu.l2cache.avg_refs 0.116022 # Average number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::0 188.120549 # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0 0.005741 # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits 42 # number of ReadReq hits
-system.cpu.l2cache.demand_hits 42 # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits 42 # number of overall hits
-system.cpu.l2cache.ReadReq_misses 367 # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses 42 # number of ReadExReq misses
-system.cpu.l2cache.demand_misses 409 # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses 409 # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency 12613500 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency 1452000 # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency 14065500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency 14065500 # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses 409 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses 42 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses 451 # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses 451 # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate 0.897311 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate 0.906874 # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate 0.906874 # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency 34369.209809 # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency 34571.428571 # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency 34389.975550 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency 34389.975550 # average overall miss latency
-system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.l2cache.fast_writes 0 # number of fast writes performed
-system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.writebacks 0 # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_hits 5 # number of ReadReq MSHR hits
-system.cpu.l2cache.demand_mshr_hits 5 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits 5 # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses 362 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses 42 # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses 404 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses 404 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 11304000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 1319000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency 12623000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency 12623000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.885086 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate 0.895787 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate 0.895787 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31226.519337 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31404.761905 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 31245.049505 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 31245.049505 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-
----------- End Simulation Statistics ----------
diff --git a/tests/quick/00.hello/ref/arm/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/arm/linux/simple-atomic/config.ini
deleted file mode 100644
index 1ee45ad85..000000000
--- a/tests/quick/00.hello/ref/arm/linux/simple-atomic/config.ini
+++ /dev/null
@@ -1,102 +0,0 @@
-[root]
-type=Root
-children=system
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
-
-[system]
-type=System
-children=cpu membus physmem
-mem_mode=atomic
-memories=system.physmem
-num_work_ids=16
-physmem=system.physmem
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
-system_port=system.membus.port[0]
-
-[system.cpu]
-type=AtomicSimpleCPU
-children=dtb itb tracer workload
-checker=Null
-clock=500
-cpu_id=0
-defer_registration=false
-do_checkpoint_insts=true
-do_statistics_insts=true
-dtb=system.cpu.dtb
-function_trace=false
-function_trace_start=0
-itb=system.cpu.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-numThreads=1
-phase=0
-progress_interval=0
-simulate_data_stalls=false
-simulate_inst_stalls=false
-system=system
-tracer=system.cpu.tracer
-width=1
-workload=system.cpu.workload
-dcache_port=system.membus.port[3]
-icache_port=system.membus.port[2]
-
-[system.cpu.dtb]
-type=ArmTLB
-size=64
-
-[system.cpu.itb]
-type=ArmTLB
-size=64
-
-[system.cpu.tracer]
-type=ExeTracer
-
-[system.cpu.workload]
-type=LiveProcess
-cmd=hello
-cwd=
-egid=100
-env=
-errout=cerr
-euid=100
-executable=/dist/m5/regression/test-progs/hello/bin/arm/linux/hello
-gid=100
-input=cin
-max_stack_size=67108864
-output=cout
-pid=100
-ppid=99
-simpoint=0
-system=system
-uid=100
-
-[system.membus]
-type=Bus
-block_size=64
-bus_id=0
-clock=1000
-header_cycles=1
-use_default_range=false
-width=64
-port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
-
-[system.physmem]
-type=PhysicalMemory
-file=
-latency=30000
-latency_var=0
-null=false
-range=0:134217727
-zero=false
-port=system.membus.port[1]
-
diff --git a/tests/quick/00.hello/ref/arm/linux/simple-atomic/simerr b/tests/quick/00.hello/ref/arm/linux/simple-atomic/simerr
deleted file mode 100755
index e45cd058f..000000000
--- a/tests/quick/00.hello/ref/arm/linux/simple-atomic/simerr
+++ /dev/null
@@ -1,2 +0,0 @@
-warn: Sockets disabled, not accepting gdb connections
-hack: be nice to actually delete the event here
diff --git a/tests/quick/00.hello/ref/arm/linux/simple-atomic/simout b/tests/quick/00.hello/ref/arm/linux/simple-atomic/simout
deleted file mode 100755
index 13e73ddc3..000000000
--- a/tests/quick/00.hello/ref/arm/linux/simple-atomic/simout
+++ /dev/null
@@ -1,11 +0,0 @@
-gem5 Simulator System. http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-gem5 compiled Jan 23 2012 04:16:21
-gem5 started Jan 23 2012 04:24:50
-gem5 executing on zizzer
-command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/quick/00.hello/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/opt/quick/00.hello/arm/linux/simple-atomic
-Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0. Starting simulation...
-Hello world!
-Exiting @ tick 2875500 because target called exit()
diff --git a/tests/quick/00.hello/ref/arm/linux/simple-atomic/stats.txt b/tests/quick/00.hello/ref/arm/linux/simple-atomic/stats.txt
deleted file mode 100644
index 8e7751fe7..000000000
--- a/tests/quick/00.hello/ref/arm/linux/simple-atomic/stats.txt
+++ /dev/null
@@ -1,87 +0,0 @@
-
----------- Begin Simulation Statistics ----------
-sim_seconds 0.000003 # Number of seconds simulated
-sim_ticks 2875500 # Number of ticks simulated
-final_tick 2875500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 25921 # Simulator instruction rate (inst/s)
-host_tick_rate 12986430 # Simulator tick rate (ticks/s)
-host_mem_usage 208728 # Number of bytes of host memory used
-host_seconds 0.22 # Real time elapsed on the host
-sim_insts 5739 # Number of instructions simulated
-system.physmem.bytes_read 22944 # Number of bytes read from this memory
-system.physmem.bytes_inst_read 18452 # Number of instructions bytes read from this memory
-system.physmem.bytes_written 3648 # Number of bytes written to this memory
-system.physmem.num_reads 5771 # Number of read requests responded to by this memory
-system.physmem.num_writes 924 # Number of write requests responded to by this memory
-system.physmem.num_other 0 # Number of other requests responded to by this memory
-system.physmem.bw_read 7979134064 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read 6416970962 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write 1268648931 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total 9247782994 # Total bandwidth to/from this memory (bytes/s)
-system.cpu.dtb.inst_hits 0 # ITB inst hits
-system.cpu.dtb.inst_misses 0 # ITB inst misses
-system.cpu.dtb.read_hits 0 # DTB read hits
-system.cpu.dtb.read_misses 0 # DTB read misses
-system.cpu.dtb.write_hits 0 # DTB write hits
-system.cpu.dtb.write_misses 0 # DTB write misses
-system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses 0 # DTB read accesses
-system.cpu.dtb.write_accesses 0 # DTB write accesses
-system.cpu.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu.dtb.hits 0 # DTB hits
-system.cpu.dtb.misses 0 # DTB misses
-system.cpu.dtb.accesses 0 # DTB accesses
-system.cpu.itb.inst_hits 0 # ITB inst hits
-system.cpu.itb.inst_misses 0 # ITB inst misses
-system.cpu.itb.read_hits 0 # DTB read hits
-system.cpu.itb.read_misses 0 # DTB read misses
-system.cpu.itb.write_hits 0 # DTB write hits
-system.cpu.itb.write_misses 0 # DTB write misses
-system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.itb.read_accesses 0 # DTB read accesses
-system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.inst_accesses 0 # ITB inst accesses
-system.cpu.itb.hits 0 # DTB hits
-system.cpu.itb.misses 0 # DTB misses
-system.cpu.itb.accesses 0 # DTB accesses
-system.cpu.workload.num_syscalls 13 # Number of system calls
-system.cpu.numCycles 5752 # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.num_insts 5739 # Number of instructions executed
-system.cpu.num_int_alu_accesses 4985 # Number of integer alu accesses
-system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses
-system.cpu.num_func_calls 185 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 793 # number of instructions that are conditional controls
-system.cpu.num_int_insts 4985 # number of integer instructions
-system.cpu.num_fp_insts 16 # number of float instructions
-system.cpu.num_int_register_reads 25237 # number of times the integer registers were read
-system.cpu.num_int_register_writes 5345 # number of times the integer registers were written
-system.cpu.num_fp_register_reads 16 # number of times the floating registers were read
-system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
-system.cpu.num_mem_refs 2139 # number of memory refs
-system.cpu.num_load_insts 1201 # Number of load instructions
-system.cpu.num_store_insts 938 # Number of store instructions
-system.cpu.num_idle_cycles 0 # Number of idle cycles
-system.cpu.num_busy_cycles 5752 # Number of busy cycles
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.idle_fraction 0 # Percentage of idle cycles
-
----------- End Simulation Statistics ----------
diff --git a/tests/quick/00.hello/ref/arm/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/arm/linux/simple-timing/config.ini
deleted file mode 100644
index d881a3977..000000000
--- a/tests/quick/00.hello/ref/arm/linux/simple-timing/config.ini
+++ /dev/null
@@ -1,205 +0,0 @@
-[root]
-type=Root
-children=system
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
-
-[system]
-type=System
-children=cpu membus physmem
-mem_mode=atomic
-memories=system.physmem
-num_work_ids=16
-physmem=system.physmem
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
-system_port=system.membus.port[0]
-
-[system.cpu]
-type=TimingSimpleCPU
-children=dcache dtb icache itb l2cache toL2Bus tracer workload
-checker=Null
-clock=500
-cpu_id=0
-defer_registration=false
-do_checkpoint_insts=true
-do_statistics_insts=true
-dtb=system.cpu.dtb
-function_trace=false
-function_trace_start=0
-itb=system.cpu.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-numThreads=1
-phase=0
-progress_interval=0
-system=system
-tracer=system.cpu.tracer
-workload=system.cpu.workload
-dcache_port=system.cpu.dcache.cpu_side
-icache_port=system.cpu.icache.cpu_side
-
-[system.cpu.dcache]
-type=BaseCache
-addr_range=0:18446744073709551615
-assoc=2
-block_size=64
-forward_snoops=true
-hash_delay=1
-is_top_level=true
-latency=1000
-max_miss_count=0
-mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
-prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-repl=Null
-size=262144
-subblock_size=0
-tgts_per_mshr=5
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.dcache_port
-mem_side=system.cpu.toL2Bus.port[1]
-
-[system.cpu.dtb]
-type=ArmTLB
-size=64
-
-[system.cpu.icache]
-type=BaseCache
-addr_range=0:18446744073709551615
-assoc=2
-block_size=64
-forward_snoops=true
-hash_delay=1
-is_top_level=true
-latency=1000
-max_miss_count=0
-mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
-prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-repl=Null
-size=131072
-subblock_size=0
-tgts_per_mshr=5
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.icache_port
-mem_side=system.cpu.toL2Bus.port[0]
-
-[system.cpu.itb]
-type=ArmTLB
-size=64
-
-[system.cpu.l2cache]
-type=BaseCache
-addr_range=0:18446744073709551615
-assoc=2
-block_size=64
-forward_snoops=true
-hash_delay=1
-is_top_level=false
-latency=10000
-max_miss_count=0
-mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=100000
-prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-repl=Null
-size=2097152
-subblock_size=0
-tgts_per_mshr=5
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[2]
-
-[system.cpu.toL2Bus]
-type=Bus
-block_size=64
-bus_id=0
-clock=1000
-header_cycles=1
-use_default_range=false
-width=64
-port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
-
-[system.cpu.tracer]
-type=ExeTracer
-
-[system.cpu.workload]
-type=LiveProcess
-cmd=hello
-cwd=
-egid=100
-env=
-errout=cerr
-euid=100
-executable=/dist/m5/regression/test-progs/hello/bin/arm/linux/hello
-gid=100
-input=cin
-max_stack_size=67108864
-output=cout
-pid=100
-ppid=99
-simpoint=0
-system=system
-uid=100
-
-[system.membus]
-type=Bus
-block_size=64
-bus_id=0
-clock=1000
-header_cycles=1
-use_default_range=false
-width=64
-port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
-
-[system.physmem]
-type=PhysicalMemory
-file=
-latency=30000
-latency_var=0
-null=false
-range=0:134217727
-zero=false
-port=system.membus.port[1]
-
diff --git a/tests/quick/00.hello/ref/arm/linux/simple-timing/simerr b/tests/quick/00.hello/ref/arm/linux/simple-timing/simerr
deleted file mode 100755
index e45cd058f..000000000
--- a/tests/quick/00.hello/ref/arm/linux/simple-timing/simerr
+++ /dev/null
@@ -1,2 +0,0 @@
-warn: Sockets disabled, not accepting gdb connections
-hack: be nice to actually delete the event here
diff --git a/tests/quick/00.hello/ref/arm/linux/simple-timing/simout b/tests/quick/00.hello/ref/arm/linux/simple-timing/simout
deleted file mode 100755
index 25474862b..000000000
--- a/tests/quick/00.hello/ref/arm/linux/simple-timing/simout
+++ /dev/null
@@ -1,11 +0,0 @@
-gem5 Simulator System. http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-gem5 compiled Jan 23 2012 04:16:21
-gem5 started Jan 23 2012 04:24:50
-gem5 executing on zizzer
-command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/quick/00.hello/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/quick/00.hello/arm/linux/simple-timing
-Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0. Starting simulation...
-Hello world!
-Exiting @ tick 26361000 because target called exit()
diff --git a/tests/quick/00.hello/ref/arm/linux/simple-timing/stats.txt b/tests/quick/00.hello/ref/arm/linux/simple-timing/stats.txt
deleted file mode 100644
index 9108e20ee..000000000
--- a/tests/quick/00.hello/ref/arm/linux/simple-timing/stats.txt
+++ /dev/null
@@ -1,274 +0,0 @@
-
----------- Begin Simulation Statistics ----------
-sim_seconds 0.000026 # Number of seconds simulated
-sim_ticks 26361000 # Number of ticks simulated
-final_tick 26361000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 20483 # Simulator instruction rate (inst/s)
-host_tick_rate 95024596 # Simulator tick rate (ticks/s)
-host_mem_usage 217432 # Number of bytes of host memory used
-host_seconds 0.28 # Real time elapsed on the host
-sim_insts 5682 # Number of instructions simulated
-system.physmem.bytes_read 22400 # Number of bytes read from this memory
-system.physmem.bytes_inst_read 14400 # Number of instructions bytes read from this memory
-system.physmem.bytes_written 0 # Number of bytes written to this memory
-system.physmem.num_reads 350 # Number of read requests responded to by this memory
-system.physmem.num_writes 0 # Number of write requests responded to by this memory
-system.physmem.num_other 0 # Number of other requests responded to by this memory
-system.physmem.bw_read 849740146 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read 546261523 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total 849740146 # Total bandwidth to/from this memory (bytes/s)
-system.cpu.dtb.inst_hits 0 # ITB inst hits
-system.cpu.dtb.inst_misses 0 # ITB inst misses
-system.cpu.dtb.read_hits 0 # DTB read hits
-system.cpu.dtb.read_misses 0 # DTB read misses
-system.cpu.dtb.write_hits 0 # DTB write hits
-system.cpu.dtb.write_misses 0 # DTB write misses
-system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses 0 # DTB read accesses
-system.cpu.dtb.write_accesses 0 # DTB write accesses
-system.cpu.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu.dtb.hits 0 # DTB hits
-system.cpu.dtb.misses 0 # DTB misses
-system.cpu.dtb.accesses 0 # DTB accesses
-system.cpu.itb.inst_hits 0 # ITB inst hits
-system.cpu.itb.inst_misses 0 # ITB inst misses
-system.cpu.itb.read_hits 0 # DTB read hits
-system.cpu.itb.read_misses 0 # DTB read misses
-system.cpu.itb.write_hits 0 # DTB write hits
-system.cpu.itb.write_misses 0 # DTB write misses
-system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.itb.read_accesses 0 # DTB read accesses
-system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.inst_accesses 0 # ITB inst accesses
-system.cpu.itb.hits 0 # DTB hits
-system.cpu.itb.misses 0 # DTB misses
-system.cpu.itb.accesses 0 # DTB accesses
-system.cpu.workload.num_syscalls 13 # Number of system calls
-system.cpu.numCycles 52722 # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.num_insts 5682 # Number of instructions executed
-system.cpu.num_int_alu_accesses 4985 # Number of integer alu accesses
-system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses
-system.cpu.num_func_calls 185 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 793 # number of instructions that are conditional controls
-system.cpu.num_int_insts 4985 # number of integer instructions
-system.cpu.num_fp_insts 16 # number of float instructions
-system.cpu.num_int_register_reads 28701 # number of times the integer registers were read
-system.cpu.num_int_register_writes 5345 # number of times the integer registers were written
-system.cpu.num_fp_register_reads 16 # number of times the floating registers were read
-system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
-system.cpu.num_mem_refs 2139 # number of memory refs
-system.cpu.num_load_insts 1201 # Number of load instructions
-system.cpu.num_store_insts 938 # Number of store instructions
-system.cpu.num_idle_cycles 0 # Number of idle cycles
-system.cpu.num_busy_cycles 52722 # Number of busy cycles
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.icache.replacements 1 # number of replacements
-system.cpu.icache.tagsinuse 114.525744 # Cycle average of tags in use
-system.cpu.icache.total_refs 4373 # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs 241 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 18.145228 # Average number of references to valid blocks.
-system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0 114.525744 # Average occupied blocks per context
-system.cpu.icache.occ_percent::0 0.055921 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits 4373 # number of ReadReq hits
-system.cpu.icache.demand_hits 4373 # number of demand (read+write) hits
-system.cpu.icache.overall_hits 4373 # number of overall hits
-system.cpu.icache.ReadReq_misses 241 # number of ReadReq misses
-system.cpu.icache.demand_misses 241 # number of demand (read+write) misses
-system.cpu.icache.overall_misses 241 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency 12824000 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency 12824000 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency 12824000 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses 4614 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses 4614 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses 4614 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate 0.052232 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate 0.052232 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate 0.052232 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency 53211.618257 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency 53211.618257 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency 53211.618257 # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.icache.fast_writes 0 # number of fast writes performed
-system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses 241 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses 241 # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses 241 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency 12101000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency 12101000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency 12101000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.052232 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate 0.052232 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate 0.052232 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 50211.618257 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 50211.618257 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 50211.618257 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.replacements 0 # number of replacements
-system.cpu.dcache.tagsinuse 82.937979 # Cycle average of tags in use
-system.cpu.dcache.total_refs 1941 # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs 141 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 13.765957 # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::0 82.937979 # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0 0.020249 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits 1049 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits 870 # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits 11 # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits 11 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits 1919 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits 1919 # number of overall hits
-system.cpu.dcache.ReadReq_misses 98 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses 43 # number of WriteReq misses
-system.cpu.dcache.demand_misses 141 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses 141 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency 4816000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency 2408000 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency 7224000 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency 7224000 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses 1147 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses 913 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses 11 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses 11 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses 2060 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses 2060 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate 0.085440 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate 0.047097 # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate 0.068447 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate 0.068447 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency 49142.857143 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency 51234.042553 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency 51234.042553 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks 0 # number of writebacks
-system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses 98 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses 43 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses 141 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses 141 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency 4522000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency 2279000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency 6801000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency 6801000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.085440 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.047097 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate 0.068447 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate 0.068447 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 46142.857143 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 48234.042553 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 48234.042553 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.replacements 0 # number of replacements
-system.cpu.l2cache.tagsinuse 153.954484 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 32 # Total number of references to valid blocks.
-system.cpu.l2cache.sampled_refs 307 # Sample count of references to valid blocks.
-system.cpu.l2cache.avg_refs 0.104235 # Average number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::0 153.954484 # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0 0.004698 # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits 32 # number of ReadReq hits
-system.cpu.l2cache.demand_hits 32 # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits 32 # number of overall hits
-system.cpu.l2cache.ReadReq_misses 307 # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses 43 # number of ReadExReq misses
-system.cpu.l2cache.demand_misses 350 # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses 350 # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency 15964000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency 2236000 # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency 18200000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency 18200000 # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses 339 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses 43 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses 382 # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses 382 # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate 0.905605 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate 0.916230 # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate 0.916230 # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
-system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.l2cache.fast_writes 0 # number of fast writes performed
-system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.writebacks 0 # number of writebacks
-system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses 307 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses 43 # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses 350 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses 350 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 12280000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 1720000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency 14000000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency 14000000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.905605 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate 0.916230 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate 0.916230 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-
----------- End Simulation Statistics ----------
generated by cgit v1.2.3 (git 2.25.1) at 2024-10-31 21:11:46 +0000