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authorAli Saidi <Ali.Saidi@ARM.com>2012-01-25 17:19:50 +0000
committerAli Saidi <Ali.Saidi@ARM.com>2012-01-25 17:19:50 +0000
commita17dbdf8834b84f05a8f5154a74ac819fe8adc7c (patch)
tree8761136c790b84e20d6df2e84207eca3c553984b /tests/quick/00.hello/ref/arm
parentbd55c9e2af7fd6c06af48a020c29cb33ba1ca3fc (diff)
downloadgem5-a17dbdf8834b84f05a8f5154a74ac819fe8adc7c.tar.xz
stats: Update stats for final tick and memory bandwidth patches
Diffstat (limited to 'tests/quick/00.hello/ref/arm')
-rw-r--r--tests/quick/00.hello/ref/arm/linux/o3-timing/config.ini10
-rwxr-xr-xtests/quick/00.hello/ref/arm/linux/o3-timing/simout6
-rw-r--r--tests/quick/00.hello/ref/arm/linux/o3-timing/stats.txt18
-rw-r--r--tests/quick/00.hello/ref/arm/linux/simple-atomic/config.ini11
-rwxr-xr-xtests/quick/00.hello/ref/arm/linux/simple-atomic/simerr1
-rwxr-xr-xtests/quick/00.hello/ref/arm/linux/simple-atomic/simout16
-rw-r--r--tests/quick/00.hello/ref/arm/linux/simple-atomic/stats.txt109
-rw-r--r--tests/quick/00.hello/ref/arm/linux/simple-timing/config.ini9
-rwxr-xr-xtests/quick/00.hello/ref/arm/linux/simple-timing/simerr1
-rwxr-xr-xtests/quick/00.hello/ref/arm/linux/simple-timing/simout16
-rw-r--r--tests/quick/00.hello/ref/arm/linux/simple-timing/stats.txt466
11 files changed, 346 insertions, 317 deletions
diff --git a/tests/quick/00.hello/ref/arm/linux/o3-timing/config.ini b/tests/quick/00.hello/ref/arm/linux/o3-timing/config.ini
index 35f7f2ba7..21dc694d7 100644
--- a/tests/quick/00.hello/ref/arm/linux/o3-timing/config.ini
+++ b/tests/quick/00.hello/ref/arm/linux/o3-timing/config.ini
@@ -10,6 +10,7 @@ type=System
children=cpu membus physmem
mem_mode=atomic
memories=system.physmem
+num_work_ids=16
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@@ -18,6 +19,7 @@ work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
+system_port=system.membus.port[0]
[system.cpu]
type=DerivO3CPU
@@ -477,7 +479,7 @@ trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
+mem_side=system.membus.port[2]
[system.cpu.toL2Bus]
type=Bus
@@ -500,7 +502,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=/projects/pd/randd/dist/test-progs/hello/bin/arm/linux/hello
+executable=/dist/m5/regression/test-progs/hello/bin/arm/linux/hello
gid=100
input=cin
max_stack_size=67108864
@@ -519,7 +521,7 @@ clock=1000
header_cycles=1
use_default_range=false
width=64
-port=system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
[system.physmem]
type=PhysicalMemory
@@ -529,5 +531,5 @@ latency_var=0
null=false
range=0:134217727
zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
diff --git a/tests/quick/00.hello/ref/arm/linux/o3-timing/simout b/tests/quick/00.hello/ref/arm/linux/o3-timing/simout
index 2cb4f1a9c..f402d7e9e 100755
--- a/tests/quick/00.hello/ref/arm/linux/o3-timing/simout
+++ b/tests/quick/00.hello/ref/arm/linux/o3-timing/simout
@@ -1,9 +1,9 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 21 2011 16:28:02
-gem5 started Nov 22 2011 19:01:51
-gem5 executing on u200540-lin
+gem5 compiled Jan 23 2012 04:16:21
+gem5 started Jan 23 2012 04:24:50
+gem5 executing on zizzer
command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/quick/00.hello/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/quick/00.hello/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/quick/00.hello/ref/arm/linux/o3-timing/stats.txt b/tests/quick/00.hello/ref/arm/linux/o3-timing/stats.txt
index 3aaa40ec4..19b87b225 100644
--- a/tests/quick/00.hello/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/quick/00.hello/ref/arm/linux/o3-timing/stats.txt
@@ -2,12 +2,22 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000010 # Number of seconds simulated
sim_ticks 10001500 # Number of ticks simulated
+final_tick 10001500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 48143 # Simulator instruction rate (inst/s)
-host_tick_rate 83889434 # Simulator tick rate (ticks/s)
-host_mem_usage 212568 # Number of bytes of host memory used
-host_seconds 0.12 # Real time elapsed on the host
+host_inst_rate 15723 # Simulator instruction rate (inst/s)
+host_tick_rate 27400304 # Simulator tick rate (ticks/s)
+host_mem_usage 218472 # Number of bytes of host memory used
+host_seconds 0.37 # Real time elapsed on the host
sim_insts 5739 # Number of instructions simulated
+system.physmem.bytes_read 25856 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 17856 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 0 # Number of bytes written to this memory
+system.physmem.num_reads 404 # Number of read requests responded to by this memory
+system.physmem.num_writes 0 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 2585212218 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 1785332200 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total 2585212218 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
diff --git a/tests/quick/00.hello/ref/arm/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/arm/linux/simple-atomic/config.ini
index 327106c53..1ee45ad85 100644
--- a/tests/quick/00.hello/ref/arm/linux/simple-atomic/config.ini
+++ b/tests/quick/00.hello/ref/arm/linux/simple-atomic/config.ini
@@ -9,6 +9,8 @@ time_sync_spin_threshold=100000000
type=System
children=cpu membus physmem
mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@@ -17,6 +19,7 @@ work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
+system_port=system.membus.port[0]
[system.cpu]
type=AtomicSimpleCPU
@@ -44,8 +47,8 @@ system=system
tracer=system.cpu.tracer
width=1
workload=system.cpu.workload
-dcache_port=system.membus.port[2]
-icache_port=system.membus.port[1]
+dcache_port=system.membus.port[3]
+icache_port=system.membus.port[2]
[system.cpu.dtb]
type=ArmTLB
@@ -85,7 +88,7 @@ clock=1000
header_cycles=1
use_default_range=false
width=64
-port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
[system.physmem]
type=PhysicalMemory
@@ -95,5 +98,5 @@ latency_var=0
null=false
range=0:134217727
zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
diff --git a/tests/quick/00.hello/ref/arm/linux/simple-atomic/simerr b/tests/quick/00.hello/ref/arm/linux/simple-atomic/simerr
index eabe42249..e45cd058f 100755
--- a/tests/quick/00.hello/ref/arm/linux/simple-atomic/simerr
+++ b/tests/quick/00.hello/ref/arm/linux/simple-atomic/simerr
@@ -1,3 +1,2 @@
warn: Sockets disabled, not accepting gdb connections
-For more information see: http://www.m5sim.org/warn/d946bea6
hack: be nice to actually delete the event here
diff --git a/tests/quick/00.hello/ref/arm/linux/simple-atomic/simout b/tests/quick/00.hello/ref/arm/linux/simple-atomic/simout
index 974d1c8f4..13e73ddc3 100755
--- a/tests/quick/00.hello/ref/arm/linux/simple-atomic/simout
+++ b/tests/quick/00.hello/ref/arm/linux/simple-atomic/simout
@@ -1,14 +1,10 @@
-M5 Simulator System
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Apr 19 2011 12:47:10
-M5 started Apr 19 2011 13:32:52
-M5 executing on maize
-command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/quick/00.hello/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/fast/quick/00.hello/arm/linux/simple-atomic
+gem5 compiled Jan 23 2012 04:16:21
+gem5 started Jan 23 2012 04:24:50
+gem5 executing on zizzer
+command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/quick/00.hello/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/opt/quick/00.hello/arm/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
Hello world!
diff --git a/tests/quick/00.hello/ref/arm/linux/simple-atomic/stats.txt b/tests/quick/00.hello/ref/arm/linux/simple-atomic/stats.txt
index 1364619fb..8e7751fe7 100644
--- a/tests/quick/00.hello/ref/arm/linux/simple-atomic/stats.txt
+++ b/tests/quick/00.hello/ref/arm/linux/simple-atomic/stats.txt
@@ -1,76 +1,87 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 931505 # Simulator instruction rate (inst/s)
-host_mem_usage 249344 # Number of bytes of host memory used
-host_seconds 0.01 # Real time elapsed on the host
-host_tick_rate 451909477 # Simulator tick rate (ticks/s)
-sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 5739 # Number of instructions simulated
sim_seconds 0.000003 # Number of seconds simulated
sim_ticks 2875500 # Number of ticks simulated
-system.cpu.dtb.accesses 0 # DTB accesses
-system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.hits 0 # DTB hits
-system.cpu.dtb.inst_accesses 0 # ITB inst accesses
+final_tick 2875500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq 1000000000000 # Frequency of simulated ticks
+host_inst_rate 25921 # Simulator instruction rate (inst/s)
+host_tick_rate 12986430 # Simulator tick rate (ticks/s)
+host_mem_usage 208728 # Number of bytes of host memory used
+host_seconds 0.22 # Real time elapsed on the host
+sim_insts 5739 # Number of instructions simulated
+system.physmem.bytes_read 22944 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 18452 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 3648 # Number of bytes written to this memory
+system.physmem.num_reads 5771 # Number of read requests responded to by this memory
+system.physmem.num_writes 924 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 7979134064 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 6416970962 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write 1268648931 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total 9247782994 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
-system.cpu.dtb.misses 0 # DTB misses
-system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
-system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
-system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.itb.accesses 0 # DTB accesses
-system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.itb.hits 0 # DTB hits
-system.cpu.itb.inst_accesses 0 # ITB inst accesses
+system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses 0 # DTB read accesses
+system.cpu.dtb.write_accesses 0 # DTB write accesses
+system.cpu.dtb.inst_accesses 0 # ITB inst accesses
+system.cpu.dtb.hits 0 # DTB hits
+system.cpu.dtb.misses 0 # DTB misses
+system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
-system.cpu.itb.misses 0 # DTB misses
-system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
-system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.itb.read_accesses 0 # DTB read accesses
+system.cpu.itb.write_accesses 0 # DTB write accesses
+system.cpu.itb.inst_accesses 0 # ITB inst accesses
+system.cpu.itb.hits 0 # DTB hits
+system.cpu.itb.misses 0 # DTB misses
+system.cpu.itb.accesses 0 # DTB accesses
+system.cpu.workload.num_syscalls 13 # Number of system calls
system.cpu.numCycles 5752 # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.num_busy_cycles 5752 # Number of busy cycles
-system.cpu.num_conditional_control_insts 793 # number of instructions that are conditional controls
-system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses
-system.cpu.num_fp_insts 16 # number of float instructions
-system.cpu.num_fp_register_reads 16 # number of times the floating registers were read
-system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
-system.cpu.num_func_calls 185 # number of times a function call or return occured
-system.cpu.num_idle_cycles 0 # Number of idle cycles
+system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.num_insts 5739 # Number of instructions executed
system.cpu.num_int_alu_accesses 4985 # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses
+system.cpu.num_func_calls 185 # number of times a function call or return occured
+system.cpu.num_conditional_control_insts 793 # number of instructions that are conditional controls
system.cpu.num_int_insts 4985 # number of integer instructions
+system.cpu.num_fp_insts 16 # number of float instructions
system.cpu.num_int_register_reads 25237 # number of times the integer registers were read
system.cpu.num_int_register_writes 5345 # number of times the integer registers were written
-system.cpu.num_load_insts 1201 # Number of load instructions
+system.cpu.num_fp_register_reads 16 # number of times the floating registers were read
+system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu.num_mem_refs 2139 # number of memory refs
+system.cpu.num_load_insts 1201 # Number of load instructions
system.cpu.num_store_insts 938 # Number of store instructions
-system.cpu.workload.num_syscalls 13 # Number of system calls
+system.cpu.num_idle_cycles 0 # Number of idle cycles
+system.cpu.num_busy_cycles 5752 # Number of busy cycles
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.idle_fraction 0 # Percentage of idle cycles
---------- End Simulation Statistics ----------
diff --git a/tests/quick/00.hello/ref/arm/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/arm/linux/simple-timing/config.ini
index 4214b8570..d881a3977 100644
--- a/tests/quick/00.hello/ref/arm/linux/simple-timing/config.ini
+++ b/tests/quick/00.hello/ref/arm/linux/simple-timing/config.ini
@@ -9,6 +9,8 @@ time_sync_spin_threshold=100000000
type=System
children=cpu membus physmem
mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@@ -17,6 +19,7 @@ work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
+system_port=system.membus.port[0]
[system.cpu]
type=TimingSimpleCPU
@@ -146,7 +149,7 @@ trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
+mem_side=system.membus.port[2]
[system.cpu.toL2Bus]
type=Bus
@@ -188,7 +191,7 @@ clock=1000
header_cycles=1
use_default_range=false
width=64
-port=system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
[system.physmem]
type=PhysicalMemory
@@ -198,5 +201,5 @@ latency_var=0
null=false
range=0:134217727
zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
diff --git a/tests/quick/00.hello/ref/arm/linux/simple-timing/simerr b/tests/quick/00.hello/ref/arm/linux/simple-timing/simerr
index eabe42249..e45cd058f 100755
--- a/tests/quick/00.hello/ref/arm/linux/simple-timing/simerr
+++ b/tests/quick/00.hello/ref/arm/linux/simple-timing/simerr
@@ -1,3 +1,2 @@
warn: Sockets disabled, not accepting gdb connections
-For more information see: http://www.m5sim.org/warn/d946bea6
hack: be nice to actually delete the event here
diff --git a/tests/quick/00.hello/ref/arm/linux/simple-timing/simout b/tests/quick/00.hello/ref/arm/linux/simple-timing/simout
index e4f30d324..25474862b 100755
--- a/tests/quick/00.hello/ref/arm/linux/simple-timing/simout
+++ b/tests/quick/00.hello/ref/arm/linux/simple-timing/simout
@@ -1,14 +1,10 @@
-M5 Simulator System
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Apr 19 2011 12:47:10
-M5 started Apr 19 2011 13:33:02
-M5 executing on maize
-command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/quick/00.hello/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/fast/quick/00.hello/arm/linux/simple-timing
+gem5 compiled Jan 23 2012 04:16:21
+gem5 started Jan 23 2012 04:24:50
+gem5 executing on zizzer
+command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/quick/00.hello/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/quick/00.hello/arm/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
Hello world!
diff --git a/tests/quick/00.hello/ref/arm/linux/simple-timing/stats.txt b/tests/quick/00.hello/ref/arm/linux/simple-timing/stats.txt
index e792babc2..9108e20ee 100644
--- a/tests/quick/00.hello/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/quick/00.hello/ref/arm/linux/simple-timing/stats.txt
@@ -1,264 +1,274 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 534023 # Simulator instruction rate (inst/s)
-host_mem_usage 257088 # Number of bytes of host memory used
-host_seconds 0.01 # Real time elapsed on the host
-host_tick_rate 2428466145 # Simulator tick rate (ticks/s)
-sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 5682 # Number of instructions simulated
sim_seconds 0.000026 # Number of seconds simulated
sim_ticks 26361000 # Number of ticks simulated
-system.cpu.dcache.LoadLockedReq_accesses 11 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_hits 11 # number of LoadLockedReq hits
-system.cpu.dcache.ReadReq_accesses 1147 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 49142.857143 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 46142.857143 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 1049 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 4816000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate 0.085440 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 98 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency 4522000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.085440 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 98 # number of ReadReq MSHR misses
-system.cpu.dcache.StoreCondReq_accesses 11 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_hits 11 # number of StoreCondReq hits
-system.cpu.dcache.WriteReq_accesses 913 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 870 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 2408000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.047097 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 43 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency 2279000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.047097 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 43 # number of WriteReq MSHR misses
-system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 13.765957 # Average number of references to valid blocks.
-system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses 2060 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 51234.042553 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 48234.042553 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 1919 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 7224000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.068447 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 141 # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 6801000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.068447 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 141 # number of demand (read+write) MSHR misses
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.occ_blocks::0 82.937979 # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0 0.020249 # Average percentage of cache occupancy
-system.cpu.dcache.overall_accesses 2060 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 51234.042553 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 48234.042553 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 1919 # number of overall hits
-system.cpu.dcache.overall_miss_latency 7224000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.068447 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 141 # number of overall misses
-system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 6801000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.068447 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 141 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.dcache.replacements 0 # number of replacements
-system.cpu.dcache.sampled_refs 141 # Sample count of references to valid blocks.
-system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 82.937979 # Cycle average of tags in use
-system.cpu.dcache.total_refs 1941 # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 0 # number of writebacks
-system.cpu.dtb.accesses 0 # DTB accesses
-system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.hits 0 # DTB hits
-system.cpu.dtb.inst_accesses 0 # ITB inst accesses
+final_tick 26361000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq 1000000000000 # Frequency of simulated ticks
+host_inst_rate 20483 # Simulator instruction rate (inst/s)
+host_tick_rate 95024596 # Simulator tick rate (ticks/s)
+host_mem_usage 217432 # Number of bytes of host memory used
+host_seconds 0.28 # Real time elapsed on the host
+sim_insts 5682 # Number of instructions simulated
+system.physmem.bytes_read 22400 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 14400 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 0 # Number of bytes written to this memory
+system.physmem.num_reads 350 # Number of read requests responded to by this memory
+system.physmem.num_writes 0 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 849740146 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 546261523 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total 849740146 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
-system.cpu.dtb.misses 0 # DTB misses
-system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
-system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
-system.cpu.icache.ReadReq_accesses 4614 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 53211.618257 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 50211.618257 # average ReadReq mshr miss latency
+system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
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+system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses 0 # DTB read accesses
+system.cpu.dtb.write_accesses 0 # DTB write accesses
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+system.cpu.dtb.misses 0 # DTB misses
+system.cpu.dtb.accesses 0 # DTB accesses
+system.cpu.itb.inst_hits 0 # ITB inst hits
+system.cpu.itb.inst_misses 0 # ITB inst misses
+system.cpu.itb.read_hits 0 # DTB read hits
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+system.cpu.itb.write_misses 0 # DTB write misses
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+system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.itb.read_accesses 0 # DTB read accesses
+system.cpu.itb.write_accesses 0 # DTB write accesses
+system.cpu.itb.inst_accesses 0 # ITB inst accesses
+system.cpu.itb.hits 0 # DTB hits
+system.cpu.itb.misses 0 # DTB misses
+system.cpu.itb.accesses 0 # DTB accesses
+system.cpu.workload.num_syscalls 13 # Number of system calls
+system.cpu.numCycles 52722 # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu.num_insts 5682 # Number of instructions executed
+system.cpu.num_int_alu_accesses 4985 # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses
+system.cpu.num_func_calls 185 # number of times a function call or return occured
+system.cpu.num_conditional_control_insts 793 # number of instructions that are conditional controls
+system.cpu.num_int_insts 4985 # number of integer instructions
+system.cpu.num_fp_insts 16 # number of float instructions
+system.cpu.num_int_register_reads 28701 # number of times the integer registers were read
+system.cpu.num_int_register_writes 5345 # number of times the integer registers were written
+system.cpu.num_fp_register_reads 16 # number of times the floating registers were read
+system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
+system.cpu.num_mem_refs 2139 # number of memory refs
+system.cpu.num_load_insts 1201 # Number of load instructions
+system.cpu.num_store_insts 938 # Number of store instructions
+system.cpu.num_idle_cycles 0 # Number of idle cycles
+system.cpu.num_busy_cycles 52722 # Number of busy cycles
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.idle_fraction 0 # Percentage of idle cycles
+system.cpu.icache.replacements 1 # number of replacements
+system.cpu.icache.tagsinuse 114.525744 # Cycle average of tags in use
+system.cpu.icache.total_refs 4373 # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs 241 # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs 18.145228 # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::0 114.525744 # Average occupied blocks per context
+system.cpu.icache.occ_percent::0 0.055921 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits 4373 # number of ReadReq hits
+system.cpu.icache.demand_hits 4373 # number of demand (read+write) hits
+system.cpu.icache.overall_hits 4373 # number of overall hits
+system.cpu.icache.ReadReq_misses 241 # number of ReadReq misses
+system.cpu.icache.demand_misses 241 # number of demand (read+write) misses
+system.cpu.icache.overall_misses 241 # number of overall misses
system.cpu.icache.ReadReq_miss_latency 12824000 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency 12824000 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency 12824000 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses 4614 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses 4614 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses 4614 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate 0.052232 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses 241 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_miss_latency 12101000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.052232 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses 241 # number of ReadReq MSHR misses
-system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 18.145228 # Average number of references to valid blocks.
-system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.icache.demand_miss_rate 0.052232 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate 0.052232 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency 53211.618257 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency 53211.618257 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency 53211.618257 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses 4614 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 53211.618257 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 50211.618257 # average overall mshr miss latency
-system.cpu.icache.demand_hits 4373 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 12824000 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate 0.052232 # miss rate for demand accesses
-system.cpu.icache.demand_misses 241 # number of demand (read+write) misses
+system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses 241 # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses 241 # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses 241 # number of overall MSHR misses
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+system.cpu.icache.ReadReq_mshr_miss_latency 12101000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency 12101000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency 12101000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.052232 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate 0.052232 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses 241 # number of demand (read+write) MSHR misses
-system.cpu.icache.fast_writes 0 # number of fast writes performed
-system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.occ_blocks::0 114.525744 # Average occupied blocks per context
-system.cpu.icache.occ_percent::0 0.055921 # Average percentage of cache occupancy
-system.cpu.icache.overall_accesses 4614 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 53211.618257 # average overall miss latency
+system.cpu.icache.overall_mshr_miss_rate 0.052232 # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 50211.618257 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 50211.618257 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 50211.618257 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 4373 # number of overall hits
-system.cpu.icache.overall_miss_latency 12824000 # number of overall miss cycles
-system.cpu.icache.overall_miss_rate 0.052232 # miss rate for overall accesses
-system.cpu.icache.overall_misses 241 # number of overall misses
-system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 12101000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate 0.052232 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses 241 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.icache.replacements 1 # number of replacements
-system.cpu.icache.sampled_refs 241 # Sample count of references to valid blocks.
+system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 114.525744 # Cycle average of tags in use
-system.cpu.icache.total_refs 4373 # Total number of references to valid blocks.
-system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.itb.accesses 0 # DTB accesses
-system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.itb.hits 0 # DTB hits
-system.cpu.itb.inst_accesses 0 # ITB inst accesses
-system.cpu.itb.inst_hits 0 # ITB inst hits
-system.cpu.itb.inst_misses 0 # ITB inst misses
-system.cpu.itb.misses 0 # DTB misses
-system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.itb.read_accesses 0 # DTB read accesses
-system.cpu.itb.read_hits 0 # DTB read hits
-system.cpu.itb.read_misses 0 # DTB read misses
-system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.write_hits 0 # DTB write hits
-system.cpu.itb.write_misses 0 # DTB write misses
-system.cpu.l2cache.ReadExReq_accesses 43 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_miss_latency 2236000 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_misses 43 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 1720000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses 43 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadReq_accesses 339 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
+system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.replacements 0 # number of replacements
+system.cpu.dcache.tagsinuse 82.937979 # Cycle average of tags in use
+system.cpu.dcache.total_refs 1941 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 141 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 13.765957 # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::0 82.937979 # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0 0.020249 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits 1049 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits 870 # number of WriteReq hits
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+system.cpu.dcache.StoreCondReq_hits 11 # number of StoreCondReq hits
+system.cpu.dcache.demand_hits 1919 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits 1919 # number of overall hits
+system.cpu.dcache.ReadReq_misses 98 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses 43 # number of WriteReq misses
+system.cpu.dcache.demand_misses 141 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses 141 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency 4816000 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency 2408000 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency 7224000 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency 7224000 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses 1147 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses 913 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses 11 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses 11 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses 2060 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses 2060 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate 0.085440 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate 0.047097 # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate 0.068447 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate 0.068447 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency 49142.857143 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency 51234.042553 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency 51234.042553 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.writebacks 0 # number of writebacks
+system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses 98 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses 43 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses 141 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses 141 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.dcache.ReadReq_mshr_miss_latency 4522000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency 2279000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency 6801000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency 6801000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.085440 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.047097 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate 0.068447 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate 0.068447 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 46142.857143 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 48234.042553 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 48234.042553 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
+system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.l2cache.replacements 0 # number of replacements
+system.cpu.l2cache.tagsinuse 153.954484 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 32 # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs 307 # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs 0.104235 # Average number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::0 153.954484 # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0 0.004698 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits 32 # number of ReadReq hits
+system.cpu.l2cache.demand_hits 32 # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits 32 # number of overall hits
+system.cpu.l2cache.ReadReq_misses 307 # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses 43 # number of ReadExReq misses
+system.cpu.l2cache.demand_misses 350 # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses 350 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency 15964000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency 2236000 # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency 18200000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency 18200000 # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses 339 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses 43 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses 382 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses 382 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate 0.905605 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses 307 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 12280000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.905605 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses 307 # number of ReadReq MSHR misses
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 0.104235 # Average number of references to valid blocks.
-system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate 0.916230 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate 0.916230 # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.demand_accesses 382 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
-system.cpu.l2cache.demand_hits 32 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 18200000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate 0.916230 # miss rate for demand accesses
-system.cpu.l2cache.demand_misses 350 # number of demand (read+write) misses
+system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses 307 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses 43 # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses 350 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses 350 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 12280000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency 1720000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency 14000000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency 14000000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.905605 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate 0.916230 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses 350 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.fast_writes 0 # number of fast writes performed
-system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.occ_blocks::0 153.954484 # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0 0.004698 # Average percentage of cache occupancy
-system.cpu.l2cache.overall_accesses 382 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
+system.cpu.l2cache.overall_mshr_miss_rate 0.916230 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits 32 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 18200000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 0.916230 # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 350 # number of overall misses
-system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 14000000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 0.916230 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 350 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.replacements 0 # number of replacements
-system.cpu.l2cache.sampled_refs 307 # Sample count of references to valid blocks.
+system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 153.954484 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 32 # Total number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks 0 # number of writebacks
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 52722 # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.num_busy_cycles 52722 # Number of busy cycles
-system.cpu.num_conditional_control_insts 793 # number of instructions that are conditional controls
-system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses
-system.cpu.num_fp_insts 16 # number of float instructions
-system.cpu.num_fp_register_reads 16 # number of times the floating registers were read
-system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
-system.cpu.num_func_calls 185 # number of times a function call or return occured
-system.cpu.num_idle_cycles 0 # Number of idle cycles
-system.cpu.num_insts 5682 # Number of instructions executed
-system.cpu.num_int_alu_accesses 4985 # Number of integer alu accesses
-system.cpu.num_int_insts 4985 # number of integer instructions
-system.cpu.num_int_register_reads 28701 # number of times the integer registers were read
-system.cpu.num_int_register_writes 5345 # number of times the integer registers were written
-system.cpu.num_load_insts 1201 # Number of load instructions
-system.cpu.num_mem_refs 2139 # number of memory refs
-system.cpu.num_store_insts 938 # Number of store instructions
-system.cpu.workload.num_syscalls 13 # Number of system calls
+system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------