stats: update reference outputs now that compatibility is gone

Because of the initialization bug, it wasn't consistent anyway.

1 files changed, 71 insertions, 75 deletions

diff --git a/tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt b/tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt
index abebc01ef..5137cef3d 100644
--- a/tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt
+++ b/tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                  62820                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 202152                       # Number of bytes of host memory used
-host_seconds                                     0.08                       # Real time elapsed on the host
-host_tick_rate                              173066613                       # Simulator tick rate (ticks/s)
+host_inst_rate                                  69701                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 203728                       # Number of bytes of host memory used
+host_seconds                                     0.07                       # Real time elapsed on the host
+host_tick_rate                              191895105                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                        5024                       # Number of instructions simulated
 sim_seconds                                  0.000014                       # Number of seconds simulated
@@ -71,13 +71,13 @@ system.cpu.dcache.WriteReq_mshr_hits              226                       # nu
 system.cpu.dcache.WriteReq_mshr_miss_latency      2310000                       # number of WriteReq MSHR miss cycles
 system.cpu.dcache.WriteReq_mshr_miss_rate     0.069264                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_misses             64                       # number of WriteReq MSHR misses
-system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_refs                  20.970370                       # Average number of references to valid blocks.
-system.cpu.dcache.blocked_no_mshrs                  0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_no_targets                0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles_no_mshrs            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.demand_accesses                3210                       # number of demand (read+write) accesses
 system.cpu.dcache.demand_avg_miss_latency 29612.709832                       # average overall miss latency
@@ -96,7 +96,7 @@ system.cpu.dcache.no_allocate_misses                0                       # Nu
 system.cpu.dcache.overall_accesses               3210                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_avg_miss_latency 29612.709832                       # average overall miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency        36060                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
 system.cpu.dcache.overall_hits                   2793                       # number of overall hits
 system.cpu.dcache.overall_miss_latency       12348500                       # number of overall miss cycles
 system.cpu.dcache.overall_miss_rate          0.129907                       # miss rate for overall accesses
@@ -169,13 +169,13 @@ system.cpu.icache.ReadReq_mshr_hits               101                       # nu
 system.cpu.icache.ReadReq_mshr_miss_latency     11522000                       # number of ReadReq MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate     0.152636                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_misses             330                       # number of ReadReq MSHR misses
-system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.icache.avg_refs                   5.245455                       # Average number of references to valid blocks.
-system.cpu.icache.blocked_no_mshrs                  0                       # number of cycles access was blocked
-system.cpu.icache.blocked_no_targets                0                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles_no_mshrs            0                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.demand_accesses                2162                       # number of demand (read+write) accesses
 system.cpu.icache.demand_avg_miss_latency        35500                       # average overall miss latency
@@ -194,7 +194,7 @@ system.cpu.icache.no_allocate_misses                0                       # Nu
 system.cpu.icache.overall_accesses               2162                       # number of overall (read+write) accesses
 system.cpu.icache.overall_avg_miss_latency        35500                       # average overall miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency 34915.151515                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
 system.cpu.icache.overall_hits                   1731                       # number of overall hits
 system.cpu.icache.overall_miss_latency       15300500                       # number of overall miss cycles
 system.cpu.icache.overall_miss_rate          0.199352                       # miss rate for overall accesses
@@ -257,58 +257,54 @@ system.cpu.iew.predictedNotTakenIncorrect          276                       # N
 system.cpu.iew.predictedTakenIncorrect            385                       # Number of branches that were predicted taken incorrectly
 system.cpu.ipc                               0.180954                       # IPC: Instructions Per Cycle
 system.cpu.ipc_total                         0.180954                       # IPC: Total IPC of All Threads
-system.cpu.iq.ISSUE:FU_type_0                    8620                       # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0.start_dist
-                      No_OpClass            0      0.00%            # Type of FU issued
-                          IntAlu         4988     57.87%            # Type of FU issued
-                         IntMult            5      0.06%            # Type of FU issued
-                          IntDiv            2      0.02%            # Type of FU issued
-                        FloatAdd            2      0.02%            # Type of FU issued
-                        FloatCmp            0      0.00%            # Type of FU issued
-                        FloatCvt            0      0.00%            # Type of FU issued
-                       FloatMult            0      0.00%            # Type of FU issued
-                        FloatDiv            0      0.00%            # Type of FU issued
-                       FloatSqrt            0      0.00%            # Type of FU issued
-                         MemRead         2560     29.70%            # Type of FU issued
-                        MemWrite         1063     12.33%            # Type of FU issued
-                       IprAccess            0      0.00%            # Type of FU issued
-                    InstPrefetch            0      0.00%            # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0.end_dist
+system.cpu.iq.ISSUE:FU_type_0::No_OpClass            0      0.00%            # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::IntAlu            4988     57.87%            # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::IntMult              5      0.06%            # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::IntDiv               2      0.02%            # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatAdd             2      0.02%            # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatCmp             0      0.00%            # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatCvt             0      0.00%            # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatMult            0      0.00%            # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatDiv             0      0.00%            # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatSqrt            0      0.00%            # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::MemRead           2560     29.70%            # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::MemWrite          1063     12.33%            # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::IprAccess            0      0.00%            # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::InstPrefetch            0      0.00%            # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::total             8620                       # Type of FU issued
 system.cpu.iq.ISSUE:fu_busy_cnt                   162                       # FU busy when requested
 system.cpu.iq.ISSUE:fu_busy_rate             0.018794                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.ISSUE:fu_full.start_dist
-                      No_OpClass            0      0.00%            # attempts to use FU when none available
-                          IntAlu           10      6.17%            # attempts to use FU when none available
-                         IntMult            0      0.00%            # attempts to use FU when none available
-                          IntDiv            0      0.00%            # attempts to use FU when none available
-                        FloatAdd            0      0.00%            # attempts to use FU when none available
-                        FloatCmp            0      0.00%            # attempts to use FU when none available
-                        FloatCvt            0      0.00%            # attempts to use FU when none available
-                       FloatMult            0      0.00%            # attempts to use FU when none available
-                        FloatDiv            0      0.00%            # attempts to use FU when none available
-                       FloatSqrt            0      0.00%            # attempts to use FU when none available
-                         MemRead           98     60.49%            # attempts to use FU when none available
-                        MemWrite           54     33.33%            # attempts to use FU when none available
-                       IprAccess            0      0.00%            # attempts to use FU when none available
-                    InstPrefetch            0      0.00%            # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full.end_dist
-system.cpu.iq.ISSUE:issued_per_cycle::samples        15217                      
-system.cpu.iq.ISSUE:issued_per_cycle::min_value            0                      
-system.cpu.iq.ISSUE:issued_per_cycle::underflows            0      0.00%           
-system.cpu.iq.ISSUE:issued_per_cycle::0-1        11370     74.72%           
-system.cpu.iq.ISSUE:issued_per_cycle::1-2         1673     10.99%           
-system.cpu.iq.ISSUE:issued_per_cycle::2-3          787      5.17%           
-system.cpu.iq.ISSUE:issued_per_cycle::3-4          717      4.71%           
-system.cpu.iq.ISSUE:issued_per_cycle::4-5          332      2.18%           
-system.cpu.iq.ISSUE:issued_per_cycle::5-6          198      1.30%           
-system.cpu.iq.ISSUE:issued_per_cycle::6-7           91      0.60%           
-system.cpu.iq.ISSUE:issued_per_cycle::7-8           34      0.22%           
-system.cpu.iq.ISSUE:issued_per_cycle::8            15      0.10%           
-system.cpu.iq.ISSUE:issued_per_cycle::overflows            0      0.00%           
-system.cpu.iq.ISSUE:issued_per_cycle::total        15217                      
-system.cpu.iq.ISSUE:issued_per_cycle::max_value            8                      
-system.cpu.iq.ISSUE:issued_per_cycle::mean     0.566472                      
-system.cpu.iq.ISSUE:issued_per_cycle::stdev     1.217507                      
+system.cpu.iq.ISSUE:fu_full::No_OpClass             0      0.00%            # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::IntAlu                10      6.17%            # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::IntMult                0      0.00%            # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::IntDiv                 0      0.00%            # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatAdd               0      0.00%            # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatCmp               0      0.00%            # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatCvt               0      0.00%            # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatMult              0      0.00%            # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatDiv               0      0.00%            # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatSqrt              0      0.00%            # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::MemRead               98     60.49%            # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::MemWrite              54     33.33%            # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::IprAccess              0      0.00%            # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::InstPrefetch            0      0.00%            # attempts to use FU when none available
+system.cpu.iq.ISSUE:issued_per_cycle::samples        15217                       # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::min_value            0                       # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::underflows            0      0.00%            # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::0-1        11370     74.72%            # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::1-2         1673     10.99%            # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::2-3          787      5.17%            # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::3-4          717      4.71%            # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::4-5          332      2.18%            # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::5-6          198      1.30%            # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::6-7           91      0.60%            # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::7-8           34      0.22%            # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::8            15      0.10%            # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::overflows            0      0.00%            # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::total        15217                       # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::max_value            8                       # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::mean     0.566472                       # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::stdev     1.217507                       # Number of insts issued each cycle
 system.cpu.iq.ISSUE:rate                     0.310474                       # Inst issue rate
 system.cpu.iq.iqInstsAdded                       9773                       # Number of instructions added to the IQ (excludes non-spec)
 system.cpu.iq.iqInstsIssued                      8620                       # Number of instructions issued
@@ -353,13 +349,13 @@ system.cpu.l2cache.UpgradeReq_misses               15                       # nu
 system.cpu.l2cache.UpgradeReq_mshr_miss_latency       467500                       # number of UpgradeReq MSHR miss cycles
 system.cpu.l2cache.UpgradeReq_mshr_miss_rate            1                       # mshr miss rate for UpgradeReq accesses
 system.cpu.l2cache.UpgradeReq_mshr_misses           15                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_refs                  0.010076                       # Average number of references to valid blocks.
-system.cpu.l2cache.blocked_no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked_no_targets               0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles_no_mshrs            0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.demand_accesses                465                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_avg_miss_latency 34350.325380                       # average overall miss latency
@@ -378,7 +374,7 @@ system.cpu.l2cache.no_allocate_misses               0                       # Nu
 system.cpu.l2cache.overall_accesses               465                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_avg_miss_latency 34350.325380                       # average overall miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency 31159.436009                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
 system.cpu.l2cache.overall_hits                     4                       # number of overall hits
 system.cpu.l2cache.overall_miss_latency      15835500                       # number of overall miss cycles
 system.cpu.l2cache.overall_miss_rate         0.991398                       # miss rate for overall accesses