diff options
| author | Korey Sewell <ksewell@umich.edu> | 2011-06-20 18:57:14 -0400 |
|---|---|---|
| committer | Korey Sewell <ksewell@umich.edu> | 2011-06-20 18:57:14 -0400 |
| commit | b5736ba4ef3ae82238c7c9811e182c8a13a58fdd (patch) | |
| tree | ce28586e5b2957d629b7041e78cc56cc7e1457ed /tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt | |
| parent | affad299320e767b18c45a760c69a1ef287565bc (diff) | |
| download | gem5-b5736ba4ef3ae82238c7c9811e182c8a13a58fdd.tar.xz | |
alpha:o3:simple: update simout/err files
A few prior changesets have changed the gem5 output in a way that wont cause
errors but may be confusing for someone trying to debug the regressions. Ones that I caught
were:
- no more "warn: <hash address"
- typo in the ALPHA Prefetch unimplemented warning
Additionaly, the last updated stats changes rearrange the ordering of the stats output even though
they are still correct stats (gem5 is smart enough to detect this). All the regressions pass
w/the same stats even though it looks like they are being changed.
Diffstat (limited to 'tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt')
| -rw-r--r-- | tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt | 796 |
1 files changed, 398 insertions, 398 deletions
diff --git a/tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt b/tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt index 57f562650..ad65ae514 100644 --- a/tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt +++ b/tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt @@ -1,153 +1,52 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 83007 # Simulator instruction rate (inst/s) -host_mem_usage 207744 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host -host_tick_rate 204865540 # Simulator tick rate (ticks/s) -sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 5169 # Number of instructions simulated sim_seconds 0.000013 # Number of seconds simulated sim_ticks 12793500 # Number of ticks simulated -system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 531 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 1503 # Number of BTB lookups -system.cpu.BPredUnit.RASInCorrect 66 # Number of incorrect RAS predictions. -system.cpu.BPredUnit.condIncorrect 380 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 1180 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 1716 # Number of BP lookups -system.cpu.BPredUnit.usedRAS 206 # Number of times the RAS was used to get a target. -system.cpu.commit.branchMispredicts 339 # The number of times a branch was mispredicted -system.cpu.commit.branches 916 # Number of branches committed -system.cpu.commit.bw_lim_events 77 # number cycles where commit BW limit reached -system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.commitCommittedInsts 5826 # The number of committed instructions -system.cpu.commit.commitNonSpecStalls 10 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 3363 # The number of squashed insts skipped by commit -system.cpu.commit.committed_per_cycle::samples 12220 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.476759 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.219720 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 9742 79.72% 79.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 995 8.14% 87.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 703 5.75% 93.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 335 2.74% 96.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 169 1.38% 97.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 98 0.80% 98.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 69 0.56% 99.11% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 32 0.26% 99.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 77 0.63% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 12220 # Number of insts commited each cycle -system.cpu.commit.count 5826 # Number of instructions committed -system.cpu.commit.fp_insts 2 # Number of committed floating point instructions. -system.cpu.commit.function_calls 87 # Number of function calls committed. -system.cpu.commit.int_insts 5124 # Number of committed integer instructions. -system.cpu.commit.loads 1164 # Number of loads committed -system.cpu.commit.membars 0 # Number of memory barriers committed -system.cpu.commit.refs 2089 # Number of memory references committed -system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.committedInsts 5169 # Number of Instructions Simulated -system.cpu.committedInsts_total 5169 # Number of Instructions Simulated -system.cpu.cpi 4.950281 # CPI: Cycles Per Instruction -system.cpu.cpi_total 4.950281 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 1798 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 36128.906250 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35938.888889 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 1670 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 4624500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.071190 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 128 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 38 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 3234500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.050056 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 90 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 925 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 34186.416185 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36205.882353 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 579 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 11828500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.374054 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 346 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 295 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 1846500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.055135 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 51 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 15.950355 # Average number of references to valid blocks. -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 2723 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 34710.970464 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 36035.460993 # average overall mshr miss latency -system.cpu.dcache.demand_hits 2249 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 16453000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.174073 # miss rate for demand accesses -system.cpu.dcache.demand_misses 474 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 333 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 5081000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.051781 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 141 # number of demand (read+write) MSHR misses -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_blocks::0 91.720291 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.022393 # Average percentage of cache occupancy -system.cpu.dcache.overall_accesses 2723 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 34710.970464 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 36035.460993 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 2249 # number of overall hits -system.cpu.dcache.overall_miss_latency 16453000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.174073 # miss rate for overall accesses -system.cpu.dcache.overall_misses 474 # number of overall misses -system.cpu.dcache.overall_mshr_hits 333 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 5081000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.051781 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 141 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.sampled_refs 141 # Sample count of references to valid blocks. -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 91.720291 # Cycle average of tags in use -system.cpu.dcache.total_refs 2249 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.decode.BlockedCycles 742 # Number of cycles decode is blocked -system.cpu.decode.BranchMispred 42 # Number of times decode detected a branch misprediction -system.cpu.decode.BranchResolved 89 # Number of times decode resolved a branch -system.cpu.decode.DecodedInsts 10279 # Number of instructions handled by decode -system.cpu.decode.IdleCycles 8753 # Number of cycles decode is idle -system.cpu.decode.RunCycles 2688 # Number of cycles decode is running -system.cpu.decode.SquashCycles 636 # Number of cycles decode is squashing -system.cpu.decode.SquashedInsts 153 # Number of squashed instructions handled by decode -system.cpu.decode.UnblockCycles 37 # Number of cycles decode is unblocking -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.read_accesses 0 # DTB read accesses +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 95916 # Simulator instruction rate (inst/s) +host_tick_rate 237306997 # Simulator tick rate (ticks/s) +host_mem_usage 193796 # Number of bytes of host memory used +host_seconds 0.05 # Real time elapsed on the host +sim_insts 5169 # Number of instructions simulated system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.read_accesses 0 # DTB read accesses system.cpu.dtb.write_hits 0 # DTB write hits system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 8 # Number of system calls +system.cpu.numCycles 25588 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.BPredUnit.lookups 1716 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 1180 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 380 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 1503 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 531 # Number of BTB hits +system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.BPredUnit.usedRAS 206 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 66 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 1531 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 10867 # Number of instructions fetch has processed system.cpu.fetch.Branches 1716 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 1531 # Number of cache lines fetched +system.cpu.fetch.predictedBranches 737 # Number of branches that fetch has predicted taken system.cpu.fetch.Cycles 2794 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 211 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 10867 # Number of instructions fetch has processed -system.cpu.fetch.MiscStallCycles 15 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.SquashCycles 387 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.067063 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 1531 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 737 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 0.424691 # Number of inst fetches per cycle +system.cpu.fetch.MiscStallCycles 15 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.CacheLines 1531 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 211 # Number of outstanding Icache misses that were squashed system.cpu.fetch.rateDist::samples 12856 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::mean 0.845286 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::stdev 2.112165 # Number of instructions fetched each cycle (Total) @@ -165,111 +64,95 @@ system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Nu system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::total 12856 # Number of instructions fetched each cycle (Total) -system.cpu.fp_regfile_reads 3 # number of floating regfile reads -system.cpu.fp_regfile_writes 1 # number of floating regfile writes -system.cpu.icache.ReadReq_accesses 1531 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 36303.482587 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 35016.717325 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 1129 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 14594000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.262573 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 402 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 73 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 11520500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.214892 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 329 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 3.431611 # Average number of references to valid blocks. -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 1531 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 36303.482587 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 35016.717325 # average overall mshr miss latency -system.cpu.icache.demand_hits 1129 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 14594000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.262573 # miss rate for demand accesses -system.cpu.icache.demand_misses 402 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 73 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 11520500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.214892 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 329 # number of demand (read+write) MSHR misses -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_blocks::0 158.750706 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.077515 # Average percentage of cache occupancy -system.cpu.icache.overall_accesses 1531 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 36303.482587 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 35016.717325 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 1129 # number of overall hits -system.cpu.icache.overall_miss_latency 14594000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.262573 # miss rate for overall accesses -system.cpu.icache.overall_misses 402 # number of overall misses -system.cpu.icache.overall_mshr_hits 73 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 11520500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.214892 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 329 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.replacements 15 # number of replacements -system.cpu.icache.sampled_refs 329 # Sample count of references to valid blocks. -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 158.750706 # Cycle average of tags in use -system.cpu.icache.total_refs 1129 # Total number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 12732 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.branchMispredicts 377 # Number of branch mispredicts detected at execute -system.cpu.iew.exec_branches 1171 # Number of branches executed -system.cpu.iew.exec_nop 1220 # number of nop insts executed -system.cpu.iew.exec_rate 0.276575 # Inst execution rate -system.cpu.iew.exec_refs 2915 # number of memory reference insts executed -system.cpu.iew.exec_stores 1038 # Number of stores executed -system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.iewBlockCycles 165 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 2109 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 10 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 198 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 1127 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 9195 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 1877 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 216 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 7077 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 6 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 1 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 636 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 14 # Number of cycles IEW is unblocking -system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread0.forwLoads 59 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread0.memOrderViolation 5 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.squashedLoads 945 # Number of loads squashed -system.cpu.iew.lsq.thread0.squashedStores 202 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 5 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 259 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 118 # Number of branches that were predicted taken incorrectly -system.cpu.iew.wb_consumers 3566 # num instructions consuming a value -system.cpu.iew.wb_count 6732 # cumulative count of insts written-back -system.cpu.iew.wb_fanout 0.716489 # average fanout of values written-back -system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.wb_producers 2555 # num instructions producing a value -system.cpu.iew.wb_rate 0.263092 # insts written-back per cycle -system.cpu.iew.wb_sent 6801 # cumulative count of insts sent to commit -system.cpu.int_regfile_reads 9689 # number of integer regfile reads -system.cpu.int_regfile_writes 4703 # number of integer regfile writes -system.cpu.ipc 0.202009 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.202009 # IPC: Total IPC of All Threads +system.cpu.fetch.branchRate 0.067063 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.424691 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 8753 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 742 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2688 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 37 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 636 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 89 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 42 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 10279 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 153 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 636 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 8904 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 238 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 420 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2577 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 81 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 9880 # Number of instructions processed by rename +system.cpu.rename.LSQFullEvents 71 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 6029 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 11929 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 11924 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 5 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 3410 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 2619 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 15 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 10 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 193 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2109 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1127 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 7965 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 10 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 7293 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 31 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 2360 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1480 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.issued_per_cycle::samples 12856 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.567284 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.210668 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 9551 74.29% 74.29% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1436 11.17% 85.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 786 6.11% 91.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 503 3.91% 95.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 300 2.33% 97.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 160 1.24% 99.07% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 76 0.59% 99.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 32 0.25% 99.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 12 0.09% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 12856 # Number of insts issued each cycle +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 7 4.90% 4.90% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 4.90% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 4.90% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.90% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.90% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.90% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 4.90% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.90% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 4.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 4.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.90% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 84 58.74% 63.64% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 52 36.36% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued system.cpu.iq.FU_type_0::IntAlu 4286 58.77% 58.77% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 4 0.05% 58.82% # Type of FU issued @@ -305,175 +188,292 @@ system.cpu.iq.FU_type_0::MemWrite 1047 14.36% 100.00% # Ty system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::total 7293 # Type of FU issued -system.cpu.iq.fp_alu_accesses 2 # Number of floating point alu accesses -system.cpu.iq.fp_inst_queue_reads 4 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_wakeup_accesses 2 # Number of floating instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_writes 2 # Number of floating instruction queue writes +system.cpu.iq.rate 0.285016 # Inst issue rate system.cpu.iq.fu_busy_cnt 143 # FU busy when requested system.cpu.iq.fu_busy_rate 0.019608 # FU busy rate (busy events/executed inst) -system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 7 4.90% 4.90% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 4.90% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 4.90% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.90% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.90% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.90% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 4.90% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.90% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 4.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 4.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.90% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 84 58.74% 63.64% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 52 36.36% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.int_alu_accesses 7434 # Number of integer alu accesses system.cpu.iq.int_inst_queue_reads 27612 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_wakeup_accesses 6730 # Number of integer instruction queue wakeup accesses system.cpu.iq.int_inst_queue_writes 10338 # Number of integer instruction queue writes -system.cpu.iq.iqInstsAdded 7965 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 7293 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 10 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 2360 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 31 # Number of squashed instructions issued -system.cpu.iq.iqSquashedOperandsExamined 1480 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.issued_per_cycle::samples 12856 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.567284 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.210668 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 9551 74.29% 74.29% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1436 11.17% 85.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 786 6.11% 91.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 503 3.91% 95.49% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 300 2.33% 97.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 160 1.24% 99.07% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 76 0.59% 99.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 32 0.25% 99.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 12 0.09% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 12856 # Number of insts issued each cycle -system.cpu.iq.rate 0.285016 # Inst issue rate -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.l2cache.ReadExReq_accesses 51 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 34686.274510 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31490.196078 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 1769000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 51 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 1606000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 51 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 419 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 34317.307692 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31129.807692 # average ReadReq mshr miss latency +system.cpu.iq.int_inst_queue_wakeup_accesses 6730 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 4 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 2 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 2 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 7434 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 2 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 59 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.squashedLoads 945 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 5 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 202 # Number of stores squashed +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewSquashCycles 636 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 165 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 14 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 9195 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 198 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2109 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1127 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 10 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 6 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 1 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 5 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 118 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 259 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 377 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 7077 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 1877 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 216 # Number of squashed instructions skipped in execute +system.cpu.iew.exec_swp 0 # number of swp insts executed +system.cpu.iew.exec_nop 1220 # number of nop insts executed +system.cpu.iew.exec_refs 2915 # number of memory reference insts executed +system.cpu.iew.exec_branches 1171 # Number of branches executed +system.cpu.iew.exec_stores 1038 # Number of stores executed +system.cpu.iew.exec_rate 0.276575 # Inst execution rate +system.cpu.iew.wb_sent 6801 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 6732 # cumulative count of insts written-back +system.cpu.iew.wb_producers 2555 # num instructions producing a value +system.cpu.iew.wb_consumers 3566 # num instructions consuming a value +system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ +system.cpu.iew.wb_rate 0.263092 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.716489 # average fanout of values written-back +system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu.commit.commitCommittedInsts 5826 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 3363 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 10 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 339 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 12220 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.476759 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.219720 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 9742 79.72% 79.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 995 8.14% 87.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 703 5.75% 93.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 335 2.74% 96.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 169 1.38% 97.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 98 0.80% 98.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 69 0.56% 99.11% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 32 0.26% 99.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 77 0.63% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 12220 # Number of insts commited each cycle +system.cpu.commit.count 5826 # Number of instructions committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.refs 2089 # Number of memory references committed +system.cpu.commit.loads 1164 # Number of loads committed +system.cpu.commit.membars 0 # Number of memory barriers committed +system.cpu.commit.branches 916 # Number of branches committed +system.cpu.commit.fp_insts 2 # Number of committed floating point instructions. +system.cpu.commit.int_insts 5124 # Number of committed integer instructions. +system.cpu.commit.function_calls 87 # Number of function calls committed. +system.cpu.commit.bw_lim_events 77 # number cycles where commit BW limit reached +system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits +system.cpu.rob.rob_reads 21319 # The number of ROB reads +system.cpu.rob.rob_writes 19020 # The number of ROB writes +system.cpu.timesIdled 260 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 12732 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 5169 # Number of Instructions Simulated +system.cpu.committedInsts_total 5169 # Number of Instructions Simulated +system.cpu.cpi 4.950281 # CPI: Cycles Per Instruction +system.cpu.cpi_total 4.950281 # CPI: Total CPI of All Threads +system.cpu.ipc 0.202009 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.202009 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 9689 # number of integer regfile reads +system.cpu.int_regfile_writes 4703 # number of integer regfile writes +system.cpu.fp_regfile_reads 3 # number of floating regfile reads +system.cpu.fp_regfile_writes 1 # number of floating regfile writes +system.cpu.misc_regfile_reads 134 # number of misc regfile reads +system.cpu.icache.replacements 15 # number of replacements +system.cpu.icache.tagsinuse 158.750706 # Cycle average of tags in use +system.cpu.icache.total_refs 1129 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 329 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 3.431611 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::0 158.750706 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.077515 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 1129 # number of ReadReq hits +system.cpu.icache.demand_hits 1129 # number of demand (read+write) hits +system.cpu.icache.overall_hits 1129 # number of overall hits +system.cpu.icache.ReadReq_misses 402 # number of ReadReq misses +system.cpu.icache.demand_misses 402 # number of demand (read+write) misses +system.cpu.icache.overall_misses 402 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 14594000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 14594000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 14594000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 1531 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 1531 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 1531 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.262573 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.262573 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.262573 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 36303.482587 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 36303.482587 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 36303.482587 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.writebacks 0 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits 73 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 73 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 73 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 329 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 329 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 329 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.ReadReq_mshr_miss_latency 11520500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 11520500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 11520500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.214892 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate 0.214892 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate 0.214892 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 35016.717325 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 35016.717325 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 35016.717325 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.replacements 0 # number of replacements +system.cpu.dcache.tagsinuse 91.720291 # Cycle average of tags in use +system.cpu.dcache.total_refs 2249 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 141 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 15.950355 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::0 91.720291 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.022393 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 1670 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 579 # number of WriteReq hits +system.cpu.dcache.demand_hits 2249 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 2249 # number of overall hits +system.cpu.dcache.ReadReq_misses 128 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 346 # number of WriteReq misses +system.cpu.dcache.demand_misses 474 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 474 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 4624500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 11828500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency 16453000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 16453000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 1798 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses 925 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses 2723 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 2723 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.071190 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate 0.374054 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate 0.174073 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.174073 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 36128.906250 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 34186.416185 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency 34710.970464 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 34710.970464 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks 0 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 38 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 295 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits 333 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 333 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 90 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 51 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses 141 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 141 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.ReadReq_mshr_miss_latency 3234500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 1846500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 5081000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 5081000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.050056 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate 0.055135 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate 0.051781 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate 0.051781 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35938.888889 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36205.882353 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 36035.460993 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 36035.460993 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.replacements 0 # number of replacements +system.cpu.l2cache.tagsinuse 218.141494 # Cycle average of tags in use +system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 416 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.007212 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::0 218.141494 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.006657 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits 3 # number of ReadReq hits +system.cpu.l2cache.demand_hits 3 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 3 # number of overall hits +system.cpu.l2cache.ReadReq_misses 416 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses 51 # number of ReadExReq misses +system.cpu.l2cache.demand_misses 467 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 467 # number of overall misses system.cpu.l2cache.ReadReq_miss_latency 14276000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 1769000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 16045000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 16045000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 419 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses 51 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 470 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 470 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate 0.992840 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 416 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 12950000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.992840 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 416 # number of ReadReq MSHR misses -system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.007212 # Average number of references to valid blocks. -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 0.993617 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.993617 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 34317.307692 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34686.274510 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34357.601713 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34357.601713 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 470 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 34357.601713 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31169.164882 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 3 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 16045000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.993617 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 467 # number of demand (read+write) misses +system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses 416 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 51 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses 467 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 467 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 12950000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 1606000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency 14556000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 14556000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.992840 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate 0.993617 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 467 # number of demand (read+write) MSHR misses -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_blocks::0 218.141494 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.006657 # Average percentage of cache occupancy -system.cpu.l2cache.overall_accesses 470 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 34357.601713 # average overall miss latency +system.cpu.l2cache.overall_mshr_miss_rate 0.993617 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31129.807692 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31490.196078 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31169.164882 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 31169.164882 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 3 # number of overall hits -system.cpu.l2cache.overall_miss_latency 16045000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.993617 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 467 # number of overall misses -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 14556000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.993617 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 467 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 416 # Sample count of references to valid blocks. +system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 218.141494 # Cycle average of tags in use -system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 2109 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1127 # Number of stores inserted to the mem dependence unit. -system.cpu.misc_regfile_reads 134 # number of misc regfile reads -system.cpu.numCycles 25588 # number of cpu cycles simulated -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.rename.BlockCycles 238 # Number of cycles rename is blocking -system.cpu.rename.CommittedMaps 3410 # Number of HB maps that are committed -system.cpu.rename.IdleCycles 8904 # Number of cycles rename is idle -system.cpu.rename.LSQFullEvents 71 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenameLookups 11929 # Number of register rename lookups that rename has made -system.cpu.rename.RenamedInsts 9880 # Number of instructions processed by rename -system.cpu.rename.RenamedOperands 6029 # Number of destination operands rename has renamed -system.cpu.rename.RunCycles 2577 # Number of cycles rename is running -system.cpu.rename.SquashCycles 636 # Number of cycles rename is squashing -system.cpu.rename.UnblockCycles 81 # Number of cycles rename is unblocking -system.cpu.rename.UndoneMaps 2619 # Number of HB maps that are undone due to squashing -system.cpu.rename.fp_rename_lookups 5 # Number of floating rename lookups -system.cpu.rename.int_rename_lookups 11924 # Number of integer rename lookups -system.cpu.rename.serializeStallCycles 420 # count of cycles rename stalled for serializing inst -system.cpu.rename.serializingInsts 15 # count of serializing insts renamed -system.cpu.rename.skidInsts 193 # count of insts added to the skid buffer -system.cpu.rename.tempSerializingInsts 10 # count of temporary serializing insts renamed -system.cpu.rob.rob_reads 21319 # The number of ROB reads -system.cpu.rob.rob_writes 19020 # The number of ROB writes -system.cpu.timesIdled 260 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.workload.num_syscalls 8 # Number of system calls +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |