diff options
author | Gabe Black <gblack@eecs.umich.edu> | 2010-01-02 07:06:26 -0500 |
---|---|---|
committer | Gabe Black <gblack@eecs.umich.edu> | 2010-01-02 07:06:26 -0500 |
commit | 4f4e6fc099349cf34e9ac4cfae4211379a4a030f (patch) | |
tree | 5828a10fcbaed0a0530e2547d6e2e73c3a0e4b16 /tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt | |
parent | 47a1f113811173ebd52365bbe09ec2477c003780 (diff) | |
download | gem5-4f4e6fc099349cf34e9ac4cfae4211379a4a030f.tar.xz |
MIPS: Update the stats of the RUBY version of the regressions.
Diffstat (limited to 'tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt')
-rw-r--r-- | tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt | 22 |
1 files changed, 11 insertions, 11 deletions
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt b/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt index 15c68a6b0..8a4afd8c9 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt +++ b/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 3701 # Simulator instruction rate (inst/s) -host_mem_usage 1265204 # Number of bytes of host memory used -host_seconds 1.54 # Real time elapsed on the host -host_tick_rate 15119806 # Simulator tick rate (ticks/s) +host_inst_rate 6560 # Simulator instruction rate (inst/s) +host_mem_usage 2303716 # Number of bytes of host memory used +host_seconds 0.89 # Real time elapsed on the host +host_tick_rate 26729951 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 5685 # Number of instructions simulated -sim_seconds 0.000023 # Number of seconds simulated -sim_ticks 23227000 # Number of ticks simulated +sim_insts 5827 # Number of instructions simulated +sim_seconds 0.000024 # Number of seconds simulated +sim_ticks 23749000 # Number of ticks simulated system.cpu.dtb.accesses 0 # DTB accesses system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses @@ -28,9 +28,9 @@ system.cpu.itb.write_accesses 0 # DT system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 46454 # number of cpu cycles simulated -system.cpu.num_insts 5685 # Number of instructions executed -system.cpu.num_refs 2058 # Number of memory references -system.cpu.workload.PROG:num_syscalls 13 # Number of system calls +system.cpu.numCycles 47498 # number of cpu cycles simulated +system.cpu.num_insts 5827 # Number of instructions executed +system.cpu.num_refs 2090 # Number of memory references +system.cpu.workload.PROG:num_syscalls 8 # Number of system calls ---------- End Simulation Statistics ---------- |